CN114284234A - Packaging structure and manufacturing method for packaging structure - Google Patents
Packaging structure and manufacturing method for packaging structure Download PDFInfo
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- CN114284234A CN114284234A CN202111544252.7A CN202111544252A CN114284234A CN 114284234 A CN114284234 A CN 114284234A CN 202111544252 A CN202111544252 A CN 202111544252A CN 114284234 A CN114284234 A CN 114284234A
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Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Surface Acoustic Wave Elements And Circuit Networks Thereof (AREA)
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Abstract
The application relates to the technical field of chip packaging, and discloses a packaging structure, including: the to-be-packaged substrate is used for supporting the to-be-packaged filter chip; the filter chip to be packaged is flip-chip welded on the substrate to be packaged; the isolation layer is arranged on one side, close to the filter chip to be packaged, of the substrate to be packaged; and the plastic packaging layer, the filter chip to be packaged, the substrate to be packaged and the isolation layer enclose to form a cavity. Like this, through treating that the packaging substrate is close to one side of treating the encapsulation filter chip and setting up the insulating layer, under the condition of high temperature, block volatile organic matter dielectric material and hinder the solder mask material through the insulating layer for organic matter dielectric material and hinder the solder mask material and can not adhere to and treat the encapsulation filter chip, can not cause the wave filter frequency offset, make the wave filter reliability high. The application also discloses a manufacturing method for the packaging structure.
Description
Technical Field
The present application relates to the field of chip packaging technologies, and for example, to a package structure and a manufacturing method for the package structure.
Background
The package of the filter generally has a cavity, and currently, a wafer containing a filter chip to be packaged is cut into a single filter chip to be packaged, then the single filter chip to be packaged is flip-chip bonded on a substrate to be packaged, and then the single filter chip to be packaged and the substrate to be packaged are enclosed by a plastic packaging film to form the cavity. However, 250 degree reflow soldering is involved in the process of assembling the filter at the client end, and the high temperature makes the organic medium material and the solder resist material of the substrate to be packaged easily volatilize and adhere to the filter chip to be packaged, so that the frequency of the filter is shifted, and the reliability of the filter is low.
Disclosure of Invention
The following presents a simplified summary in order to provide a basic understanding of some aspects of the disclosed embodiments. This summary is not an extensive overview nor is intended to identify key/critical elements or to delineate the scope of such embodiments but rather as a prelude to the more detailed description that is presented later.
The embodiment of the invention provides a packaging structure and a manufacturing method for the packaging structure, so that the reliability of a filter can be improved.
In some embodiments, the package structure comprises: the to-be-packaged substrate is used for supporting the to-be-packaged filter chip; the filter chip to be packaged is flip-chip welded on the substrate to be packaged; the isolation layer is arranged on one side, close to the filter chip to be packaged, of the substrate to be packaged; and the plastic packaging layer, the filter chip to be packaged, the substrate to be packaged and the isolation layer enclose to form a cavity.
In some embodiments, the substrate to be packaged is provided with a plurality of first pads; the filter chip to be packaged is provided with a plurality of second bonding pads; and the first bonding pads are correspondingly connected with the second bonding pads through welding bumps.
In some embodiments, each of the solder bumps has a thickness greater than a thickness of the insulating layer.
In some embodiments, the insulating layer is not in contact with each of the first pads.
In some embodiments, the insulating layer covers each of the first pads and does not contact each of the bonding bumps.
In some embodiments, the molding layer comprises: the first plastic packaging material layer, the filter chip to be packaged, the substrate to be packaged and the isolation layer enclose to form a cavity; and the second plastic packaging material layer is arranged on one side of the first plastic packaging material layer, which is far away from the filter chip to be packaged, the substrate to be packaged and the isolation layer.
In some embodiments, the package structure further includes a third pad disposed on a side of the substrate to be packaged away from the filter chip to be packaged.
In some embodiments, the insulating layer is made of a dry film, a plastic-encapsulated thin film material, or polyimide.
In some embodiments, the method for manufacturing a package structure includes: forming an isolation layer on a preset substrate to be packaged; flip-chip welding a plurality of preset filter chips to be packaged on the substrate to be packaged; carrying out plastic package on each filter chip to be packaged to form a plastic package layer; the filter chips to be packaged, the plastic packaging layers corresponding to the filter chips to be packaged, the isolation layers and the substrate to be packaged are respectively enclosed to form a cavity; each filter chip to be packaged, the plastic packaging layer corresponding to each filter chip to be packaged, the isolation layer and the substrate to be packaged form a plastic packaging structure; and cutting the plastic package structure into a plurality of package structures.
In some embodiments, the substrate to be packaged is provided with a plurality of first pads, and an isolation layer is formed on a predetermined substrate to be packaged, including: depositing the isolation layer on the substrate to be packaged; and etching the isolation layer to expose the first bonding pads.
The embodiment of the invention provides a packaging structure and a manufacturing method for the packaging structure. The following technical effects can be achieved: the filter chip packaging structure comprises a substrate to be packaged, a substrate to be packaged and a chip support plate, wherein the substrate to be packaged is used for supporting the filter chip to be packaged; the filter chip to be packaged is inversely welded on the substrate to be packaged; the isolation layer is arranged on one side, close to the filter chip to be packaged, of the substrate to be packaged; and the plastic packaging layer, the filter chip to be packaged, the substrate to be packaged and the isolation layer enclose to form a cavity. Like this, through treating that the packaging substrate is close to one side of treating the encapsulation filter chip and setting up the insulating layer, under the condition of high temperature, block volatile organic matter dielectric material and hinder the solder mask material through the insulating layer for organic matter dielectric material and hinder the solder mask material and can not adhere to and treat the encapsulation filter chip, can not cause the wave filter frequency offset, make the wave filter reliability high.
The foregoing general description and the following description are exemplary and explanatory only and are not restrictive of the application.
Drawings
One or more embodiments are illustrated by way of example in the accompanying drawings, which correspond to the accompanying drawings and not in limitation thereof, in which elements having the same reference numeral designations are shown as like elements and not in limitation thereof, and wherein:
fig. 1 is a schematic structural diagram of a package structure according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of a second package structure according to an embodiment of the invention;
fig. 3 is a schematic structural diagram of a third package structure according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of a fourth package structure according to an embodiment of the invention;
FIG. 5 is a schematic diagram of a method for fabricating a package structure according to an embodiment of the present invention;
fig. 6 is a schematic diagram of another manufacturing method for a package structure according to an embodiment of the present invention.
Reference numerals:
100: a substrate to be packaged; 101: a first pad; 102: a third pad; 110: a filter chip is to be packaged; 111: a second pad; 120: an insulating layer; 130: a plastic packaging layer; 140: welding the salient points; 150: a first plastic package material layer; 160: and a second plastic package material layer.
Detailed Description
So that the manner in which the features and aspects of the embodiments of the present invention can be understood in detail, a more particular description of the embodiments of the invention, briefly summarized above, may be had by reference to the embodiments, some of which are illustrated in the appended drawings. In the following description of the technology, for purposes of explanation, numerous details are set forth in order to provide a thorough understanding of the disclosed embodiments. However, one or more embodiments may be practiced without these details. In other instances, well-known structures and devices may be shown in simplified form in order to simplify the drawing.
The terms "first," "second," and the like in the description and in the claims, and in the drawings, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It should be understood that the data so used may be interchanged under appropriate circumstances such that embodiments of the invention described herein may be used. Furthermore, the terms "comprising" and "having," as well as any variations thereof, are intended to cover non-exclusive inclusions.
In the embodiments of the present invention, the terms "upper", "lower", "inner", "middle", "outer", "front", "rear", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings. These terms are used primarily to better describe embodiments of the invention and its embodiments, and are not intended to limit the indicated devices, elements or components to a particular orientation or to be constructed and operated in a particular orientation. Moreover, some of the above terms may be used to indicate other meanings besides the orientation or positional relationship, for example, the term "on" may also be used to indicate some kind of attachment or connection relationship in some cases. Specific meanings of these terms in the embodiments of the present invention may be understood by those skilled in the art according to specific situations.
In addition, the terms "disposed," "connected," and "secured" are to be construed broadly. For example, "connected" may be a fixed connection, a detachable connection, or a unitary construction; can be a mechanical connection, or an electrical connection; may be directly connected, or indirectly connected through intervening media, or may be in internal communication between two devices, elements or components. Specific meanings of the above terms in the embodiments of the present invention can be understood by those of ordinary skill in the art according to specific situations.
The term "plurality" means two or more unless otherwise specified.
In the embodiment of the present invention, the character "/" indicates that the preceding and following objects are in an or relationship. For example, A/B represents: a or B.
The term "and/or" is an associative relationship that describes objects, meaning that three relationships may exist. For example, a and/or B, represents: a or B, or A and B.
It should be noted that, in the case of no conflict, the embodiments of the present invention and features of the embodiments may be combined with each other.
Referring to fig. 1, an embodiment of the present invention provides a package structure, including: the package structure comprises a substrate 100 to be packaged, a filter chip 110 to be packaged, an isolation layer 120 and a plastic package layer 130, wherein the substrate 100 to be packaged is used for supporting the filter chip 110 to be packaged; the filter chip 110 to be packaged is flip-chip bonded on the substrate 100 to be packaged; the insulating layer 120 is arranged on one side of the substrate to be packaged 100 close to the filter chip to be packaged 110; the plastic package layer 130, the filter chip 110 to be packaged, the substrate 100 to be packaged, and the isolation layer 120 enclose a cavity.
The packaging structure provided by the embodiment of the invention can realize the following technical effects: the filter chip packaging structure comprises a substrate to be packaged, a substrate to be packaged and a chip support plate, wherein the substrate to be packaged is used for supporting the filter chip to be packaged; the filter chip to be packaged is inversely welded on the substrate to be packaged; the isolation layer is arranged on one side, close to the filter chip to be packaged, of the substrate to be packaged; and the plastic packaging layer, the filter chip to be packaged, the substrate to be packaged and the isolation layer enclose to form a cavity. Like this, through treating that the packaging substrate is close to one side of treating the encapsulation filter chip and setting up the insulating layer, under the condition of high temperature, block volatile organic matter dielectric material and hinder the solder mask material through the insulating layer for organic matter dielectric material and hinder the solder mask material and can not adhere to and treat the encapsulation filter chip, can not cause the wave filter frequency offset, make the wave filter reliability high.
Optionally, the substrate to be packaged 100 is provided with a plurality of first pads 101; the filter chip to be packaged 110 is provided with a plurality of second pads 111; the first pads 101 and the second pads 111 are connected in a one-to-one correspondence by the solder bumps 140.
Optionally, the isolation layer 120 covers each first pad 101 and does not contact each solder bump 140.
Optionally, the package structure further includes a third pad 102 disposed on a side of the substrate 100 to be packaged away from the filter chip 110 to be packaged.
Optionally, the solder bumps are made of a material that can be used for flip-chip bonding, such as: one or more of solder balls, copper pillars, gold bumps, and conductive paste.
Optionally, the first pad, the second pad and the third pad are all made of a material capable of conducting electricity, such as metal.
Optionally, the isolation layer is made of a dry film, a plastic-encapsulated film material, or polyimide.
Optionally, the molding layer includes: the first plastic packaging material layer, the filter chip to be packaged, the substrate to be packaged and the isolation layer enclose to form a cavity; and the second plastic packaging material layer is arranged on one side, far away from the filter chip to be packaged, of the first plastic packaging material layer, and far away from the substrate to be packaged and the isolation layer.
Optionally, the first plastic packaging material layer is made of Dry Film or plastic packaging Film.
Optionally, the second plastic package material layer is made of Dry Film, plastic Film, or plastic resin material.
Optionally, the insulating layer covers each first pad and does not contact each bonding bump.
In some embodiments, as shown in fig. 2, each second pad 111 of the filter chip 110 to be packaged is connected to each first pad 101 of the substrate 100 to be packaged through each solder bump 140; the isolation layer 120 is arranged on one side, close to the filter chip 110 to be packaged, of the substrate 00 to be packaged, and the isolation layer 120 covers each first pad 101 and is not in contact with each welding bump 140; the plastic packaging layer consists of a first plastic packaging material layer 150 and a second plastic packaging material layer 160, and the first plastic packaging material layer 150, the filter chip 110 to be packaged, the substrate 100 to be packaged and the isolation layer 120 enclose to form a cavity; and a second plastic encapsulation layer 160 disposed on a side of the first plastic encapsulation layer 150 away from the filter chip 110 to be packaged, the substrate 100 to be packaged, and the isolation layer 120. Therefore, the isolation layer is arranged on the substrate to be packaged and covers all the surface of the substrate to be packaged except the first bonding pad. The method can prevent the organic medium material and the solder resist material volatilized by the substrate to be packaged at high temperature from being attached to the filter chip to be packaged to the maximum extent. Meanwhile, the water vapor in the external environment can be prevented from entering the packaging structure through the substrate to be packaged to the maximum extent, and the reliability of the packaging structure can be improved.
Optionally, the insulating layer is not in contact with each first pad.
In some embodiments, as shown in fig. 3, each second pad 111 of the filter chip 110 to be packaged is connected to each first pad 101 of the substrate 100 to be packaged through each solder bump 140; the isolation layer 120 is arranged on one side, close to the filter chip 110 to be packaged, of the substrate 100 to be packaged, and the isolation layer 120 is not in contact with the first pads 101; the plastic package layer 130 is a single-layer plastic package structure, and a cavity is formed by enclosing the plastic package layer 130, the filter chip 110 to be packaged, the substrate 100 to be packaged, and the isolation layer 120. Like this, owing to set up the insulating layer on treating the packaging substrate, the insulating layer does not contact with each first pad for when setting up the welding bump, can set up the welding bump shorter, reduced the encapsulation cost, can avoid treating the volatile organic matter dielectric material of packaging substrate and hinder the solder material and adhere to and treat the encapsulation filter chip under the high temperature when reducing the encapsulation cost. Moreover, water vapor in the external environment can not enter the packaging structure through the substrate to be packaged, and the reliability of the packaging structure is improved.
In some embodiments, as shown in fig. 4, each second pad 111 of the filter chip 110 to be packaged is connected to each first pad 101 of the substrate 100 to be packaged through each solder bump 140; the isolation layer 120 is arranged on one side, close to the filter chip 110 to be packaged, of the substrate 100 to be packaged, and the isolation layer 120 is not in contact with the first pads 101; the plastic packaging layer consists of a first plastic packaging material layer 150 and a second plastic packaging material layer 160, and the first plastic packaging material layer 150, the filter chip 110 to be packaged, the substrate 100 to be packaged and the isolation layer 120 enclose to form a cavity; and a second plastic encapsulation layer 160 disposed on a side of the first plastic encapsulation layer 150 away from the filter chip 110 to be packaged, the substrate 100 to be packaged, and the isolation layer 120. Like this, owing to set up the insulating layer on treating the packaging substrate, the insulating layer does not contact with each first pad for when setting up the welding bump, can set up the welding bump shorter, reduced the encapsulation cost, can avoid treating the volatile organic matter dielectric material of packaging substrate and hinder the solder material and adhere to and treat the encapsulation filter chip under the high temperature when reducing the encapsulation cost. Moreover, water vapor in the external environment can not enter the packaging structure through the substrate to be packaged, and the reliability of the packaging structure is improved.
Optionally, the thickness of each solder bump is greater than the thickness of the insulating layer. Like this, treat that the packaging substrate passes through flip-chip bonding for treat that each first pad of packaging substrate and each second pad of treating the encapsulation filter chip pass through the welding bump one-to-one and connect the back, treat that the surface of encapsulation filter chip can not with the surface contact who treats the packaging substrate, also can not with the surface contact of insulating layer, thereby treat the packaging substrate and treat and can form the cavity between the encapsulation filter chip.
In some embodiments, the plastic packaging with the plastic packaging film is to directly cover the chip with a high-ductility, extremely-low-volatility, cured after heating and high-viscosity organic film, and to apply the vacuum adhesive to each surface of the chip, if the plastic packaging is directly performed with a thick plastic packaging film, the thickness of the organic film is usually required to exceed 200 micrometers, and the price is expensive. The epoxy resin molding compound is a powdery molding compound prepared by mixing epoxy resin serving as matrix resin, high-performance phenolic resin serving as a curing agent, silicon micropowder and the like serving as fillers and a plurality of auxiliaries. The plastic package is carried out through the epoxy resin molding compound, and compared with the plastic package which adopts a plastic package film, the plastic package cost is lower.
In some embodiments, the first layer of plastic molding compound is made of a plastic molding film and the second layer of plastic molding compound is made of an epoxy molding compound. Like this, by first plastic envelope layer with wait to encapsulate the filter chip, wait that encapsulation base plate and isolation layer enclose to close and form the cavity, by the second plastic envelope layer to by first plastic envelope layer with wait to encapsulate the filter chip, wait that encapsulation base plate and isolation layer enclose the cavity that closes and form and protect, the thickness on first plastic envelope layer need not make 200 microns, and the cost of manufacture is lower.
Referring to fig. 5, an embodiment of the present invention provides a method for manufacturing a package structure, including:
step S501, forming an isolation layer on a preset substrate to be packaged;
step S502, flip-chip welding a plurality of preset filter chips to be packaged on a substrate to be packaged;
step S503, carrying out plastic package on each filter chip to be packaged to form a plastic package layer; the filter chips to be packaged, the plastic packaging layers corresponding to the filter chips to be packaged, the isolation layers and the substrates to be packaged are respectively enclosed to form cavities; each filter chip to be packaged, the plastic packaging layer corresponding to each filter chip to be packaged, the isolation layer and the substrate to be packaged form a plastic packaging structure;
and step S504, cutting the plastic package structure into a plurality of package structures.
By adopting the manufacturing method for the packaging structure provided by the embodiment of the invention, the isolation layer is formed on the preset substrate to be packaged; flip-chip welding a plurality of preset filter chips to be packaged on a substrate to be packaged; carrying out plastic package on each filter chip to be packaged to form a plastic package layer; the filter chips to be packaged, the plastic packaging layers corresponding to the filter chips to be packaged, the isolation layers and the substrates to be packaged are respectively enclosed to form cavities; each filter chip to be packaged, the plastic packaging layer corresponding to each filter chip to be packaged, the isolation layer and the substrate to be packaged form a plastic packaging structure; and cutting the plastic package structure into a plurality of package structures. Like this, through treating that the packaging substrate is close to one side of treating the encapsulation filter chip and setting up the insulating layer, under the condition of high temperature, block volatile organic matter dielectric material and hinder the solder mask material through the insulating layer for organic matter dielectric material and hinder the solder mask material and can not adhere to and treat the encapsulation filter chip, can not cause the wave filter frequency offset, make the wave filter reliability high.
Optionally, treat that the package substrate is provided with a plurality of first pads, form the insulating layer on the predetermined package substrate of treating, include: depositing an isolation layer on the substrate to be packaged and each first bonding pad; the etching isolation layer exposes each first bonding pad.
In some embodiments, etching the insulating layer exposes each first pad, i.e., etching the insulating layer such that the insulating layer does not contact each first pad.
In some embodiments, the etching of the isolation layer exposes each first pad, i.e., the etching of the isolation layer, such that the predetermined range of each first pad is not covered by the isolation layer. Optionally, the preset range is a circle with the center of the first pad as a center and the preset length as a radius.
In some embodiments, the isolation layer is a high stability organic material such as Dry Film used in a wafer level packaging process, plastic Film material used in a filter packaging process, Polyimide used in a semiconductor process, or the like. In some embodiments, the insulating layer may also be other types of non-conductive materials. And under the condition that the isolation layer is made of a Dry Film Dry Film or Polyimide, directly patterning by adopting a photoetching process to expose the first bonding pads. And under the condition that the isolation layer is made of non-photoetching materials such as a plastic film and the like, a laser drilling process is adopted to expose the first bonding pads.
Optionally, the preset filter chips to be packaged are obtained by the following method: providing a filter wafer, wherein the filter wafer comprises a plurality of filter chips to be packaged, and each filter chip to be packaged is provided with a plurality of second bonding pads; welding salient points are respectively arranged on the second welding pads; and cutting the filter wafer to obtain a plurality of filter chips to be packaged, wherein each filter chip to be packaged is provided with a second bonding pad with a welding salient point.
In some embodiments, a filter chip to be packaged includes: the filter comprises an electrode layer, a piezoelectric layer, a to-be-packaged filter chip substrate for supporting the electrode layer and the piezoelectric layer, and a plurality of second bonding pads for connecting with a to-be-packaged substrate.
Optionally, flip-chip bonding a plurality of preset filter chips to be packaged on a substrate to be packaged includes: and flip-chip bonding each filter chip to be packaged on the substrate to be packaged through each second bonding pad and each welding salient point.
Alternatively, the flip chip bonding method is solder reflow, metal ultrasonic bonding, or conductive adhesive bonding.
In some embodiments, after each filter chip to be packaged is flip-chip bonded on the substrate to be packaged through each second bonding pad and each welding bump, each second bonding pad of each filter chip to be packaged is connected with each first bonding pad of the substrate to be packaged in a one-to-one correspondence manner through each welding bump.
Optionally, the plastic package is performed on each filter chip to be packaged to form a plastic package layer, including: applying a first plastic packaging material layer to each filter chip to be packaged, and respectively enclosing each filter chip to be packaged, the first plastic packaging material layer corresponding to each filter chip to be packaged, the isolation layer and the substrate to be packaged to form a cavity; applying a second plastic packaging material layer on one side of the first plastic packaging material layer, which is far away from each filter chip to be packaged, and forming a plastic packaging layer by the first plastic packaging material layer and the second plastic packaging material layer; and the filter chips to be packaged, the plastic packaging layers corresponding to the filter chips to be packaged, the isolation layers and the substrates to be packaged are respectively enclosed to form cavities.
In some embodiments, the first plastic packaging material layer is applied first, and then the second plastic packaging material layer is applied, and the first plastic packaging material layer adopts a plastic packaging film, and the second plastic packaging material layer adopts an epoxy resin molding compound. Therefore, the thickness of the first plastic packaging material layer does not need to be made to be 200 microns, and compared with a plastic packaging layer formed by directly adopting a thick plastic packaging film as the plastic packaging layer, the plastic packaging layer formed by the first plastic packaging material layer and the second plastic packaging material layer can reduce the cost of a manufacturing process.
Optionally, applying a second plastic packaging material layer on one side of the first plastic packaging material layer far away from each filter chip to be packaged through a plastic packaging material melting and plastic packaging process. Like this, the pad pasting is to waiting to encapsulate the filter chip surface under the vacuum environment for the first plastic envelope layer can be well along the welding treat on the packaging substrate treat the packaging filter chip the lateral wall of packaging filter chip will treat the packaging filter chip parcel, therefore can be fine by treat the packaging filter chip, treat the first plastic envelope layer, the isolation layer that the packaging filter chip corresponds and treat the packaging substrate formation cavity. And then a second plastic packaging material layer is formed through a plastic packaging material melting and plastic packaging process, so that a cavity formed by the first plastic packaging material layer, the filter chip to be packaged, the substrate to be packaged and the isolation layer in a surrounding mode is protected better.
Referring to fig. 6, an embodiment of the present invention provides a method for manufacturing a package structure, including:
step S601, forming an isolation layer on a preset substrate to be packaged;
step S602, flip-chip welding a plurality of preset filter chips to be packaged on a substrate to be packaged;
step S603, applying a first plastic packaging material layer to each filter chip to be packaged, and respectively enclosing each filter chip to be packaged, the first plastic packaging material layer corresponding to each filter chip to be packaged, an isolation layer and a substrate to be packaged to form a cavity; applying a second plastic packaging material layer on one side of the first plastic packaging material layer, which is far away from each filter chip to be packaged, and forming a plastic packaging layer by the first plastic packaging material layer and the second plastic packaging material layer; each filter chip to be packaged, the plastic packaging layer corresponding to each filter chip to be packaged, the isolation layer and the substrate to be packaged form a plastic packaging structure;
step S604, the plastic package structure is cut into a plurality of package structures.
By adopting the manufacturing method for the packaging structure provided by the embodiment of the invention, the isolation layer is formed on the preset substrate to be packaged; flip-chip welding a plurality of preset filter chips to be packaged on a substrate to be packaged; applying a first plastic packaging material layer to each filter chip to be packaged, and respectively enclosing each filter chip to be packaged, the first plastic packaging material layer corresponding to each filter chip to be packaged, the isolation layer and the substrate to be packaged to form a cavity; applying a second plastic packaging material layer on one side of the first plastic packaging material layer, which is far away from each filter chip to be packaged, and forming a plastic packaging layer by the first plastic packaging material layer and the second plastic packaging material layer; each filter chip to be packaged, the plastic packaging layer corresponding to each filter chip to be packaged, the isolation layer and the substrate to be packaged form a plastic packaging structure; and cutting the plastic package structure into a plurality of package structures. Like this, through treating that the packaging substrate is close to one side of treating the encapsulation filter chip and setting up the insulating layer, under the condition of high temperature, block volatile organic matter dielectric material and hinder the solder mask material through the insulating layer for organic matter dielectric material and hinder the solder mask material and can not adhere to and treat the encapsulation filter chip, can not cause the wave filter frequency offset, make the wave filter reliability high. Meanwhile, a first plastic package material layer is formed firstly, and then a second plastic package material layer is formed, so that a cavity formed by enclosing the first plastic package material layer, the filter chip to be packaged, the substrate to be packaged and the isolation layer is protected better.
The above description and drawings sufficiently illustrate embodiments of the invention to enable those skilled in the art to practice them. Other embodiments may incorporate structural, logical, electrical, process, and other changes. The examples merely typify possible variations. Individual components and functions are optional unless explicitly required, and the sequence of operations may vary. Portions and features of some embodiments may be included in or substituted for those of others. Furthermore, the words used in the specification are words of description only and are not intended to limit the claims. As used in the description of the embodiments and the claims, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. Similarly, the term "and/or" as used in this application is meant to encompass any and all possible combinations of one or more of the associated listed. Furthermore, the terms "comprises" and/or "comprising," when used in this application, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. Without further limitation, an element defined by the phrase "comprising an …" does not exclude the presence of other like elements in a process, method or apparatus that comprises the element. In this document, each embodiment may be described with emphasis on differences from other embodiments, and the same and similar parts between the respective embodiments may be referred to each other. For methods, products, etc. of the embodiment disclosures, reference may be made to the description of the method section for relevance if it corresponds to the method section of the embodiment disclosure.
Claims (10)
1. A package structure, comprising:
the to-be-packaged substrate is used for supporting the to-be-packaged filter chip;
the filter chip to be packaged is flip-chip welded on the substrate to be packaged;
the isolation layer is arranged on one side, close to the filter chip to be packaged, of the substrate to be packaged;
and the plastic packaging layer, the filter chip to be packaged, the substrate to be packaged and the isolation layer enclose to form a cavity.
2. The package structure of claim 1, wherein the substrate to be packaged is provided with a plurality of first pads; the filter chip to be packaged is provided with a plurality of second bonding pads; and the first bonding pads are correspondingly connected with the second bonding pads through welding bumps.
3. The package structure of claim 2, wherein a thickness of each of the solder bumps is greater than a thickness of the insulating layer.
4. The package structure of claim 2, wherein the insulating layer does not contact each of the first pads.
5. The package structure of claim 2, wherein the insulating layer covers each of the first pads and does not contact each of the solder bumps.
6. The package structure of claim 1, wherein the molding layer comprises:
the first plastic packaging material layer, the filter chip to be packaged, the substrate to be packaged and the isolation layer enclose to form a cavity;
and the second plastic packaging material layer is arranged on one side of the first plastic packaging material layer, which is far away from the filter chip to be packaged, the substrate to be packaged and the isolation layer.
7. The package structure of claim 1, further comprising a third pad disposed on a side of the substrate to be packaged away from the filter chip to be packaged.
8. The package structure according to claim 1, wherein the isolation layer is made of a dry film, a plastic-encapsulated thin-film material, or polyimide.
9. A method for fabricating a package structure, comprising:
forming an isolation layer on a preset substrate to be packaged;
flip-chip welding a plurality of preset filter chips to be packaged on the substrate to be packaged;
carrying out plastic package on each filter chip to be packaged to form a plastic package layer; the filter chips to be packaged, the plastic packaging layers corresponding to the filter chips to be packaged, the isolation layers and the substrate to be packaged are respectively enclosed to form a cavity; each filter chip to be packaged, the plastic packaging layer corresponding to each filter chip to be packaged, the isolation layer and the substrate to be packaged form a plastic packaging structure;
and cutting the plastic package structure into a plurality of package structures.
10. The method of claim 9, wherein the substrate to be packaged is provided with a plurality of first pads, and the forming of the isolation layer on the predetermined substrate to be packaged comprises:
depositing the isolation layer on the substrate to be packaged;
and etching the isolation layer to expose the first bonding pads.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115020396A (en) * | 2022-05-25 | 2022-09-06 | 杭州道铭微电子有限公司 | Chip packaging structure and packaging method |
| CN115882811A (en) * | 2023-02-09 | 2023-03-31 | 深圳新声半导体有限公司 | Surface acoustic wave filter packaging structure and preparation method thereof |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109087911A (en) * | 2018-08-10 | 2018-12-25 | 付伟 | With the multichip packaging structure and preparation method thereof for accommodating functional chip chamber |
| CN109473539A (en) * | 2018-12-14 | 2019-03-15 | 苏州科阳光电科技有限公司 | A kind of filter chip mould group and preparation method thereof |
| CN209057183U (en) * | 2018-12-20 | 2019-07-02 | 杰群电子科技（东莞）有限公司 | SAW filter and electronic product |
| CN113035855A (en) * | 2021-03-01 | 2021-06-25 | 青岛歌尔智能传感器有限公司 | Radio frequency module system-in-package structure, manufacturing method thereof and electronic equipment |
| CN113675102A (en) * | 2021-10-22 | 2021-11-19 | 深圳新声半导体有限公司 | Method for chip packaging and chip particles |
| CN113794461A (en) * | 2021-09-13 | 2021-12-14 | 江苏卓胜微电子股份有限公司 | Module chip packaging structure and circuit board |
-
2021
- 2021-12-16 CN CN202111544252.7A patent/CN114284234B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109087911A (en) * | 2018-08-10 | 2018-12-25 | 付伟 | With the multichip packaging structure and preparation method thereof for accommodating functional chip chamber |
| CN109473539A (en) * | 2018-12-14 | 2019-03-15 | 苏州科阳光电科技有限公司 | A kind of filter chip mould group and preparation method thereof |
| CN209057183U (en) * | 2018-12-20 | 2019-07-02 | 杰群电子科技（东莞）有限公司 | SAW filter and electronic product |
| CN113035855A (en) * | 2021-03-01 | 2021-06-25 | 青岛歌尔智能传感器有限公司 | Radio frequency module system-in-package structure, manufacturing method thereof and electronic equipment |
| CN113794461A (en) * | 2021-09-13 | 2021-12-14 | 江苏卓胜微电子股份有限公司 | Module chip packaging structure and circuit board |
| CN113675102A (en) * | 2021-10-22 | 2021-11-19 | 深圳新声半导体有限公司 | Method for chip packaging and chip particles |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115020396A (en) * | 2022-05-25 | 2022-09-06 | 杭州道铭微电子有限公司 | Chip packaging structure and packaging method |
| CN115882811A (en) * | 2023-02-09 | 2023-03-31 | 深圳新声半导体有限公司 | Surface acoustic wave filter packaging structure and preparation method thereof |
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| Publication number | Publication date |
|---|---|
| CN114284234B (en) | 2024-06-25 |
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