CN115020260A - Wafer defect detection method and wafer detection device - Google Patents

Wafer defect detection method and wafer detection device Download PDF

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Publication number
CN115020260A
CN115020260A CN202110246994.5A CN202110246994A CN115020260A CN 115020260 A CN115020260 A CN 115020260A CN 202110246994 A CN202110246994 A CN 202110246994A CN 115020260 A CN115020260 A CN 115020260A
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China
Prior art keywords
wafer
detected
detection
detection areas
areas
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Pending
Application number
CN202110246994.5A
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Chinese (zh)
Inventor
申相旭
曲扬
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Institute of Microelectronics of CAS
Zhenxin Beijing Semiconductor Co Ltd
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Institute of Microelectronics of CAS
Zhenxin Beijing Semiconductor Co Ltd
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Application filed by Institute of Microelectronics of CAS, Zhenxin Beijing Semiconductor Co Ltd filed Critical Institute of Microelectronics of CAS
Priority to CN202110246994.5A priority Critical patent/CN115020260A/en
Publication of CN115020260A publication Critical patent/CN115020260A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
    • H01L22/24—Optical enhancement of defects or not directly visible states, e.g. selective electrolytic deposition, bubbles in liquids, light emission, colour change
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67242—Apparatus for monitoring, sorting or marking
    • H01L21/67288—Monitoring of warpage, curvature, damage, defects or the like
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10—Measuring as part of the manufacturing process
    • H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions

Abstract

The application belongs to the technical field of semiconductors, and particularly relates to a wafer defect detection method and a wafer detection device, wherein the wafer defect detection method comprises the steps of obtaining at least four detection areas on a wafer to be detected; comparing the at least four detection areas; and determining that the wafer to be detected has defects according to the existence of different items in at least four detection areas. According to the wafer defect detection method provided by the embodiment of the invention, when the wafer to be detected is detected, the number of the detection areas is increased, and the number of the detection areas is changed from three detection areas to at least four detection areas in the prior art. By increasing the number of the detection areas, whether real defects exist in the detection areas can be accurately judged, the problem that the original design on the wafer is mistaken for the defects is avoided, the manual re-judgment time is shortened, and the accuracy of detecting the wafer to be detected is improved.

Description

Wafer defect detection method and wafer detection device
Technical Field
The application belongs to the technical field of semiconductors, and particularly relates to a wafer defect detection method and a wafer detection device.
Background
This section provides background information related to the present disclosure only and is not necessarily prior art.
The wafer is a silicon wafer used for manufacturing a silicon semiconductor integrated circuit, and is called a wafer because it has a circular shape. Various circuit element structures can be processed and fabricated on a silicon wafer to form an integrated circuit product with specific electrical functions.
In the wafer processing process, the wafer needs to be detected for multiple times to ensure the processing quality of the wafer, the problem that the wafer cannot be saved when non-surface defects appear in the process of detection after the processing is finished is avoided, the specific defective process can be found out through the multiple detection, and the yield of the wafer is improved.
In the prior art, in the detection process, three regions are selected, whether the three regions are the same or not is compared, the three regions and the other two different regions are judged as defects, and then further judgment is carried out manually. However, the defects cannot be determined to be real defects, and the original design on the wafer is mistaken for the defects, so that the manual re-judgment time is long.
Disclosure of Invention
A first aspect of the present application provides a wafer defect detection method, including:
acquiring at least four detection areas on a wafer to be detected;
comparing the at least four detection areas;
and determining that the wafer to be detected has defects according to the existence of different items in the at least four detection areas.
According to the wafer defect detection method provided by the embodiment of the application, when the wafer to be detected is detected, the number of the detection areas is increased, and the number of the detection areas is changed from three detection areas to at least four detection areas in the prior art. Through increasing the number of the detection areas, whether the detection areas have real defects or not can be accurately judged, the problem that the original design on the wafer is mistaken for the defects is avoided, the manual re-judgment time is shortened, and the accuracy of detecting the wafer to be detected is improved.
A second aspect of the present application provides a wafer inspection apparatus for performing a wafer inspection method, including:
the acquisition module is used for acquiring at least four detection areas on the wafer to be detected;
a comparison module for comparing the at least four detection regions;
and the determining module is used for determining that the wafer to be detected has defects according to the existence of different items in the at least four detection areas.
According to the wafer detection device of the embodiment, when the wafer to be detected is detected, the number of the detection areas is increased, and the number of the detection areas is changed from three to at least four in the prior art. Through increasing the number of the detection areas, whether the detection areas have real defects or not can be accurately judged, the problem that the original design on the wafer is mistaken for the defects is avoided, the manual re-judgment time is shortened, and the accuracy of detecting the wafer to be detected is improved.
Drawings
Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the application. Also, like reference numerals are used to refer to like parts throughout the drawings. In the drawings:
FIG. 1 is a flowchart illustrating a wafer defect detection method according to an embodiment of the present disclosure;
fig. 2 is a flowchart of fig. 1 for obtaining at least four detection regions on a wafer to be detected;
FIG. 3 is a schematic diagram of a wafer to be tested in a cell matrix inspection method according to an embodiment of the present disclosure;
FIG. 4 is a schematic diagram illustrating a wafer to be inspected in a random inspection mode of an exposure unit according to an embodiment of the present disclosure;
fig. 5 is a block diagram of a wafer defect detecting apparatus according to an embodiment of the present disclosure.
Detailed Description
Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
It is to be understood that the terminology used herein is for the purpose of describing particular example embodiments only, and is not intended to be limiting. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. The terms "comprises," "comprising," "including," and "having" are inclusive and therefore specify the presence of stated features, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, steps, operations, elements, components, and/or groups thereof.
Although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms may be only used to distinguish one element, component, region, layer or section from another region, layer or section. Terms such as "first," "second," and other numerical terms when used herein do not imply a sequence or order unless clearly indicated by the context. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the example embodiments.
For convenience in description, the relationship of one element or feature to another element or feature as illustrated in the figures may be described herein using spatially relative terms, such as "inner", "outer", "lower", "below", "upper", "over", and the like. This spatially relative term is intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" or "over" the other elements or features. Thus, the example term "below … …" can include both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
As shown in fig. 1, an embodiment of the present application provides a method for detecting a wafer defect, including:
acquiring at least four detection areas on a wafer to be detected;
comparing the at least four detection areas;
and determining that the wafer to be detected has defects according to the existence of different items in at least four detection areas.
According to the wafer defect detection method provided by the embodiment of the application, when the wafer to be detected is detected, the number of the detection areas is increased, and the number of the detection areas is changed from three detection areas to at least four detection areas in the prior art. Through increasing the number of the detection areas, whether the detection areas have real defects or not can be accurately judged, the problem that the original design on the wafer is mistaken for the defects is avoided, the manual re-judgment time is shortened, and the accuracy of detecting the wafer to be detected is improved.
In some embodiments of the present application, the wafer to be detected is a wafer with a processed pattern. The wafer defect detection process aims at the wafer with patterns so as to ensure the yield of finally formed semiconductor devices. Specifically, as shown in fig. 2, acquiring at least four detection area regions on a wafer to be detected includes providing the wafer to be detected; conveying the wafer to be detected to an inspection instrument; controlling an inspection tester to obtain an image of a wafer to be detected; at least four detection regions are selected from the image. The wafer to be detected can be conveyed manually, can also be conveyed automatically by a mechanical arm, and can also be conveyed automatically by arranging a conveyor belt and the like. The inspection instrument shoots images of the wafer to be detected, analyzes the images, selects at least four detection areas from the images, and determines whether the wafer to be detected has defects according to the difference of brightness, the difference of gray and dark in the images and the like.
In some embodiments of the present application, the selection of the at least four detection regions from the image is arbitrary and random, but is guaranteed to be adjacent to each other.
In some embodiments of the present application, in a processing process of forming a semiconductor device on a wafer, the wafer gradually forms a multilayer structure, and if a non-surface defect occurs after the processing is completed and then the inspection is performed, a problem that the wafer cannot be saved may be caused. Wafer defect detection can be performed after each process, or wafer defect detection can be performed in a key process, namely, a process in which defects occur after the current process is completed and the quality of the wafer and the semiconductor device is greatly affected, so that specific processes with problems can be found out, and the yield of the wafer is improved.
In some embodiments of the present application, the number of detection zones may be the same for different processes, reducing the alteration of detection parameters of the detector. The detection areas can be set to be different according to specific procedures, and the number of the detection areas is selected to be proper, so that the defect detection errors are further reduced, and the defect detection accuracy is improved.
In some embodiments of the present application, the wafer defect detection method may be performed in a bright field detection mode after the wafer to be detected is cleaned and then inspected, or may also be performed in a dark field detection mode after the wafer to be detected is chemically and mechanically planarized, and the wafer defect detection method provided in the embodiments of the present application can improve the accuracy of defect detection regardless of the detection mode.
In some embodiments of the present application, the target for wafer defect detection is different, and may be detection between cells (cells) of a wafer, and for detection between cells, a matrix detection method is usually adopted, and at least four detection areas arranged in a matrix and adjacent to each other left and right or up and down are selected for detection. In the prior art, three adjacent detection areas are randomly selected, whether the three detection areas are the same or not is compared, and when one detection area is different from the other two detection areas, the different detection area is considered as a defect and is further judged by a test engineer. As shown in fig. 3, according to the wafer defect detection method provided by the embodiment of the present application, at least four adjacent detection areas are randomly selected, in one embodiment, fourteen detection areas are selected, and whether a wafer has a defect is determined by the fourteen detection areas, so that a detection error caused by the design of the wafer itself is eliminated, the labor investment is reduced, and the detection accuracy is improved. The object can be the exposure unit (block) of the wafer and the detection of the exposure unit, and for the detection between the exposure unit and the exposure unit, at least four detection areas which are adjacent to each other at the left and right or up and down are randomly selected to carry out the detection when random detection is issued. For example, in the prior art, three adjacent detection areas are randomly selected, whether the three detection areas are the same or not is compared, and when one of the three detection areas is different from the other two detection areas, the different detection area is determined as a defect and is submitted to a test engineer for further judgment. As shown in fig. 4, according to the wafer defect detection method provided by the embodiment of the present application, at least four adjacent detection areas are randomly selected, in one embodiment, sixteen detection areas are selected, and whether a wafer has a defect is determined by the sixteen detection areas, so that a detection error caused by the design of the wafer itself is eliminated, the labor investment is reduced, and the detection accuracy is improved. The object can also be the detection of the outer circumference of the wafer, and four detection areas adjacent to the outer circumference in the left and right or up and down are randomly selected for detection.
As shown in fig. 5, an embodiment of the present application further provides a wafer inspection apparatus, which is configured to perform the wafer inspection method of the foregoing embodiment, and includes:
the acquisition module is used for acquiring at least four detection areas on the wafer to be detected;
the comparison module is used for comparing at least four detection areas;
and the determining module is used for determining that the wafer to be detected has defects according to the existence of different items in the at least four detection areas.
According to the wafer detection device of the embodiment, when the wafer to be detected is detected, the number of the detection areas is increased, and the number of the detection areas is changed from three to at least four in the prior art. Through increasing the number of the detection areas, whether the detection areas have real defects or not can be accurately judged, the problem that the original design on the wafer is mistaken for the defects is avoided, the manual re-judgment time is shortened, and the accuracy of detecting the wafer to be detected is improved.
The above description is only for the preferred embodiment of the present application, but the scope of the present application is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present application should be covered within the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims (10)

1. A wafer defect detection method, comprising:
acquiring at least four detection areas on a wafer to be detected;
comparing the at least four detection regions;
and determining that the wafer to be detected has defects according to the existence of different items in the at least four detection areas.
2. The wafer defect detection method of claim 1, wherein the acquiring at least four detection areas on the wafer to be detected comprises:
providing the wafer to be detected;
conveying the wafer to be detected to an inspection instrument;
controlling the inspection instrument to acquire an image of the wafer to be detected;
selecting the at least four detection regions from the image.
3. The wafer defect detecting method as claimed in claim 2, wherein the at least four detection areas are arbitrarily acquired in the selecting of the at least four detection areas from the image, and the at least four detection areas are adjacent to each other.
4. The wafer defect detection method as claimed in claim 1, wherein the wafer defect detection method is performed after any process from the activation step of the wafer to be detected to the chemical mechanical planarization process of the back end of the production line process.
5. The wafer defect detecting method according to claim 4, wherein the number of the detecting areas is different for different processes.
6. The wafer defect detecting method according to claim 1, wherein the wafer defect detecting method is performed in a bright field detection mode after the wafer to be detected is cleaned and inspected and a dark field detection mode after the wafer to be detected is chemically and mechanically planarized.
7. The wafer defect detecting method as claimed in claim 1, wherein the wafer defect detecting method is performed in a matrix detecting manner used in the wafer detecting unit to be detected.
8. The wafer defect detecting method as claimed in claim 1, wherein the wafer defect detecting method is performed in a random detecting manner used when the wafer to be detected detects the outer circumference.
9. The wafer defect detecting method as claimed in claim 1, wherein the wafer defect detecting method is performed in a random detecting manner used when the wafer to be detected detects the exposure unit.
10. A wafer inspecting apparatus for performing the wafer inspecting method according to any one of claims 1 to 9, comprising:
the acquisition module is used for acquiring at least four detection areas on the wafer to be detected;
a comparison module for comparing the at least four detection regions;
and the determining module is used for determining that the wafer to be detected has defects according to the existence of different items in the at least four detection areas.
CN202110246994.5A 2021-03-05 2021-03-05 Wafer defect detection method and wafer detection device Pending CN115020260A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202110246994.5A CN115020260A (en) 2021-03-05 2021-03-05 Wafer defect detection method and wafer detection device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202110246994.5A CN115020260A (en) 2021-03-05 2021-03-05 Wafer defect detection method and wafer detection device

Publications (1)

Publication Number Publication Date
CN115020260A true CN115020260A (en) 2022-09-06

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
CN202110246994.5A Pending CN115020260A (en) 2021-03-05 2021-03-05 Wafer defect detection method and wafer detection device

Country Status (1)

Country Link
CN (1) CN115020260A (en)

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