CN115017846A - Interface-based time sequence repairing method, equipment and medium - Google Patents
Interface-based time sequence repairing method, equipment and medium Download PDFInfo
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- CN115017846A CN115017846A CN202210828773.3A CN202210828773A CN115017846A CN 115017846 A CN115017846 A CN 115017846A CN 202210828773 A CN202210828773 A CN 202210828773A CN 115017846 A CN115017846 A CN 115017846A
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Abstract
The application provides a time sequence repairing method, equipment and medium based on an interface, and relates to the technical field of chips. The method comprises the following steps: acquiring an interface path establishment timing violation report of a target integrated circuit based on an initial interface constraint condition; establishing a time sequence violation report according to the interface path, acquiring a target path group corresponding to a target clock domain in a target integrated circuit, and dividing the target integrated circuit into a plurality of path groups according to the clock domain; updating the initial interface constraint condition according to the target path group to obtain a target interface constraint condition; the driving parameters of the logic unit and/or the logic unit in the target clock domain in the target integrated circuit are adjusted by adopting a preset layout wiring tool and a target interface constraint condition, so that the data path corresponding to the target clock domain meets the preset time sequence requirement, the data path in the target integrated circuit can be adjusted from the dimensionality of the clock domain by combining the target interface constraint condition, and the time sequence repair capability can be improved.
Description
Technical Field
The present application relates to the field of chip technologies, and in particular, to a method, an apparatus, and a medium for repairing a timing sequence based on an interface.
Background
In the design process of an integrated circuit chip, timing problems are one of the most concerned problems, and the designed chip is required to have a good timing convergence effect from the viewpoint of performance and stability. Particularly, in the back-end design of an integrated circuit, how to reasonably utilize limited resources to complete timing convergence and consider power consumption and area is a challenging matter.
In the prior art, the timing sequence inside each module in the chip is mainly optimized to enable the chip to have the timing sequence convergence effect.
However, the existing time sequence repairing method is single, so that the repairing capability is limited.
Disclosure of Invention
An object of the present application is to provide a method, an apparatus, and a medium for repairing a timing sequence based on an interface, which can improve the capability of repairing the timing sequence.
In order to achieve the above purpose, the technical solutions adopted in the embodiments of the present application are as follows:
in a first aspect, the present invention provides a method for repairing a timing sequence based on an interface, including:
acquiring an interface path establishment timing violation report of a target integrated circuit based on an initial interface constraint condition, wherein the target integrated circuit comprises a plurality of logic units;
establishing a time sequence violation report according to the interface path, and acquiring a target path group corresponding to a target clock domain in the target integrated circuit, wherein the target path group comprises at least one data path, and the target integrated circuit is divided into a plurality of path groups according to the clock domain;
updating the initial interface constraint condition according to the target path group to obtain a target interface constraint condition;
and adjusting the logic unit and/or the driving parameter of the logic unit in the target clock domain in the target integrated circuit by adopting a preset layout and wiring tool and the target interface constraint condition so as to enable the data path corresponding to the target clock domain to meet the preset time sequence requirement.
In an optional embodiment, the updating the initial interface constraint condition according to the target path group to obtain a target interface constraint condition includes:
dividing a plurality of target path groups into a critical path group and a non-critical path group based on violation thresholds corresponding to the target clock domains;
and updating the initial interface constraint condition according to the critical path group and the non-critical path group, and respectively acquiring a first target interface constraint condition corresponding to the critical path group and a second target interface constraint condition corresponding to the non-critical path group.
In an optional implementation manner, the dividing the plurality of target path groups into a critical path group and a non-critical path group based on the violation threshold corresponding to the target clock domain includes:
acquiring a time sequence violation value of each target path group;
calculating a difference between each of the timing violation values and the violation threshold;
and determining a critical path group and a non-critical path group in the plurality of target path groups according to each difference value.
In an alternative embodiment, the method further comprises:
respectively setting a first optimization weight of the critical path group and a second optimization weight of the non-critical path group according to a preset weight setting rule, wherein the first optimization weight is higher than the second optimization weight;
the adjusting, by using a preset layout and routing tool and the target interface constraint condition, the driving parameters of the logic unit and/or the logic unit in the target clock domain in the target integrated circuit includes:
based on the first optimization weight, inputting the first target interface constraint condition into the preset layout and wiring tool, and adjusting the first logic unit corresponding to the critical path group and/or the driving parameter of the first logic unit;
and inputting the second target interface constraint condition into the preset layout and wiring tool based on the second optimization weight, and adjusting the driving parameters of the second logic unit and/or the second logic unit corresponding to the non-critical path group.
In an optional embodiment, the updating the initial interface constraint condition according to the target path group to obtain a target interface constraint condition includes:
updating the constraint coefficient corresponding to the target clock domain according to the key path group corresponding to the target clock domain;
and acquiring a target interface constraint condition according to the updated constraint coefficient and clock period corresponding to the target clock domain.
In an optional embodiment, the updating, according to the critical path group corresponding to the target clock domain, the constraint coefficient corresponding to the target clock domain includes;
establishing a time sequence violation report according to the interface path, and respectively acquiring the path delay and the time sequence violation value of the key path group;
and updating the constraint coefficient corresponding to the target clock domain according to the path delay of the key path group, the time sequence violation value and the clock cycle corresponding to the target clock domain, and acquiring the updated constraint coefficient.
In an alternative embodiment, the method further comprises:
and updating the violation threshold corresponding to the target clock domain according to the target interface constraint condition, the clock cycle corresponding to the target clock domain and the path logic level corresponding to the key path group, and acquiring the updated violation threshold.
In an alternative embodiment, the path group comprises: a group of input paths and/or a group of output paths;
the driving parameters of the logic unit comprise at least one of the following: the type number of the logic units, the number of the logic units and the level of the routing metal layer corresponding to the logic units.
In a second aspect, the present invention provides an interface-based timing recovery apparatus, including:
a first obtaining module, configured to obtain an interface path establishment timing violation report of a target integrated circuit based on an initial interface constraint condition, where the target integrated circuit includes a plurality of logic units;
a second obtaining module, configured to establish a timing violation report according to the interface path, and obtain a target path group corresponding to a target clock domain in the target integrated circuit, where the target path group includes at least one data path, and the target integrated circuit is divided into multiple path groups according to the clock domain;
the updating module is used for updating the initial interface constraint condition according to the target path group to obtain a target interface constraint condition;
and the adjusting module is used for adjusting the logic unit and/or the driving parameter of the logic unit in the target clock domain in the target integrated circuit by adopting a preset layout and wiring tool and the target interface constraint condition so as to enable the data path corresponding to the target clock domain to meet the preset time sequence requirement.
In an optional implementation manner, the update module is specifically configured to divide the plurality of target path groups into a critical path group and a non-critical path group based on a violation threshold corresponding to the target clock domain;
and updating the initial interface constraint condition according to the critical path group and the non-critical path group, and respectively acquiring a first target interface constraint condition corresponding to the critical path group and a second target interface constraint condition corresponding to the non-critical path group.
In an optional implementation manner, the update module is specifically configured to obtain a timing violation value of each target path group;
calculating a difference between each of the timing violation values and the violation threshold;
and determining a critical path group and a non-critical path group in the plurality of target path groups according to each difference value.
In an optional embodiment, the updating module is further configured to set a first optimization weight of the critical path group and a second optimization weight of the non-critical path group according to a preset weight setting rule, respectively, where the first optimization weight is higher than the second optimization weight;
the adjusting, by using a preset layout and routing tool and the target interface constraint condition, the driving parameters of the logic unit and/or the logic unit in the target clock domain in the target integrated circuit includes:
based on the first optimization weight, inputting the first target interface constraint condition into the preset layout and wiring tool, and adjusting the first logic unit corresponding to the critical path group and/or the driving parameter of the first logic unit;
and inputting the second target interface constraint condition into the preset layout and wiring tool based on the second optimization weight, and adjusting the driving parameters of the second logic unit and/or the second logic unit corresponding to the non-critical path group.
In an optional embodiment, the updating module is specifically configured to update a constraint coefficient corresponding to the target clock domain according to the critical path group corresponding to the target clock domain;
and acquiring a target interface constraint condition according to the updated constraint coefficient and clock period corresponding to the target clock domain.
In an optional implementation manner, the update module is specifically configured to establish a timing violation report according to the interface path, and respectively obtain the path delay and the timing violation value of the critical path group;
and updating the constraint coefficient corresponding to the target clock domain according to the path delay of the key path group, the time sequence violation value and the clock cycle corresponding to the target clock domain, and acquiring the updated constraint coefficient.
In an optional implementation manner, the updating module is further configured to update the violation threshold corresponding to the target clock domain according to the target interface constraint condition, the clock cycle corresponding to the target clock domain, and the path logic level corresponding to the critical path group, and obtain the updated violation threshold.
In an alternative embodiment, the path group comprises: a group of input paths and/or a group of output paths;
the driving parameters of the logic unit comprise at least one of the following: the type of the logic unit, the number of the logic units and the level of the routing metal layer corresponding to the logic unit.
In a third aspect, the present invention provides an electronic device comprising: the timing recovery device comprises a processor, a storage medium and a bus, wherein the storage medium stores machine-readable instructions executable by the processor, when an electronic device runs, the processor and the storage medium communicate through the bus, and the processor executes the machine-readable instructions to execute the steps of the interface-based timing recovery method according to any one of the preceding embodiments.
In a fourth aspect, the present invention provides a computer-readable storage medium, having a computer program stored thereon, where the computer program is executed by a processor to perform the steps of the interface-based timing recovery method according to any one of the preceding embodiments.
The beneficial effect of this application is:
in the interface-based timing recovery method, device, and medium provided in the embodiments of the present application, an interface path establishment timing violation report of a target integrated circuit is obtained based on an initial interface constraint condition, where the target integrated circuit includes a plurality of logic units; establishing a time sequence violation report according to an interface path, and acquiring a target path group corresponding to a target clock domain in a target integrated circuit, wherein the target path group comprises at least one data path, and the target integrated circuit is divided into a plurality of path groups according to the clock domain; updating the initial interface constraint condition according to the target path group to obtain a target interface constraint condition; the method adopts a preset layout and wiring tool and a target interface constraint condition to adjust the logic unit and/or the driving parameter of the logic unit in the target clock domain in the target integrated circuit, so that the data path corresponding to the target clock domain meets the preset time sequence requirement, the data path in the target integrated circuit can be adjusted from the dimensionality of the clock domain by combining the target interface constraint condition, compared with the prior art, another time sequence repairing way is provided, and the time sequence repairing capability can be improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are required to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained from the drawings without inventive effort.
Fig. 1 is a schematic flowchart of a timing recovery method based on an interface according to an embodiment of the present disclosure;
fig. 2 is a schematic flowchart of another interface-based timing recovery method according to an embodiment of the present disclosure;
FIG. 3 is a schematic diagram of an input data path according to an embodiment of the present disclosure;
FIG. 3 (a) is a schematic diagram of an input data path before adjustment according to an embodiment of the present application;
FIG. 3 (b) is a schematic diagram of an adjusted input data path according to an embodiment of the present application;
fig. 4 is a schematic flowchart of another method for repairing a timing sequence based on an interface according to an embodiment of the present application;
fig. 5 is a schematic flowchart of another interface-based timing recovery method according to an embodiment of the present disclosure;
fig. 6 is a schematic flowchart of another method for repairing a timing sequence based on an interface according to an embodiment of the present application;
fig. 7 is a schematic flowchart of another interface-based timing recovery method according to an embodiment of the present disclosure;
fig. 8 is a functional block diagram of an interface-based timing recovery apparatus according to an embodiment of the present disclosure;
fig. 9 is a schematic structural diagram of an electronic device according to an embodiment of the present application.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. The components of the embodiments of the present application, generally described and illustrated in the figures herein, can be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the present application, presented in the accompanying drawings, is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.
In the prior art, in the design process of an integrated circuit chip, the chip has a timing convergence effect by mainly optimizing the timing inside each module in the chip. It can be seen that the existing timing recovery method is relatively single, and therefore, the timing recovery capability is relatively limited.
In view of this, embodiments of the present application provide a timing recovery method based on an interface, and the timing recovery method can improve timing recovery capability.
Fig. 1 is a flowchart illustrating a method for repairing a timing sequence based on an interface according to an embodiment of the present disclosure, where an execution subject of the method may be an electronic device with computing processing capability, such as a server, a computer, a desktop computer, and the like. As shown in fig. 1, the method may include:
s101, acquiring an interface path establishment timing violation report of the target integrated circuit based on the initial interface constraint condition.
Wherein the target integrated circuit comprises a plurality of logic cells, which may comprise basic logic gates in sequential circuits, such as: and gate, or gate, not gate, etc., and may further include a buffer (buffer), a register, etc., which are not limited herein.
The initial interface constraint condition is used for representing initial delay corresponding to each interface path in the target integrated circuit, and optionally, the interface path establishment timing violation report of the target integrated circuit can be acquired through a static timing analysis tool based on the initial interface constraint condition.
In some embodiments, the obtained interface path establishment timing violation report may include: the starting point and the end point of each data path violating the time sequence, the unit delay of all passing points, the line delay, the initial interface constraint value required in the initial interface constraint condition, that is, the initial interface delay constraint, the actual delay of each data path, the calculated time sequence violation value, and the like, are not limited herein.
And S102, establishing a time sequence violation report according to the interface path, and acquiring a target path group corresponding to a target clock domain in the target integrated circuit.
The target path group comprises at least one data path, the target integrated circuit is divided into a plurality of path groups according to a clock domain, and the clock domain is also an area controlled by the same clock signal. Based on the definition of the clock domain, the target integrated circuit may be divided into a plurality of path groups according to the clock signal, for example, the target integrated circuit may be divided into n path groups of G1, G2, …, Gn, etc. according to the clock signal, where n is an integer greater than 0.
Alternatively, the target clock domain may be a region controlled by a target clock signal of a plurality of clock signals corresponding to the target integrated circuit, wherein the target clock signal may be any one of the plurality of clock signals. In some embodiments, a clock signal to which each data path in the target integrated circuit belongs may be determined according to the interface path setup timing violation report, and a target path group corresponding to the target clock domain may be determined according to the clock signal to which each data path belongs and the target clock signal, where the target path group may include at least one data path.
S103, updating the initial interface constraint conditions according to the target path group to obtain target interface constraint conditions.
In some embodiments, because the target path group is obtained based on the initial interface constraint condition, that is, the target path group strongly depends on the setting of the initial interface constraint condition, an improper setting of the initial interface constraint condition will cause the target path group to include a data path with too loose constraint or too tight constraint, where the data path with too loose constraint, that is, the path delay of the data path is large, and the corresponding timing violation value is small; and (3) a data path with too strict constraint, namely the path delay of the data path is smaller, and the corresponding time sequence violation value is larger.
Based on the above description, it can be seen that it is necessary to update the initial interface constraint condition according to the delay condition of each data path in the target path group and the corresponding time sequence violation value, so as to obtain the target interface constraint condition.
And S104, adjusting the logic unit and/or the driving parameter of the logic unit in the target clock domain in the target integrated circuit by adopting a preset layout and wiring tool and a target interface constraint condition so as to enable the data path corresponding to the target clock domain to meet the preset time sequence requirement.
Alternatively, the preset place and route tool may be an Electronic Design Automation (EDA) tool, which is not limited herein.
In some embodiments, the obtained target interface constraints may be input into a pre-set place and route tool, logic cells and/or driving parameters of logic cells in a target clock domain in a target integrated circuit are adjusted by the place and route tool, by adjusting, the data path corresponding to the target clock domain can meet the preset time sequence requirement, that is, each data path in the target path group can meet the preset time sequence requirement, thereby avoiding that part of data paths are too loosely or too tightly constrained, realizing that the initial interface constraint condition can be updated from the dimension of the clock domain, setting different target interface constraint conditions for different clock domains, when the data path in the target integrated circuit is adjusted by combining the constraint condition of the target interface, compared with the prior art, another time sequence repairing way is provided, and the time sequence repairing capability can be improved.
In addition, compared with a method for optimizing the whole target integrated circuit by adopting a uniform constraint condition in the prior art, the method and the device for optimizing the target integrated circuit can realize accurate optimization from the dimension of a clock domain, and improve the optimization effect.
It should be noted that the adjustment may be batch adjustment, for example, the drive parameters of a plurality of logic units in a target clock domain in a target integrated circuit may be adjusted together, so that the repair efficiency of the timing repair method may be improved; of course, the process of adjusting the logic unit and/or the driving parameter of the logic unit in the target clock domain in the target integrated circuit may also be iterative adjustment, that is, multiple adjustments may be performed, which is not limited herein.
It should be noted that, during the adjustment process, the logic unit in the target clock domain in the target integrated circuit may be replaced, or the driving parameter of the logic unit may be adjusted, where the driving parameter of the logic unit may represent the driving capability of the logic unit, that is, the purpose of adjusting the driving capability of the logic unit may be achieved by adjusting the driving parameter of the logic unit.
In summary, an embodiment of the present application provides a method for repairing a timing sequence based on an interface, where the method includes: acquiring an interface path establishment timing violation report of a target integrated circuit based on an initial interface constraint condition, wherein the target integrated circuit comprises a plurality of logic units; establishing a time sequence violation report according to an interface path, and acquiring a target path group corresponding to a target clock domain in a target integrated circuit, wherein the target path group comprises at least one data path, and the target integrated circuit is divided into a plurality of path groups according to the clock domain; updating the initial interface constraint condition according to the target path group to obtain a target interface constraint condition; the method and the device adopt a preset layout and wiring tool and a target interface constraint condition to adjust the logic unit and/or the driving parameter of the logic unit in a target clock domain in the target integrated circuit so as to enable a data path corresponding to the target clock domain to meet a preset time sequence requirement.
Fig. 2 is a schematic flowchart of another interface-based timing recovery method according to an embodiment of the present disclosure. Optionally, as shown in fig. 2, the updating the initial interface constraint condition according to the target path group to obtain the target interface constraint condition includes:
s201, dividing a plurality of target path groups into a critical path group and a non-critical path group based on violation thresholds corresponding to target clock domains.
Optionally, the violation threshold corresponding to the target clock domain may be a default value, or may be predefined by the user according to the timing recovery experience, which is not limited herein.
According to the violation threshold, a plurality of target path groups corresponding to the target clock domain may be divided into a critical path group and a non-critical path group, where the critical path group may be a loosely constrained path group, the critical path group may include at least one critical data path, and the non-critical path group may be a tightly constrained path group, and the critical path group may include at least one critical data path.
Of course, the number of critical data paths in the critical path group and the number of non-critical data paths in the non-critical path group are not limited in this embodiment, and may be different according to the actual application scenario.
S202, updating the initial interface constraint condition according to the critical path group and the non-critical path group, and respectively obtaining a first target interface constraint condition corresponding to the critical path group and a second target interface constraint condition corresponding to the non-critical path group.
For the critical path group, the initial interface constraint condition may be updated according to the path delay of each critical data path in the critical path group and the time sequence violation value corresponding to the critical path group, so as to obtain a first target interface constraint condition corresponding to the critical path group. For the non-critical path group, the initial interface constraint condition may be updated according to the path delay of each non-critical data path in the non-critical path group and the time sequence violation value corresponding to the non-critical path group, so as to obtain a second target interface constraint condition corresponding to the non-critical path group.
Based on the above description, that is, the critical path group and the non-critical path group may be optimized in different situations to obtain respective corresponding target interface constraint conditions, so that the critical path data may be optimized heavily according to the first target interface constraint condition, the timing recovery effect is improved, the wiring resources in the area where the non-critical data path is located may be released according to the second target interface constraint condition, and the convergence of the interface timing is accelerated.
Fig. 3 is a schematic diagram of an input data path according to an embodiment of the present disclosure. In some embodiments, the path group may include: the input path group and/or the output path group, that is, each path group may include an input path group and/or an output path group, and optionally, the input path group may be represented as: in2Gi (i =0, 1, 2, …, n), the group of output paths may be represented as: gj2out (j =0, 1, 2, …, n), where i denotes the identity of the input data path and j denotes the identity of the output data path. Referring to fig. 3 (a), an input data path refers to a path of a clock signal from a Flip-Flop (FF) 11 to a destination port 14 through a multi-stage combinational logic 12 and a first buffer 13; otherwise, it is the output data path.
The description is made in conjunction with the above-mentioned critical path group and non-critical path group, that is, the critical path group may be further divided into a critical input path group in2Gk and/or a critical output path group Gh2out, and the non-critical path group may be further divided into a non-critical input path group in2Gm and/or a non-critical output path group Gn2 out. For example, the critical input path group and the critical output path group are taken as an example for explanation, the critical input path group may include at least one critical input data path, and the critical output path group may include at least one critical output data path.
Based on the above description, the key path group is taken as an example for further description, in some embodiments, different target interface constraint conditions may also be set for the key input path group and the key output path group for the key path group, that is, the initial interface constraint condition may be updated according to the key input path group and the key output path group, and a third target interface constraint condition corresponding to the key input path group and a fourth target interface constraint condition corresponding to the key output path group are obtained respectively, so that the key path group may be optimized more accurately in combination with the flow direction of the data path in the dimension of the clock domain, and the time sequence repairing effect may be further improved.
Fig. 4 is a schematic flowchart of another interface-based timing recovery method according to an embodiment of the present disclosure. Optionally, as shown in fig. 4, dividing a plurality of target path groups into a critical path group and a non-critical path group based on a violation threshold corresponding to a target clock domain includes:
s301, acquiring a time sequence violation value of each target path group.
S302, calculating the difference value between each time sequence violation value and the violation threshold value.
S303, determining a critical path group and a non-critical path group in the plurality of target path groups according to the difference values.
The time sequence violation value of the target path group is the difference between the actual delay time and the preset delay time of the target path group; the violation threshold corresponding to the target clock domain may be a preset timing violation threshold.
In some embodiments, after the timing violation value of each target path group is obtained, a difference between each timing violation value and a violation threshold may be calculated, and if a certain timing violation value is greater than the violation threshold, the target path group corresponding to the timing violation value may be determined to be a path group with too loose constraint and regarded as a critical path group; otherwise, if the time sequence violation value is smaller than the violation threshold, the target path group corresponding to the time sequence violation value can be determined as a too-constrained path group, and the target path group is regarded as a non-critical path group.
Optionally, the method further includes:
and respectively setting a first optimization weight of the critical path group and a second optimization weight of the non-critical path group according to a preset weight setting rule, wherein the first optimization weight is higher than the second optimization weight. Optionally, the preset weight setting rule may indicate that the non-critical path group and the critical path group need to be set to different optimization weights, and the optimization weight of the critical path group needs to be higher than that of the non-critical path group, and based on the setting rule, the above settings may be made for the non-critical path group and the critical path group. The first optimization weight may be denoted as "high", and the second optimization weight may be denoted as "low".
Fig. 5 is a flowchart illustrating another interface-based timing recovery method according to an embodiment of the present disclosure. Optionally, as shown in fig. 5, the adjusting the logic unit and/or the driving parameter of the logic unit in the target clock domain in the target integrated circuit by using the preset place and route tool and the target interface constraint condition includes:
s401, based on the first optimization weight, inputting the first target interface constraint condition into a preset layout and wiring tool, and adjusting the first logic unit corresponding to the critical path group and/or the driving parameters of the first logic unit.
As can be seen from the foregoing description, the critical path group is a path group with too loose constraint, and optionally, when performing adjustment, the first target interface constraint condition may be input to a preset layout and routing tool based on the first optimization weight, and the driving parameters of the first logic unit and/or the first logic unit corresponding to the critical path group are preferentially adjusted, so that the data paths in the critical path group may be optimized through adjustment, and the data paths in the critical path group may meet the preset timing requirement.
S402, inputting the second target interface constraint condition into a preset layout and wiring tool based on the second optimization weight, and adjusting the driving parameters of the second logic unit and/or the second logic unit corresponding to the non-critical path group.
The non-critical path group is a path group with too strict constraint, wherein, for the non-critical path group, because the non-critical path group has a certain optimization space, in the adjustment process, the constraint condition of the second target interface can be input into a preset layout and wiring tool, and the driving parameters of the second logic unit and/or the second logic unit corresponding to the non-critical path group are adjusted, so that the wiring resources of the area where the non-critical path group is located can be released to a certain extent through adjustment, and the convergence of the interface timing sequence is accelerated.
It should be noted that, for the critical path group and the non-critical path group, the number of times of adjustment is not limited in the embodiment of the present application, that is, iterative adjustment may be performed. In addition, it should be further noted that, according to an actual application scenario, the embodiment of the present application does not limit the sequence between step S401 and step S402, and according to the actual application scenario, step S401 may be executed first and then step S402 is executed, or step S402 may be executed first and then step S401 is executed.
In some embodiments, when performing timing optimization, the first optimization may be performed in combination with step S401 and step S402, and of course, the optimization timing of step S401 and step S402 is not limited herein.
Fig. 6 is a schematic flowchart of another interface-based timing recovery method according to an embodiment of the present disclosure. Optionally, as shown in fig. 6, the updating the initial interface constraint condition according to the target path group to obtain the target interface constraint condition includes:
s501, updating the constraint coefficient corresponding to the target clock domain according to the key path group corresponding to the target clock domain.
And S502, acquiring a target interface constraint condition according to the updated constraint coefficient and clock period corresponding to the target clock domain.
Optionally, the updated constraint coefficient corresponding to the target clock domain may be obtained by establishing a timing violation report through the interface path; in some embodiments, the initial interface constraints may include initial interface constraint values, and the target interface constraints may include target interface constraint values, which may characterize target latencies for respective interface paths in the target integrated circuit.
After the updated constraint coefficient is determined, a target interface constraint value is calculated according to the updated constraint coefficient and the clock period. In some embodiments, the target interface constraint value may be expressed as: target interface constraint value = updated constraint coefficient × clock cycle corresponding to the target clock domain, and of course, the calculation mode of the target interface constraint value is not limited to this, and may be flexibly adjusted according to the actual application scenario.
Fig. 7 is a flowchart illustrating another interface-based timing recovery method according to an embodiment of the present disclosure. Optionally, as shown in fig. 7, the updating the constraint coefficient corresponding to the target clock domain according to the critical path group corresponding to the target clock domain includes;
s601, establishing a time sequence violation report according to the interface path, and respectively acquiring the path delay and the time sequence violation value of the key path group.
S602, updating the constraint coefficient corresponding to the target clock domain according to the path delay of the key path group, the time sequence violation value and the clock cycle corresponding to the target clock domain, and acquiring the updated constraint coefficient.
In some embodiments, when the constraint coefficient corresponding to the target clock domain is updated, the constraint coefficient may be updated according to a magnitude relationship between a clock cycle corresponding to the target clock domain and a path delay of the critical path group, and a magnitude relationship between a clock cycle corresponding to the target clock domain and a timing violation value of the critical path group. The path delay and the timing violation value of the critical path group can be obtained by establishing a timing violation report query through the interface path.
Optionally, the updating may be performed according to an updating rule that the clock period corresponding to the target clock domain is T, the path delay of the critical path group is D delay, and the timing violation value of the critical path group is slack, if the target clock domain corresponds to the clock period T, the critical path group corresponds to the path delay D delay, and the timing violation value of the critical path group is slack, then if the target clock domain corresponds to the clock period T, the critical path group corresponds to the path delay D delay, and the timing violation value of the critical path group corresponds to the timing violation value of the critical path group is slack, the target clock domain is updated according to the updating rule
And is
If the delay D delay of the critical path group is greater, the set value of the timing violation slack of the critical path group is smaller, and in this case, the constraint coefficient corresponding to the target clock domain may be increased; if it is
And is
If the delay D delay of the critical path group is smaller, the set value of the timing violation slack of the critical path group is larger, and in this case, the constraint coefficient corresponding to the target clock domain may be reduced.
It should be noted that, the magnitude of each increase or decrease of the constraint coefficient is not limited in the present application, and may be increased or decreased by 0.1, 0.2, 0.5, etc. according to an actual application scenario, which is not limited herein. If the constraint coefficient corresponding to the target clock domain is increased by 0.1, it can be seen from the foregoing description that, at this time, the constraint value of the target interface (specifically, the input port delay constraint value or the output port delay constraint value) is increased by 10% of the clock cycle, and conversely, if the constraint coefficient corresponding to the target clock domain is decreased by 0.1, the constraint value of the target interface is decreased by 10% of the clock cycle.
In addition, it should be noted that if slope < - (T × 10%) and D delay > T × 60%, it is indicated that the path delay D delay of the critical path group is large, and the set timing violation value slack of the critical path group is large, it is understood that, in this case, the optimization strength for further optimization is relatively small by adjusting the constraint coefficient corresponding to the target clock domain, and optionally, the optimization weight of the path may be increased, for example, the optimization weight of the path may be adjusted to "high", so that the path may be further optimized by another optimization method in the optimization process, for example, the driving parameters of the logic units in the critical path group may be adjusted to achieve the purpose of further optimization.
Optionally, the driving parameters of the logic unit include at least one of: the type of the logic unit, the number of the logic units and the level of the routing metal layer corresponding to the logic unit.
By combining the description of the driving parameters of the logic units, the model and the number of the logic units corresponding to the target clock domain in the target integrated circuit and the corresponding levels of the routing metal layer can be replaced during adjustment, so as to achieve the purpose of adjusting the driving capability of the logic units.
For example, in the adjustment process, the type a logic unit may be adjusted to a type B logic unit with a larger driving capability, so as to reduce the unit delay; or, the logic unit disposed in the trace metal layer M1 may be adjusted to the trace metal layer M2, where the level of the trace metal layer M2 is higher than the level of the trace metal layer M2; still alternatively, the number of logic units may be reduced, as described with reference to fig. 3 (b), optionally, before the adjustment, the input data path may include 5 first buffers 13, and after the adjustment, the input data path may include 3 second buffers 15, where the driving capability of the second buffers may be greater than that of the first buffers, and of course, the specific adjustment manner is not limited to that shown in fig. 3 (b), and may be different according to the actual application scenario.
It should be noted that, according to the actual application scenario, the adjustment may be performed based on one or more driving parameters, and is not limited herein.
Optionally, the method further includes: and updating the violation threshold corresponding to the target clock domain according to the target interface constraint condition, the clock period corresponding to the target clock domain and the path logic level corresponding to the key path group, and acquiring the updated violation threshold.
The clock uncertainty of the clock signal corresponding to the target clock domain can represent the deviation of the actual arrival time of the clock edge corresponding to the target clock domain relative to the ideal arrival time; the data path logic level corresponding to the critical path group refers to the number of logic units existing on the data path in the critical path group. Furthermore, as can be seen from the foregoing description, the target interface constraints may include: an input port delay constraint value and/or an input port delay constraint value.
In some embodiments, if the target path group includes: the critical path group and the non-critical path group, which is described by taking the critical path group as an example, the critical path group may include: a critical input path group and a critical output path group. Accordingly, the violation threshold corresponding to the target clock domain may include: the critical input path violation threshold and the critical output violation threshold, and the updated violation threshold may include: an updated critical input path violation threshold and an updated critical output violation threshold.
In some embodiments, the updated critical input path violation threshold is taken as an example, which can be calculated in the following manner: the updated critical input path violation threshold = (clock cycle of the clock signal corresponding to the target clock domain-clock uncertainty of the clock signal corresponding to the target clock domain-critical input path delay constraint value) - (data path logical level number × unit average delay). The unit average delay is determined by the process, and the updated output path violation threshold may refer to the calculation formula of the updated input path violation threshold, which is not described herein again.
In summary, by applying the embodiment of the application, the layout and wiring tool can be used for classifying and optimizing in batch aiming at various interface violations, the time sequence repair capability and the time sequence repair effect can be improved, the difficulty of later Engineering Change Order (ECO) is reduced, and the chip design period is shortened. In addition, the embodiment of the application effectively optimizes the interface key path, releases partial resources of the non-key path and obtains more reasonable physical realization by subdividing the interface path, setting different optimization weights and modifying constraint conditions.
Fig. 8 is a functional module schematic diagram of an interface-based timing recovery apparatus according to an embodiment of the present application, the basic principle and the technical effect of the apparatus are the same as those of the foregoing corresponding method embodiment, and for brief description, reference may be made to corresponding contents in the method embodiment for a part not mentioned in this embodiment. As shown in fig. 8, the timing recovery apparatus 100 may include:
a first obtaining module 110, configured to obtain an interface path setup timing violation report of a target integrated circuit based on an initial interface constraint condition, where the target integrated circuit includes a plurality of logic units;
a second obtaining module 120, configured to establish a timing violation report according to the interface path, and obtain a target path group corresponding to a target clock domain in the target integrated circuit, where the target path group includes at least one data path, and the target integrated circuit is divided into multiple path groups according to the clock domain;
an updating module 130, configured to update the initial interface constraint condition according to the target path group, and obtain a target interface constraint condition;
the adjusting module 140 is configured to adjust the logic unit and/or the driving parameter of the logic unit in the target clock domain in the target integrated circuit by using a preset layout and routing tool and the target interface constraint condition, so that the data path corresponding to the target clock domain meets a preset timing requirement.
In an optional implementation manner, the updating module 130 is specifically configured to divide the target path groups into a critical path group and a non-critical path group based on a violation threshold corresponding to the target clock domain;
and updating the initial interface constraint condition according to the critical path group and the non-critical path group, and respectively acquiring a first target interface constraint condition corresponding to the critical path group and a second target interface constraint condition corresponding to the non-critical path group.
In an optional implementation manner, the updating module 130 is specifically configured to obtain a timing violation value of each target path group;
calculating a difference between each of the timing violation values and the violation threshold;
and determining a critical path group and a non-critical path group in the plurality of target path groups according to each difference value.
In an optional embodiment, the updating module 130 is further configured to set a first optimization weight of the critical path group and a second optimization weight of the non-critical path group according to a preset weight setting rule, respectively, where the first optimization weight is higher than the second optimization weight;
the adjusting, by using a preset layout and routing tool and the target interface constraint condition, the driving parameters of the logic unit and/or the logic unit in the target clock domain in the target integrated circuit includes:
based on the first optimization weight, inputting the first target interface constraint condition into the preset layout and wiring tool, and adjusting the first logic unit corresponding to the critical path group and/or the driving parameter of the first logic unit;
and inputting the second target interface constraint condition into the preset layout and wiring tool based on the second optimization weight, and adjusting the driving parameters of the second logic unit and/or the second logic unit corresponding to the non-critical path group.
In an optional embodiment, the updating module 130 is specifically configured to update the constraint coefficient corresponding to the target clock domain according to the critical path group corresponding to the target clock domain;
and acquiring a target interface constraint condition according to the updated constraint coefficient and clock period corresponding to the target clock domain.
In an optional implementation manner, the updating module 130 is specifically configured to establish a timing violation report according to the interface path, and respectively obtain the path delay and the timing violation value of the critical path group;
and updating the constraint coefficient corresponding to the target clock domain according to the path delay of the key path group, the time sequence violation value and the clock cycle corresponding to the target clock domain, and acquiring the updated constraint coefficient.
In an optional implementation manner, the updating module 130 is further configured to update the violation threshold corresponding to the target clock domain according to the target interface constraint condition, the clock cycle corresponding to the target clock domain, and the path logic level corresponding to the critical path group, and obtain the updated violation threshold.
In an alternative embodiment, the path group comprises: a group of input paths and/or a group of output paths;
the driving parameters of the logic unit comprise at least one of the following: the type of the logic unit, the number of the logic units and the level of the routing metal layer corresponding to the logic unit.
The above-mentioned apparatus is used for executing the method provided by the foregoing embodiment, and the implementation principle and technical effect are similar, which are not described herein again.
The above modules may be one or more integrated circuits configured to implement the above methods, such as: one or more Application Specific Integrated Circuits (ASICs), or one or more microprocessors, or one or more Field Programmable Gate Arrays (FPGAs), etc. For another example, when one of the above modules is implemented in the form of a Processing element scheduler code, the Processing element may be a general-purpose processor, such as a Central Processing Unit (CPU) or other processor capable of calling program code. For another example, these modules may be integrated together and implemented in the form of a system-on-a-chip (SOC).
Fig. 9 is a schematic structural diagram of an electronic device according to an embodiment of the present application, where the electronic device may be integrated in the timing recovery apparatus. As shown in fig. 9, the electronic device may include: a processor 210, a storage medium 220 and a bus 230, wherein the storage medium 220 stores machine-readable instructions executable by the processor 210, when the electronic device is running, the processor 210 communicates with the storage medium 220 via the bus 230, and the processor 210 executes the machine-readable instructions to perform the steps of the above-mentioned method embodiments. The specific implementation and technical effects are similar, and are not described herein again.
Optionally, the present application further provides a storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the computer program performs the steps of the above method embodiments. The specific implementation and technical effects are similar, and are not described herein again.
In the several embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other manners. For example, the above-described apparatus embodiments are merely illustrative, and for example, a division of a unit is merely a logical division, and an actual implementation may have another division, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.
Units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit may be implemented in the form of hardware, or in the form of hardware plus a software functional unit.
The integrated unit implemented in the form of a software functional unit may be stored in a computer readable storage medium. The software functional unit is stored in a storage medium and includes several instructions to enable a computer device (which may be a personal computer, a server, or a network device) or a processor (processor) to execute some steps of the methods according to the embodiments of the present application. And the aforementioned storage medium includes: a U disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.
It is noted that, in this document, relational terms such as "first" and "second," and the like, may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
The above description is only a preferred embodiment of the present application and is not intended to limit the present application, and various modifications and changes may be made to the present application by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application. It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures. The above description is only a preferred embodiment of the present application and is not intended to limit the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims (10)
1. An interface-based timing sequence repair method is characterized by comprising the following steps:
acquiring an interface path establishment timing violation report of a target integrated circuit based on an initial interface constraint condition, wherein the target integrated circuit comprises a plurality of logic units;
establishing a time sequence violation report according to the interface path, and acquiring a target path group corresponding to a target clock domain in the target integrated circuit, wherein the target path group comprises at least one data path, and the target integrated circuit is divided into a plurality of path groups according to the clock domain;
updating the initial interface constraint condition according to the target path group to obtain a target interface constraint condition;
and adjusting the logic unit and/or the driving parameter of the logic unit in the target clock domain in the target integrated circuit by adopting a preset layout and wiring tool and the target interface constraint condition so as to enable the data path corresponding to the target clock domain to meet the preset time sequence requirement.
2. The method according to claim 1, wherein the updating the initial interface constraint to obtain a target interface constraint according to the target path group comprises:
dividing a plurality of target path groups into a critical path group and a non-critical path group based on violation thresholds corresponding to the target clock domains;
and updating the initial interface constraint condition according to the critical path group and the non-critical path group, and respectively obtaining a first target interface constraint condition corresponding to the critical path group and a second target interface constraint condition corresponding to the non-critical path group.
3. The method according to claim 2, wherein the dividing the plurality of target path groups into a critical path group and a non-critical path group based on the violation threshold corresponding to the target clock domain comprises:
acquiring a time sequence violation value of each target path group;
calculating a difference between each of the timing violation values and the violation threshold;
and determining a critical path group and a non-critical path group in the plurality of target path groups according to each difference value.
4. The method of claim 3, further comprising:
respectively setting a first optimization weight of the critical path group and a second optimization weight of the non-critical path group according to a preset weight setting rule, wherein the first optimization weight is higher than the second optimization weight;
the adjusting, by using a preset layout and routing tool and the target interface constraint condition, the driving parameters of the logic unit and/or the logic unit in the target clock domain in the target integrated circuit includes:
based on the first optimization weight, inputting the first target interface constraint condition into the preset layout and wiring tool, and adjusting the first logic unit corresponding to the critical path group and/or the driving parameter of the first logic unit;
and inputting the second target interface constraint condition into the preset layout and wiring tool based on the second optimization weight, and adjusting the driving parameters of the second logic unit and/or the second logic unit corresponding to the non-critical path group.
5. The method according to claim 2, wherein the updating the initial interface constraint to obtain a target interface constraint according to the target path group comprises:
updating the constraint coefficient corresponding to the target clock domain according to the key path group corresponding to the target clock domain;
and acquiring a target interface constraint condition according to the updated constraint coefficient and clock period corresponding to the target clock domain.
6. The method according to claim 5, wherein the updating the constraint coefficient corresponding to the target clock domain according to the critical path group corresponding to the target clock domain comprises;
establishing a time sequence violation report according to the interface path, and respectively acquiring the path delay and the time sequence violation value of the key path group;
and updating the constraint coefficient corresponding to the target clock domain according to the path delay of the key path group, the time sequence violation value and the clock cycle corresponding to the target clock domain, and acquiring the updated constraint coefficient.
7. The method of claim 5, further comprising:
and updating the violation threshold corresponding to the target clock domain according to the target interface constraint condition, the clock cycle corresponding to the target clock domain and the path logic level corresponding to the key path group, and acquiring the updated violation threshold.
8. The method according to any of claims 1-7, wherein the path group comprises: a group of input paths and/or a group of output paths;
the driving parameters of the logic unit comprise at least one of the following: the type number of the logic units, the number of the logic units and the level of the routing metal layer corresponding to the logic units.
9. An electronic device, comprising: a processor, a storage medium and a bus, wherein the storage medium stores machine-readable instructions executable by the processor, when an electronic device runs, the processor communicates with the storage medium through the bus, and the processor executes the machine-readable instructions to execute the steps of the interface-based timing recovery method according to any one of claims 1 to 8.
10. A computer-readable storage medium, having stored thereon a computer program for performing, when being executed by a processor, the steps of the interface-based timing recovery method according to any one of claims 1 to 8.
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