CN112783065A - Time sequence circuit optimization method, device and storage medium thereof - Google Patents
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Abstract
The invention discloses a sequential circuit optimization method, a sequential circuit optimization device and a storage medium thereof, and belongs to the field of digital integrated circuits. The invention mainly provides a time sequence circuit optimization method, which comprises the following steps: grouping a plurality of continuous time sequence paths which are provided with a plurality of continuous violation time sequence paths in the time sequence transmission direction and at least one abundant time sequence path behind the plurality of continuous violation time sequence paths according to a time margin value of each time sequence path in the plurality of continuous time sequence paths to obtain at least one optimized time sequence path group; and setting the clock delay of the local clock end of the first trigger after each time sequence path in each group of the time sequence path groups according to the time margin value of each time sequence path in each group of the time sequence path groups, so as to optimize a plurality of time sequence violation paths continuously appearing in the time sequence circuit.
Description
Technical Field
The present invention relates to the field of digital integrated circuits, and in particular, to a method and an apparatus for optimizing a sequential circuit, and a storage medium thereof.
Background
Timing closure is a crucial link in the design of data integrated circuits. Generally, means such as optimizing register transfer level codes (RTL codes), setting reasonable constraint files, and improving process nodes are adopted to optimize a system architecture to achieve timing convergence. However, in the middle and later stage processes of integrated circuit design, when the register transfer level code is already reasonable, if the timing sequence in the circuit is not converged at this time, it will take a lot of time to adopt the optimization system architecture and improve the process node. In the prior art, a time sequence is optimized by setting a delay (latency) of a clock at a point where a timing violation (timing-violation) occurs, and for a case where a plurality of timing violation paths continuously occur, only a timing violation path closest to a point where no timing violation occurs can be optimized, and all timing violation paths cannot be optimized.
Disclosure of Invention
Aiming at the problems in the prior art, the invention mainly provides a sequential circuit optimization method, a sequential circuit optimization device and a sequential circuit optimization storage medium, wherein the sequential circuit optimization is realized by grouping a plurality of continuous violation sequential paths and subsequent rich time paths and setting a local clock end of a first trigger behind the violation sequential paths according to the time margin of each sequential path in a group.
In order to achieve the above purpose, the invention adopts a technical scheme that: provided is a sequential circuit optimization method, which comprises the following steps: grouping a plurality of continuous time sequence paths which are provided with a plurality of continuous violation time sequence paths in the time sequence transmission direction and at least one abundant time sequence path behind the plurality of continuous violation time sequence paths according to a time margin value of each time sequence path in the plurality of continuous time sequence paths to obtain at least one optimized time sequence path group;
and setting the clock delay of the local clock end of the first trigger behind each time sequence path in each group of the optimizable time sequence path groups according to the time margin value of each time sequence path in each group of the optimizable time sequence path groups.
The invention adopts another technical scheme that: provided is a sequential circuit optimization device, including:
a module for grouping a plurality of continuous time sequence paths which have a plurality of continuous violation time sequence paths in the time sequence transmission direction and at least one abundant time sequence path behind the plurality of continuous violation time sequence paths according to a time margin value of each time sequence path in the plurality of continuous time sequence paths to obtain at least one time sequence path group which can be optimized; and the number of the first and second groups,
means for setting a clock delay of a local clock terminal of a first flip-flop after each timing path in each group of optimizable timing paths based on a time margin value for each timing path in each group of optimizable timing paths in at least one group of optimizable timing paths
The invention adopts another technical scheme that: a computer-readable storage medium is provided that stores computer instructions operable to perform the sequential circuit optimization method of scenario one.
The technical scheme of the invention can achieve the following beneficial effects: the invention realizes the optimization of a plurality of continuous time sequence violation paths in the sequence circuit by grouping a plurality of continuous violation time sequence paths and subsequent rich time paths and setting the local clock end of the first trigger behind the violation time sequence paths according to the time margin of each time sequence path in the group.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and those skilled in the art can also obtain other drawings according to the drawings without inventive exercise.
FIG. 1 is a schematic diagram of a timing path in which a timing violation occurs;
FIG. 2 is a diagram illustrating a prior art method for eliminating timing violations;
FIG. 3 is a schematic diagram of a prior art process for acquiring data by a clock before and after a timing violation is resolved;
FIG. 4 is a schematic diagram illustrating one embodiment of a sequential circuit optimization method according to the present application;
FIG. 5 is a diagram illustrating a grouping process performed by a sequential circuit optimization method according to an embodiment of the present disclosure;
fig. 6 is a schematic diagram of an embodiment of a sequential circuit optimization apparatus according to the present application.
Embodiments of the present invention have been illustrated by the accompanying drawings and described in greater detail below. The drawings and written description are not intended to limit the scope of the disclosed concepts in any way, but rather to illustrate the concepts of the invention by those skilled in the art with reference to specific embodiments.
Detailed Description
The following detailed description of the preferred embodiments of the present invention, taken in conjunction with the accompanying drawings, will make the advantages and features of the invention easier to understand by those skilled in the art, and thus will clearly and clearly define the scope of the invention.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
As shown in FIG. 1, when the time margin (slack) of CK 1- > D2 is-100 ps, and the time margin of CK 2- > D3 is +300 ps; as shown in fig. 2, the CK 2- > D3 rich time margin can be generally borrowed to eliminate the timing violation (bias) of CK 1- > D2, a Buffer (BUF) with a delay (delay) value of 200ps can be inserted into the local CK end of FF2, or the clock delay (Latency) of CK2 can be set to 100ps, so that the clock period of CK 2- > D3 is reduced by 100ps, while the clock period of CK 1- > D2 is increased by 100ps, which is equivalent to borrowing the time of the rich timing path to the violating timing path on the premise that the total clock period is not changed. The clock relationship is shown in fig. 3. Before optimization, CK 1-D2 has large path delay, so that CK2 cannot acquire data2, and CK 2' can acquire data2 after optimization.
But when the situation of fig. 3 occurs: both the slack1 and the slack2 are less than 0, and the slack3 and the slack are more than 0, although inserting BUF/setting Latency at the local clock end (CK3) of FF3 can eliminate the violation of CK 2- > D3, so that the slack3 is more than 0, but can not eliminate the violation of CK 1- > D2.
That is, when timing violations occur on a plurality of consecutive timing paths and subsequent timing paths have a margin of time, all timing violations cannot be optimized, and only one violating timing path closest to the timing path having a margin of time can be optimized.
The following describes the technical solutions of the present invention and how to solve the above technical problems in detail with specific embodiments in conjunction with the accompanying drawings. The following several specific embodiments may be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments.
Fig. 4 shows a specific embodiment of a sequential circuit optimization method according to the present application.
In the specific embodiment shown in fig. 4, the sequential circuit optimization method of the present application includes a process S401, and a process S402.
The process S401 in fig. 4 illustrates a process of grouping consecutive multiple time-series paths having multiple consecutive violating time-series paths in the time-series transmission direction and having at least one slack time-series path following the multiple consecutive violating time-series paths according to the time margin value of each time-series path in the consecutive multiple time-series paths to obtain at least one optimizable time-series path group, so as to facilitate setting clock delays in each obtained group according to the time margins of the time-series paths, thereby optimizing the violating time-series paths therein.
In an embodiment of the application, the process of grouping the consecutive time series paths according to the time margin value of each of the consecutive time series paths to obtain at least one optimizable time series path group includes, in an order opposite to the time sequence transmission direction, sequentially grouping the consecutive time series paths according to a sum of the slack time margin value of at least one slack time series path of the consecutive time series paths and the violation time margin values of the consecutive violation time series paths to obtain at least one optimizable time series path group, so as to facilitate setting a clock delay in each obtained optimizable time series path group according to the time margin value of each time series path, thereby optimizing the violation time series path group.
In a specific embodiment of the present application, the above-mentioned sequentially grouping the consecutive time series paths according to the sum of the slack time margin value of at least one of the slack time series paths and the break time margin value of the consecutive break time series paths in the order opposite to the time series transmission direction to obtain at least one optimizable time series path group includes obtaining at least one optimizable time series path group by using the consecutive break time series paths corresponding to the break time margin values of which the sum of the slack time margin values is greater than 0 and the at least one slack time series path, that is, it needs to satisfy:
only when the time margin values of a group of timing paths meet the condition that the sum is greater than 0, the condition that the surplus time margin is enough to optimize the illegal timing path is indicated. The grouping of this embodiment is a premise for optimizing all violating timing paths within the group of optimizable timing paths.
FIG. 5 shows a specific example of the present application, in which P is shown in FIG. 51-PnRepresenting the time margin of n successive timing paths, from the nth timing pathK is N, N is 1(K represents a natural number of 1-N, N represents a packet number), and the packet is performed in the direction opposite to the timing transfer direction if P is Pk-1With group N { PkThe sum of the time margins is greater than 0, then P is addedk-1Merge into group N, otherwise Pk-1And forming an N +1 th group, continuously grouping the rest time margin, and finally grouping the corresponding time sequence paths according to the grouping of the time margin.
In a specific example of the present application, P1-P 10Respectively as follows:
-3, -5,6, -2,7, -8, -9,1,5,9, the grouping to obtain at least one set of groups of optimizable timing paths being:
step 1: the first set is initially: {9}, 9>0, and a9 ═ 7>0, (5+9)/2, the first set is updated to {5,9 };
step 2: a8 ═ (5+9+1)/3 ═ 5>0, with the first group updated to {1,5,9 };
step 3, a7 { -9+1+5+9)/4 { -1.5 >0, and the first set of updates is { -9,1,5,9 };
step 4, a6 ═ -8+ -9+1+5+9)/5 ═ -0.4<0, the first group is defined as { -9,1,5,9}, and the second group is defined as { -8 };
and 5: 8<0, so the second set is defined as { -8} and the third set is defined as {7 };
step 6: a4 (-2+7)/2 > 2.5, updated as: -2,7 };
and 7: a3 ═ (6+ -2+7)/3 ═ 3.67>0, with a third set updated as: {6, -2,7 };
step 8, a2 ═ (-5+6+ -2+7)/4 ═ 1.5>0, and the third group is updated as: -5,6, -2,7 };
step 9 a1 ═ (-3+ -5+6+ -2+7)/5 ═ 0.6>0, and the third set is updated as: { -3, -5,6, -2,7}.
The set of timing paths can be optimized: { -3, -5,6, -2,7},{ -8},{ -9,1,5,9}.
In another embodiment of the present application, P1-P 10Respectively as follows:
-8，-6，-3，-4，-8，9，7，6，5，10
obtaining at least one optimizable timing path set: { -8, -6, -3, -4, -8,9,7,6,5,10}
The process S402 in fig. 4 represents a process of setting the clock delay at the local clock end of the first flip-flop after each timing path in each group of optimizable timing paths according to the time margin value of each timing path in each group of optimizable timing paths in at least one group of optimizable timing paths, and by reasonably setting the corresponding clock delay according to the time margin value of each group of paths in each group of optimizable timing paths, all violative timing paths in the group can be optimized, not only the timing path closest to the time margin.
In a specific embodiment of the present application, the step of setting the clock delay of the local clock terminal of the first flip-flop after each timing path in each of the at least one group of optimizable timing paths according to the time margin value of each timing path in each of the at least one group of optimizable timing paths comprises setting the clock delay of the local clock terminal of the first flip-flop after each timing path in each of the group of optimizable timing paths according to the time margin value of each timing path and the average value of the time margins of each timing path in each of the group of optimizable timing paths, setting the corresponding clock delay according to the average value of the time margins in the group of optimizable timing paths, the setting of the clock delay can be made more reasonable.
In an embodiment of the application, the setting, according to the time margin value of each timing path and the average value of the time margin values of each timing path in each group of optimizable timing paths, the clock delay of the local clock end of the first flip-flop after each timing path in each group of optimizable timing paths includes setting, in each group of optimizable timing paths, the clock delay of the local clock end of the first flip-flop after the first timing path as the difference between the average value of the time margins and the time margin value of the first timing path according to the timing propagation direction, that is, the following formula is satisfied:
Aver＝(slack1+...+slackn)/n
Latency1＝Aver-slack1
aver: a time margin average value;
Latency1: and setting the clock delay value of the local clock end of the first trigger after the 1 st timing path. Therefore, the delay of the local clock end of the first trigger after the first timing path can be set more reasonably.
In an embodiment of the application, the setting, according to the time margin value of each timing path and the average value of the time margin values of each timing path in each group of optimizable timing paths, the clock delay of the local clock end of the first flip-flop after each timing path in each group of optimizable timing paths includes setting, in the direction of time sequence propagation in each group of optimizable timing paths, the clock delay of the local clock end of the first flip-flop after each timing path in each group of optimizable timing paths according to the time margin value, the average value of the time margin values of the ith timing path and the setting value of the first flip-flop before the ith timing path, where i is an integer greater than or equal to 2. And setting the corresponding clock delay according to the average value of the time margins in the optimized time sequence path group, the time margin of the time sequence path and the set value of the previous clock delay, so that the corresponding clock delay can be set more reasonably, and the illegal time sequence paths in each optimized time sequence path group can be optimized.
In an embodiment of the application, the setting, according to the time-sharing direction of the ith time-sharing path in each optimizable time-sharing path group, the clock delay of the local clock end of the first flip-flop after each time-sharing path in each optimizable time-sharing path group according to the time-sharing value of the ith time-sharing path, the average value of the time-sharing values, and the setting value of the first flip-flop before the ith time-sharing path includes setting the clock delay of the local clock end of the first flip-flop after the ith time-sharing path to be a difference between the average value of the time-sharing values of the ith time-sharing path and the setting value of the first flip-flop before the ith time-sharing path, that is, the following formula is satisfied:
Latencyi+1＝Aver-(slacki-latencyi-1)
aver: a time margin average value;
Latencyi: and setting the clock delay value of the local clock end of the first trigger after the ith timing path. And setting the corresponding clock delay according to the average value of the time margins in the optimized time sequence path group, the time margin of the ith time sequence path and the set value of the previous clock delay, so that the setting of the corresponding clock delay can be more reasonably carried out.
In a specific example of the present application, an optimized timing path group comprises ten consecutive timing paths, and the corresponding time margin values Slack 1-Slack 10 are-8, -6, -3, -4, -8,9,7,6,5,10, respectively, and the average value is 0.8 according to the formula.
L2(Latency2)＝0.8-(-8)＝8.8；
L3＝0.8-(-6-8.8)＝15.6
L4＝0.8-(-3-15.6)＝19.4
L5＝0.8-(-4-19.4)＝24.2
L6＝0.8-(-8-24.2)＝33
L7＝0.8-(9-33)＝24.8
L8＝0.8-(7-24.8)＝18.6
L9＝0.8-(6-18.6)＝13.4
L10＝0.8-(5-13.4)＝9.2
L11＝0.8-(10-9.2)＝0
Therefore, the clock delay values of the local clock terminal of the first flip-flop after each of the first to tenth timing paths are set to 8.8, 15.6, 19.4, 24.2, 33, 24.8, 18.6,13.4,9.2, and 0, respectively, i.e., the total clock delay in the group of optimizable timing paths is 0.
This makes it possible to optimize all violating timing paths within an optimizable set of timing paths reasonably.
Fig. 6 shows an embodiment of a sequential circuit optimization apparatus according to the present application.
In the specific embodiment shown in fig. 6, the sequential circuit optimization method of the present application includes a module 601, and a module 602.
Fig. 6 shows a module 601, which is a module for grouping a plurality of consecutive time-series paths having a plurality of violating time-series paths in a time-series transmission direction and at least one slack time-series path following the consecutive violating time-series paths according to a time margin value of each time-series path in the plurality of consecutive time-series paths to obtain at least one optimizable time-series path group, where, in each optimizable time-series path group obtained by the module 601, a clock delay may be set according to the time margin of each time-series path to optimize the violating time-series path therein.
In a specific embodiment of the present application, the module 601 may sequentially group the consecutive time series paths according to a sum of a slack time margin value of at least one of the consecutive time series paths and a violation time margin value of the consecutive violation time paths in an order opposite to the time series transmission direction, to obtain at least one optimizable time series path group, so as to facilitate setting clock delays in the obtained optimizable time series path groups according to a time margin of each time series path, so as to optimize violation time series paths therein.
In a specific embodiment of the present application, the module 601 may derive at least one optimizable group of timing paths using consecutive violating timing paths and at least one slack timing path corresponding to violating time margin values having a sum of slack time margin values greater than 0. Only when the time margin values of a group of timing paths meet the condition that the sum is greater than 0, the condition that the surplus time margin is enough to optimize the illegal timing path is indicated. Grouping to obtain the set of optimizable timing paths is a precondition for optimizing all violative timing paths in the set of optimizable timing paths.
In an embodiment of the present application, the module 601 may set the clock delay of the local clock end of the first flip-flop after each timing path in each group of optimizable timing paths according to the time margin value of each timing path and the average value of the time margins of the time margin values of each timing path in each group of optimizable timing paths, and set the corresponding clock delay according to the average value of the time margins in each group of optimizable timing paths, so that the setting of the clock delay can be performed more reasonably.
In one embodiment of the present application, the module 601 may set the clock delay of the local clock end of the first flip-flop after the first timing path to a difference between the average value of the time margins and the value of the time margin of the first timing path in the time sequence transmission direction in each optimizable timing path group, and set the clock delay of the local clock end of the first flip-flop after the ith timing path to a difference between the average value of the time margins and the value of the time margin of the ith timing path and the value of the first flip-flop before the ith timing path in the time sequence transmission direction in each optimizable timing path group, where i is an integer greater than or equal to 2, based on the average value of the time margins in the optimizable timing path group, the time margin of the ith time sequence path and the set value of the previous clock delay are set for the corresponding clock delay, so that the corresponding clock delay can be set more reasonably, and the illegal time sequence paths in each optimized time sequence path group can be optimized.
The device for optimizing a sequential circuit provided by the present invention can be used for executing the sequential circuit optimization method described in any of the above embodiments, and the implementation principle and the technical effect are similar, and are not described herein again.
In an embodiment of the present invention, each functional block in the sequential circuit optimization apparatus of the present invention may be directly in hardware, in a software module executed by a processor, or in a combination of the two.
A software module may reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor such the processor can read information from, and write information to, the storage medium.
The Processor may be a Central Processing Unit (CPU), other general-purpose Processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA), other Programmable logic devices, discrete Gate or transistor logic, discrete hardware components, or any combination thereof. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration. In the alternative, the storage medium may be integral to the processor. The processor and the storage medium may reside in an ASIC. The ASIC may reside in a user terminal. In the alternative, the processor and the storage medium may reside as discrete components in a user terminal.
In another embodiment of the present invention, a computer-readable storage medium stores computer instructions operable to perform the sequential circuit optimization method of scenario one.
In the embodiments provided in the present invention, it should be understood that the disclosed apparatus and method may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative, and for example, the division of the units is only one logical division, and other divisions may be realized in practice, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
The above description is only an embodiment of the present invention, and not intended to limit the scope of the present invention, and all equivalent structural changes made by using the contents of the present specification and the drawings, or applied directly or indirectly to other related technical fields, are included in the scope of the present invention.
Claims (9)
1. A method for optimizing a sequential circuit, comprising:
grouping a plurality of continuous time sequence paths which are provided with a plurality of continuous violation time sequence paths in a time sequence transmission direction and at least one abundant time sequence path behind the plurality of continuous violation time sequence paths according to a time margin value of each time sequence path in the plurality of continuous time sequence paths to obtain at least one optimized time sequence path group; and the number of the first and second groups,
and setting the clock delay of the local clock end of the first trigger behind each time sequence path in each group of the optimizable time sequence path group according to the time margin value of each time sequence path in each group of the optimizable time sequence path group.
2. The method of claim 1, wherein grouping the plurality of consecutive timing paths according to the time margin value for each of the plurality of consecutive timing paths to obtain at least one group of optimizable timing paths comprises,
and according to the sequence opposite to the time sequence transmission direction, sequentially grouping the continuous multiple time sequence paths according to the sum of the margin time margin value of the at least one margin time sequence path in the continuous multiple time sequence paths and the violation time margin values of the continuous multiple violation paths to obtain at least one optimized time sequence path group.
3. The sequential circuit optimization method according to claim 2, wherein said process of sequentially grouping the consecutive plurality of sequential paths according to a sum of a slack time margin value of the at least one of the consecutive plurality of sequential paths and a violation time margin value of the consecutive plurality of violation paths in an order opposite to the sequential transfer direction to obtain at least one of the optimizable groups of sequential paths comprises,
and obtaining at least one optimizable time sequence path group by using the continuous violation time sequence paths corresponding to the violation time allowance values of which the sum of the allowance time values is greater than 0 and the at least one allowance time sequence path.
4. The method of claim 1, wherein setting the clock delay of the local clock terminal of the first flip-flop after each of the timing paths in each of the groups of optimizable timing paths based on the time margin values for each of the timing paths in each of the groups of optimizable timing paths comprises,
and setting the clock delay of the local clock end of the first trigger behind each time sequence path in each group of the optimizable time sequence path groups according to the time margin value of each time sequence path and the average value of the time margins of the time margin values of each time sequence path in each group of the optimizable time sequence path groups.
5. The sequential circuit optimization method of claim 4, wherein said setting a clock delay of a local clock terminal of a first flip-flop after each of said sequential paths in each of said groups of optimizable sequential paths according to a time margin value of each of said sequential paths and an average of time margins of said time margin values of each of said sequential paths in each of said groups of optimizable sequential paths comprises,
and setting the clock delay of the local clock end of the first trigger after the first time sequence path as the difference between the average value of the time margins and the value of the time margins of the first time sequence path according to the time sequence transmission direction in each group of the groups of the time sequence paths which can be optimized.
6. The sequential circuit optimization method of claim 4, wherein said setting a clock delay of a local clock terminal of a first flip-flop after each of said sequential paths in each of said groups of optimizable sequential paths according to a time margin value of each of said sequential paths and an average of time margins of said time margin values of each of said sequential paths in each of said groups of optimizable sequential paths comprises,
setting the clock delay of the local clock end of the first trigger behind each time sequence path in each group of the time sequence path groups according to the time margin value of the ith time sequence path, the average value of the time margins and the setting value of the first trigger in front of the ith time sequence path in the time sequence transmission direction of each group of the time sequence path groups which can be optimized;
wherein i is an integer of 2 or more.
7. The sequential circuit optimization method of claim 6, wherein said setting the clock delay at the local clock terminal of the first flip-flop after each of said sequential paths in each said set of optimizable sequential paths based on the time margin value of the ith said sequential path, said time margin average value, and the setting of the first flip-flop before the ith said sequential path comprises,
setting the clock delay of the local clock end of the first trigger after the ith time sequence path as the difference value between the average value of the time margins and the difference value between the value of the time margin of the ith time sequence path and the setting value of the first trigger in front of the ith time sequence path.
8. A sequential circuit optimization apparatus, comprising:
a module for grouping a plurality of continuous time sequence paths which have a plurality of continuous violation time sequence paths in a time sequence transmission direction and at least one abundant time sequence path behind the plurality of continuous violation time sequence paths according to a time margin value of each of the plurality of continuous time sequence paths to obtain at least one time sequence path group which can be optimized; and the number of the first and second groups,
means for setting a clock delay of a local clock terminal of a first flip-flop after each of the timing paths in each of the at least one group of optimizable timing paths according to a time margin value of each of the timing paths in each of the at least one group of optimizable timing paths.
9. A computer-readable storage medium storing computer instructions, wherein the computer instructions are operable to perform the sequential circuit optimization method of any one of claims 1-7.
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