CN111859836A - Method and system for optimizing integrated circuit unbalanced clock network - Google Patents
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Abstract
The application discloses a method and a system for optimizing an unbalanced clock network of an integrated circuit, and belongs to the technical field of integrated circuits. The method comprises the following steps: acquiring an initial state space of a pre-analyzed time sequence path; judging whether the initial state space of the pre-analyzed time sequence path is larger than a preset state space value or not; if the state space value is larger than the preset state space value, outputting an initial execution coefficient of each node in the pre-analyzed time sequence path, otherwise, randomly selecting the nodes in the pre-analyzed time sequence path to perform n times of adjustment, and outputting the execution coefficient corresponding to each node after the nth time of adjustment, wherein n is smaller than or equal to the preset time, the state space of the pre-analyzed time sequence path after the n times of adjustment is larger than the preset state space value, and n is an integer larger than 0. By randomly selecting nodes in the pre-analyzed time sequence path for adjustment, the convergence speed and quality can be controlled arbitrarily, the design period is effectively shortened, and the adjustment times are reduced.
Description
Technical Field
The present application relates to the field of integrated circuit technologies, and in particular, to a method and a system for optimizing an unbalanced clock network of an integrated circuit.
Background
The existing eda (electronic design automation) technology can construct a clock network with good quality in most scenes. The basis for this construction is that the delay of the clock source arriving at each register clock port is as uniform as possible. Thereby enabling the setup time and hold time of the entire digital circuit to be satisfied jointly. The satisfaction of the settling time is now entirely determined by the clock period. While the satisfaction of the hold times benefits from the fact that the clock network arrives at each register almost equally. However, the clock network can be constructed in a manner that the local quality is not high enough in most designs.
First, we can usually only do in one working scenario when building a clock architecture. Such as building a clock network in a low voltage and high temperature scenario. This causes the scene to change to high voltage and low temperature. The optimal solution in the old scenario is noted as not being the optimal solution in the new scenario. While EDA tools provide some means of optimization, there are many times when manual intervention is required to solve the clock imbalance problem. Since the timing paths in a digital integrated circuit are in the millions. The workload of such manual intervention is sometimes substantial.
Second, for some timing paths with shorter delays, a balanced clock network may leave a lot of margin. For those timing paths with longer delay, the balanced clock network cannot meet the requirement of large delay. The handling of the global unbalanced clock network built by EDA tools in some detail scenarios is also not particularly desirable. And the larger the unbalanced clock network size, the more overhead needs to be considered for additional correction hold time. These overheads are very large in many designs.
Disclosure of Invention
In view of the above technical problems in the prior art, the present application provides a method and system for optimizing an unbalanced clock network of an integrated circuit.
In one embodiment of the present application, a method for optimizing an unbalanced clock network of an integrated circuit includes: acquiring an initial state space of a pre-analyzed time sequence path, wherein the initial state space comprises the sum of products of initial time sequence values and initial execution coefficients of all nodes in the pre-analyzed time sequence path; judging whether the initial state space is larger than a preset state space value or not; if the state space value is larger than the preset state space value, outputting an initial execution coefficient of each node in the pre-analyzed time sequence path, otherwise, randomly selecting the nodes in the pre-analyzed time sequence path to perform n times of adjustment, and outputting the execution coefficient corresponding to each node after the nth time of adjustment, wherein n is smaller than or equal to the preset time, the state space of the pre-analyzed time sequence path after the n times of adjustment is larger than the preset state space value, and n is an integer larger than 0.
In another aspect of the present application, a system for optimizing an unbalanced clock network of an integrated circuit is provided, including: the acquisition module is used for acquiring an initial state space of the pre-analyzed time sequence path, wherein the initial state space comprises the sum of products of initial time sequence values and initial execution coefficients of all nodes in the pre-analyzed time sequence path; the judging and circulating module is used for judging whether the initial state space is larger than a preset state space value or not, and if the initial state space is larger than the preset state space value, outputting an initial execution coefficient of each node in a pre-analyzed time sequence path; otherwise, randomly selecting nodes in the pre-analyzed time sequence path to perform n times of adjustment, and outputting execution coefficients corresponding to the nodes after the nth time of adjustment, wherein n is less than or equal to the preset times, the state space of the pre-analyzed time sequence path after the n times of adjustment is greater than the preset state space value, and n is an integer greater than 0.
Another technical scheme adopted by the application is as follows: a computer readable storage medium having stored thereon computer instructions operative to perform a method of optimizing an unbalanced clock network of an integrated circuit.
According to the technical scheme, the nodes in the pre-analyzed time sequence path are randomly selected for adjustment, so that the difficulty and the workload of top time sequence convergence can be effectively reduced, the design period can be effectively shortened, the adjustment times are reduced, and high precision which cannot be obtained during global state space convergence can be realized.
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FIG. 1 is a schematic diagram of one embodiment of a method for optimizing an unbalanced clock network of an integrated circuit according to the present application;
FIG. 2 is a schematic diagram illustrating one embodiment of a method for optimizing an unbalanced clock network of an integrated circuit according to the present application;
FIG. 3 is a schematic diagram of one embodiment of a system for optimizing an unbalanced clock network of an integrated circuit according to the present application.
Detailed Description
In order to make the aforementioned features and advantages of the present application more comprehensible, the present application is described in further detail below with reference to the accompanying drawings and the detailed description. This detailed description is merely intended to facilitate an understanding of the present application and the scope of the present application is not limited to the specific description stored in the detailed description.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
FIG. 1 illustrates one embodiment of a method of optimizing an unbalanced clock network of an integrated circuit. In this embodiment, the method for optimizing an unbalanced clock network of an integrated circuit of the present application mainly includes step S101. The method mainly comprises the following steps: and acquiring an initial state space of the pre-analyzed time sequence path, wherein the initial state space of the pre-analyzed time sequence path comprises the sum of products of initial time sequence values and initial execution coefficients of all nodes in the pre-analyzed time sequence path.
In an embodiment of the present application, before step S101, it is further required to collect information of a pre-analyzed timing path in a clock network. The pre-analyzed timing path comprises a timing violation path, each path related to the timing violation path, a timing path reaching each node in the timing violation path, and a timing path starting from each node in the timing violation path.
Specifically, information of pre-analyzed time series paths is gathered using a digital time series analysis tool and stored in a particular format in a switching database. Preferably, the information of each node in the pre-analyzed time-series path is recorded by a linked list. The digital implementation tool retrieves information of the pre-analyzed temporal path from the exchange database.
In practical cases, all timing paths are not generally analyzed for computational speed. Generally, only one main branch or one main subbranch under the main branch in the clock network and the path related to the main branch need to be selected as a pre-analyzed timing path according to the needs of a user. After the pre-analyzed time sequence path is selected, the information of each corresponding node in the pre-analyzed time sequence path and the information of the relationship between the nodes are obtained.
Preferably, those skilled in the art focus on analyzing paths in the clock network for timing violations. But adjusting any one path may affect the state of the other paths. For example, adjusting the X path to timing is satisfied, which may result in a new timing violation of the Y path. The present application therefore requires that all paths associated with timing violation paths be analyzed together. For example, if there is an order violation between the timing node a and the timing node B, firstly, all the branches on the path with the order violation are recorded, that is, as long as a branch is found to have an order violation, all the branches related to it need to be recorded; secondly, recording all timing paths reaching the timing node A, namely, whether any timing path is the timing path or not, whether the timing path is a timing violation or not needs to be recorded; thirdly, recording all timing paths from a timing node A, namely whether the timing node B is reached or not, wherein the timing paths need to be recorded; fourthly, recording all paths reaching the time sequence node B, namely whether the paths come from A or not, the paths need to be recorded; and fifthly, recording all time sequence paths from B, namely recording all the time sequence paths from B wherever the time sequence paths arrive.
In a specific embodiment of the present application, the state of each node in the pre-analyzed timing path is encoded as a 2-ary sequence of 128 bits. Wherein the upper 64bits is the timing value and the lower 64bits is the execution coefficient. Since the initial timing value of the initial state of the randomly selected node must be between-1 ns and +3ns, the initial timing value set to the randomly selected node is G rand (-1, 3).
Specifically, the random selection is a pure rand value, and then normalization rounding is performed to obtain the second node to be adjusted on the pre-analyzed timing path.
Specifically, the satisfaction or violation of the timing is physically embodied as the satisfaction of the setup time (setup time) and the satisfaction of the hold time (hold time) of the timing path. The setup time and hold time are required to be satisfied simultaneously, so that hundreds of millions of transistors in the integrated circuit can work together at a specific clock under the driving of the clock signal.
This formula, setup (x), is the setup time margin/delay of node x on pre-analyzed temporal path a, hold (x) is the hold time margin/delay of node x on pre-analyzed temporal path a, setup (x) and hold (x) are the timing values of node x. ω (x) is the implementation coefficient, which is the encoded representation of the adjustment scheme, and by decoding the implementation coefficient, it can be known which nodes need to be adjusted and what adjustment is specifically made. S (x) is the state space of the pre-analyzed timing path A.
In a specific embodiment of the present application, the information of the pre-analyzed timing path includes the pre-analyzed timing path, and an initial timing value and an initial execution coefficient, signal propagation delay information, and signal integrity interference information of each node in the pre-analyzed timing path.
In a specific embodiment of the present application, the information of the pre-analyzed time-series path includes an initial time-series value and an initial execution coefficient of each node in the corresponding pre-analyzed time-series path in a plurality of scenarios. The multiple scenes are scenes formed by combining different scene variables, wherein the scene variables comprise at least two of the working mode of the integrated circuit, the RC network characteristic of the integrated circuit, the working temperature of the chip and the working voltage of the chip.
In particular, the present application needs to be performed in a variety of scenarios. The scene variables are composed of various parameter information such as the working mode of the integrated circuit, the RC network characteristic of the integrated circuit, the working temperature and the voltage of the chip and the like. For example, in the RC network, scenes such as rcbest, RC best, C best, and C best need to be considered. The voltage needs to take into account high, normal and low voltages. The temperature also needs to take into account high, normal and low temperatures. Combining any of these permutations of parameters results in a wide variety of different scenarios. For the same timing path, the timing information of all its nodes in all scenes needs to be collected.
In the specific embodiment, the structure of the clock network is planned by mainly considering the condition that the time sequence violates the path, so that the overhead caused by global imbalance is avoided, and high precision which cannot be obtained when the global state space is converged can be obtained.
In the embodiment shown in fig. 1, the method for optimizing an unbalanced clock network of an integrated circuit further includes step S102. The method mainly comprises the following steps: judging whether the initial state space of the pre-analyzed time sequence path is larger than a preset state space value or not; if the state space value is larger than the preset state space value, outputting an initial execution coefficient of each node in the pre-analyzed time sequence path; otherwise, randomly selecting nodes in the pre-analyzed time sequence path to perform n times of adjustment, and outputting execution coefficients corresponding to the nodes after the nth time of adjustment, wherein n is less than or equal to the preset times, the state space of the pre-analyzed time sequence path after the n times of adjustment is greater than the preset state space value, and n is an integer greater than 0.
FIG. 2 illustrates one embodiment of a method for optimizing an unbalanced clock network of an integrated circuit. In this specific embodiment, the specific steps of randomly selecting a node in a pre-analyzed time sequence path to perform n times of adjustment, and outputting an execution coefficient corresponding to each node after the nth adjustment include:
firstly, calculating individual fitness of each node in a pre-analyzed time sequence path, and randomly selecting the nodes in the pre-analyzed time sequence path for first adjustment, wherein the initial time sequence value of the randomly selected nodes is between-1 ns and +3 ns.
Secondly, judging whether the state space of the pre-analyzed time sequence path after the first adjustment is larger than a preset state space value or not, if so, finishing the adjustment, and outputting an execution coefficient corresponding to each node after the first adjustment.
Finally, if the state space of the pre-analyzed time sequence path after the first adjustment is less than or equal to the preset state space value, the pre-analyzed time sequence path after the first adjustment is continuously adjusted until n is less than or equal to the preset times and the state space of the pre-analyzed time sequence path after the n times of adjustment is greater than the preset state space value, wherein the adjusting process comprises,
calculating the individual fitness of the node after the mth adjustment, randomly selecting the node in the pre-analyzed time sequence path after the mth adjustment to perform the (m + 1) th adjustment, and calculating and judging the state space of the pre-analyzed time sequence path after the (m + 1) th adjustment, wherein m is an integer which is more than 0 and less than n.
Specifically, after the pre-analyzed time sequence path is adjusted every time, the individual fitness of the node adjusted every time is calculated, so as to analyze what influence the adjustment of the node has on the state space of the pre-analyzed time sequence path.
In a particular embodiment of the present application, the adjusting may include: at least one of randomly selecting a predetermined node in the pre-analyzed timing path for duplication, performing mutation on one node, and crossing two nodes.
Where the replica node is constrained, if the device of the node is a single input single output device it may be replicated to introduce a new delay. Or simply to keep this node unchanged. It should be noted that more than 95% of the clock networks are single-input single-output devices.
The mutation and exchange are random and one can be chosen by any attempt. Wherein for switching, when both nodes can be allowed to be selected, then one can try to interchange the devices of node 1 with those of node 2 (mainly referring to single input single output devices). The delay information of the paths of the two nodes is substantially unchanged, but node 1 and/or node 2 may cause the delay information of the timing path associated therewith to change. In which, for a variation, the device of a node is replaced, or no device is replaced, only the input and output conditions are changed, such as the delay of a line or the transition rate of a signal on the line or the output load. This results in a different delay for the node after the node has been mutated, resulting in a change in the delay of the timing path associated therewith.
In one example of this embodiment, the preset state space value may be 0, or may be a value set by a person skilled in the art according to the actual situation of the integrated circuit.
In a specific embodiment of the present application, after step S102, it is further required to obtain node adjustment information corresponding to the adjustment process for n times, determine whether to perform adjustment according to the corresponding node adjustment information and the physical state of the area to be adjusted of the corresponding integrated circuit, if the area to be adjusted of the integrated circuit is full, abandon the adjustment of the corresponding node, otherwise, perform the corresponding adjustment.
In particular, the digital implementation decodes the execution coefficients to obtain which nodes need to be adjusted, and what adjustments are specifically made. But the actual adjustment can be made to see also whether the physical area at the time can be performed. The digital implementation tool records these adjustments to a physical database. This may not be possible if the physical area is completely full and has no space and requires that a node be duplicated next to it. But even if there is no space if the user forcibly requires adjustment, it is necessary to move other devices, make the space free, and then place new devices on the space made free.
For example, if there is no room around a node, the node cannot be replicated again, and vice versa. Or one wire is already very short, optimizing the wire so that it becomes shorter may refuse execution.
In this particular embodiment, partial modifications are discarded without physical space, taking into account the effect of physical location, and while the quality of the adjustment is lost, it is guaranteed that the physical design rules are not violated.
In an embodiment of the present application, if n is equal to a preset adjustment number of times, and a state space of the n-th adjusted pre-analyzed time sequence path is less than or equal to a preset state space value, an initial timing value and an initial execution coefficient of each node in the pre-analyzed time sequence path are adjusted.
For example, assuming the preset number of adjustments is 100, when Sx >0 is reached before 100 times, the adjustment is exited otherwise. If n is equal to 100 times, the initial timing value and the initial coefficient of the adjusting node are selected, so as to adjust the fitness of the method.
In this embodiment, the free selection of the initial state values of the nodes and the randomly selected range can achieve arbitrary control of convergence speed and quality, and the method is very useful for small-scale adjustment when project duration is tight.
In a specific embodiment of the present application, after the pre-analyzed timing path is adjusted, a next pre-analyzed timing path in the clock network is adjusted until the clock network converges successfully. The adjustment mode of the next pre-analyzed timing path is similar in principle to the adjustment mode of the pre-analyzed timing path, and is not described herein again.
The method and the device effectively reduce the difficulty and the workload of top-layer time sequence convergence, can effectively shorten the design period, reduce the times of adjustment, and can achieve high precision which cannot be obtained during the convergence of the global state space.
FIG. 3 illustrates one embodiment of a system for optimizing an unbalanced clock network of an integrated circuit according to the present application. In this embodiment, the system for optimizing an unbalanced clock network of an integrated circuit according to the present application comprises: and the adjusting module is used for acquiring an initial state space of the pre-analyzed time sequence path, wherein the initial state space of the pre-analyzed time sequence path comprises the sum of products of initial timing values and initial execution coefficients of all nodes in the pre-analyzed time sequence path.
In a specific embodiment of the present application, a search module is included before the adjustment module for gathering information of the pre-analyzed timing path in the clock network. The pre-analyzed timing path comprises a timing violation path, each path related to the timing violation path, a timing path reaching each node in the timing violation path, and a timing path starting from each node in the timing violation path.
In a specific embodiment of the present application, the information of the pre-analyzed timing path includes the pre-analyzed timing path, and an initial timing value and an initial execution coefficient, signal propagation delay information, and signal integrity interference information of each node in the pre-analyzed timing path.
In a specific embodiment of the present application, the information of the pre-analyzed time-series path includes an initial time-series value and an initial execution coefficient of each node in the corresponding pre-analyzed time-series path in a plurality of scenarios. The multiple scenes are scenes formed by combining different scene variables, wherein the scene variables comprise at least two of the working mode of the integrated circuit, the RC network characteristic of the integrated circuit, the working temperature of the chip and the working voltage of the chip.
In the specific embodiment shown in fig. 3, the system for optimizing an unbalanced clock network of an integrated circuit according to the present application further includes: the judgment circulation module is used for judging whether the initial state space of the pre-analyzed time sequence path is larger than a preset state space value or not; if the state space value is larger than the preset state space value, outputting an initial execution coefficient of each node in the pre-analyzed time sequence path; otherwise, randomly selecting nodes in the pre-analyzed time sequence path to perform n times of adjustment, and outputting execution coefficients corresponding to the nodes after the nth time of adjustment, wherein n is less than or equal to the preset times, the state space of the pre-analyzed time sequence path after the n times of adjustment is greater than the preset state space value, and n is an integer greater than 0.
In a specific embodiment of the present application, the determining and cycling module is further configured to calculate an individual fitness of each node in the pre-analyzed time sequence path, randomly select a node in the pre-analyzed time sequence path for a first adjustment, where an initial time sequence value of the randomly selected node is between-1 ns and +3ns, determine whether a state space of the pre-analyzed time sequence path after the first adjustment is greater than a preset state space value, if the state space is greater than the preset state space value, end the adjustment, output an execution coefficient corresponding to each node after the first adjustment, otherwise continue to adjust the pre-analyzed time sequence path after the first adjustment until n is less than or equal to the preset number of times and the state space of the pre-analyzed time sequence path after the n adjustments is greater than the preset state space value, where the adjusting process includes calculating the individual fitness of the node after the m-th adjustment, and randomly selecting nodes in the pre-analysis time sequence path after the m-th adjustment to perform the m + 1-th adjustment, and calculating and judging the state space of the pre-analysis time sequence path after the m + 1-th adjustment, wherein m is an integer which is more than 0 and less than n.
In a specific embodiment of the present application, the determining and circulating module is further configured to obtain node adjustment information corresponding to the adjustment process for n times, determine whether to perform adjustment according to the corresponding node adjustment information and a physical state of a region of the integrated circuit that needs to be adjusted, abandon adjustment of the corresponding node if the region of the integrated circuit that needs to be adjusted is full, and otherwise perform corresponding adjustment.
In an embodiment of the present application, if n is equal to a preset adjustment number of times, and a state space of the n-th adjusted pre-analyzed time sequence path is less than or equal to a preset state space value, an initial timing value and an initial execution coefficient of each node in the pre-analyzed time sequence path are adjusted.
In a specific embodiment of the present application, after the pre-analyzed timing path is adjusted, a next pre-analyzed timing path in the clock network is adjusted until the clock network converges successfully.
The system for optimizing an unbalanced clock network of an integrated circuit provided by the present application can be used to implement the method for optimizing an unbalanced clock network of an integrated circuit described in any of the above embodiments, and the implementation principle and the technical effect are similar, and are not described herein again.
In one embodiment of the present application, the tuning module and the decision loop module may be implemented directly in hardware, in a software module executed by a processor, or in a combination thereof.
A software module may reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor such the processor can read information from, and write information to, the storage medium.
The Processor may be a Central Processing Unit (CPU), other general-purpose Processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA), other Programmable logic devices, discrete Gate or transistor logic, discrete hardware components, or any combination thereof. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration. In the alternative, the storage medium may be integral to the processor. The processor and the storage medium may reside in an ASIC. The ASIC may reside in a user terminal. In the alternative, the processor and the storage medium may reside as discrete components in a user terminal.
In another embodiment of the present application, a computer-readable storage medium stores computer instructions, wherein the computer instructions are operable to perform the method for optimizing an unbalanced clock network of an integrated circuit described in any of the embodiments.
In another embodiment of the present application, a program product includes a computer program stored in a readable storage medium, from which the computer program can be read by at least one processor, and the computer program is executed by the at least one processor to perform the method for optimizing an unbalanced clock network of an integrated circuit described in any of the embodiments.
In the several embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative, and for example, the division of the units is only one logical division, and other divisions may be realized in practice, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
The above description is only an example of the present application and is not intended to limit the scope of the present application, and all equivalent structural changes made by using the contents of the specification and the drawings, which are directly or indirectly applied to other related technical fields, are included in the scope of the present application.
Claims (10)
1. A method of optimizing an unbalanced clock network of an integrated circuit,
acquiring an initial state space of a pre-analyzed time sequence path, wherein the initial state space comprises the sum of products of initial time sequence values and initial execution coefficients of all nodes in the pre-analyzed time sequence path;
judging whether the initial state space is larger than a preset state space value or not, if so, outputting an initial execution coefficient of each node in the pre-analyzed time sequence path,
otherwise, randomly selecting nodes in the pre-analyzed time sequence path to perform n times of adjustment, and outputting execution coefficients corresponding to each node after the nth time of adjustment, wherein n is less than or equal to a preset number of times, the state space of the pre-analyzed time sequence path after the n times of adjustment is greater than the preset state space value, and n is an integer greater than 0.
2. The method of claim 1, wherein the randomly selecting nodes in the pre-analyzed timing path for n times of adjustment and outputting the execution coefficients corresponding to the nodes after the n-th adjustment, further comprises:
calculating individual fitness of each node in the pre-analyzed time sequence path, randomly selecting the nodes in the pre-analyzed time sequence path for first adjustment, wherein the initial time sequence value of the randomly selected nodes is between-1 ns and +3ns,
judging whether the state space of the pre-analyzed time sequence path after the first adjustment is larger than the preset state space value or not, if so, finishing the adjustment, outputting the execution coefficient corresponding to each node after the first adjustment,
otherwise, continuously adjusting the pre-analyzed time sequence path after the first adjustment until n is less than or equal to the preset times and the state space of the pre-analyzed time sequence path after the n times of adjustment is greater than the preset state space value, wherein the adjusting process comprises,
calculating the individual fitness of the node after the mth adjustment, randomly selecting the node in the pre-analysis time sequence path after the mth adjustment to perform the (m + 1) th adjustment, and calculating and judging the state space of the pre-analysis time sequence path after the (m + 1) th adjustment, wherein m is an integer which is more than 0 and less than n.
3. The method of optimizing an unbalanced clock network of an integrated circuit of claim 1, further comprising: and when n is equal to the preset times and the state space of the pre-analyzed time sequence path after n times of adjustment is less than or equal to the preset state space value, adjusting the initial time sequence value and the initial execution coefficient of each node in the pre-analyzed time sequence path.
4. The method of optimizing an unbalanced clock network of an integrated circuit of claim 2, wherein randomly selecting a predetermined node in the pre-analyzed timing path for a first adjustment comprises: randomly selecting at least one of a predetermined node in the pre-analyzed timing path for duplication, a node for mutation, and a node for intersection.
5. The method of optimizing an unbalanced clock network of an integrated circuit of claim 1, further comprising: acquiring corresponding node adjustment information in the adjustment process for n times, judging whether to adjust or not according to the corresponding node adjustment information and the physical state of the area to be adjusted of the corresponding integrated circuit, if the area to be adjusted of the integrated circuit is full, abandoning the adjustment of the corresponding node, otherwise, carrying out corresponding adjustment.
6. The method of optimizing an unbalanced clock network of an integrated circuit according to claim 1, wherein the obtaining an initial state space of a pre-analyzed timing path is preceded by: in a clock network, gathering information of the pre-analyzed timing paths, wherein the pre-analyzed timing paths include a timing violation path, respective paths associated with the timing violation path, timing paths to reach respective nodes in the timing violation path, and timing paths from the respective nodes in the timing violation path, and the information of the pre-analyzed timing paths includes the pre-analyzed timing paths, and initial timing values and initial execution coefficients, signal propagation delay information, and signal integrity disturbance information of the respective nodes in the pre-analyzed timing paths.
7. The method of claim 1, wherein the information of the pre-analyzed timing path comprises initial timing values and initial execution coefficients of respective nodes in the pre-analyzed timing path corresponding to a plurality of scenarios, wherein the plurality of scenarios are scenarios combined from different scenario variables, wherein the scenario variables comprise at least two of an operation mode of the integrated circuit, an RC network characteristic of the integrated circuit, a chip operation temperature, and a chip operation voltage.
8. The method of claim 1, further comprising adjusting a next pre-analyzed timing path in the clock network after adjusting the pre-analyzed timing path until clock network convergence is successful.
9. A system for optimizing an unbalanced clock network of an integrated circuit, comprising:
the system comprises an acquisition module, a processing module and a processing module, wherein the acquisition module is used for acquiring an initial state space of a pre-analyzed time sequence path, and the initial state space comprises the sum of products of initial time sequence values and initial execution coefficients of all nodes in the pre-analyzed time sequence path;
a judging circulation module, configured to judge whether the initial state space is greater than a preset state space value, and if so, output an initial execution coefficient of each node in the pre-analyzed time sequence path;
otherwise, randomly selecting nodes in the pre-analyzed time sequence path to perform n times of adjustment, and outputting execution coefficients corresponding to each node after the nth time of adjustment, wherein n is less than or equal to a preset number of times, the state space of the pre-analyzed time sequence path after the n times of adjustment is greater than the preset state space value, and n is an integer greater than 0.
10. A computer readable storage medium having stored thereon computer instructions operable to perform the method of optimizing an unbalanced clock network of an integrated circuit of any of claims 1 to 8.
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