CN107103144B

CN107103144B - FPGA-based arbitration type PUF (physical unclonable function) wiring delay deviation rapid calibration method

Info

Publication number: CN107103144B
Application number: CN201710315269.2A
Authority: CN
Inventors: 裴颂伟; 王若男; 张静东
Original assignee: Beijing University of Chemical Technology
Current assignee: Beijing University of Chemical Technology
Priority date: 2017-05-08
Filing date: 2017-05-08
Publication date: 2020-06-26
Anticipated expiration: 2037-05-08
Also published as: CN107103144A

Abstract

The invention discloses a rapid calibration method for delay deviation of wiring of an arbitration type PUF (physical unclonable function) based on an FPGA (field programmable gate array). And the excitation storage module starts to output the stored first excitation to the PUF after the input reading signal is valid, and sets an excitation mark signal connected with the counter to be valid after the last excitation is output. When the input adjustment completion signal is valid, the counter clears the counter and starts to count the response of the PUF in an accumulated manner, and when the excitation mark signal is valid, the counter stops counting and transmits the counting result to the comparator. In the comparator, according to the relation between the counting result and the set threshold value range, an adjusting mark signal for calculating the next adjusting stage is output to the dichotomy module. And in the dichotomy calculation module, calculating the next regulating stage and outputting a corresponding regulating stage configuration to be applied to a delay regulating block of the PUF. And then, under the adjustment level, the PUF input excitation is re-excited, a new round of adjustment is carried out until the counting result is within the threshold range in the comparator, and the comparator outputs an adjustment level identification signal. The PUF adjusting method and the PUF adjusting device can effectively reduce time overhead in the PUF adjusting process.

Description

FPGA-based arbitration type PUF (physical unclonable function) wiring delay deviation rapid calibration method

Technical Field

The invention relates to the field of hardware security and FPGA application, and aims to compensate the wiring asymmetric delay of two signal channels of an arbitration type PUF based on an FPGA by inputting a proper adjusting level into a PUF circuit, so that the arbiter PUF has better randomness and unpredictability, and further the security of the PUF is improved. In addition, the efficiency can be greatly improved for the adjustment of the FPGA-based arbiter PUF before the PUF is put into use.

Background

As information security is more and more important, the conventional method of storing confidential information in a nonvolatile memory faces many challenges, the confidential information is stored in the nonvolatile memory such as a fuse or an EEPROM, and in most cases, in order to improve security, an additional protection circuit is required to be disposed around the memory, which increases circuit consumption in addition to increasing cost. In this case, a new hardware security protection method Physical Unclonable Function (PUF) is proposed. PUFs use physical inherent variations as their own identifying fingerprint, which is not reproducible. Compared with the traditional method, the PUF utilizes the characteristic difference of the physical device, does not need extra circuit consumption, and has the advantage of low cost. Since the development of such hardware security protection methods, there has been an increasing interest in them, and research on them is also ongoing.

A model of a conventional arbitrated PUF architecture is shown in fig. 1. The output ends of the two parallel signal channels are respectively connected to the data input end (end D) and the clock input end (end C) of the trigger, and the two parallel signal channels are respectively formed by connecting a plurality of multiplexers. Input bit C through a multiplexer_iControl the transmission path of signals in the ith multiplexer when C_iWhen the signal is 0, the signal at the input terminal of the multiplexer 0 is taken as the output, and when C is_iWhen the signal is 1, taking the signal at the input end of the multiplexer 1 as output; because the transmission signal paths of the multiplexers are different, the delays generated in the signal transmission process are different. The outputs of the two multiplexers of the last stage are connected to a data port (D port) and a clock port (C port) of the flip-flop, respectively. A step signal is input into the two signal channels from the signal input end, when a signal of the D port of the trigger arrives first, the output of the PUF is 1, and otherwise, the output is 0. Inputting bit C through multiplexers of various stages₀-C_n-1The different 0, 1 combinations of (a) and (b) allow for multiple combinations of signal transmission on the multiplexer, resulting in a binary system with very good randomness.

When an arbitrated PUF is implemented on an FPGA, the signal path will be composed using a Look-Up Table (LUT) instead of a multiplexer. Because, when the input bits of the lookup table are different, the delay of the signal generated by the lookup table is also different. Thus, the inputs C of the two lookup tables of the ith stage_iRespectively 0 or 1, corresponding to adding two different delays to the two signals, respectively. Different control bits are input into each level of lookup tables to serve as input stimuli of the PUF, and the control bits are equal to various combinations of delay generated by each level of lookup tables, so that the response of the generated PUF also has good randomness. An arbitration type PUF configuration implemented on an FPGA is shown in the Challenge part and the trigger part of figure 2. Since the structure of an arbitrated PUF requires that the two signal paths must be perfectly symmetric, the randomness of the response is only generated by the inherent differences in delay in the multiplexers or look-up tables. When the arbitration type PUF is realized on the FPGA, the FPGA adopts a netThe layout is formatted, so that the layout between lookup tables with a symmetrical structure cannot achieve complete symmetry, and the generated delay deviation on the layout will affect the randomness of the PUF output. Therefore, it is necessary to compensate for some delay of the arbiter PUF implemented on the FPGA to counteract the uneven delay of the two signal paths and improve the randomness of the PUF response.

Foreign researchers have developed corresponding studies. There are researchers who propose an adaptation scheme of the FPGA-based arbiter PUF as shown in fig. 2. The first half of fig. 2 is the excitation input part of the arbitration type PUF, and the second half is the added delay adjustment part. The delay adjustment part is arranged between the last level lookup table of the arbitration type PUF and the arbiter, and is composed of a plurality of lookup tables in cascade connection. The symmetrical lookup tables in the upper and lower paths different from the arbitration type PUF excitation part pass through the same control bit C_iAnd each lookup table of the delay adjusting part has an input bit, and different values are input through the control bits of the delay adjusting block part, so that delay difference between the upper adjusting block part and the lower adjusting block part just counteracts delay deviation on the wiring. Each triangle in fig. 2 represents an adjustable delay element (PDL) implemented by a look-up table, characterized by a delay generated at the input of 1 that is greater than the delay at the input of 0. Because, for a lookup table, the internal structure is as shown in fig. 4, taking a 3-input lookup table that implements the inverter function as an example. It can be seen from the figure that there is a difference in length of signal transmission paths at different inputs, which will cause different delays. It was found that for a look-up table, the delay introduced into the circuit when all 1's are activated is greater than when all 0's are activated. For ease of understanding, one look-up table is equivalent to a multiplexer with different delays in fig. 5, and the delays of a, b are greater than the delays of d, c, respectively. For the delay adjustment part of the circuit, the input Tu [1-k ] of the lookup table of the current path]When all 1 s are input, the maximum delay is added to the upper signal path, and when all 0 s are input, the minimum delay is input. The number of delay units input to the upper and lower signal paths of the delay adjusting part is expressed by the concept of the adjusting stage, and the calculation formula is that the input Tu [1-k ] of the upper path of the delay adjusting part is used]1 minus the next inputTd[1-k]1 in the above-mentioned order. When no delay difference is added to the upper path and the lower path of the delay adjusting part, if the response value of the PUF is greatly biased to 1, the lower path of the PUF is more than the upper path of the PUF, so that the delay of the upper path needs to be more than the delay of the lower path in the delay adjusting part, namely the adjusting stage needs to be a positive value at the moment; otherwise, the adjustment should be negative. In general, the maximum adjustment range of the adjustment stage is set according to the number of programmable delay cells included in the delay adjustment section, and if the number of programmable delay cells included in the delay adjustment section is k, the maximum adjustment range of the adjustment stage is [ -k, k]. For the scheme of the structure in fig. 2, the corresponding regulation stage with the best proportional randomness of 1 in the response value is selected as the final regulation stage of the circuit by artificially controlling the input of the delay regulation part and then counting the number of 1 in the response value of the PUF at each regulation stage. This approach often requires a relatively large number of measurements to find the final adjustment stage, so that the finding process takes relatively much time and power.

Disclosure of Invention

It is an object of the invention to provide a method for automatic adjustment of wiring delay deviations of an FPGA-based arbiter PUF with less overhead, less required adjustment time and higher efficiency. The automatic regulation method is realized by an automatic regulation circuit which consists of a counter, a comparator, a dichotomy calculation module and an excitation storage module. The output of the dichotomy computing module controls the input of the PUF delay adjusting part, when the PUF delay adjusting part obtains an adjusting level, the excitation module inputs a large number of excitations stored in the output to the arbitration type PUF, the counter counts the output response of the PUF, when all the excitations are output, the counter stops counting, the counting result is compared with a set threshold range in the comparator, according to the comparison result, the comparator outputs an adjusting mark signal for calculating the next adjusting level, and the dichotomy computing module calculates a new adjusting level according to the adjusting mark signal and outputs the new adjusting level to the PUF delay adjusting part. The process is automatically completed until the counting result in the comparator is within the threshold range, and the adjusting process is completed.

Another object of the present invention is to compute the adjustment level of the arbiter PUF by using the dichotomy, which can be used for the adjustment before the FPGA-based arbitration type PUF is applied, and improve the randomness of PUF response. In the dichotomy calculation module, first, an adjustment interval [0, k ] of an adjustment stage is initialized, where k is the number of programmable units included in an upper path of the delay adjustment part. The median k/2 of the interval is then calculated as the initial adjustment stage of the circuit. When a new adjusting level needs to be found, the upper and lower intervals of the adjustment are correspondingly updated according to the size relationship between the new adjusting level and the current adjusting level. When the new adjusting level is smaller than the current adjusting level, the adjusting interval is updated to [0, k/2 ]; if the new adjusting level is larger than the current adjusting level, the adjusting interval is updated to [ k/2, k ]; the median is then calculated in the new interval and used as the new adjustment level. Half of the adjusting stages in the area are eliminated during each searching, so that the method has very high searching efficiency, and the power consumption overhead and the time overhead are greatly reduced.

In order to achieve the purpose, the technical scheme adopted by the invention is a rapid wiring delay deviation calibration method of the arbitration type PUF based on the FPGA. The method is characterized in that the rapid calibration of the delay deviation is realized by an automatic adjusting circuit consisting of a counter, a comparator, a dichotomy calculating module and an excitation storage module. The connection between the autoregulating circuit and the arbitration type PUF is shown in fig. 3. The excitation storage module of the automatic adjusting circuit provides input excitation of the PUF, the adjusting level configuration bit output by the dichotomy calculating module serves as the input of the PUF delay adjusting part, and the counter reads the response of the PUF and counts the number of 1 in the response. In the automatic adjustment circuit, after the bisection computation module outputs an adjustment stage configuration bit, an adjustment completion signal (Tune _ finish) connected to the counter module is asserted at the same time, and a read signal (read) connected to the excitation storage module is asserted. The excitation storage module starts to output the stored first excitation to the PUF after the input read signal (read) is valid, and sets an excitation flag signal (Challenge _ flag) connected with the counter to be valid after the last excitation is output. The counter clears the counter when the inputted adjustment completion signal (Tune _ finish) is valid, and starts accumulation counting of the response of the PUF, and stops counting when the excitation flag signal (Challenge _ flag) is valid, and transmits the counted result to the comparator. In the comparator, according to the relation between the counting result and the set threshold value range, an adjusting mark signal (Tune _ state) for calculating the next adjusting stage is output to the dichotomy module. Wherein, the threshold range set in the comparator is calculated according to the total number of the statistical response values and the set error:

Threshold＝N×(50％±e) (1)

where N represents the total number of PUF response values and e represents the tolerance error for randomness.

In the comparator, a decreasing relationship exists between the counting result of the number of 1's in the PUF response and the adjustment level as shown in fig. 8, and a magnitude relationship between the next adjustment level and the current adjustment level is generated based on the counting result and the threshold range.

In the comparator, when the statistical result is in the threshold value range, the current adjusting stage can compensate the wiring delay deviation, and then an adjusting mark signal is output to be 11(Tune _ state is 11); if the current calculation result is smaller than the lowest value of the threshold range, which indicates that the next adjustment level to be searched is smaller than the current adjustment level, the adjustment flag signal is output to be 10(Tune _ state is 10); if the current calculation result is larger than the maximum value of the threshold range, which indicates that the next adjustment level to be searched is larger than the current adjustment level, the adjustment flag signal is output as 01(Tune _ state is 01).

In the dichotomy calculation module, a new adjustment stage is calculated according to the value of the adjustment flag signal (Tune _ state), and an adjustment stage configuration bit corresponding to the new adjustment stage is output. First, a method of calculating a new adjustment level (Middle) and then obtaining a corresponding adjustment level configuration bit is introduced. Since the previous adjustment level is stored in Middle _ pre, the new adjustment level calculated is Middle. To configure the bit Tu for the output regulation stage_i(i∈[1,k]) From the output Tu [1: Middle _ pre]＝1,Tu[Middle_pre+1:k]0. Change to a new trim configuration bit output Tu [1: Middle]＝1,Tu[Middle+1:k]0, as shown in the following figure. Tui need to be shifted, wherein the sum of the directions of the shiftThe number of bits is calculated by the variation between the adjustment stages:

Shift_bits＝Midian–Midian_pre (2)

wherein the sign bit of shift _ bits represents the direction to be shifted, the negative sign represents a left shift, the positive sign represents a right shift, and the value represents the number of bits to be shifted. Midi represents the calculated new adjustment level; midian _ pre represents the previous adjustment stage.

In the dichotomy calculation module, a state machine is designed, and the functions of calculating a new adjustment level and obtaining a new adjustment level configuration bit are realized by performing state conversion among the state machines through different values of an adjustment flag signal (Tune _ state). The four states of the state machine are: start, left-turn state, right-turn state and stop. The transition relationship between the states is shown in fig. 5. The functions mainly realized in each state are as follows:

first, in the start state, the initialization function for some registers is mainly implemented. The initial value of the lower boundary (Low) of the adjustment interval is 0, the initial value of the upper boundary (High) of the adjustment interval is k, wherein k is the number of programmable delay units included in the PUF delay adjustment part, the initial value of the new adjustment stage (Middle) is k/2, the initial value of the current adjustment stage (Middle _ pre) is k/2, and the initial value of the Shift flag (Shift _ bits) is 0, wherein the Shift flag is used for setting bits based on the current adjustment stage, and the flag needs to be shifted in order to obtain new adjustment stage setting bits.

In the left-hand state, three functions are mainly implemented: 1) storing the current trim level Middle in Middle _ pre; 2) updating the adjustment interval to [ Low, Middle ], and calculating the median value in the new interval as a new adjustment level; 3) and obtaining and outputting the configuration bit corresponding to the adjustment level.

In the right-hand state, the functions implemented are: 1) storing the current Middle adjustment stage Middle in Middle _ pre; 2) updating the adjustment interval to [ Middle, High ], and calculating the median value in the new interval as a new adjustment level; 3) and obtaining and outputting the configuration bit corresponding to the adjustment level.

In the sotp state, which indicates that the adjustment process is finished, the values in all registers will be kept unchanged.

In each state, the main functions realized by the registers and the change of the values of the registers are shown in the following table:

and when the dichotomy calculation module outputs a new adjusting stage configuration bit each time, the adjusting circuit automatically performs a new adjusting process until the number of 1 in the response value of the PUF in the comparator is within the threshold value, and the adjusting process of the circuit is completed. Since the number of times the adjustment stage is found is related to the size of the threshold range, an equilibrium between the number of adjustments and the error is found, as desired.

Compared with the prior art, the method A for rapidly calibrating the wiring delay deviation on the FPGA is compared with the method B for manually searching the optimal adjustment level shown in the figure 1. In which figure 7 shows a PUF circuit applying 4 adjustment processes according to the invention to find a suitable adjustment level. Fig. 8 shows a comparison of the two methods of finding the adjustment level. As can be seen from fig. 8, the number of adjustments required for this invention is also much smaller for the same PUF circuit than for manually finding the adjustment level. The power consumption expense in the PUF adjusting process can be effectively reduced. In addition, the present invention seeks to provide a tuning stage that adequately compensates for wiring delays at a much faster rate than method B. The time overhead of the PUF adjusting process can be effectively reduced.

Drawings

Fig. 1 is a schematic diagram of a classical architecture of an arbiter PUF. Fig. 2 is a schematic diagram of an FPGA-based arbitrated PUF with PDL.

Fig. 3 is a schematic diagram of an inventive FPGA-based arbitrated PUF that can implement auto-finding adjustment levels.

Fig. 4 is a schematic diagram of the internal structure of the 3-input lookup table.

FIG. 5 is an equivalent diagram of look-up tables producing different delays at either all 0 or all 1 inputs.

Fig. 6 is a transition diagram of a state in which the adjustment stage number is calculated based on the dichotomy.

Fig. 7 is a comparison of the number of adjustments made by the auto-seek adjustment level method and the manual seek adjustment level method shown in fig. 1.

FIG. 8 is a graph of the relationship between the statistics and the adjustment level.

Fig. 9 is a schematic diagram of shifting the trim level configuration bits.

Detailed Description

By adopting the method for quickly calibrating the routing delay deviation of the arbitration type PUF based on the FPGA, the schematic circuit structure diagram is shown in FIG. 3. The adjusting range of the adjusting stage can be selected according to requirements, the automatic adjustment of the delay of the single-picking signal channel can be carried out, and the automatic adjustment of the delay of two signal channels can also be carried out simultaneously. In this method, the adjustment range is set to [0,40], and the auto-adjustment circuit is implemented on the upper signal path.

The basic steps for realizing automatic adjustment of the on-line delay by adopting the arbitration type PUF wiring delay quick calibration method based on the FPGA are as follows:

step 1: the randomness of 0 and 1 distribution in PUF response values of two boundary values of the regulation level is measured, and the existence of the regulation level to be searched is determined.

Step 2: and obtaining a first regulating stage configuration bit to send to the PUF circuit by initializing a regulating interval and a regulating stage in the bisection calculation module. At the same time, the start signal (Read) connected to the excitation memory module is asserted and the set completion signal (Tune _ finish) connected to the counter is asserted.

And step 3: the stimulus storage module outputs all stored random stimuli to the PUF after the start signal (Read) is active and asserts a completion signal (Challenge _ flag) connected to the counter after the stimulus output is complete.

And 4, step 4: after detecting that the adjustment completion signal (Tune _ finish) is valid, the counter performs a zero clearing operation on the internal counter and starts to perform accumulated counting on the response value of the PUF. When the completion signal (Challenge _ flag) from the excitation module is asserted, the counter stops counting, asserts the count completion signal (Cnt _ finish), and outputs the current count result (counter) to the comparator.

And 5: a threshold range Ref is first initialized in the comparator. When the comparator detects that the count completion signal (Cnt _ finish) is valid, the input count value counter is compared with a given threshold range Rdf, the magnitude relation between the count value counter and the given threshold range Rdf is judged, and an adjustment state signal (Tune _ state) is output to the dichotomy calculation module.

Step 6: and in the dichotomy calculation module, according to the value of Tune _ state, calculating a new adjusting level based on the current adjusting level, and outputting an adjusting level configuration bit corresponding to the adjusting level to be applied to an adjusting part of the PUF.

And 7: the preceding steps will be automatically repeated at the new regulation stage until the number of 1's in the response value of the PUF is within the threshold range, completing the automatic regulation of the regulation stage of the circuit.

Claims

1. A fast wiring delay deviation calibration method of an arbitration type PUF based on FPGA is characterized in that: the method comprises the following steps of using an automatic adjusting circuit to realize quick calibration of delay deviation, wherein the automatic adjusting circuit consists of a counter, a comparator, a dichotomy calculating module and an excitation storage module; an excitation storage module of the automatic adjusting circuit provides input excitation of the PUF, an adjusting level configuration bit output by a dichotomy calculating module is used as the input of a PUF delay adjusting part, and a counter reads the response of the PUF and counts the number of 1 s in the response; in the automatic adjusting circuit, after an adjusting stage configuration bit is output by a bisection calculating module, an adjusting completion signal connected with a counter module is set to be effective, and a reading signal connected with an excitation storage module is set to be effective; after the input reading signal is effective, the excitation storage module starts to output the stored first excitation to the PUF, and after the last excitation is output, the excitation storage module sets an excitation mark signal connected with the counter to be effective; when the input adjustment completion signal is effective, the counter is cleared, the response of the PUF starts to be accumulated and counted, when the excitation mark signal is effective, the counter stops counting, and the counting result is transmitted to the comparator; in the comparator, according to the relation between the counting result and the set threshold range, outputting an adjusting mark signal for calculating the next adjusting level to the dichotomy calculating module; wherein, the threshold range set in the comparator is calculated according to the total number of the statistical response values and the set error:

Threshold＝N×(50％±e) (1)

wherein N represents the total number of PUF response values, and e represents the tolerance error of randomness;

in the comparator, according to the decreasing relation between the counting result of the number of 1 in the PUF response and the adjusting level, and according to the relation between the counting result and the threshold range, generating the size relation between the next adjusting level and the current adjusting level;

in the comparator, when the statistical result is in the threshold range, the current adjusting stage can compensate the wiring delay deviation, and then an adjusting mark signal is output as 11; if the current calculation result is smaller than the lowest value of the threshold range, the adjustment level to be searched next is smaller than the current adjustment level, and then an adjustment mark signal is output to be 10; if the current calculation result is larger than the maximum value of the threshold range, the adjustment level which is searched next is larger than the current adjustment level, and an adjustment mark signal is output to be 01;

in the dichotomy calculation module, calculating a new adjustment stage according to the value of the adjustment flag signal, and outputting an adjustment stage configuration bit corresponding to the new adjustment stage; firstly, introducing a method for obtaining a corresponding adjusting level configuration bit after calculating a new adjusting level; since the previous adjustment level is stored in Middle _ pre, the new adjustment level calculated is Middle; to configure the bit Tu for the output regulation stage_i，i∈[1,k]From the output Tu [1: Middle _ pre]＝1,Tu[Middle_pre+1:k]0; change to a new trim configuration bit output Tu [1: Middle]＝1,Tu[Middle+1:k]0, it is necessary to do for Tu_iShifting is performed, wherein the direction and number of bits of the shift are calculated by the variation between the adjustment stages:

Shift_bits＝Middle–Middle_pre (2)

wherein, the sign bit of the Shift _ bits represents the direction to be moved, the negative sign represents the leftward Shift, the positive sign represents the rightward Shift, and the value represents the number of bits to be moved; middle represents the calculated new adjustment level; middle _ pre represents the previous adjustment stage;

in the dichotomy calculation module, a state machine is designed, and the functions of calculating a new adjustment level and obtaining a new adjustment level configuration bit are realized by performing state conversion between the state machines through adjusting different values of the sign signals; the four states of the state machine are: start, left-turn state, right-turn state and stop; the functions implemented in each state are as follows:

firstly, in a starting state, the initialization function of some registers is realized; the initial value of the lower boundary of the adjustment interval is 0, the initial value of the upper boundary of the adjustment interval is k, wherein k is the number of programmable delay units contained in the PUF delay adjustment part, the initial value of a new adjustment stage is k/2, the initial value of the current adjustment stage is k/2, and the initial value of a shift flag is 0, wherein the shift flag is used for setting a new adjustment stage configuration bit based on the current adjustment stage configuration bit and is used for setting a flag which needs to be shifted in order to obtain the new adjustment stage configuration bit;

in the left-hand state, three functions are implemented: 1) storing the current trim level Middle in Middle _ pre; 2) updating the adjustment interval to [ Low, Middle ], and calculating the median value in the new interval as a new adjustment level; 3) obtaining and outputting a configuration bit corresponding to the adjustment level;

in the right-hand state, the functions implemented are: 1) storing the current trim level Middle in Middle _ pre; 2) updating the adjustment interval to [ Middle, High ], and calculating the median value in the new interval as a new adjustment level; 3) obtaining and outputting a configuration bit corresponding to the adjustment level;

in the stop state, which indicates the end of the adjustment process, the values in all registers will be kept unchanged;

when the dichotomy calculation module outputs a new adjusting stage configuration bit each time, the adjusting circuit automatically performs a new adjusting process until the number of 1 in the response value of the PUF in the comparator is within a threshold value, and the adjusting process of the circuit is completed; since the number of times the adjustment stage is found is related to the size of the threshold range, an equilibrium between the number of adjustments and the error is found, as desired.

2. The method for rapidly calibrating the wiring delay deviation of the arbitration type PUF based on the FPGA according to claim 1, wherein the method comprises the following steps:

step 1: measuring the randomness of 0 and 1 distribution in response values of two boundary PUFs of the regulating level, and determining the existence of the regulating level to be searched;

step 2: obtaining a first regulating stage configuration bit to send to the PUF circuit by initializing a regulating interval and a regulating stage in the bisection calculation module; meanwhile, setting a starting signal connected with the excitation storage module to be effective, and setting an adjustment finishing signal connected with the counter to be effective;

and step 3: the excitation storage module outputs all stored random excitation to the PUF after the start signal is effective, and sets a completion signal connected with the counter to be effective after excitation output is completed;

and 4, step 4: after detecting that the adjustment completion signal is effective, the counter performs zero clearing operation on an internal calculator and starts to perform accumulated counting on response values of the PUF; when the completion signal from the excitation module is effective, the counter stops counting, sets the counting completion signal to be effective, and outputs the current counting result to the comparator;

and 5: firstly, initializing a threshold range Ref in a comparator; when the comparator detects that the counting completion signal is effective, the input counting value counter is compared with a given threshold range Ref, the size relation of the counting value counter and the given threshold range Ref is judged, and an adjustment state signal is output to the dichotomy calculation module;

step 6: in a dichotomy calculation module, calculating a new adjusting level based on the current adjusting level according to the value of Tune _ state, and outputting an adjusting level configuration bit corresponding to the adjusting level to be applied to an adjusting part of the PUF;