CN116298795A - In-chip finished testing trimming circuit - Google Patents
In-chip finished testing trimming circuit Download PDFInfo
- Publication number
- CN116298795A CN116298795A CN202310253984.3A CN202310253984A CN116298795A CN 116298795 A CN116298795 A CN 116298795A CN 202310253984 A CN202310253984 A CN 202310253984A CN 116298795 A CN116298795 A CN 116298795A
- Authority
- CN
- China
- Prior art keywords
- counter
- trimming
- signal
- input end
- decoder
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000009966 trimming Methods 0.000 title claims abstract description 106
- 238000012360 testing method Methods 0.000 title claims abstract description 38
- 230000000630 rising effect Effects 0.000 claims description 11
- 238000011161 development Methods 0.000 abstract description 9
- 230000009286 beneficial effect Effects 0.000 abstract description 3
- 230000008439 repair process Effects 0.000 abstract description 2
- 238000000034 method Methods 0.000 description 15
- 230000008569 process Effects 0.000 description 15
- 238000007664 blowing Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 239000013256 coordination polymer Substances 0.000 description 2
- 230000001419 dependent effect Effects 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000012356 Product development Methods 0.000 description 1
- 230000006978 adaptation Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 230000002035 prolonged effect Effects 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
The invention relates to the technical field of chip testing, in particular to an integrated testing trimming circuit in a chip, which comprises the following components: the input end of the first counter is connected to the signal pin of the chip; the signal pin receives a clock pulse signal; the first input end of the second counter is connected with the output end of the first counter, the second input end of the second counter is connected with the signal pin, and the third input end of the second counter is connected to the enabling pin; the enable pin receives an enable signal; the first input end of the decoder is connected with the second counter, and the second input end of the decoder is connected with the enabling pin; and the input end of the fuse array unit is connected with the decoder. The beneficial effects are that: through setting up first counter, second counter and the decoder that connects gradually, realized reading, judgement, the decoding of the clock pulse signal of external input, and then control fuse array unit and repair the adjustment to the circuit in the chip, this scheme can control the fuse array unit of arbitrary digit, is convenient for multiplex on different grade type's chip, has reduced development cost.
Description
Technical Field
The invention relates to the technical field of chip testing, in particular to an integrated testing trimming circuit in a chip.
Background
The circuit parameters deviate from the expected target values due to process fluctuation in the chip flow process, so that the parameter precision is reduced, and even the parameter precision exceeds the specification range, thereby reducing the yield of the chip; on the other hand, because some circuits need to realize different functions, if the circuit and the flow sheet are redesigned, higher cost is generated, and the product development period is prolonged, so that the circuit precision and the yield are ensured, meanwhile, the circuit function can be more conveniently changed according to the requirements of customers, engineers can design a trimming circuit in the initial stage of circuit design, after the chip production is finished, the key parameters are tested, and the precision is improved by adopting a trimming technology according to the test result. At present, two general types of trimming technologies exist, one is to complete trimming in the middle test stage and the other is to complete trimming in the finished test stage. The common trimming and adjusting modes in the middle measuring stage are as follows: the laser trimming and pin powering up trimming are two kinds, and the characteristic of this trimming mode is: the circuit implementation is simple, but errors due to packaging cannot be avoided, which cannot be met for products with high precision requirements. And the test trimming is to finish trimming the parameters according to the test result after the chip is packaged, so that the tiny errors introduced by the package can be effectively avoided, and the parameter value is closer to the central value.
In the prior art, there are technical solutions for testing and trimming packaged chips. The technical scheme is that corresponding trimming pins are reserved on a chip package, and trimming operation of a circuit in the chip is realized by inputting corresponding trimming signals according to a test result after the test is finished.
However, in the practical implementation process, the inventor finds that, in the trimming circuit in the prior art, in order to achieve a better trimming effect on the circuit in the chip, a plurality of fusing branches are often required to be set for fusing respectively, and because different types of fusing branches with different numbers of bits are often arranged on different types of chips, when the fusing branches on different chips are controlled, different types of trimming control circuits are required to be adopted, which results in that the trimming control circuits between different chips cannot be directly reused, need to be re-developed, and may cause a further increase in chip area in the re-development process.
Disclosure of Invention
Aiming at the problems in the prior art, a finished test trimming circuit in a chip is provided.
The specific technical scheme is as follows:
an on-chip test trimming circuit comprising:
the input end of the first counter is connected to the signal pin of the chip;
the signal pin receives a clock pulse signal input from the outside, and the first counter controls the test trimming circuit to enter a trimming mode according to the clock pulse signal;
the first input end of the second counter is connected with the output end of the first counter, the second input end of the second counter is connected with the signal pin, and the third input end of the second counter is connected with the enabling pin of the chip;
the enabling pin receives an enabling signal input from the outside;
when the test trimming circuit enters a trimming mode, the second counter generates a trimming counting result according to the clock pulse signal under the control of the enabling signal;
the first input end of the decoder is connected with the output end of the second counter, and the second input end of the decoder is connected with the enabling pin;
the decoder generates a decoding result according to the counting result;
and the input end of the fuse array unit is connected with the output end of the decoder so as to receive the decoding result.
Preferably, the first counter counts rising edges of the clock pulse signal and generates a pattern count result;
when the mode counting result reaches a first threshold, the first counter outputs a trimming control signal to control the testing trimming circuit to enter a trimming mode.
Preferably, the enable signal transitions from a high level to a low level or from a low level to a high level while the mode count result reaches the first threshold;
when the second counter receives the trimming control signal and the level of the enabling signal is inverted, the second counter counts the rising edge of the clock pulse signal and generates the trimming counting result.
Preferably, the fuse array unit includes a plurality of blowing branches, and the fuse array unit selects the corresponding blowing branches to blow according to the decoding result and the number of fuses of the fuse array unit.
Preferably, the trimming counting result is input to the decoder through a counting pulse signal;
the decoder counts the counting pulse signals to generate the decoding result;
when the enable signal is level-inverted, the decoder stops counting the count pulse signal.
Preferably, the fusing branch circuit includes an input terminal and a ground terminal, the input terminal being connected to an on-chip circuit of the chip;
a fuse and a switching tube are sequentially connected in series between the input end and the grounding end;
the grid electrode of the switching tube is connected to the controlled end of the fusing branch circuit;
the fuse array unit blows the fuse by controlling the switching tube to be turned on.
Preferably, the first counter is a 2-bit binary addition counter and is composed of three class D flip-flops.
Preferably, the second counter is a binary addition counter, and is composed of a plurality of class D flip-flops in cascade connection.
Preferably, the first threshold is 5 rising edges.
Preferably, the number of bits of the second counter is determined according to the number of fusing branches.
The technical scheme has the following advantages or beneficial effects: by arranging the first counter, the second counter and the decoder which are sequentially connected, the externally input clock pulse signals are read, judged and decoded, and then the fuse array unit is controlled to be trimmed. In the process, the trimming bit number of the circuit is only dependent on the bit number of the counter, and the effective control of the fuse array unit with any trimming bit can be realized by changing the bit number of the counter, so that the multiplexing of the trimming circuit in different chips is realized, the development cost is reduced, and the problem that the chip area is possibly increased in the redevelopment process is avoided.
Drawings
Embodiments of the present invention will now be described more fully with reference to the accompanying drawings. The drawings, however, are for illustration and description only and are not intended as a definition of the limits of the invention.
FIG. 1 is an overall schematic of an embodiment of the present invention;
FIG. 2 is a schematic diagram of input signals according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a fuse array unit according to an embodiment of the invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
It should be noted that, without conflict, the embodiments of the present invention and features of the embodiments may be combined with each other.
The invention is further described below with reference to the drawings and specific examples, which are not intended to be limiting.
The invention comprises the following steps:
an on-chip test trimming circuit, as shown in fig. 1, comprises:
the first counter 1, the input end of the first counter 1 is connected to the signal pin TR_CP of the chip;
the first input end of the second counter 2 is connected with the output end of the first counter 1, the second input end of the second counter 2 is connected with the signal pin TR_CP, and the third input end of the second counter 2 is connected with the enable pin TR_CON of the chip;
the first input end of the decoder 3 is connected with the output end of the second counter 2, and the second input end of the decoder 3 is connected with the enable pin TR_CON;
and the input end of the fuse array unit 4 is connected with the output end of the decoder 3.
Specifically, aiming at the problem that the development cost is raised because the test trimming circuit in the prior art is applied to different chips and redesigned according to different directions of the fusing branch circuits, the embodiment realizes the receiving and reading processes of the input clock pulse signals by arranging the first counter 1, the second counter 2 and the decoder 3 which are sequentially connected, and further controls the fuse array unit 4 to fuse, so that the control of the fusing branch circuits with any number of bits can be realized only by changing the bits of the first counter 1 and the second counter 2 while trimming the circuits in the chips, thereby reducing the device cost.
In a preferred embodiment, the signal pin tr_cp receives a clock pulse signal inputted from the outside;
the first counter 1 counts rising edges of the clock pulse signals and generates a mode counting result;
when the mode counting result reaches a first threshold, the first counter outputs a trimming control signal to control the trimming circuit to enter a trimming mode.
Specifically, the development cost is increased for the repair circuit to be tested again according to different chips, and the problem that the chip area is further increased possibly is caused in the redesign process.
In operation, as shown in fig. 2, the signal pin tr_cp receives an externally input clock signal, which is generated by an external test instrument or other device. After the chip is tested, the device generates a corresponding clock pulse signal according to the test result to control the test trimming circuit, so that trimming of the chip is realized.
The clock pulse signal comprises a first part and a second part which are sequentially arranged, wherein the first part is a signal for controlling the test trimming circuit to enter a trimming mode, and the clock pulse signal comprises a specific number of pulse signals serving as control signals. The first counter 1 confirms that the currently-tested trimming circuit enters the trimming mode by counting the part. The second part is a trimming bit which is controlled to trim a specific fusing branch by the trimming circuit by inputting a specific number of pulse signals.
In a preferred embodiment, the enable pin tr_con receives an enable signal from an external input;
when the mode counting result reaches a first threshold value, the enabling signal is changed from a high level to a low level or from the low level to the high level;
when the second counter 2 receives the trimming control signal and the level of the enable signal is inverted, the second counter 2 counts the rising edge of the clock pulse signal and generates a trimming count result.
Specifically, the test trimming circuit is designed again according to different chips, which causes an increase in development cost and may cause a further increase in chip area in the redesign process, and in this embodiment, the first counter 1 and the enable pin tr_con are set to trigger the second counter 2 at the same time, so that the second counter 2 counts the rising edge of the clock pulse signal when receiving the signal flip and the trimming control signal of the first counter 1, so as to obtain a trimming counting result for representing any trimming bit number, and further realize a better adaptation effect on chips with different trimming bits.
In an implementation, as shown in fig. 2, the clock pulse signal is sent while the enable signal remains high while the pulse signal of the first portion is sent. And after the first part of the clock pulse signal is sent, the enabling signal is turned to a low level, and meanwhile, the first counter 1 counts the clock pulse signal, judges that the clock pulse signal enters a trimming mode and generates a trimming control signal. The second counter 2 starts counting the clock pulse signal after receiving the trimming control signal and the level inversion of the enable signal to obtain the trimming bit portion of the clock pulse signal.
In a preferred embodiment, the decoder 3 generates a decoding result according to the trimming count result and inputs the decoding result to the fuse array unit 4;
the fuse array unit 4 includes a plurality of blowing branches, and the fuse array unit 4 selects a corresponding blowing branch to blow according to the decoding result and the number of fuses of the fuse array unit 4.
Specifically, the test trimming circuit needs to be re-tuned for different chips, which causes an increase in development cost and may cause a further increase in chip area during the redesign process, and in this embodiment, the second counter 2 and the decoder 3, which are sequentially connected, are provided to process signals. When the test trimming circuit enters a trimming mode, the second counter 2 counts the pulse number of the clock pulse signal from 0, outputs the trimming counting result generated each time on the pulse rising edge as an input signal of the decoder, so that the decoder 3 can directly control the fuse array unit 4 by decoding the trimming counting result, and can trim the fuse array unit 4 with any bit number by adjusting the bit numbers of the first counter 1 and the second counter 2 in the control process, thereby saving the cost of redevelopment into the test trimming circuit.
In a preferred embodiment, the trimming count result is input to the decoder 3 via a count pulse signal;
the decoder 3 counts the count pulse signals to generate a decoding result;
when the enable signal is level-inverted, the decoder stops counting the count pulse signal.
Specifically, for the test trimming circuit in the prior art, the test trimming circuit is required to be re-tested for different chips, so that development cost is increased, and the problem that the chip area is further increased possibly is caused in the redesign process.
In practice, as shown in fig. 2, the enable signal is held low while the second counter 2 receives the trimming bit, at which time the second counter 2 and the decoder 3 cooperate to obtain the trimming bit. When the trimming bit is sent, the enable signal is level-inverted, so that the decoder 3 knows that the trimming bit is sent, and the decoder 3 sends the decoding result to the fuse array unit 4.
In a preferred embodiment, as shown in FIG. 3, the fuse branch includes an input terminal and a ground terminal, the input terminal being connected to the on-chip circuitry of the chip;
a Fuse wire Fuse 1-Fuse n and a switch tube M1-Mn are sequentially connected in series between the input end and the grounding end;
the grid electrodes of the switching tubes M1-Mn are connected to the controlled end of the fusing branch circuit;
the Fuse array unit 4 is turned on by controlling the switching transistors M1 to Mn to blow the fuses Fuse 1 to Fuse n.
Specifically, in order to achieve a better trimming effect on the on-chip circuit, in this embodiment, a plurality of fusing branches composed of fuses Fuse 1 to Fuse n and switching tubes M1 to Mn are respectively provided, and after the decoder 3 outputs a decoding result, the switching tubes M1 to Mn in the Fuse array unit 4 are controlled to be turned on according to the decoding result to blow the fuses, so that a better trimming effect on the on-chip circuit is achieved.
In a preferred embodiment, the first counter 1 is a 2-bit binary addition counter, consisting of three class D flip-flops.
In a preferred embodiment, the second counter 2 is a binary addition counter, consisting of a cascade of a plurality of class D flip-flops.
In a preferred embodiment, the first threshold is 5 rising edges.
In a preferred embodiment, the number of bits of the second counter 2 is determined according to the number of fused branches.
Specifically, to the problem that in the prior art, different testing trimming circuits need to be redesigned and the multiplexing rate is poor, in this embodiment, the second counter 2 is set to be an addition counter formed by cascading a plurality of D-type triggers, so that the testing trimming circuit can adjust the number of cascaded D-type triggers according to the number of the fusing branches, and then change the number of bits of the second counter 2, thereby enabling the circuit to be multiplexed on different chips very conveniently and reducing the research and development cost.
The invention has the beneficial effects that: by arranging the first counter, the second counter and the decoder which are sequentially connected, the externally input clock pulse signals are read, judged and decoded, and then the fuse array unit is controlled to be trimmed. In the process, the trimming bit number of the circuit is only dependent on the bit number of the counter, and the effective control of the fuse array unit with any trimming bit can be realized by changing the bit number of the counter, so that the multiplexing of the trimming circuit in different chips is realized, the development cost is reduced, and the problem that the chip area is possibly increased in the redevelopment process is avoided.
The foregoing is merely illustrative of the preferred embodiments of the present invention and is not intended to limit the embodiments and scope of the present invention, and it should be appreciated by those skilled in the art that equivalent substitutions and obvious variations may be made using the description and illustrations of the present invention, and are intended to be included in the scope of the present invention.
Claims (10)
1. An on-chip test trimming circuit, comprising:
the input end of the first counter is connected to the signal pin of the chip;
the signal pin receives a clock pulse signal input from the outside, and the first counter controls the test trimming circuit to enter a trimming mode according to the clock pulse signal;
the first input end of the second counter is connected with the output end of the first counter, the second input end of the second counter is connected with the signal pin, and the third input end of the second counter is connected with the enabling pin of the chip;
the enabling pin receives an enabling signal input from the outside;
when the test trimming circuit enters a trimming mode, the second counter generates a trimming counting result according to the clock pulse signal under the control of the enabling signal;
the first input end of the decoder is connected with the output end of the second counter, and the second input end of the decoder is connected with the enabling pin;
the decoder generates a decoding result according to the counting result;
and the input end of the fuse array unit is connected with the output end of the decoder so as to receive the decoding result.
2. The trimming circuit of claim 1, wherein the first counter counts rising edges of the clock signal and generates a pattern count result;
when the mode counting result reaches a first threshold, the first counter outputs a trimming control signal to control the testing trimming circuit to enter a trimming mode.
3. The trimming circuit according to claim 2, wherein,
when the mode counting result reaches the first threshold value, the enabling signal is changed from a high level to a low level or from a low level to a high level;
when the second counter receives the trimming control signal and the level of the enabling signal is inverted, the second counter counts the rising edge of the clock pulse signal and generates the trimming counting result.
4. The trimming circuit according to claim 1, wherein the fuse array unit includes a plurality of fusing branches, and the fuse array unit selects the corresponding fusing branches to fuse according to the decoding result and the number of fuses of the fuse array unit.
5. The trimming circuit for test according to claim 4, wherein the trimming count result is inputted to the decoder by a count pulse signal;
the decoder counts the counting pulse signals to generate the decoding result;
when the enable signal is level-inverted, the decoder stops counting the count pulse signal.
6. The trimming circuit of claim 4, wherein the fusing branch circuit comprises an input terminal and a ground terminal, the input terminal being connected to an on-chip circuit of the chip;
a fuse and a switching tube are sequentially connected in series between the input end and the grounding end;
the grid electrode of the switching tube is connected to the controlled end of the fusing branch circuit;
the fuse array unit blows the fuse by controlling the switching tube to be turned on.
7. The trimming circuit of claim 1, wherein the first counter is a 2-bit binary addition counter consisting of three class D flip-flops.
8. The trimming circuit of claim 1, wherein the second counter is a binary addition counter comprising a cascade of a plurality of class D flip-flops.
9. The trimming circuit of claim 2, wherein the first threshold is 5 rising edges.
10. The trimming circuit of claim 4, wherein the number of bits of the second counter is determined based on the number of fused branches.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310253984.3A CN116298795A (en) | 2023-03-14 | 2023-03-14 | In-chip finished testing trimming circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310253984.3A CN116298795A (en) | 2023-03-14 | 2023-03-14 | In-chip finished testing trimming circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN116298795A true CN116298795A (en) | 2023-06-23 |
Family
ID=86837481
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202310253984.3A Pending CN116298795A (en) | 2023-03-14 | 2023-03-14 | In-chip finished testing trimming circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN116298795A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115567050A (en) * | 2022-08-30 | 2023-01-03 | 贵州振华风光半导体股份有限公司 | Fuse trimming circuit |
-
2023
- 2023-03-14 CN CN202310253984.3A patent/CN116298795A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115567050A (en) * | 2022-08-30 | 2023-01-03 | 贵州振华风光半导体股份有限公司 | Fuse trimming circuit |
| CN115567050B (en) * | 2022-08-30 | 2023-10-24 | 贵州振华风光半导体股份有限公司 | Fuse trimming circuit |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6034548A (en) | Programmable delay element | |
| US7295057B2 (en) | Methods and apparatus for characterizing electronic fuses used to personalize an integrated circuit | |
| US6133751A (en) | Programmable delay element | |
| CN116298795A (en) | In-chip finished testing trimming circuit | |
| KR20000005251A (en) | Apparatus and method for providing a programmable delay | |
| JPH07170162A (en) | Variable impedance delay device | |
| US4697140A (en) | Semiconductor integrated circuit having a test circuit for testing an internal circuit | |
| US7791367B1 (en) | Driver with selectable output impedance | |
| CN105575436B (en) | Programmable control poly fuse circuit and integrated circuit comprising same | |
| CN114814556B (en) | Efficient integrated circuit chip trimming test circuit and test method | |
| CN107743035B (en) | Chip trimming circuit and trimming method | |
| US5345112A (en) | Integrated circuit with programmable speed/power adjustment | |
| US6448799B1 (en) | Timing adjustment method and apparatus for semiconductor IC tester | |
| JPH1166862A (en) | Semiconductor memory | |
| US7183829B2 (en) | Semiconductor device including a plurality of circuit blocks provided on a chip and having different functions | |
| KR0140030B1 (en) | Fusing system | |
| KR100387192B1 (en) | Semiconductor device having an internal power supply circuit | |
| JPH04321320A (en) | Buffer circuit | |
| US5459734A (en) | Test circuit for signal input circuit having threshold | |
| JPH08204582A (en) | Semiconductor integrated circuit | |
| KR100593139B1 (en) | Counter circuit for controlling off chip driver and method for changing output current value of off chip driver using the same | |
| JP2000201058A (en) | Semiconductor device | |
| KR20020061233A (en) | Auto fusing circuit | |
| KR100366833B1 (en) | Method of generating pattern for integrated circuit | |
| KR102233516B1 (en) | Otp memory control system, programming and read circuitry for small pin package otp memory |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |