CN102339338A - Time sequence repairing method - Google Patents
Time sequence repairing method Download PDFInfo
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- CN102339338A CN102339338A CN2010102341765A CN201010234176A CN102339338A CN 102339338 A CN102339338 A CN 102339338A CN 2010102341765 A CN2010102341765 A CN 2010102341765A CN 201010234176 A CN201010234176 A CN 201010234176A CN 102339338 A CN102339338 A CN 102339338A
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Abstract
The invention discloses a time sequence repairing method, which is used for solving the problem of increase in chip design area caused by repair of a time sequence circuit during integrated circuit application by intervening with a clock channel and transferring a part of design problems of a data channel onto the clock channel. The method comprises the following steps of: analyzing the characteristic of a time sequence violating example; analyzing routes in which violating examples exists; when all routes of which start points serve as start points are provided with sufficient build-up time margins and all routes of which start points serve as end points are provided with sufficient build-up time margins, repairing and keeping a time sequence by increasing the clock delays of the start points of the routes; and when all routes of which end points serve as end points are provided with sufficient build-up time margins and all routes of which end points serve as start points are provided with sufficient build-up time margins, repairing and keeping a time sequence by decreasing the clock delays of the end points of the routes. In the method disclosed by the invention, different clock delay design modes are selected, so that the circuit complexity of the integrated circuit chip design can be lowered effectively, and the chip design area is reduced.
Description
Technical field
The present invention relates to a kind of sequential restorative procedure, relate in particular to the method that sequential is repaired in a kind of integrated circuit diagram design.
Background technology
Current multimedia has obtained general application in daily life.No matter mobile phone, TV, still game machine, the design of its product chips all need perfect function and travelling speed fast.Speed decision performance of products, and the area of chip design has directly determined production cost.Therefore guaranteeing also must to guarantee to have enough fast travelling speed and enough little chip design area under the correct prerequisite of product function.
Travelling speed and the design area principal element of decision IC chip have several aspects: production technology, code volume style, code are to the implementation procedure of domain etc.In the domain implementation procedure, repair one of important often committed step of sequential at code.Traditional implementation method is handled and is kept the sequential reparation to adopt inserting a large amount of impact dampers, (D wherein shown in traditional the Application Design mode such as accompanying drawing 2
nBe data path, clk is a clock, and two clock branch roads are m at the progression of balance posterior bumper).Such design can increase the design area of chip, thereby can increase production cost.
Sequential in the IC design is violated nothing more than being to be caused inadequately by Time Created and retention time.When generally we do the clock via design, require its different branches to have identical delay.When the sequential of critical data path in the high frequency chip is relatively harsher, can consider to interfere the clock path.How to pass through the intervention to the clock path, make the harsh conditions of data path partly transfer on the clock path, sequential is restrained fast becomes technical matters to be solved by this invention.
Summary of the invention
The object of the invention provides a kind of sequential restorative procedure, solves in integrated circuit is used the problem that the chip design area that reparation brought by sequential circuit strengthens.Be implemented under the prerequisite that guarantees the sequential circuit operate as normal, reduce the chip design area, thereby reduce production costs.
The present invention relates to a kind of sequential restorative procedure, comprise following implementation content:
(1) the analysis sequential is violated the characteristics of example, finds out and violates routine starting point and terminal point and affiliated clock forehearth limb;
(2) analysis is against the path of counter-example;
(3) when all starting points be that the path of starting point has enough surpluses Time Created, and all starting points are that the path of terminal point has enough retention times during surplus, get into step (4); When all terminal points are that the path of terminal point has enough surpluses Time Created, and all terminal points are that the path of starting point has enough retention times during surplus, get into step (5);
(4) adopt the mode of the clock delay that strengthens the path starting point to repair the maintenance sequential;
(5) adopt the mode of the clock delay that shortens path termination to repair the maintenance sequential;
(6) reparation of the whole maintenance sequential of completion.
Violate the characteristics of example in the step (1), comprise one of following situation and can adopt method provided by the present invention to repair:
1. a large amount of violation examples occurs on two interfaces between the physical division, and its related register or latch belong to same clock zone in physical division inside separately;
2. a large amount of violation examples occurs in two fully independently in the clock branch;
3. a large amount of violation examples occurs on the relevant path of storer;
4. a large amount of violation examples occurs on the same starting point;
5. a large amount of violation examples occur on the same terminal point.
In step (3), when all satisfying simultaneously, both can select to get into step (4) as if the condition that gets into step (4) and step (5), also can select to get into (5).
In step (4), find the clock forehearth limb root node of this path starting point, according to the value of violating example, insert the corresponding buffers number.Insert the number N=D/d of impact damper, wherein D is for violating the value of example, and d is the time-delay of an impact damper under equal operating environment.If N comprises remainder, then number adds 1.The node condition of inserting impact damper is: the starting point that 1. can arrive all concerns; 2. and can not arrive and contain all terminal points of violating example.For bottom line reduces the negative effect that the back operation brings; This node preferably can not arrive all registers or the latch except that starting point; Only if with these registers or latch is that also to satisfy all starting points that relate in the step (3) be that the path of starting point has enough surpluses Time Created all paths of terminal point, and all starting points are the condition that there are enough retention time surpluses in the path of terminal point.
In step (5), find the clock forehearth limb root node of this path termination, according to the value of violating example, deletion corresponding buffers number must have enough impact dampers can supply deletion in this clock forehearth limb.The condition of deletion buffer node is:
3. can reach all terminal points of being paid close attention to;
4. can not reach and contain all starting points of violating example;
For operating the negative effect that brings in the MIN back that reduces; This node preferably can not arrive all registers or the latch except that terminal point; Only if with these registers or latch is that also to satisfy all terminal points that relate in the step (3) be that the path of terminal point has enough surpluses Time Created all paths of starting point, and all terminal points are the condition that there are enough retention time surpluses in the path of starting point.
Through content proposed by the invention, according to practical application, select the design of different clock delays, can effectively reduce the circuit complexity of design of integrated circuit, reduce the design area of chip, effectively practiced thrift resource when raising the efficiency again.
Description of drawings
The basic flow sheet of a kind of sequential restorative procedure of Fig. 1
A kind of traditional sequential of Fig. 2 is repaired electrical block diagram
Fig. 3 adopts the mode of the clock delay that strengthens the path starting point to repair the circuit diagram of sequential
Fig. 4 adopts the mode of the clock delay that shortens path termination to repair the circuit diagram of sequential
Specific embodiments
Below in conjunction with each accompanying drawing content proposed by the invention is carried out detailed description.Fig. 1 is the basic flow sheet of sequential restorative procedure involved in the present invention, has comprised each implementation step of the present invention.
(1) the analysis sequential is violated the characteristics of example, finds out and violates routine starting point and terminal point and affiliated clock forehearth limb.
When the characteristics of violating example meet one of following condition, can adopt sequential restorative procedure provided by the present invention to repair:
1. a large amount of violation examples occurs on two interfaces between the physical division, and its related register or latch belong to same clock zone in physical division inside separately;
2. a large amount of violation examples occurs in two fully independently in the clock branch;
3. a large amount of violation examples occurs on the relevant path of storer;
4. a large amount of violation examples occurs on the same starting point;
5. a large amount of violation examples occur on the same terminal point.
(2) analysis is against the path of counter-example
(3) all starting points are that the path of starting point has enough surpluses Time Created, and all starting points are that the path of terminal point has enough retention times during surplus, get into step (4); All terminal points are that the path of terminal point has enough surpluses Time Created, and all terminal points are that the path of starting point has enough retention times during surplus, get into step (5).
In this step, when all satisfying simultaneously, both can select to get into step (4), and also can select to get into (5) as if the condition that gets into step (4) and step (5).
(4) adopt the mode of the clock delay that strengthens the path starting point to repair the maintenance sequential
Find the clock forehearth limb root node of this path starting point,, insert the corresponding buffers number according to the value of violating example.Insert the data N=D/d of impact damper, wherein D is for violating the value of example, and d is the time-delay of an impact damper under equal operating environment.If N comprises remainder, then number adds 1.The node condition of inserting impact damper is: the starting point that 1. can arrive all concerns; 2. and can not arrive and contain all terminal points of violating example.For bottom line reduces the negative effect that the back operation brings; This node preferably can not arrive all registers or the latch except that starting point; Only if with these registers or latch is that also to satisfy all starting points that relate in the step (3) be that the path of starting point has enough surpluses Time Created all paths of terminal point, and all starting points are the condition that there are enough retention time surpluses in the path of terminal point.
Than classic method, suppose that the violation example of the type has H, then need increase H*N impact damper, and this method has only increased N impact damper, has practiced thrift the area of chip design.As shown in Figure 3.
Because of having prolonged the time-delay of clock forehearth limb; So all registers or the sequential of latch to hanging in this clock branch will have following influence: 1. be all paths of terminal point with these registers or latch; The retention time surplus can reduce N*d (d is the time-delay of an impact damper under equal operating environment); If surplus originally is not enough, then can forms new maintenance and violate example; 2. be all paths of starting point with these registers or latch, Time Created, surplus can reduce N*d, if original surplus is not enough, then can forms new foundation and violate example.
If the clock forehearth limb node of selecting to insert impact damper can't satisfy condition fully, just might produce these new violation examples, need compensatory sequential reparation operation.
(5) adopt the mode of the clock delay that shortens path termination to repair the maintenance sequential
Find the clock forehearth limb root node of this path termination, according to the value of violating example, deletion corresponding buffers number must have enough impact dampers can supply deletion in this clock forehearth limb.The condition of deletion buffer node is: 1. can reach all terminal points of being paid close attention to; 2. can not reach and contain all starting points of violating example.
For operating the negative effect that brings in the MIN back that reduces; This node preferably can not arrive all registers or the latch except that terminal point; Only if with these registers or latch is that also to satisfy all terminal points that relate in the step (3) be that the path of terminal point has enough surpluses Time Created all paths of starting point, and all terminal points are the condition that there are enough retention time surpluses in the path of starting point.
Need increase the scheme of H*N impact damper than tradition, N impact damper of this method deletion do not increase any unit, practiced thrift the area of chip design.As shown in Figure 4.
Because of shortening this clock forehearth limb time-delay; So all registers or the sequential of latch to hanging in this clock branch will have following influence: 1. be all paths of terminal point with these registers or latch; Surplus will reduce N*d Time Created; If surplus originally is not enough, will forms and violate example new Time Created; 2. be all paths of starting point with these registers or latch, the retention time surplus will reduce N*d (d is the time-delay of an impact damper under equal operating environment), if original surplus is not enough, will form new retention time violation example.If select the clock forehearth limb node of deletion impact damper to satisfy condition fully, just might produce these new violation examples, need compensatory sequential reparation operation.
(6) reparation of the whole maintenance sequential of completion.
Claims (9)
1. sequential restorative procedure is characterized in that: comprise following implementation step:
(1) the analysis sequential is violated the characteristics of example, finds out and violates routine starting point and terminal point and affiliated clock forehearth limb;
(2) analysis is against the path of counter-example;
(3) when all starting points be that the path of starting point has enough surpluses Time Created, and all starting points are that the path of terminal point has enough retention times during surplus, get into step (4); When all terminal points are that the path of terminal point has enough surpluses Time Created, and all terminal points are that the path of starting point has enough retention times during surplus, get into step (5);
(4) adopt the mode of the clock delay that strengthens the path starting point to repair the maintenance sequential;
(5) adopt the mode of the clock delay that shortens path termination to repair the maintenance sequential;
(6) reparation of the whole maintenance sequential of completion.
2. a kind of sequential restorative procedure as claimed in claim 1 is characterized in that: the said characteristics of violating example comprise one of following condition and can be for further processing:
1. a large amount of violation examples occurs on two interfaces between the physical division, and its related register or latch belong to same clock zone in physical division inside separately;
2. a large amount of violation examples occurs in two fully independently in the clock branch;
3. a large amount of violation examples occurs on the relevant path of storer;
4. a large amount of violation examples occurs on the same starting point;
5. a large amount of violation examples occur on the same terminal point.
3. a kind of sequential restorative procedure as claimed in claim 1; It is characterized in that: when the condition of entering step (4) and (5) satisfies simultaneously in the said step (3), can select to adopt the mode of the clock delay that strengthens the path starting point to repair the maintenance sequential or adopt the mode of the clock delay that shortens path termination to repair the maintenance sequential.
4. a kind of sequential restorative procedure as claimed in claim 1; It is characterized in that: said step (4) adopts the mode of the clock delay that strengthens the path starting point to repair when keeping sequential; Find the clock forehearth limb root node of this path starting point,, insert number of buffers according to the value of violating example.
5. like claim 1 or 4 described a kind of sequential restorative procedures, it is characterized in that: the number of buffers N=D/d of said insertion, wherein D is for violating the value of example, and d is the time-delay of an impact damper under equal operating environment.
6. a kind of sequential restorative procedure as claimed in claim 5 is characterized in that: when said number of buffers calculated value comprised remainder, number added 1.
7. a kind of sequential restorative procedure as claimed in claim 4, it is characterized in that: the condition of said insertion buffer node is:
1. can arrive the starting point of all concerns;
2. and can not arrive and contain all terminal points of violating example.
8. a kind of sequential restorative procedure as claimed in claim 1; It is characterized in that: said step (5) adopts the mode of the clock delay that shortens path termination to repair the maintenance sequential; Find the clock forehearth limb root node of this path termination, according to the value of violating example, deletion corresponding buffers number.
9. like claim 1 or 8 described a kind of sequential restorative procedures, it is characterized in that: the node condition of said deletion impact damper is:
1. can reach all terminal points of being paid close attention to;
2. can not reach and contain all starting points of violating example.
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| CN 201010234176 CN102339338B (en) | 2010-07-22 | 2010-07-22 | Time sequence repairing method |
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| CN 201010234176 CN102339338B (en) | 2010-07-22 | 2010-07-22 | Time sequence repairing method |
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Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104639124A (en) * | 2013-11-08 | 2015-05-20 | 联芯科技有限公司 | Method and circuit for improving margin for setup time and hold time of input signal of time sequence device |
| CN104714842A (en) * | 2013-12-17 | 2015-06-17 | 北京华大九天软件有限公司 | Method for repairing time sequence violation through adjusting clock path delay |
| CN106874593A (en) * | 2017-02-13 | 2017-06-20 | 上海兆芯集成电路有限公司 | Digital electronics design method of adjustment and server |
| CN107862154A (en) * | 2017-11-29 | 2018-03-30 | 成都锐成芯微科技股份有限公司 | A kind of timing adjusting method |
| CN108170956A (en) * | 2017-12-28 | 2018-06-15 | 佛山中科芯蔚科技有限公司 | The sequential signing method and device of a kind of retention time |
| CN110111020A (en) * | 2019-05-16 | 2019-08-09 | 天津飞腾信息技术有限公司 | Retention time restorative procedure, system and medium based on automatic assessment settling time surplus |
| CN110377922A (en) * | 2018-04-12 | 2019-10-25 | 龙芯中科技术有限公司 | Retention time fault restorative procedure, device and equipment |
| CN112214097A (en) * | 2020-10-20 | 2021-01-12 | 天津飞腾信息技术有限公司 | Method, device, equipment and storage medium for reducing low threshold unit |
| CN112597739A (en) * | 2020-12-30 | 2021-04-02 | 瓴盛科技有限公司 | Method and apparatus for repairing hold time violations in a circuit |
| CN112783065A (en) * | 2021-01-08 | 2021-05-11 | 重庆百瑞互联电子技术有限公司 | Time sequence circuit optimization method, device and storage medium thereof |
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Cited By (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104639124A (en) * | 2013-11-08 | 2015-05-20 | 联芯科技有限公司 | Method and circuit for improving margin for setup time and hold time of input signal of time sequence device |
| CN104714842A (en) * | 2013-12-17 | 2015-06-17 | 北京华大九天软件有限公司 | Method for repairing time sequence violation through adjusting clock path delay |
| CN104714842B (en) * | 2013-12-17 | 2018-04-13 | 北京华大九天软件有限公司 | It is a kind of to adjust clock path delay to repair the method for sequential violation |
| CN106874593B (en) * | 2017-02-13 | 2020-11-13 | 上海兆芯集成电路有限公司 | Digital electronic device design adjustment method and server |
| CN106874593A (en) * | 2017-02-13 | 2017-06-20 | 上海兆芯集成电路有限公司 | Digital electronics design method of adjustment and server |
| CN107862154A (en) * | 2017-11-29 | 2018-03-30 | 成都锐成芯微科技股份有限公司 | A kind of timing adjusting method |
| CN108170956A (en) * | 2017-12-28 | 2018-06-15 | 佛山中科芯蔚科技有限公司 | The sequential signing method and device of a kind of retention time |
| CN110377922A (en) * | 2018-04-12 | 2019-10-25 | 龙芯中科技术有限公司 | Retention time fault restorative procedure, device and equipment |
| CN110111020A (en) * | 2019-05-16 | 2019-08-09 | 天津飞腾信息技术有限公司 | Retention time restorative procedure, system and medium based on automatic assessment settling time surplus |
| CN110111020B (en) * | 2019-05-16 | 2021-03-02 | 天津飞腾信息技术有限公司 | Method, system and medium for repairing retention time based on automatic evaluation of establishment time margin |
| CN112214097A (en) * | 2020-10-20 | 2021-01-12 | 天津飞腾信息技术有限公司 | Method, device, equipment and storage medium for reducing low threshold unit |
| CN112214097B (en) * | 2020-10-20 | 2021-11-05 | 飞腾信息技术有限公司 | Method, device, equipment and storage medium for reducing low threshold unit |
| CN112597739A (en) * | 2020-12-30 | 2021-04-02 | 瓴盛科技有限公司 | Method and apparatus for repairing hold time violations in a circuit |
| CN112783065A (en) * | 2021-01-08 | 2021-05-11 | 重庆百瑞互联电子技术有限公司 | Time sequence circuit optimization method, device and storage medium thereof |
| CN112783065B (en) * | 2021-01-08 | 2022-01-28 | 重庆百瑞互联电子技术有限公司 | Time sequence circuit optimization method, device and storage medium thereof |
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