CN110619166B - Design method of low-power-consumption clock tree - Google Patents
Design method of low-power-consumption clock tree Download PDFInfo
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Abstract
The invention discloses a design method of a low-power consumption clock tree, which comprises the following implementation steps: preparing a clock tree and a customization unit, wherein the customization unit comprises a customization unit for customizing pull-down or pull-up drive reduction aiming at inverters, buffers and clock control units with various specified sizes and subtypes, does not change the position of a unit output pin, does not change the size of the pin, and keeps the size of the unit unchanged; all register input pins driven by a target clock are obtained from a clock tree, and inverters, buffers and clock control units in a path driven by the target clock are replaced by corresponding customization units by tracing back from the register input pins step by step; repairing the clock tree to establish the perturbation of the timing sequence. The invention utilizes the circuit and layout design technology and the layout wiring technology, reduces the power consumption of the clock tree on the premise of maintaining the performance of the clock tree, and has the minimum influence on the existing layout wiring process.
Description
Technical Field
The invention belongs to the field of integrated circuit physical design, relates to the field of clock tree design of modules in physical design, and particularly relates to a design method of a low-power clock tree.
Background
In the physical design of an integrated circuit, a module often has thousands, even hundreds of thousands of register units, and the registers are clocked by a phase-locked loop; the logic between the output of the phase locked loop to the clock terminal of each register becomes a clock tree. Clock trees come in many forms, balanced trees, H-trees, and nets. The clock tree is composed of an inverter, a buffer, a metal connecting wire and a clock control unit. The power consumption of the clock tree consists of two parts, namely dynamic power consumption and static power consumption. As the clock frequency increases, the dynamic power consumption increases linearly. The progress of the process itself is beneficial to reducing the power consumption of the device, and particularly the FinFET process is invented, and the leakage current of the device is reduced by about 2 orders of magnitude due to the enhancement of the control capability of the grid electrode on the channel. Due to the use of the FinFET process, the leakage power consumption of each module in physical design is reduced; in contrast, the dynamic power consumption fraction increases, thereby changing the power consumption fraction of components in the physical design. High-performance physical design practices under the 16nm FinFET process show that the clock power consumption is increased by 40-60% of the total module power consumption. Suppressing clock power consumption is an urgent need for high performance physical designs.
Disclosure of Invention
The technical problems to be solved by the invention are as follows: the invention provides a design method of a low-power consumption clock tree, which aims at solving the problem of higher power consumption of the clock tree in the current physical design.
In order to solve the technical problems, the technical scheme adopted by the invention is as follows:
a design method of a low-power consumption clock tree comprises the following implementation steps:
1) Preparing a clock tree and a customization unit, wherein the customization unit customizes a pull-down or pull-up drive reduction customization unit aiming at various specified sizes and subtypes of inverters, buffers and clock control units, and the pull-down or pull-up drive reduction customization unit does not change the position of a unit output pin, does not change the size of the pin and keeps the unit size unchanged;
2) All register input pins driven by a target clock are obtained from a clock tree, and inverters, buffers and clock control units in a path driven by the target clock are replaced by corresponding customization units by tracing back from the register input pins step by step;
3) Repairing the clock tree establishes a perturbation in timing.
Preferably, in the customization unit in step 1), the inverter comprises a customization unit with customized up and down drive reduction; the buffers comprise a front-stage inverter INV1 and a rear-stage inverter INV2, and each buffer comprises a customization unit for reducing the pull-up drive of the rear-stage inverter INV2 and the pull-down drive of the front-stage inverter INV1, and a customization unit for reducing the pull-down drive of the rear-stage inverter INV2 and the pull-up drive of the front-stage inverter INV 1; the clocked cells include custom cells with pull-down drive falling whose working edge is a positive edge, and custom cells with pull-up drive falling whose working edge is a negative edge.
Preferably, the detailed steps of step 2) include:
a2.1 One, a plurality of or all clocks of a target module are selected from a clock tree, clock input pins of sequential logic except all kinds of control units driven by the clocks are obtained to obtain a current input pin set cur _ pin _ cols, each pin in the current input pin set cur _ pin _ cols is set to have an initial phase ipin _ phase of 0, and the current replacement stage number n is 0;
a2.2 Comparing the current replacement number of stages N with a preset threshold value N, wherein the preset threshold value N is greater than or equal to 0 and is less than the depth from a clock root in a clock tree to the longest leaf node of the clock tree; if the current replacing series N is smaller than a preset threshold value N, skipping to execute the step A2.3); if the current replacement stage number N is greater than or equal to the preset threshold value N and the preset threshold value N is equal to 0, skipping to execute the step A2.7); if the current replacement stage number N is greater than or equal to the preset threshold value N and the preset threshold value N is greater than 0, skipping to execute the step A2.6); if the current replacement stage number N is equal to the preset threshold value N and the preset threshold value N is larger than 0, skipping to execute the step 3);
a2.3 Obtaining a previous-stage unit set pre _ cell _ cols by backtracking and obtaining a previous-stage logic unit of each pin of a current input pin set cur _ pin _ cols, wherein the phase _ of _ cell of each previous-stage unit in the previous-stage unit set pre _ cell _ cols is assigned as the value of an initial phase ipin _ phase of the pin with a connection relation;
a2.4 For each preceding stage unit in the preceding stage unit set pre _ cell _ colls), judging the type of the preceding stage unit, wherein the type of the preceding stage unit is one of an inverter, a buffer, a clock control unit and a multiplexer, and the preceding stage unit is replaced by a corresponding customization unit according to the type of the preceding stage unit: if the pre-stage unit is an inverter, replacing the customized unit with reduced pull-down network driving when the phase _ of _ cell of the inverter is 0, replacing the customized unit with reduced pull-up network driving when the phase _ of _ cell is 1, and taking the value of adding 1 to 2 of the phase _ of _ cell as the value of the initial phase ipin _ phase of the clock input pin of the customized unit; if the pre-stage unit is a buffer, the pull-down network driven down customized unit is used for replacing when the phase _ of _ cell of the buffer is 0, and the pull-up network driven down customized unit is used for replacing when the phase _ of _ cell is 1, taking the value of the phase _ of _ cell as the value of the initial phase ipin _ phase of the clock input pin of the customized unit; if the pre-stage unit is a clock control unit, the clock control unit is replaced by a customized unit with reduced pull-down network drive, and the value of the phase _ of _ cell of the clock control unit is directly used as the value of the initial phase ipin _ phase of a clock input pin of the customized unit;
a2.5 Add 1 to the current replacement stage number n, take the previous unit set pre _ cell _ colls as the new current input pin set cur _ pin _ colls, jump to execute step a 2.2).
Preferably, the customization unit in step 1) further comprises a customization unit of a multiplexer, and the customization unit of the multiplexer comprises a customization unit with a pull-down driving reduction whose working edge is a positive edge and a customization unit with a pull-up driving reduction whose working edge is a negative edge; step A2.4) also comprises the judgment that the type of the preceding stage unit is a multiplexer, if the type of the preceding stage unit is judged to be the multiplexer, the multiplexer is replaced by a customized unit with reduced pull-down network drive, and the value of the phase _ of _ cell of the multiplexer is directly used as the value of the initial phase ipin _ phase of the clock input pin of the customized unit.
Preferably, the detailed steps of step 2) include:
b2.1 One, a plurality of or all clocks of a target module are selected from a clock tree, clock input pins of sequential logic except all kinds of control units driven by the clocks are obtained to obtain a current input pin set cur _ pin _ colls, each pin in the current input pin set cur _ pin _ colls is set to be 0 in initial phase ipin _ phase, and the current replacement stage number n is 0;
b2.2 Comparing the current replacement number of stages N with a preset threshold value N, wherein the preset threshold value N is greater than or equal to 0 and is less than the depth from a clock root in a clock tree to the longest leaf node of the clock tree; if the current replacing series N is smaller than a preset threshold value N, skipping to execute the step B2.3); if the current replacing series N is larger than or equal to the preset threshold value N and the preset threshold value N is equal to 0, skipping to execute the step B2.7); if the current replacement stage number N is greater than or equal to the preset threshold value N and the preset threshold value N is greater than 0, skipping to execute the step B2.6); if the current replacement stage number N is equal to the preset threshold value N and the preset threshold value N is larger than 0, skipping to execute the step 3);
b2.3 Backtracking and acquiring a previous logic unit of each pin of a current input pin set cur _ pin _ colls to obtain a previous unit set pre _ cell _ colls, wherein the phase _ of _ cell of each previous unit in the previous unit set pre _ cell _ colls is assigned as the value of the initial phase ipin _ phase of the pin with a connection relation;
b2.4 For each preceding unit in the preceding unit set pre _ cell _ colls), judging the type of the preceding unit, wherein the type of the preceding unit is one of an inverter, a buffer, a clock control unit and a multiplexer, and the preceding unit is replaced by a corresponding customized unit according to the type of the preceding unit: if the pre-stage unit is an inverter, replacing the customized unit with pull-up network drive reduction when the phase _ of _ cell of the inverter is 0, replacing the customized unit with pull-down network drive reduction when the phase _ of _ cell is 1, and taking the value of adding 1 to 2 of the phase _ of _ cell as the value of the initial phase ipin _ phase of the clock input pin of the customized unit; if the pre-stage unit is a buffer, replacing the customized unit driven to be reduced by a pull-up network when the phase _ of _ cell of the buffer is 0, replacing the customized unit driven to be reduced by the pull-down network when the phase _ of _ cell is 1, and taking the value of the phase _ of _ cell as the value of the initial phase ipin _ phase of the clock input pin of the customized unit; if the pre-stage unit is a clock control unit, the clock control unit is replaced by a customized unit driven to be reduced by a pull-up network, and the value of the phase _ of _ cell of the clock control unit is directly used as the value of the initial phase ipin _ phase of a clock input pin of the customized unit;
b2.5 Add 1 to the current replacement stage number n, take the previous unit set pre _ cell _ colls as the new current input pin set cur _ pin _ colls, jump to execute step B2.2).
Preferably, the customization unit in step 1) further comprises a customization unit of a multiplexer, and the customization unit of the multiplexer comprises a customization unit with a pull-down driving reduction whose working edge is a positive edge and a customization unit with a pull-up driving reduction whose working edge is a negative edge; step B2.4) also comprises the judgment that the type of the front-stage unit is a multiplexer, if the type of the front-stage unit is judged to be the multiplexer, the multiplexer is replaced by a customized unit driven to be reduced by a pull-up network, and the value of the phase _ of _ cell of the multiplexer is directly used as the value of the initial phase ipin _ phase of the clock input pin of the customized unit.
Compared with the prior art, the invention has the following advantages:
1. the invention relates to a configurable method for reducing clock power consumption by sacrificing the performance of a non-working edge of a clock, which reduces the overall power consumption of a clock tree by sacrificing the performance of the non-working edge and hardly influences the performance of the working edge of the clock when processing the clock tree.
2. The invention uses the circuit and layout design technology and the layout and wiring technology to reduce the power consumption of the clock tree on the premise of maintaining the performance of the clock tree and has the minimum influence on the existing layout and wiring process.
3. The invention processes the clock tree without changing the position of each clock buffer unit pin, thereby avoiding winding the clock tree again.
4. The processing of the clock tree by the present invention does not change the size of the individual clock buffer cells and thus does not introduce DRC violations.
Drawings
FIG. 1 is a schematic diagram of a basic process flow of a method according to an embodiment of the present invention.
FIG. 2 is a detailed flow chart of a method according to an embodiment of the present invention.
Fig. 3 is a circuit example applied in the first embodiment of the present invention.
Detailed Description
The first embodiment is as follows:
the following will describe the design method of the low power consumption clock tree in further detail by taking the case that the clock input positive edge of the module is the working edge as an example.
As shown in fig. 1, the implementation steps of the design method of the low power consumption clock tree of the present embodiment include:
1) Preparing a clock tree and a customization unit, wherein the customization unit customizes pull-down or pull-up drive reduction of the customization unit aiming at various specified sizes and subtypes of inverters, buffers and clock units, and the customization unit does not change the position of a unit output Pin, does not change the size of a Pin (Pin) and keeps the size of the unit unchanged;
in this embodiment, the clock tree in step 1) is generated based on a conventional clock tree generation technology (e.g., CTS of Innovus tool provided by Cadence) in the module layout and wiring process.
2) All register input pins driven by a target clock are obtained from a clock tree, and inverters, buffers and clock control units in a path driven by the target clock are replaced by corresponding customization units by tracing back from the register input pins step by step;
3) Repairing the clock tree to establish the perturbation of the timing sequence.
The accumulation of the multi-stage clock units inevitably causes the deflection of each branch delay of the clock tree, slight disturbance is generated to the establishment of the time sequence, and the disturbance of the establishment of the time sequence is repaired by means of the clock tree optimization function provided by the layout and wiring platform. After the clock tree is repaired and the disturbance of the time sequence is established, the subsequent links of the layout and the wiring can be continuously completed.
The design method of the low-power consumption clock tree of the embodiment is a configurable method for reducing the clock power consumption by sacrificing the performance of the non-working edge of the clock, and the low-power consumption is realized by the following principles: and the output phase of the clock buffer unit is judged and selected to be replaced by the corresponding customized unit, so that the replaced equivalent buffer unit drives the pull-up or pull-down network of the working edge to be unchanged, and drives the pull-up or pull-down network of the non-working edge to be reduced. The positive edges are mainly affected by the pull-up network of the logic cells and the negative edges are mainly affected by the pull-down network. Under the condition that the working edge is a positive edge, the pull-down network of the logic unit is in a closed state, the drive capability of the pull-down network of the logic unit is reduced, the influence on the jump of the positive edge is small, and the jump of the negative edge becomes slow, namely the performance of the negative edge is reduced and the power consumption of the unit is reduced; under the condition that the working edge is a negative edge, the pull-up network of the logic unit is in a closed state, the drive capability of the pull-up network of the logic unit is reduced, the influence on the jump of the negative edge is small, the jump of the positive edge is slowed, namely the performance of the positive edge is reduced, and the power consumption of the unit is reduced. Inside the module, the working edges of the clock alternate between positive and negative edges along the clock tree, and the output signal of each cell is either in phase with the clock input or in anti-phase with the clock input. The clock signal reaches the clock pin (CP terminal) of each register or each clocked unit at the end along the clock tree, and has the same phase as the input signal.
In this embodiment, in the customization unit in step 1), the inverter includes a customization unit with customized pull-up and pull-down driving reduction; the buffer comprises a front-stage inverter INV1 and a rear-stage inverter INV2, and each buffer comprises a customization unit for reducing the pull-up drive of the rear-stage inverter INV2 and the pull-down drive of the front-stage inverter INV1, and a customization unit for reducing the pull-down drive of the rear-stage inverter INV2 and the pull-up drive of the front-stage inverter INV 1; the clocked cells include custom cells with pull-down drive falling whose working edge is a positive edge, and custom cells with pull-up drive falling whose working edge is a negative edge. For Inverter (INV): customizing a corresponding unit with reduced pull-up drive for each size and each seed type of unit, and naming the unit with the prefix hp-added before the original name; for each size, each seed type of cell, the corresponding pull-down driver down cell is customized, named after the original name preceded by the prefix hn _. For the Buffer (BUF): each size and each seed type BUF consists of a front stage INV1 and a rear stage INV2, and a unit for pulling up and reducing the INV2 and pulling down the INV1 in the customization is named after an original name and added with hp _; units that pull down INV2 and pull down INV1 in customization are named after the original name plus hn _. For the clocked units (CG), only one kind needs to be customized because the output phase is always in the same direction as the clock phase. If the working edge is a positive edge, the pull-down CG is only needed to be customized, and the name is added with the prefix hn _beforethe original name; otherwise, the name is preceded by the prefix hp _.
As shown in fig. 1 and 2, the detailed steps of step 2) include:
a2.1 One, a plurality of or all clocks (which can be formulated according to requirements) of a target module are selected from a clock tree, clock input pins of sequential logic except all kinds of control units driven by the clocks are obtained to obtain a current input pin set cur _ pin _ cols, each pin in the current input pin set cur _ pin _ cols is set to have an initial phase ipin _ phase of 0, and the current replacement stage number n is 0;
a2.2 Comparing the current replacing series N with a preset threshold N, wherein the preset threshold N is greater than or equal to 0 and is less than the depth from a clock root in the clock tree to the longest leaf node of the clock tree (the preset threshold N is set according to actual requirements and is constrained by the min pulse index of the SRAM, and can be large or small); if the current replacing series N is smaller than a preset threshold value N, skipping to execute the step A2.3); if the current replacement stage number N is greater than or equal to the preset threshold value N and the preset threshold value N is equal to 0, skipping to execute the step A2.7); if the current replacement stage number N is greater than or equal to the preset threshold value N and the preset threshold value N is greater than 0, skipping to execute the step A2.6); if the current replacement stage number N is equal to the preset threshold value N and the preset threshold value N is larger than 0, skipping to execute the step 3);
a2.3 Obtaining a previous-stage unit set pre _ cell _ cols by backtracking and obtaining a previous-stage logic unit of each pin of a current input pin set cur _ pin _ cols, wherein the phase _ of _ cell of each previous-stage unit in the previous-stage unit set pre _ cell _ cols is assigned as the value of an initial phase ipin _ phase of the pin with a connection relation;
a2.4 For each preceding stage unit in the preceding stage unit set pre _ cell _ colls), judging the type of the preceding stage unit, wherein the type of the preceding stage unit is one of an inverter, a buffer, a clock control unit and a multiplexer, and the preceding stage unit is replaced by a corresponding customization unit according to the type of the preceding stage unit: if the pre-stage unit is an inverter, replacing the customized unit with reduced pull-down network driving when the phase _ of _ cell of the inverter is 0, replacing the customized unit with reduced pull-up network driving when the phase _ of _ cell is 1, and taking the value of adding 1 to 2 of the phase _ of _ cell as the value of the initial phase ipin _ phase of the clock input pin of the customized unit; if the pre-stage unit is a buffer, replacing the pre-stage unit with a customized unit driven to be reduced by a pull-down network when the phase _ of _ cell of the buffer is 0, replacing the pre-stage unit with a customized unit driven to be reduced by a pull-up network when the phase _ of _ cell of the buffer is 1, and taking the value of the phase _ of _ cell as the value of the initial phase ipin _ phase of the clock input pin of the customized unit; if the pre-stage unit is a clock control unit, the clock control unit is replaced by a customized unit with reduced pull-down network drive, and the value of the phase _ of _ cell of the clock control unit is directly used as the value of the initial phase ipin _ phase of a clock input pin of the customized unit;
a2.5 Add 1 to the current replacement stage number n, take the previous stage unit set pre _ cell _ colls as the new current input pin set cur _ pin _ colls, jump to execute step a 2.2).
In this embodiment, the customization unit in step 1) further includes a customization unit of a multiplexer, and the customization unit of the multiplexer includes a customization unit with reduced pull-down driving whose working edge is a positive edge, and a customization unit with reduced pull-up driving whose working edge is a negative edge; step A2.4) also comprises the judgment that the type of the preceding stage unit is a multiplexer, if the type of the preceding stage unit is judged to be the multiplexer, the multiplexer is replaced by a customized unit with reduced pull-down network drive, and the value of the phase _ of _ cell of the multiplexer is directly used as the value of the initial phase ipin _ phase of the clock input pin of the customized unit. For the MUX, customization is generally not recommended because the MUX layout is complex and is generally closer to the clock root (root).
Taking the circuit shown in fig. 3 as an example, if N =2, i.e., the number of replacement stages is 2 stages.
After completing step 1) and step a 2.1), the initial phase ipin _ phase of each pin in the current replacement series n =0, n =2, cur _pin _ cols set is 0.
In the step a 2.2), when the current replacement stage number N is smaller than the preset threshold value N, the step a 2.3) is executed.
In step a 2.3), a preceding-level cell set pre _ cell _ colls = { L6_1, L6_2, L6_ … … L6_31, L6_32} is obtained, 32 inverter units in total, and the phase _ of _ cell values of each unit in pre _ cell _ colls are assigned to the initial phase ipin _ phase values of the pins having a connection relationship in cur _ pin _ cols, that is, all the values are 0.
In step a 2.4), each cell in pre _ cell _ colls = { L6_1, L6_2, L6_ … … L6_31, L6_32} is an inverter and the respective phase _ of _ cell value is 0, and is then replaced with the corresponding cell prefixed by hn _. The value of modulo 2 added to 1 by phase _ of _ cell of each unit in pre _ cell _ cols is taken as the value of the initial phase ipin _ phase of the clock input pin of the unit, i.e. the value of the initial phase ipin _ phase of the clock input pin of each unit in pre _ cell _ cols is 1. The set formed by the clock signal input pins of each unit in pre _ cell _ colls is updated cur _ pin _ colls. Meanwhile, the current number of replacement stages n is increased by 1, i.e., n =1. Therefore, it is necessary to cycle back to step a 2.2).
Then step a 2.3) is performed again in step a 2.2) a second time, since N < N).
Then, in step a 2.3) for the second time, a preceding-level unit set pre _ cell _ colls = { L5_1, L5_2, L5_ … … L5_15, L5_16} is obtained, and a total of 16 inverter units are obtained, and the phase _ of _ cell values of each unit in pre _ cell _ colls are assigned to the initial phase value ipin _ phase of the pin having a connection relationship in cur _ pin _ cols, that is, all values are 1. The type determination is performed again, and each cell is an inverter. Then in step a 2.4), each cell in pre _ cell _ colls = { L5_1, L5_2, L5_ … … L5_15, L5_16} is an inverter and the respective phase _ of _ cell value is 1, and is then replaced with the corresponding cell prefixed by hp _. The value of modulo 2 added to 1 by each unit phase _ of _ cell in pre _ cell _ cols is used as the value of the initial phase ipin _ phase of the clock input pin of the unit, i.e. the value of the initial phase ipin _ phase of the clock input pin of each unit in pre _ cell _ cols is 0. The set formed by the clock signal input pins of each unit in pre _ cell _ colls is updated cur _ pin _ colls. Meanwhile, the current number of replacement stages n is increased by 1, i.e., n =2.
Then, in step a 2.2) for the third time, since N = N and N >0, step 3) is performed to repair the disturbance of the clock tree establishment timing, and then the process is ended.
Example two:
the present embodiment is basically the same as the first embodiment, and the main difference is that the case of using the negative clock input edge of the module as the working edge in the present embodiment is taken as an example, and the difference is actually that the processing manner in step 2) is different, specifically, the prefix hp _ and the prefix hn _ are interchanged. In this embodiment, the detailed steps of step 2) include:
b2.1 One, a plurality of or all clocks of a target module are selected from a clock tree, clock input pins of sequential logic except all kinds of control units driven by the clocks are obtained to obtain a current input pin set cur _ pin _ cols, each pin in the current input pin set cur _ pin _ cols is set to have an initial phase ipin _ phase of 0, and the current replacement stage number n is 0;
b2.2 Comparing the current replacement number of stages N with a preset threshold value N, wherein the preset threshold value N is greater than or equal to 0 and is less than the depth from a clock root in a clock tree to the longest leaf node of the clock tree; if the current replacing series N is smaller than a preset threshold value N, skipping to execute the step B2.3); if the current replacement stage number N is greater than or equal to the preset threshold value N and the preset threshold value N is equal to 0, skipping to execute the step B2.7); if the current replacement stage number N is greater than or equal to the preset threshold value N and the preset threshold value N is greater than 0, skipping to execute the step B2.6); if the current replacement stage number N is equal to the preset threshold value N and the preset threshold value N is larger than 0, skipping to execute the step 3);
b2.3 Obtaining a previous-stage unit set pre _ cell _ cols by backtracking and obtaining a previous-stage logic unit of each pin of a current input pin set cur _ pin _ cols, wherein the phase _ of _ cell of each previous-stage unit in the previous-stage unit set pre _ cell _ cols is assigned as the value of an initial phase ipin _ phase of the pin with a connection relation;
b2.4 For each preceding stage unit in the preceding stage unit set pre _ cell _ colls), judging the type of the preceding stage unit, wherein the type of the preceding stage unit is one of an inverter, a buffer, a clock control unit and a multiplexer, and the preceding stage unit is replaced by a corresponding customization unit according to the type of the preceding stage unit: if the pre-stage unit is an inverter, replacing the customized unit with pull-up network drive reduction when the phase _ of _ cell of the inverter is 0, replacing the customized unit with pull-down network drive reduction when the phase _ of _ cell is 1, and taking the value of adding 1 to 2 of the phase _ of _ cell as the value of the initial phase ipin _ phase of the clock input pin of the customized unit; if the pre-stage unit is a buffer, replacing the customized unit driven to be reduced by a pull-up network when the phase _ of _ cell of the buffer is 0, replacing the customized unit driven to be reduced by the pull-down network when the phase _ of _ cell is 1, and taking the value of the phase _ of _ cell as the value of the initial phase ipin _ phase of the clock input pin of the customized unit; if the pre-stage unit is a clock control unit, the clock control unit is replaced by a customized unit driven to be reduced by a pull-up network, and the value of the phase _ of _ cell of the clock control unit is directly used as the value of the initial phase ipin _ phase of a clock input pin of the customized unit;
b2.5 Add 1 to the current replacement stage number n, take the previous unit set pre _ cell _ colls as the new current input pin set cur _ pin _ colls, jump to execute step B2.2).
In this embodiment, the customization units in step 1) further include customization units of a multiplexer, and the customization units of the multiplexer include customization units with reduced pull-down driving whose working edge is a positive edge, and customization units with reduced pull-up driving whose working edge is a negative edge; step B2.4) also comprises the judgment that the type of the front-stage unit is a multiplexer, if the type of the front-stage unit is judged to be the multiplexer, the multiplexer is replaced by a customized unit driven to be reduced by a pull-up network, and the value of the phase _ of _ cell of the multiplexer is directly used as the value of the initial phase ipin _ phase of the clock input pin of the customized unit.
The above description is only a preferred embodiment of the present invention, and the protection scope of the present invention is not limited to the above embodiments, and all technical solutions belonging to the idea of the present invention belong to the protection scope of the present invention. It should be noted that modifications and embellishments within the scope of the invention may occur to those skilled in the art without departing from the principle of the invention, and are considered to be within the scope of the invention.
Claims (6)
1. A design method of a low-power consumption clock tree is characterized by comprising the following implementation steps:
1) Preparing a clock tree and a customization unit, wherein the customization unit customizes a pull-down or pull-up drive reduction customization unit aiming at various specified sizes and subtypes of inverters, buffers and clock control units, and the pull-down or pull-up drive reduction customization unit does not change the position of a unit output pin, does not change the size of the pin and keeps the unit size unchanged;
2) All register input pins driven by a target clock are obtained from a clock tree, and inverters, buffers and clock control units in a path driven by the target clock are replaced by corresponding customization units by tracing back from the register input pins step by step;
3) Repairing the clock tree to establish the perturbation of the timing sequence.
2. The method for designing the low power consumption clock tree according to claim 1, wherein in the customized unit in step 1), the inverter comprises a customized unit with customized pull-up and pull-down driving reduction; the buffers comprise a front-stage inverter INV1 and a rear-stage inverter INV2, and each buffer comprises a customization unit for reducing the pull-up drive of the rear-stage inverter INV2 and the pull-down drive of the front-stage inverter INV1, and a customization unit for reducing the pull-down drive of the rear-stage inverter INV2 and the pull-up drive of the front-stage inverter INV 1; the clocked cells include custom cells with pull-down drive falling whose working edge is a positive edge, and custom cells with pull-up drive falling whose working edge is a negative edge.
3. The method for designing the low-power clock tree according to claim 1 or 2, wherein the detailed step of step 2) comprises:
a2.1 One, a plurality of or all clocks of a target module are selected from a clock tree, clock input pins of sequential logic except all kinds of control units driven by the clocks are obtained to obtain a current input pin set cur _ pin _ cols, each pin in the current input pin set cur _ pin _ cols is set to have an initial phase ipin _ phase of 0, and the current replacement stage number n is 0;
a2.2 Comparing the current replacement number of stages N with a preset threshold value N, wherein the preset threshold value N is greater than or equal to 0 and is less than the depth from a clock root in a clock tree to the longest leaf node of the clock tree; if the current replacing series N is smaller than a preset threshold value N, skipping to execute the step A2.3); if the current replacement stage number N is greater than or equal to the preset threshold value N and the preset threshold value N is equal to 0, skipping to execute the step A2.7); if the current replacing series N is more than or equal to the preset threshold value N and the preset threshold value N is more than 0, skipping to execute the step A2.6); if the current replacing series N is equal to the preset threshold value N and the preset threshold value N is larger than 0, skipping to execute the step 3);
a2.3 Obtaining a previous-stage unit set pre _ cell _ cols by backtracking and obtaining a previous-stage logic unit of each pin of a current input pin set cur _ pin _ cols, wherein the phase _ of _ cell of each previous-stage unit in the previous-stage unit set pre _ cell _ cols is assigned as the value of an initial phase ipin _ phase of the pin with a connection relation;
a2.4 For each preceding stage unit in the preceding stage unit set pre _ cell _ colls), judging the type of the preceding stage unit, wherein the type of the preceding stage unit is one of an inverter, a buffer, a clock control unit and a multiplexer, and the preceding stage unit is replaced by a corresponding customization unit according to the type of the preceding stage unit: if the preceding-stage unit is an inverter, the customized unit driven to be reduced by a pull-down network is used for replacing when the phase _ of _ cell of the inverter is 0, the customized unit driven to be reduced by a pull-up network is used for replacing when the phase _ of _ cell is 1, and the value obtained by adding 1 to modulo 2 to the phase _ of _ cell is used as the value of the initial phase ipin _ phase of the clock input pin of the customized unit; if the pre-stage unit is a buffer, replacing the pre-stage unit with a customized unit driven to be reduced by a pull-down network when the phase _ of _ cell of the buffer is 0, replacing the pre-stage unit with a customized unit driven to be reduced by a pull-up network when the phase _ of _ cell of the buffer is 1, and taking the value of the phase _ of _ cell as the value of the initial phase ipin _ phase of the clock input pin of the customized unit; if the pre-stage unit is a clock control unit, the clock control unit is replaced by a customized unit with reduced pull-down network drive, and the value of the phase _ of _ cell of the clock control unit is directly used as the value of the initial phase ipin _ phase of a clock input pin of the customized unit;
a2.5 Add 1 to the current replacement stage number n, take the previous unit set pre _ cell _ colls as the new current input pin set cur _ pin _ colls, jump to execute step a 2.2).
4. The method for designing the low power consumption clock tree according to claim 3, wherein the customization units in step 1) further include customization units of a multiplexer, and the customization units of the multiplexer include customization units whose pull-down driving is reduced and whose working edges are positive edges and customization units whose pull-up driving is reduced and whose working edges are negative edges; step a 2.4) further includes a judgment that the type of the pre-stage unit is a multiplexer, if the type of the pre-stage unit is judged to be the multiplexer, the multiplexer is replaced by a customized unit with reduced pull-down network drive, and the value of the phase _ of _ cell of the multiplexer is directly used as the value of the initial phase ipin _ phase of the clock input pin of the customized unit.
5. The method for designing the low-power clock tree according to claim 1 or 2, wherein the detailed step of step 2) comprises:
b2.1 One, a plurality of or all clocks of a target module are selected from a clock tree, clock input pins of sequential logic except all kinds of control units driven by the clocks are obtained to obtain a current input pin set cur _ pin _ cols, each pin in the current input pin set cur _ pin _ cols is set to have an initial phase ipin _ phase of 0, and the current replacement stage number n is 0;
b2.2 Comparing the current replacement number of stages N with a preset threshold value N, wherein the preset threshold value N is greater than or equal to 0 and is less than the depth from a clock root in a clock tree to the longest leaf node of the clock tree; if the current replacing series N is smaller than a preset threshold value N, skipping to execute the step B2.3); if the current replacement stage number N is greater than or equal to the preset threshold value N and the preset threshold value N is equal to 0, skipping to execute the step B2.7); if the current replacement stage number N is greater than or equal to the preset threshold value N and the preset threshold value N is greater than 0, skipping to execute the step B2.6); if the current replacement stage number N is equal to the preset threshold value N and the preset threshold value N is larger than 0, skipping to execute the step 3);
b2.3 Obtaining a previous-stage unit set pre _ cell _ cols by backtracking and obtaining a previous-stage logic unit of each pin of a current input pin set cur _ pin _ cols, wherein the phase _ of _ cell of each previous-stage unit in the previous-stage unit set pre _ cell _ cols is assigned as the value of an initial phase ipin _ phase of the pin with a connection relation;
b2.4 For each preceding unit in the preceding unit set pre _ cell _ colls), judging the type of the preceding unit, wherein the type of the preceding unit is one of an inverter, a buffer, a clock control unit and a multiplexer, and the preceding unit is replaced by a corresponding customized unit according to the type of the preceding unit: if the pre-stage unit is an inverter, replacing the customized unit with pull-up network drive reduction when the phase _ of _ cell of the inverter is 0, replacing the customized unit with pull-down network drive reduction when the phase _ of _ cell is 1, and taking the value of adding 1 to 2 of the phase _ of _ cell as the value of the initial phase ipin _ phase of the clock input pin of the customized unit; if the pre-stage unit is a buffer, replacing the customized unit driven to be reduced by a pull-up network when the phase _ of _ cell of the buffer is 0, replacing the customized unit driven to be reduced by the pull-down network when the phase _ of _ cell is 1, and taking the value of the phase _ of _ cell as the value of the initial phase ipin _ phase of a clock input pin of the customized unit; if the pre-stage unit is a clock control unit, the clock control unit is replaced by a customized unit driven to be reduced by a pull-up network, and the value of the phase _ of _ cell of the clock control unit is directly used as the value of the initial phase ipin _ phase of a clock input pin of the customized unit;
b2.5 Add 1 to the current replacement stage number n, take the previous unit set pre _ cell _ colls as the new current input pin set cur _ pin _ colls, jump to execute step B2.2).
6. The method for designing the low power consumption clock tree according to claim 5, wherein the customization units in step 1) further include customization units of a multiplexer, and the customization units of the multiplexer include customization units whose pull-down driving is reduced and whose working edges are positive edges and customization units whose pull-up driving is reduced and whose working edges are negative edges; step B2.4) also comprises the judgment that the type of the front unit is a multiplexer, if the type of the front unit is judged to be the multiplexer, the multiplexer is replaced by a customized unit with reduced pull-up network drive, and the value of the phase _ of _ cell of the multiplexer is directly used as the value of the initial phase ipin _ phase of the clock input pin of the customized unit.
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