CN111931448B - Time sequence repairing method and system for chip circuit, electronic equipment and storage medium - Google Patents
Time sequence repairing method and system for chip circuit, electronic equipment and storage medium Download PDFInfo
- Publication number
- CN111931448B CN111931448B CN202010791428.8A CN202010791428A CN111931448B CN 111931448 B CN111931448 B CN 111931448B CN 202010791428 A CN202010791428 A CN 202010791428A CN 111931448 B CN111931448 B CN 111931448B
- Authority
- CN
- China
- Prior art keywords
- buffer
- area
- time sequence
- target
- virtual
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/392—Floor-planning or layout, e.g. partitioning or placement
Abstract
The application discloses a time sequence repairing method of a chip circuit, which comprises the following steps: determining a virtual area corresponding to a driving unit in a chip circuit, and dividing the virtual area into a plurality of virtual sub-areas with equal areas by using N virtual lines; setting the virtual sub-area containing the most fan-out units as a target area, and executing a buffer adding operation in the target area; and after the buffer adding operation is finished, if the target area does not accord with the time sequence design rule constraint, taking the buffer as a new driving unit, and executing the operation of determining the virtual area corresponding to the driving unit in the chip circuit. The method and the device can repair the time sequence design rule constraint violation in the chip circuit on the premise of reducing the adding quantity of the buffers. The application also discloses a time sequence repairing system of the chip circuit, an electronic device and a storage medium, and the time sequence repairing system has the beneficial effects.
Description
Technical Field
The present disclosure relates to the field of chip design technologies, and in particular, to a method and a system for repairing a timing sequence of a chip circuit, an electronic device, and a storage medium.
Background
In the chip design, because the logic unit in the timing path has the limitation of driving capability, the logic unit itself needs to be ensured to work in a stable state while meeting the timing requirement, that is, the load driven by the logic unit should be controlled within an acceptable range. It is therefore possible to guide the timing analysis tool to correctly evaluate whether a cell can operate in a stable and reasonable state by setting a timing Design Rule Constraint (DRC).
Timing design rule constraint ensures that a Cell (a standard Cell in a chip circuit) can normally work and also influences Delay calculation in STA (static Timing analysis), so that during Timing ECO (Timing recovery), the existing DRC virtualization (Timing design rule constraint Violation) needs to be repaired. The main reasons for DRC isolation are weak driving capability of the Cell, too long routing, High Fanout (High Fanout), and the like, and the basic methods generally adopted are to insert a Buffer (Buffer) to break a long line, reduce Fanout, reduce signal conversion time, increase driving capability of the driving unit Driver, and the like.
In the related art, a buffer is inserted at a certain distance along the actual trace at the output terminal of the driving unit Driver according to the position of the driving unit Driver and the output terminal connection line. Due to the uncertainty of the locations of the inserted buffers in the above method, there still exists a problem that the number of some inserted buffer-driven cells is too small, resulting in the waste of buffers; however, some inserted buffers drive too many cells, so that there still exist timing design rule constraint violations and the balance effect is not achieved.
Therefore, how to repair the violation of the timing design rule constraint in the chip circuit with the reduced number of added buffers is a technical problem that needs to be solved by those skilled in the art at present.
Disclosure of Invention
The application aims to provide a method and a system for repairing a time sequence of a chip circuit, an electronic device and a storage medium, which can repair time sequence design rule constraint violations in the chip circuit on the premise of reducing the adding quantity of buffers.
In order to solve the above technical problem, the present application provides a method for repairing a timing sequence of a chip circuit, where the method for repairing a timing sequence of a chip circuit includes:
determining a virtual area corresponding to a driving unit in a chip circuit, and dividing the virtual area into a plurality of virtual sub-areas with equal areas by using N virtual lines; the virtual area comprises the virtual units and fan-out units corresponding to the virtual units;
setting a virtual sub-area containing the most fan-out units as a target area, and executing a buffer adding operation in the target area;
after the buffer adding operation is finished, if the target area accords with the time sequence design rule constraint, judging that the time sequence repairing operation of the chip circuit is finished;
and after the buffer adding operation is finished, if the target area does not accord with the time sequence design rule constraint, taking the buffer as a new driving unit, and executing the operation of determining the virtual area corresponding to the driving unit in the chip circuit.
Optionally, determining a virtual area including the driving unit and the fan-out unit in the chip circuit, and dividing the virtual area into a plurality of virtual sub-areas with equal areas by using N virtual lines, including:
taking a rectangular frame which comprises the driving unit and the fan-out unit and has the smallest area as the virtual area in the chip circuit;
and taking the central axes of the rectangular frame in the length direction and the width direction as the virtual lines, and dividing the virtual area into 4 virtual sub-areas with equal areas by using the virtual lines.
Optionally, the performing of the buffer adding operation in the target area includes:
determining a buffer with driving capacity ranking at a preset position in a process library as a target buffer;
adding the target buffer at the position of the intersection point of the boundary line of the target area and the interconnecting line of the driving unit;
judging whether the target area accords with the time sequence design rule constraint;
if yes, judging that the execution of the time sequence repairing operation of the chip circuit is finished;
if not, sequentially selecting buffers with driving capacity ranks higher than the target buffer from the process library according to the driving capacity ranks as alternative buffers;
sequentially adding the alternative buffers at the intersections of the boundary lines of the target area and the interconnecting lines of the driving units until the target area meets the time sequence design rule constraint and the execution of buffer adding operation is judged to be finished;
and if the alternative buffer which enables the target area to accord with the time sequence design rule constraint does not exist, adding the target buffer at the position of the intersection point of the boundary line of the target area and the interconnecting line of the driving unit, and judging that the buffer adding operation is finished.
Optionally, an occupied area of the alternative buffer is smaller than a preset value; wherein the preset value is positively correlated with the occupied area of the target buffer.
Optionally, after setting the virtual sub-area containing the most fan-out units as the target area, the method further includes:
setting a virtual sub-area which does not conform to the time sequence design rule constraint except the target area as an alternative area;
dividing the candidate region into a plurality of candidate subregions with equal areas by using N virtual lines;
adding a buffer in the candidate sub-area containing the most fan-out units.
Optionally, the timing design rule constraints include a maximum conversion time, a maximum load capacitance, and a maximum fanout; and when the conversion time of the target area is less than or equal to the maximum conversion time, the load capacitance is less than or equal to the maximum load capacitance, and the fan-out is less than or equal to the maximum fan-out, determining that the target area meets the timing design rule constraint.
Optionally, after determining that the execution of the timing recovery operation of the chip circuit is completed, the method further includes:
generating a time sequence repair script according to the position and the type of the buffer added in the chip circuit;
and utilizing the time sequence repairing script to repair the time sequence design rule constraint violation in the layout and wiring tool.
The present application further provides a timing recovery system for a chip circuit, the system including:
the area dividing module is used for determining a virtual area corresponding to the driving unit in the chip circuit and dividing the virtual area into a plurality of virtual sub-areas with equal areas by using N virtual lines; the virtual area comprises the virtual units and fan-out units corresponding to the virtual units;
the buffer adding module is used for setting the virtual sub-area containing the most fan-out units as a target area and executing buffer adding operation in the target area;
the result output module is used for judging that the execution of the time sequence repair operation of the chip circuit is finished if the target area accords with the time sequence design rule constraint after the execution of the buffer adding operation is finished;
and the iteration module is used for taking the buffer as a new driving unit and starting a working process corresponding to the region division module if the target region does not accord with the time sequence design rule constraint after the buffer adding operation is finished.
The application also provides a storage medium, on which a computer program is stored, and the computer program realizes the steps executed by the time sequence repairing method of the chip circuit when being executed.
The application also provides an electronic device, which comprises a memory and a processor, wherein the memory is stored with a computer program, and the processor realizes the execution of the time sequence repairing method of the chip circuit when calling the computer program in the memory.
The application provides a time sequence repairing method of a chip circuit, which comprises the steps of determining a virtual area corresponding to a driving unit in the chip circuit, and dividing the virtual area into a plurality of virtual sub-areas with equal areas by using N virtual lines; the virtual area comprises the virtual units and fan-out units corresponding to the virtual units; setting a virtual sub-area containing the most fan-out units as a target area, and executing a buffer adding operation in the target area; after the buffer adding operation is finished, if the target area accords with the time sequence design rule constraint, judging that the time sequence repairing operation of the chip circuit is finished; and after the buffer adding operation is finished, if the target area does not accord with the time sequence design rule constraint, taking the buffer as a new driving unit, and executing the operation of determining the virtual area corresponding to the driving unit in the chip circuit.
The method comprises the steps of determining a driving unit and a corresponding fan-out unit thereof, determining a virtual area comprising the driving unit and the fan-out unit, dividing the virtual area into a plurality of virtual sub-areas with equal areas, and executing buffer adding operation in a target area with the largest fan-out unit. And if the target area does not accord with the time sequence design rule constraint after the buffer is added, taking the added buffer area as a new driving unit to iteratively execute the operation of determining the virtual area corresponding to the driving unit in the chip circuit and adding the buffer. The method and the device can repair the time sequence design rule constraint violation in the chip circuit on the premise of reducing the adding quantity of the buffers. The application also provides a time sequence repairing system of the chip circuit, a storage medium and an electronic device, which have the beneficial effects and are not repeated.
Drawings
In order to more clearly illustrate the embodiments of the present application, the drawings needed for the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings can be obtained by those skilled in the art without inventive effort.
Fig. 1 is a flowchart of a timing recovery method for a chip circuit according to an embodiment of the present disclosure;
FIG. 2 is a flowchart of a balanced method for iteratively repairing a temporal design rule constraint violation according to an embodiment of the present application;
fig. 3 is a schematic diagram illustrating a method for determining a virtual area according to an embodiment of the present disclosure;
FIG. 4 is a schematic diagram of a first buffer adding position according to an embodiment of the present application;
FIG. 5 is a diagram illustrating a second buffer adding position according to an embodiment of the present application;
FIG. 6 is a diagram illustrating a third buffer adding position according to an embodiment of the present application;
fig. 7 is a diagram illustrating an overall effect of adding a buffer to a chip circuit according to an embodiment of the present disclosure;
fig. 8 is a schematic structural diagram of a timing recovery system of a chip circuit according to an embodiment of the present disclosure.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Referring to fig. 1, fig. 1 is a flowchart illustrating a timing recovery method for a chip circuit according to an embodiment of the present disclosure.
The method comprises the following specific steps:
s101: determining a virtual area corresponding to a driving unit in a chip circuit, and dividing the virtual area into a plurality of virtual sub-areas with equal areas by using N virtual lines;
before this step, the fan-out unit with time sequence design rule constraint violation can be determined and the corresponding drive unit can be found, so as to determine the virtual area corresponding to the drive unit, wherein the virtual area comprises the virtual unit and the fan-out unit corresponding to the virtual unit. The shape of the virtual area is not limited in this embodiment, and the virtual area may be rectangular or circular as a possible implementation. After the virtual area is obtained, the embodiment may divide the virtual area into a plurality of virtual sub-areas with equal areas by using N virtual lines, for example.
As a possible implementation manner, the present embodiment may use a rectangular frame which includes the driving unit and the fan-out unit and has a smallest area as the dummy area in the chip circuit; the central axes of the rectangular frame in the length direction and the width direction can also be used as the virtual lines, and the virtual lines are used for dividing the virtual area into 4 virtual sub-areas with equal area.
S102: setting the virtual sub-area containing the most fan-out units as a target area, and executing a buffer adding operation in the target area;
in the step, on the basis of dividing the virtual area into a plurality of virtual sub-areas with equal areas, the virtual sub-area containing the most fan-out units is set as the target area, and the buffer adding operation is performed in the target area. In the embodiment, when the position of the inserted buffer is selected, the scheme judges the area with the most fan-out units by dividing the quadrants so as to find the newly inserted buffer which can drive more fan-out units. The embodiment can also determine the position of the insertion buffer according to the point with the maximum number of fan-out units on the actual routing. If the fan-out units included in the plurality of virtual sub-areas are the most, a plurality of target areas can exist, and the fan-out units are set as the target areas at the most. When the N virtual lines are used for dividing the virtual area, if a certain fan-out unit exists in a plurality of virtual sub-areas, the fan-out unit is judged to be a common fan-out unit of the plurality of virtual sub-areas, and the common fan-out unit is included when the fan-out unit of each virtual sub-area is calculated.
The buffer addition operation refers to an operation of adding a buffer within a chip circuit of a target area, and the present embodiment does not limit the number of buffers added when performing a buffer addition operation once. As a possible implementation, the present embodiment may set the adding position of the buffer at the intersection of the boundary line of the target area and the connecting line of the driving unit.
Specifically, the present embodiment may determine a buffer with a driving capability ranked at a preset position (such as an intermediate position) in the process library as a target buffer; adding the target buffer at a position where an intersection of a boundary line of the target region and an interconnection line (Driver Net) of the driving unit is located; judging whether the target area accords with the time sequence design rule constraint; if yes, judging that the execution of the time sequence repairing operation of the chip circuit is finished; if not, sequentially selecting buffers with driving capacity ranks higher than the target buffer from the process library according to the driving capacity ranks as alternative buffers; sequentially adding the alternative buffers at the intersections of the boundary lines of the target area and the interconnecting lines of the driving units until the target area meets the time sequence design rule constraint and the execution of buffer adding operation is judged to be finished; and if the alternative buffer which enables the target area to accord with the time sequence design rule constraint does not exist, adding the selected target buffer at the position of the intersection point of the boundary line of the target area and the interconnecting line of the driving unit, and judging that the buffer adding operation is finished. The occupied area of the alternative buffer is smaller than a preset value; wherein the preset value is positively correlated with the occupied area of the target buffer.
S103: after the buffer adding operation is finished, if the target area accords with the time sequence design rule constraint, judging that the time sequence repairing operation of the chip circuit is finished;
after the buffer adding operation is performed on the target region, a timing analysis tool can be used to determine whether the target region meets the timing design rule constraint. If the target area meets the time sequence design rule constraint, the execution of the time sequence repair operation of the chip circuit is judged to be finished, and the time sequence repair process of the embodiment is finished.
S104: and after the buffer adding operation is finished, if the target area does not accord with the time sequence design rule constraint, taking the buffer as a new driving unit, and executing the operation of determining the virtual area corresponding to the driving unit in the chip circuit.
After the buffer adding operation is completed, if the target area does not meet the constraint of the timing design rule, the step takes the buffer area added in S102 as a new driving unit, and iteratively executes an operation of determining a virtual area corresponding to the driving unit in the chip circuit. In the process of executing the operation of determining the virtual area corresponding to the driving unit in the chip circuit, the buffer added in S102 is taken as a new driving unit to enter the operation steps of S101, S102 and S103 or the operation steps of S101, S102 and S104 until the target area meets the time sequence design rule constraint.
The embodiment determines a driving unit and a corresponding fan-out unit thereof, determines a virtual area comprising the driving unit and the fan-out unit, divides the virtual area into a plurality of virtual sub-areas with equal areas, and executes a buffer adding operation in a target area with the most fan-out units. And if the target area does not accord with the time sequence design rule constraint after the buffer is added, taking the added buffer area as a new driving unit to iteratively execute the operation of determining the virtual area corresponding to the driving unit in the chip circuit and adding the buffer. The embodiment can repair the time sequence design rule constraint violation in the chip circuit on the premise of reducing the adding quantity of the buffers.
For example, in the implementation process of the above embodiment, first, a driving unit and a fan-out unit corresponding to the driving unit are determined, and a virtual area including the driving unit and all the fan-out units is generated. The dummy area may be the smallest rectangle that contains the drive unit and all fan-out units. Dividing the virtual area into four virtual sub-areas (namely four quadrants) according to the horizontal center line and the vertical center line of the virtual area, selecting the virtual sub-area with the most fan-out units as a target area for adding the buffer, or taking N virtual sub-areas as target areas for adding the buffer under the condition that the fan-out units of the N virtual sub-areas are ranked and arranged in parallel first. There are interconnections between the drive unit and the fan-out unit, and the present embodiment takes the intersection of the target area and the interconnections as the location where the buffer is added. When the buffer is added to the target area, the buffer with the driving capability ranked in the middle position in the process library is selected as the target buffer, and if the target area meets the time sequence design rule constraint after the target buffer is added, the process is ended; if the target area does not accord with the time sequence design rule constraint after the target buffer is added, selecting a buffer with the driving capacity ranking higher than that of the target buffer and the occupied area less than twice that of the target buffer from the process library as an alternative buffer, and if the target area accords with the time sequence design rule constraint after the alternative buffer is added, ending the process; and if the target area does not accord with the time sequence design rule constraint after any optional buffer is added, adding the target buffer in the target area. At this time, the process of adding the buffer in the first iteration is completed. After the target buffer is added, the target area still has a phenomenon of time sequence design rule constraint violation, at this time, the target buffer can be used as a new driving unit, a new driving unit and a new virtual area of a corresponding fan-out unit of the new driving unit are generated, the process of adding the buffer in the second iteration is performed, and operations such as area division, target area determination, buffer addition and the like are performed on the new virtual area in the process of adding the buffer in the second iteration. And if the target area which does not meet the time sequence design rule constraint still exists after the buffer is added in the second iteration, carrying out operations of adding the buffer in the third and fourth iterations … … for the Nth time until the target area which does not meet the time sequence design rule constraint does not exist.
As a possible implementation manner, after the virtual sub-region containing the most fan-out units is set as a target region, a virtual sub-region which does not comply with the timing design rule constraint except the target region may be set as an alternative region; dividing the candidate region into a plurality of candidate subregions with equal areas by using N virtual lines; adding a buffer in the candidate sub-area containing the most fan-out units.
Further, after the time sequence repairing operation of the chip circuit is judged to be completed, a time sequence repairing script can be generated according to the position and the type of the buffer added in the chip circuit; and utilizing the time sequence repairing script to repair the time sequence design rule constraint violation in the layout and wiring tool.
The flow described in the above embodiment is explained below by an embodiment in practical use. The present embodiment provides a balanced iterative repair method for a time sequence design rule constraint Violation (DRC virtualization) that needs to be repaired in a time sequence repair process of static time sequence analysis, please refer to fig. 2, where fig. 2 is a flowchart of the balanced iterative repair method for the time sequence design rule constraint Violation provided in the embodiment of the present application, and in the present embodiment, an optimal position and type are selected each time a Buffer is inserted, and repair of DRC virtualization is implemented in a multiple iteration manner. The method can not only ensure that all DRC visualizations are repaired, but also control the number and types of inserted buffers, thereby reducing the increase of area and power consumption. In this embodiment, Driver is a driving unit, cell is a standard cell, cell is a generic name of various deleting units of the driving unit, Buffer is a Buffer, DRC vision is a timing design rule constraint Violation, Fanout is a Fanout, PrimeTime tool is an EDA tool for static timing analysis, and EDA is electronic design automation. The present embodiment may include the following steps:
step (1), setting a virtual area;
referring to fig. 3, fig. 3 is a schematic view illustrating a method for determining a virtual area according to an embodiment of the present disclosure. Driver in FIG. 3 is a driving unit, s 1-s 9 are fan-out units corresponding to the driving unit, and triangles in FIG. 3 are buffers. This embodiment can analyze DRC vision, defining a virtual rectangular box containing the Driver and all Fanout on the wire: the PrimeTime tool performs time sequence analysis of Physical Aware, reports cells with DRC vision, finds drivers of the cells, and obtains coordinates (Xi, Yi) of the position of each Cell. Then, the maximum values Xmax and Ymax and the minimum values Xmin and Ymin in all the Cell coordinates Xi and Yi are respectively found, a virtual rectangular frame is defined according to the coordinates, the coordinates of the vertex at the lower left corner of the rectangular frame are (Xmin and Ymin), the coordinates of the vertex at the upper right corner of the rectangular frame are (Xmax and Ymax), and at this time, the rectangular frame just covers all Fanout and drivers thereof.
Step (2), determining the position of a buffer;
as shown in fig. 3, in determining the location of the insertion buffer, the following steps may be performed: finding out the horizontal central axis of the rectangular frame as (Xmax-Xmin)/2 and the longitudinal central axis as (Ymax-Ymin)/2, and the intersection point of the two axes as the central point (Xcenter, Ycenter), equally dividing the rectangular frame into four quadrants according to the two central axes, and simultaneously finding out the intersection points of the two central axes and the connecting line of the Driver, as shown in FIG. 3, three intersection points A1, B1 and C1 are provided. The intersection points of the longitudinal central axis and the Driver Net are A1 and C1, and since the Driver is on the left side of the longitudinal central axis, the position of the intersection point is defined as the right side of the longitudinal central axis, namely, the point A1 is the intersection point of the first quadrant, and the point C1 is the intersection point of the second quadrant. The intersection point of the horizontal central axis and Driver Net is B1, and similarly, since Driver is above the horizontal central axis at this time, the position where B1 is located is defined as below the central axis, that is, B1 is the intersection point of the third quadrant. The intersection position is always defined at the other side of the position of the Driver, and the intersection position is the position which can be selected by inserting the Buffer.
And then selecting the position of inserting the Buffer according to the number of the Fanout in each quadrant, judging the number of the Fanout in the other three quadrants because the Driver is in the fourth quadrant at the moment, taking the third quadrant with the largest number of the Fanout, and selecting the intersection point B in the quadrant to insert the Buffer B1 so that the inserted Buffer drives the most cells. If the quadrants where the Fanout number is equal to the maximum number are present, buffers are inserted in these quadrants at the same time.
Step (3), selecting a buffer type;
the process of selecting the type of the insertion buffer in the embodiment includes: after determining the position of the insertion Buffer b1, the type of the insertion Buffer needs to be selected. Generally, under a certain process library, there are many buffers with driving capability, and the number of cells that can be driven by each Buffer is different, and the area size is different. For example, in a process library, 13 different buffers are present in BUFX1, BUFX2, BUFX3, BUFX4, BUFX5, BUFX6, BUFX8, BUFX10, BUFX12, BUFX14, BUFX16, BUFX20, and BUFX24, and the larger the number is, the higher the corresponding driving capability is, and the larger the area is. Firstly, the b1 type is taken as BUFX8 with the driving capability in the middle, the Area corresponding to Buffer is Area, and if BUFX8 can repair DRC decomposition of s 5-s 9 after being inserted, BUFX8 is the most reasonable Buffer type. If DRC Violation still exists in s 5-s 9 after BUFX8 is inserted, the Buffer is reselected according to the Area of BUFX 8. And (3) selecting the buffers with the Area not exceeding 2 × Area from all the buffers, such as BUFX10, BUFX12, BUFX14 and BUFX16 in the current process library, inserting the filters from the buffers with the minimum Area in sequence until the DRC vision of s 5-s 9 can be repaired, and if the BUFX16 with the maximum Area cannot be repaired, inserting the type BUFX8 of b1 and returning to the step (1) by taking b1 as a new Driver point with the DRC vision.
After determining the location of the insertion buffer b1, the process of selecting the type of insertion buffer in the present embodiment includes: generally, under a certain process library, there are buffers with various driving capabilities, and the number of fan-out units that can be driven by each buffer is different, and the area size is different. For example, in a process library, 13 different buffers, BUFX1, BUFX2, BUFX3, BUFX4, BUFX5, BUFX6, BUFX8, BUFX10, BUFX12, BUFX14, BUFX16, BUFX20, and BUFX24, exist, and the larger the number is, the stronger the corresponding driving capability is, and the larger the area is. First, the b1 type is selected as BUFX8 with the driving capability in the middle, the Area corresponding to Buffer is Area, and if BUFX8 is inserted to repair the timing design rule constraint violation of s 5-s 9, BUFX8 is the most reasonable register type. If there is a timing design rule violation at s 5-s 9 after BUFX8 is inserted, the registers are reselected according to the Area of BUFX 8. And screening out caches with the Area not exceeding 2 × Area from all caches, for example, BUFX10, BUFX12, BUFX14 and BUFX16 in the current process library, inserting the caches with the minimum areas in the screening in sequence until the time sequence design rule constraint violations from s5 to s9 can be repaired, if the BUFX16 with the maximum Area cannot be repaired, inserting the type of b1 as BUFX8, and returning to the step 1 by taking b1 as a new Driver point with the time sequence design rule constraint violations.
there may be multiple rounds of step (1), step (2), step (3): as shown in fig. 3, if the inserted b1 does not repair the DRC viewing of s 5-s 9, after the steps (2) and (3), the process jumps to the step (1) of the second round, where the Driver point is b1, as shown in fig. 4, and fig. 4 is a schematic diagram of the first buffer adding position provided in this embodiment of the present application. At this time, as shown in fig. 4, the virtual rectangular box defined in the step (1) is repeated, the intersection points of the central axis closer to the center position are a2 and B2 by repeating the step (2), the position of the Buffer B2 is finally selected as a point B2, and the type of the Buffer B2 selected by repeating the step (3) is BUFX 8.
There may be multiple rounds of step 1, step 2, step 3: if the inserted b1 does not fix the timing design rule constraint violations of s 5-s 9 as shown in fig. 3, the process goes to step 1 of the second round after step 2 and step 3, and the Driver point is b1, as shown in fig. 4. At this time, the virtual rectangular box defined in step 1 is repeated as a dotted box shown in fig. 4, step 2 is repeated to obtain intersection points of the central axis closer to the center position as a2 and B2, finally the position of inserting Buffer B2 is selected as B2, and step 3 is repeated to select the type of inserting Buffer B2 as BUFX 8.
In addition, there may be no repair to DRC Violation of s3, s4, s5, s9 in fig. 3, and then proceed to the next iteration of steps (1) (2) (3), as shown in fig. 5, where fig. 5 is a diagram of a second buffer adding position provided by the embodiment of the present application. At this time, the Driver of s3, s4, s5 and s9 is B1, the intersection points of the drawn rectangular frame and the central axis with the Driver Net are A3 and B3, and the quadrant with the largest number of Fanout is also judged, at this time, the number of inserted Buffer B2 is not counted when the quadrant with the largest number of Fanout is judged, the position where Buffer B4 is newly inserted is an A3 point, and the type of B4 is BUFX 8.
There may also be repair-free DRC visibility at Fanout points s1 and s2 of the original Driver in fig. 3, and iteration is also performed to repeat steps (1), (2), and (3), as shown in fig. 6, where fig. 6 is a schematic diagram of the third buffer adding position provided in this embodiment of the present application. The repair was done at the most Fanout insertion point D2, and the type of insertion Buffer b3 was BUFX 8.
Finally, after three iterations, the scheme repairs the overall effect of the Buffer inserted by the DRC visualization point as shown in fig. 7, fig. 7 is an overall effect diagram of adding a Buffer to the chip circuit provided in the embodiment of the present application, and 4 buffers are inserted in total in fig. 7, compared with a scheme in which a Buffer is inserted at a certain distance along the actual routing at the input end of all fan-out units, this embodiment reduces the area increase caused by excessive Buffer insertion, and also solves the DRC visualization problem that may still exist in the scheme of fig. 4. The repair scheme of balanced iteration not only ensures that all DRC violations are repaired, but also saves the area.
the process of importing the PR tool to perform the temporal design rule constraint violation restoration in the embodiment includes: and (3) importing the Time sequence repair script of the final scheme generated in the steps (1) to (4) a PR tool (layout and wiring tool) to repair Time sequence design rule constraint, performing Place (layout) and Route (wiring) of the fan-out unit again by the PR tool, and finally returning the updated Data Base (design file Data packet) to Prime Time (static Time sequence analysis EDA tool) to check again to confirm whether the Time sequence design rule constraint violation is completely repaired.
In the embodiment, a rectangular frame where all the fan-out units and the driving units are located is divided into four quadrants by drawing the central axis, and the intersection point of the central axis with the largest fan-out unit and the Driver Net is selected as the position for inserting the buffer, so that the number of the fan-out units driven by the buffer to be inserted each time is the largest, and the effect of balanced insertion of the buffer is achieved. The embodiment selects the buffer type by the dichotomy mode, and controls the area of the added buffer. In this embodiment, the constraint violation of the timing design rule is repaired in an iterative manner: after a round of repair steps, only one buffer is actually inserted and the type of buffer is controlled, and if repair is still impossible, an iterative repair step is entered. Compared with the original scheme, the embodiment selects a better position to insert the buffer, so that the buffer inserted each time can drive the most fan-out units, and then iterative repair is carried out, thereby ensuring the repair of the time sequence design rule constraint violation and controlling the increase of the number of the buffers; while controlling the type of buffer employed in fixing the violations of the timing design rule constraints. Finally, the increase in area and power consumption caused by inserting buffers when violations of the timing design rule constraints are repaired can be reduced.
The timing design rule constraints in the above embodiments include maximum Transition time (Max Transition), maximum load Capacitance (Max Capacitance), and maximum Fanout (Max Fanout). And when the conversion time of the target area is less than or equal to the maximum conversion time, the load capacitance is less than or equal to the maximum load capacitance, and the fan-out is less than or equal to the maximum fan-out, determining that the target area meets the timing design rule constraint.
Transition is the Transition time of signal jump, and reflects the speed of signal Transition. The rise time and the fall time can be divided according to the transition from low to high and the transition from low to high of the signal, the rise time is defined as the time when the voltage value of the unit port signal rises from 10% to 90%, and the fall time is defined as the time when the voltage value of the unit port signal falls from 90% to 10%. The Transition can be divided into an Input Transition of the Input port and an Output Transition (Output Transition time) of the Output port according to the direction of the port, and the Input Transition of the next-level Cell is the Output Transition of the previous-level Cell.
Since all cells have limited driving capability, Max transitions for their driving are also limited. In order to make all units in the design work normally in a normal driving force range, Max Transition is required to control the problem of driving overload of the units, otherwise normal operation can be caused.
The Output Load refers to a Load capacitor driven by a Cell Output end, and includes Net Capacitance and Cell Capacitance, and the Cell cannot work normally when the Output Load of the Cell exceeds the limit of Max Capacitance. Therefore, in order to allow all units in the design to operate within the normal driving force range, the constraint of Max capacity may also be set.
Fanout refers to the number of logic unit input ends at lower levels to which the logic unit Output ends are directly connected, and since the number of lower level input ends to which the unit Output ends are connected directly affects the magnitude of Output Load, Max Fanout of the unit Output ends can also be set in order to enable all units in the design to work within a normal driving force range.
Since Cell Delay in design is a function of Input Transition (Input Transition time) and Output Load (Output Load capacitance), the presence of DRC viewing makes the Cell Delay value large, affecting the timing of the design. Cell Delay refers to the time for a signal to reach the Input port of a Cell (standard Cell) and then reach the Output port after passing through the Cell, and is defined as the time from 50% rise or 50% fall of the Input signal voltage value to 50% rise or 50% fall of the Output signal voltage value, and is a function of the Input Transition time (Input Transition) and the Output Load (Output Load). The CMOS nonlinear delay calculation model (NLDM) is a mainstream delay calculation model in a time sequence library, and the NLDM calculates Cell delay by taking an Input Transition and an Output Load of the Cell as indexes and through a lookup table and an interpolation method.
DRC ensures that the Cell can work normally and also affects the Delay calculation in STA, so at Timing ECO, the existing DRC vision needs to be repaired. The limit values of the above 3 types of DRC are defined in the process library, and in order to keep a certain margin, a constraint is usually set manually at the Time of STA, and the set value is generally slightly lower than the limit value in the process library, and then when STA is performed in EDA (electronic design automation) tool Prime Time, DRC check is performed on the design of which the layout and wiring have been completed, and a Timing ECO script for repairing DRC Violation is generated. The main reasons for DRC isolation are that the Cell has a weak driving capability, too long traces, High Fanout, and the like, and the basic methods generally used are to insert a Buffer to break a long line, reduce Fanout, reduce Transition, and increase the driving capability of the Driver by the Upsize Cell.
Referring to fig. 8, fig. 8 is a schematic structural diagram of a timing recovery system for a chip circuit according to an embodiment of the present disclosure;
the system may include:
the area dividing module 100 is configured to determine a virtual area corresponding to a driving unit in a chip circuit, and divide the virtual area into a plurality of virtual sub-areas with equal areas by using N virtual lines; the virtual area comprises the virtual units and fan-out units corresponding to the virtual units;
a buffer adding module 200, configured to set a virtual sub-area containing the most fan-out units as a target area, and perform a buffer adding operation in the target area;
a result output module 300, configured to determine that the execution of the timing recovery operation of the chip circuit is completed if the target area meets the constraint of the timing design rule after the execution of the buffer adding operation is completed;
and the iteration module 400 is configured to, after the buffer adding operation is completed, if the target area does not meet the time sequence design rule constraint, use the buffer as a new driving unit, and start a workflow corresponding to the area dividing module.
The embodiment determines a driving unit and a corresponding fan-out unit thereof, determines a virtual area comprising the driving unit and the fan-out unit, divides the virtual area into a plurality of virtual sub-areas with equal areas, and performs a buffer adding operation in a target area with the most fan-out units. And if the target area does not accord with the time sequence design rule constraint after the buffer is added, taking the added buffer area as a new driving unit to iteratively execute the operation of determining the virtual area corresponding to the driving unit in the chip circuit and adding the buffer. The embodiment can repair the time sequence design rule constraint violation in the chip circuit on the premise of reducing the adding quantity of the buffers.
Further, the area division module 100 includes:
a virtual area determination unit configured to determine, as the virtual area, a rectangular frame that includes the driving unit and the fan-out unit and has a smallest area in the chip circuit;
and the area dividing unit is used for taking the central axes of the rectangular frame in the length direction and the width direction as the virtual lines and dividing the virtual area into 4 virtual sub-areas with equal areas by using the virtual lines.
Further, a buffer adding module 200, configured to determine a buffer with a driving capability ranked at a preset position in the process library as a target buffer; the target buffer is also added at the position where the intersection point of the boundary line of the target area and the interconnecting line of the driving unit is located; the time sequence design rule constraint is also used for judging whether the target area accords with the time sequence design rule constraint; if yes, judging that the execution of the time sequence repairing operation of the chip circuit is finished; if not, sequentially selecting buffers with driving capacity ranks higher than the target buffer from the process library according to the driving capacity ranks as alternative buffers; the alternative buffers are sequentially added to intersections of the boundary lines of the target area and the interconnecting lines of the driving units until the target area meets the time sequence design rule constraint and the execution of buffer adding operation is judged to be finished; and if the alternative buffer which enables the target area to accord with the time sequence design rule constraint does not exist, adding the target buffer at the position of the intersection point of the boundary line of the target area and the interconnecting line of the driving unit, and judging that the buffer adding operation is finished.
Further, the occupied area of the alternative buffer is smaller than a preset value; wherein the preset value is positively correlated with the occupied area of the target buffer.
Further, the method also comprises the following steps:
the alternative area optimization module is used for setting the virtual sub-area containing the most fan-out units as a target area, and then setting the virtual sub-area which does not accord with the time sequence design rule constraint except the target area as an alternative area; the N virtual lines are used for dividing the candidate region into a plurality of candidate subregions with equal areas; and also for adding a buffer in the candidate sub-area containing the most fan-out units.
Further, the timing design rule constraints include a maximum transition time, a maximum load capacitance, and a maximum fanout; and when the conversion time of the target area is less than or equal to the maximum conversion time, the load capacitance is less than or equal to the maximum load capacitance, and the fan-out is less than or equal to the maximum fan-out, determining that the target area meets the timing design rule constraint.
Further, the method also comprises the following steps:
the layout and wiring module is used for generating a time sequence repair script according to the position and the type of an added buffer in the chip circuit after judging that the time sequence repair operation of the chip circuit is finished; and the time sequence repairing script is also used for repairing the time sequence design rule constraint violation in a layout and wiring tool.
Since the embodiment of the system part corresponds to the embodiment of the method part, the embodiment of the system part is described with reference to the embodiment of the method part, and is not repeated here.
The present application also provides a storage medium having a computer program stored thereon, which when executed, may implement the steps provided by the above-described embodiments. The storage medium may include: various media capable of storing program codes, such as a usb disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk, or an optical disk.
The application further provides an electronic device, which may include a memory and a processor, where the memory stores a computer program, and the processor may implement the steps provided by the foregoing embodiments when calling the computer program in the memory. Of course, the electronic device may also include various network interfaces, power supplies, and the like.
The embodiments are described in a progressive manner in the specification, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. For the system disclosed by the embodiment, the description is relatively simple because the system corresponds to the method disclosed by the embodiment, and the relevant points can be referred to the method part for description. It should be noted that, for those skilled in the art, it is possible to make several improvements and modifications to the present application without departing from the principle of the present application, and such improvements and modifications also fall within the scope of the claims of the present application.
It is further noted that, in the present specification, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
Claims (9)
1. A time sequence repairing method of a chip circuit is characterized by comprising the following steps:
taking a rectangular frame which comprises a driving unit and a fan-out unit and has the smallest area as a virtual area in a chip circuit, taking central axes of the rectangular frame in the length direction and the width direction as virtual lines, and dividing the virtual area into 4 virtual sub-areas with the same area by using the virtual lines;
setting the virtual sub-area containing the most fan-out units as a target area, and adding a target buffer at the position of the intersection point of the boundary line of the target area and the interconnecting line of the driving unit;
after the adding operation of the target buffer is finished, if the target area accords with the time sequence design rule constraint, judging that the time sequence repairing operation of the chip circuit is finished;
and after the addition operation of the target buffer is finished, if the target area does not accord with the time sequence design rule constraint, taking the target buffer as a new driving unit, and executing the operation of taking a rectangular frame which contains the driving unit and the fan-out unit and has the smallest area as a virtual area in the chip circuit.
2. The timing recovery method according to claim 1, wherein adding a target buffer at a position where an intersection of a boundary line of the target region and an interconnection line of the driving unit is located comprises:
determining a buffer with driving capacity arranged at a preset position in a process library as the target buffer;
judging whether the target area accords with the time sequence design rule constraint;
if yes, judging that the execution of the time sequence repairing operation of the chip circuit is finished;
if not, sequentially selecting buffers with driving capacity ranks higher than the target buffer from the process library according to the driving capacity ranks as alternative buffers;
sequentially adding the alternative buffers at the intersections of the boundary lines of the target area and the interconnecting lines of the driving units until the target area meets the time sequence design rule constraint and judging that the adding operation of the target buffers is finished;
and if the alternative buffer which enables the target area to accord with the time sequence design rule constraint does not exist, adding the target buffer at the position of the intersection point of the boundary line of the target area and the interconnecting line of the driving unit, and judging that the adding operation of the target buffer is finished.
3. The timing recovery method according to claim 2, wherein the occupied area of the alternative buffer is smaller than a preset value; wherein the preset value is positively correlated with the occupied area of the target buffer.
4. The timing recovery method of claim 1, wherein after setting the virtual sub-region containing the most fan-out units as a target region, further comprising:
setting a virtual sub-area which does not conform to the time sequence design rule constraint except the target area as an alternative area;
dividing the candidate region into a plurality of candidate subregions with equal areas by using N virtual lines;
adding a buffer in the candidate sub-area containing the most fan-out units.
5. The timing recovery method of claim 1, wherein the timing design rule constraints comprise a maximum transition time, a maximum load capacitance, and a maximum fanout; wherein when the transition time of the target region is less than or equal to the maximum transition time, the load capacitance is less than or equal to the maximum load capacitance, and the fan-out is less than or equal to the maximum fan-out, it is determined that the target region conforms to the timing design rule constraint.
6. The timing recovery method according to any one of claims 1 to 5, further comprising, after determining that the execution of the timing recovery operation of the chip circuit is completed:
generating a time sequence repair script according to the position and the type of an added buffer in the chip circuit;
and utilizing the time sequence repairing script to repair the time sequence design rule constraint violation in the layout and wiring tool.
7. A timing recovery system for a chip circuit, comprising:
the chip comprises a region dividing module, a signal processing module and a signal processing module, wherein the region dividing module is used for taking a rectangular frame which comprises a driving unit and a fan-out unit and has the smallest area as a virtual region in a chip circuit, taking central axes of the rectangular frame in the length direction and the width direction as virtual lines, and dividing the virtual region into 4 virtual sub-regions with the same area by using the virtual lines;
the buffer adding module is used for setting the virtual sub-area with the most fan-out units as a target area and adding a target buffer at the position of the intersection point of the boundary line of the target area and the interconnecting line of the driving unit;
the result output module is used for judging that the execution of the time sequence repair operation of the chip circuit is finished if the target area accords with the time sequence design rule constraint after the addition operation of the target buffer is finished;
and the iteration module is used for taking the target buffer as a new driving unit and starting a working process corresponding to the region division module if the target region does not accord with the time sequence design rule constraint after the adding operation of the target buffer is finished.
8. An electronic device, comprising a memory and a processor, wherein the memory stores a computer program, and the processor, when calling the computer program in the memory, implements the steps of the timing recovery method of the chip circuit according to any one of claims 1 to 6.
9. A storage medium having stored thereon computer-executable instructions which, when loaded and executed by a processor, carry out the steps of a method of timing recovery of a chip circuit according to any one of claims 1 to 6.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010791428.8A CN111931448B (en) | 2020-08-07 | 2020-08-07 | Time sequence repairing method and system for chip circuit, electronic equipment and storage medium |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010791428.8A CN111931448B (en) | 2020-08-07 | 2020-08-07 | Time sequence repairing method and system for chip circuit, electronic equipment and storage medium |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN111931448A CN111931448A (en) | 2020-11-13 |
| CN111931448B true CN111931448B (en) | 2022-06-17 |
Family
ID=73308120
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010791428.8A Active CN111931448B (en) | 2020-08-07 | 2020-08-07 | Time sequence repairing method and system for chip circuit, electronic equipment and storage medium |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN111931448B (en) |
Families Citing this family (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112364584B (en) * | 2021-01-13 | 2021-03-23 | 南京集成电路设计服务产业创新中心有限公司 | Static time sequence analysis method based on distribution |
| CN112800704B (en) * | 2021-04-06 | 2021-06-25 | 深圳英集芯科技股份有限公司 | Function buffer-based chip rear-end revising method and device and computer equipment |
| CN113515915B (en) * | 2021-04-23 | 2023-04-25 | 成都海光集成电路设计有限公司 | Method, device, equipment and storage medium for inserting filling unit |
| CN113609626B (en) * | 2021-05-20 | 2023-09-15 | 山东云海国创云计算装备产业创新中心有限公司 | Voltage drop violation repairing method and related device |
| CN115688652B (en) * | 2022-10-31 | 2023-06-09 | 正心元科技(杭州)有限公司 | Time sequence optimization method and device based on output conversion constraint and computer equipment |
| CN115577675B (en) * | 2022-11-23 | 2023-03-07 | 飞腾信息技术有限公司 | Time sequence violation repairing method and device, server and readable storage medium |
| CN115688013A (en) * | 2023-01-03 | 2023-02-03 | 苏州浪潮智能科技有限公司 | Interconnection line time sequence optimization method, system, equipment and medium |
| CN115758989B (en) * | 2023-01-10 | 2023-04-07 | 瀚博半导体(上海)有限公司 | Method and system for repairing digital chip layout design rule time sequence violation |
| CN116702664B (en) * | 2023-08-03 | 2024-01-26 | 飞腾信息技术有限公司 | Time violation repairing method and device, computer equipment and storage medium |
| CN117313601A (en) * | 2023-10-10 | 2023-12-29 | 上海合芯数字科技有限公司 | Timing sequence convergence method, device and equipment of integrated circuit |
| CN117454832A (en) * | 2023-10-10 | 2024-01-26 | 北京市合芯数字科技有限公司 | Method, device, equipment and medium for wiring data channel in circuit chip |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101355390A (en) * | 2008-08-12 | 2009-01-28 | 武汉大学 | Method for collecting virtual cluster of underwater sensor network high time resolution data |
| US8448114B1 (en) * | 2012-01-23 | 2013-05-21 | Freescale Semiconductor, Inc. | Method for dual edge clock and buffer tree synthesis |
| CN109783956A (en) * | 2019-01-23 | 2019-05-21 | 中国人民解放军国防科技大学 | Maximum jump time violation repairing method and system based on region division |
| CN109933857A (en) * | 2019-02-19 | 2019-06-25 | 天津飞腾信息技术有限公司 | The Clock Tree trunk Topology g eneration method and system of sensing integrated circuit layout information |
| CN110598235A (en) * | 2019-06-25 | 2019-12-20 | 眸芯科技（上海）有限公司 | Method and system for repairing time sequence violation in chip design |
| CN110619166A (en) * | 2019-09-09 | 2019-12-27 | 中国人民解放军国防科技大学 | Design method of low-power-consumption clock tree |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2003003033A2 (en) * | 2001-06-26 | 2003-01-09 | Morgan And Finnegan, L.L.P., Trustee | Semiconductor programming and testing method and apparatus |
| KR102187640B1 (en) * | 2014-10-22 | 2020-12-08 | 삼성전자주식회사 | Timing matching method of timing analyzer, design method for integrated circuit using the same |
-
2020
- 2020-08-07 CN CN202010791428.8A patent/CN111931448B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101355390A (en) * | 2008-08-12 | 2009-01-28 | 武汉大学 | Method for collecting virtual cluster of underwater sensor network high time resolution data |
| US8448114B1 (en) * | 2012-01-23 | 2013-05-21 | Freescale Semiconductor, Inc. | Method for dual edge clock and buffer tree synthesis |
| CN109783956A (en) * | 2019-01-23 | 2019-05-21 | 中国人民解放军国防科技大学 | Maximum jump time violation repairing method and system based on region division |
| CN109933857A (en) * | 2019-02-19 | 2019-06-25 | 天津飞腾信息技术有限公司 | The Clock Tree trunk Topology g eneration method and system of sensing integrated circuit layout information |
| CN110598235A (en) * | 2019-06-25 | 2019-12-20 | 眸芯科技（上海）有限公司 | Method and system for repairing time sequence violation in chip design |
| CN110619166A (en) * | 2019-09-09 | 2019-12-27 | 中国人民解放军国防科技大学 | Design method of low-power-consumption clock tree |
Non-Patent Citations (3)
| Title |
|---|
| SOC test compression scheme using sequential linear decompressors with retained free variables;Sreenivaas S 等;《2013 IEEE 31st VLSI Test Symposium (VTS)》;20130627;第1-6页 * |
| 基于Innovus提升芯片性能的物理实现方法;边少鲜 等;《电子技术应用》;20191123;第45卷(第8期);第48-52+60页 * |
| 考虑物理布局布线约束的快速时序收敛;刘毅;《中国集成电路》;20160229;第44-47、59页 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN111931448A (en) | 2020-11-13 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN111931448B (en) | Time sequence repairing method and system for chip circuit, electronic equipment and storage medium | |
| US7324363B2 (en) | SPICE optimized for arrays | |
| US6405348B1 (en) | Deep sub-micron static timing analysis in the presence of crosstalk | |
| US5764532A (en) | Automated method and system for designing an optimized integrated circuit | |
| CN103080938B (en) | The method optimized for simultaneous switching noise | |
| Ababei et al. | Multi-objective circuit partitioning for cutsize and path-based delay minimization | |
| US6832361B2 (en) | System and method for analyzing power distribution using static timing analysis | |
| CN109783956B (en) | Maximum jump time violation repairing method and system based on region division | |
| JP2011209793A (en) | Method for design of semiconductor integrated circuit device | |
| CN103164585A (en) | Inserting method and inserting device of buffer | |
| US7840923B2 (en) | Methods and apparatuses for designing integrated circuits using virtual cells | |
| US7318212B2 (en) | Method and system for modeling wiring routing in a circuit design | |
| CN112257368A (en) | Clock layout method, device, EDA tool and computer readable storage medium | |
| US8762919B2 (en) | Circuit macro placement using macro aspect ratio based on ports | |
| US7984415B1 (en) | Merging of equivalent logic blocks in a circuit design | |
| CN113673191A (en) | Timing correction method and apparatus, calculation apparatus, and storage medium | |
| CN116757146A (en) | Distributed random walk parasitic capacitance extraction method, device, equipment and medium | |
| US8776003B2 (en) | System and method for employing side transition times from signoff-quality timing analysis information to reduce leakage power in an electronic circuit and an electronic design automation tool incorporating the same | |
| Nag et al. | Performance-driven simultaneous place and route for island-style FPGAs | |
| US20130152034A1 (en) | System and method for reducing integrated circuit timing derating | |
| CN110083942B (en) | Signal electromigration batch repairing method, system and medium based on physical information | |
| CN115705446A (en) | Post-simulation method and device of integrated circuit | |
| CN114492282A (en) | Through signal line layout processing method and device, chip and storage medium | |
| CN112183006A (en) | Time delay evaluation method and device and readable storage medium | |
| CN112749526A (en) | Power rail design method, apparatus and non-transitory computer readable medium thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |