CN103488457A - Variable time delay predicting method and prediction based variable time delay summator - Google Patents
Variable time delay predicting method and prediction based variable time delay summator Download PDFInfo
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- CN103488457A CN103488457A CN201310446397.2A CN201310446397A CN103488457A CN 103488457 A CN103488457 A CN 103488457A CN 201310446397 A CN201310446397 A CN 201310446397A CN 103488457 A CN103488457 A CN 103488457A
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Abstract
The invention discloses a variable time delay predicting method. The variable time delay predicting method includes steps of S101, inputting the ith to the (i+n)th operands to be summed and transfer states; S102, judging whether a long critical path in current operands is triggered or not according to logical operation of the ith to the (i+n)th operands; S103, deciding whether extra clocks are distributed to to-be-executed summing operation or not on the basis of the transfer state and an enable signal generated by partial current operands, and generating a carry selection signal to determine a carry value sending to a summator corresponding to the ith one of the current operands, wherein the transfer state is the result of comparing a current state of a carry signal outputted by a summator corresponding to the (i-1)th operand with a reservation state of the carry signal. The circuit structures of the summators improved by the predicting method can guarantee correct operating of the summators, and power supply voltage of circuits is reduced or operating frequency of the circuits is increased.
Description
Technical field
The present invention relates to the Digital Electronic Technique field, in particular to a kind of Variable delay Forecasting Methodology and the Variable delay totalizer based on prediction.
Background technology
In the Modern Digital System design, no matter be flush type circuit system or large-scale application-specific integrated circuit, high-performance and low-power consumption are all the indexs that the deviser mainly pursues.In general, in digital signal processing (DSP) field, all complex calculation can be summed up as addition and multiplying.Therefore the totalizer that designs high-performance low-power-consumption is the important component part of large scale digital system.
Along with constantly reducing of cmos device characteristic dimension, the running frequency of totalizer is also significantly promoted, and its supply voltage also constantly reduces simultaneously.But the reducing of device size brought other negative effects equally, wherein comparatively outstanding is that the offset amplitude of technological parameter increases the weight of along with constantly reducing of device size.This parameter shift effect has greatly limited the further reduction of totalizer supply voltage or the raising of running frequency.Main cause wherein is that the parameter shift meeting that small size device brings causes the time delay of totalizer critical path to produce larger fluctuation in actual motion.
Therefore, the deviser has to reserve surplus for this parameter shift phenomenon in the planning in early stage, thereby can guarantee the accurate operation of totalizer.In traditional adder designs method, in order to guarantee still to keep correct computing under situation that circuit is offset to some extent in parameter, often adopt the two kinds of means of running frequency that promote circuit supply voltage or reduce circuit.
Obviously, these two kinds of comparatively conservative methods are that circuit has brought the negative effect on power consumption or performance.Although promote the time delay that supply voltage can shorten critical path, but can increase extra energy consumption for Circuits System equally, and the energy consumption increased finally can make the running temperature of Circuits System further promote, thereby causes constantly increasing the weight of of parameter shift phenomenon, finally forms vicious cycle.If adopt to reduce the way of circuit running frequency, can lose undoubtedly characteristic dimension and reduce this advantage of brought high-performance, and in some specific application, the running frequency of Circuits System is fixing design objective and can't compromising.
Therefore, after the characteristic dimension of cmos device enters 20 nanometers, in the face of the situation of parameter shift, when how can guarantee the correct operation of totalizer, the running frequency that further reduces circuit supply voltage or raising circuit has become hot issue.
Summary of the invention
The present invention is directed to the deficiencies in the prior art, a kind of Variable delay Forecasting Methodology has been proposed, and the totalizer based on the method, when improved adder structure can guarantee the correct operation of totalizer, further reduce the running frequency of circuit supply voltage or raising circuit.
Described Variable delay Forecasting Methodology comprises the following steps:
S101, input i to the i+n position in the operand of pending additive operation and shift state, the current state of the carry signal of the totalizer output that wherein, described transfer state is i-1 position correspondence in described operand and the reservation state result relatively of described carry signal;
The logical operation that S102, basis are carried out i to the i+n position judges the situation whether the current operation number exists long critical path to be excited;
S103, the enable signal based on described transfer state and the generation of part current operation number determine whether the clock outer to pending additive operation allocation, produce the carry select signal simultaneously and determine the carry value of propagating to the totalizer of the i position correspondence in the current operation number.
According to one embodiment of present invention, when the situation that do not exist long critical path to be excited, select the carry input of described current state as i totalizer, the critical path of then totalizer being carried out to computing is divided into two sections since place, i-1 position and carries out.
According to one embodiment of present invention, when the situation that exists long critical path to be excited, described current state is predicted, and adopting the carry input of the carry signal of prediction as i totalizer, the critical path of then totalizer being carried out to computing is divided into two sections since place, i-1 position and carries out.
According to one embodiment of present invention, the reservation state that the carry signal of described prediction is i-1 position carry signal.
According to one embodiment of present invention, when described current state is stablized, whether the carry signal of more described prediction and described current state be accurate to determine prediction, if, do not enable time delay, if forecasting inaccuracy is true, enable time delay, give the outer clock of arithmetic operation allocation to re-start computing.
According to one embodiment of present invention, comprise to the outer clock of arithmetic operation allocation and latch input register and the extra clock of output register.
According to one embodiment of present invention, in step S102, if described operand (corresponding i to the i+n position is all different, there will be carry propagation, and the logical operation of carrying out at this is:
According to an aspect of the present invention, also provide a kind of Variable delay totalizer based on prediction, it comprises:
M additive operation unit, for receiving, operand is inputted and carry out additive operation output;
Register cell, with totalizer FA
i-1the carry signal of output is for inputting to produce the reservation state of described carry signal;
Comparing unit, to totalizer FA
i-1current state and the described reservation state of the carry signal of output compare to produce the transfer state;
The time delay predicting unit, using i to the i+n position in operand and described transfer state as input, judge according to the logical operation that i to the i+n position is carried out situation the output carry selection signal whether the current operation number exists long critical path to be excited, then, whether the XOR function formed based on described transfer state and part current operation number predicts the clock outer to pending additive operation allocation.
According to one embodiment of present invention, the Variable delay serial adder also comprises: selector switch, and it take described current state and described reservation state is input, the described carry select signal of take is selecting side,
When long critical path is not excited, described selecting side is controlled and is selected described current state to be exported,
When long critical path is excited, using described reservation state as totalizer FA in first clock
icarry signal exported,
After described current state is stable, described time delay predicting unit judges and usings described reservation state as totalizer FA based on the transfer state
ithe prediction of carry signal whether accurate, if accurately, calculate and as usual carry out, if inaccurate, select the current state of described carry signal as output, simultaneously, described time delay predicting unit is sent the signal of enabling time delay, and gives the outer clock of arithmetic operation allocation to re-start computing.
The present invention has brought following beneficial effect: this adder circuit structure has been considered the current state of input carry signal simultaneously and has been shifted state on the formation of time delay predicting unit.New structure has been eliminated the redundancy clock expense produced due to the correlativity between data in the actual operation.When handled input data variation is comparatively slow, as calculated the data that gathered from the temperature sensing net, owing between the input data, thering is in this case more strong correlativity, therefore can eliminate more clock redundancy by totalizer time delay prediction method of the present invention, the energy therefore consumed is lower.
Other features and advantages of the present invention will be set forth in the following description, and partly from instructions, become apparent, or understand by implementing the present invention.Purpose of the present invention and other advantages can realize and obtain by specifically noted structure in instructions, claims and accompanying drawing.
The accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, below will do simple introduction to needed accompanying drawing in embodiment or description of the Prior Art:
Fig. 1 is the schematic diagram of serial adder traditional in prior art;
Fig. 2 is ECIP Variable delay totalizer schematic diagram;
Fig. 3 is according to embodiments of the invention Variable delay low-power consumption totalizer schematic diagram;
Fig. 4 is the additive operation schematic diagram while between the operand of inputting in actual operation, having correlativity;
Fig. 5 is the circuit structure schematic diagram for generation of the PTSP control signal.
Embodiment
Describe embodiments of the present invention in detail below with reference to accompanying drawing, to the present invention, how the application technology means solve technical matters whereby, and the implementation procedure of reaching technique effect can fully understand and implement according to this.It should be noted that, only otherwise form conflict, each feature in various embodiments of the present invention and each embodiment can mutually combine, and formed technical scheme is all within protection scope of the present invention.
The problem that many researchers exist prior art has proposed corresponding scheme, as optimizes and revises the device size size or dynamically change the device bias voltage.
In design specific to totalizer, some researchs are attempted to realize the high-performance low-power-consumption purpose under the parameter shift effect by the further transformation to the conventional adders structure.Totalizer has more type and structure as the important component part of digital circuit.
Serial adder as shown in Figure 1, it is by after being connected the single-bit full adder, and current input signal can produce handing on of carry signal separately one-level one-level.Obviously, FA
1to FA
16the carry signal path of passing by be the critical path of whole serial adder, the supply voltage of circuit and running frequency must be designed according to this critical path.Under certain supply voltage, the duration of the single clock of system must be greater than the time delay of critical path, otherwise just there will be the sequential mistake.
For this structure, Mohapatra has proposed a kind of Variable delay totalizer (Elastic Clocking Based on Input Prediction, referred to as ECIP) of low-power consumption tolerable parameter shift, as shown in Figure 2.Ask for an interview document Mohapatra D about the detailed introduction of ECIP, Karakonstantis G, Roy K.Low-power process-variation tolerant arithmetic units using input-based elastic clocking.Proceedings of the2007international symposium on Low power electronics and design.ACM, 2007:74-79(Mohapatra D, Karakonstantis G, Roy K, " the tolerable computing unit design of low-power consumption process deviation based on input data elasticity clock technology ", international low power dissipation electrons in 2007 and design meeting, ACM, 2007:74-79.）。Only introduce part related to the present invention at this, other does not repeat.
The proposition of this structure of ECIP is based on 3 considerations:
The first, because the power consumption of circuit is proportional to the quadratic power of supply voltage, the supply voltage that therefore reduces circuit is the effective means that obtains low-power consumption.
The second, although reduce the effect that voltage can obtain low-power consumption, the time delay meeting of circuit increases along with the reduction of voltage.The parameter shift effect can strengthen along with the reduction of voltage equally.If want to guarantee that circuit sequence does not make a mistake, must reduce running frequency.The inapplicable structure high-performance low-power-consumption of obvious this traditional design method totalizer.Therefore, must when reducing voltage, transform original circuit structure, the time delay of its critical path is reduced.
The 3rd, by the look-ahead to present input data, original critical path time delay can be dwindled to half.Take 32 bit adder as example, and its principle of work is: the 13rd input to the 17th full adder of serial adder sent in the time delay predicting unit, reduced whole circuit supply voltage simultaneously, running frequency remains unchanged.When in prediction module, current two input bits of each full adder are not identical, as A
13 ... 17=10101, B
13 ... 17=01010, mean that the carry output meeting of the 12nd full adder propagates into the full adder of back by 5 bits of centre, now critical path likely is excited.
Because supply voltage has reduced and running frequency remains unchanged, therefore when running into this situation, prediction module meeting output low level, make the input and output register of totalizer keep lock-out state, thereby make whole totalizer can obtain in this case an extra clock, guaranteed that computing can correctly carry out.
In other cases, while not forming the situation of carry propagation in prediction module, the carry chain of whole totalizer will be interrupted.Now, prediction module output high level, whole totalizer only needs a clock period just can obtain correct operation result.Because the probability that forms 5 bit successive carries propagation in actual computing is less, therefore, this structure makes totalizer running frequency under the low voltage operating situation not be lowered, and is conducive to the error that tolerance parameter shift to a certain degree brings.
But in order to make extra clock expense be limited in less magnitude, this structure has to adopt the above prediction of 5 bits, this requirement can not be received when the shorter serial adder of design figure place, and this structure is not considered in calculating continuously, the reservation meeting of last carry status causes Different Results to the computing of totalizer, thereby has caused the partial redundance clock.
Given this, the present invention proposes a kind of Variable delay Forecasting Methodology.In the method, at first perform step S101, input operand A and i to the i+n position in B of pending additive operation and shift state CompSignal, the current state Cout_Present of the carry signal of the totalizer output that wherein, transfer state CompSignal is i-1 position correspondence in operand and the reservation state Cout_Preserved result relatively of carry signal.
In step S102, judge that according to the logical operation that i to the i+n position is carried out current operation counts the situation situation that long critical path is excited in other words that whether has carry propagation in A and B, and output carry selection signal Carry_Tmp, be also carry select signal Carry_sel as shown in Figure 3.The present invention judges whether to occur that carry propagation is mainly that decision operation is counted A, and whether i to the i+n position that B is corresponding is all different, if so, there will be carry propagation.Therefore, the logical operation of carrying out is:
In step S103, count A based on shifting state CompSignal and part current operation, the enable signal that B produces determines whether the clock outer to pending additive operation allocation, produce carry select signal Carry_sel determines to propagate and counts A to current operation, the carry value of the totalizer of the i position correspondence in B simultaneously.
When long critical path is not excited, select the current state Cout_Present of carry signal of totalizer output of i-1 position correspondence as the carry input of i totalizer, the critical path of then totalizer being carried out to computing is located to be divided into two sections and is carried out since the i-1 position.Therefore, in a clock, computing can complete.
When long critical path is excited, current state Cout_Present to be predicted, and adopted the carry input of the carry signal of prediction as i totalizer, the critical path of then totalizer being carried out to computing is divided into two sections since place, i-1 position and carries out.In one embodiment, the reservation state Cout_Preserved that the carry signal of prediction is i-1 position carry signal.Therefore in the first clock period, due to the Cout_Preserved signal, in steady state (SS), whole totalizer is broken into two sections at place, i-1 position equally, in the time of a clock before and after two sections additions can stability Calculation out.
When the current state Cout_Present of i-1 position carry signal stablizes, whether the carry signal of comparison prediction (the namely reservation state Cout_Preserved in the present embodiment) is accurate to determine prediction with current state Cout_Present, if, do not enable time delay, if forecasting inaccuracy is true, enable time delay, give the outer clock of arithmetic operation allocation to re-start computing.
Comprise to the outer clock of arithmetic operation allocation here, and latch input register and the extra clock of output register.
According to one embodiment of present invention, also provide a kind of Variable delay serial adder based on above-mentioned Forecasting Methodology.It comprises: M additive operation unit F A
m, register cell, comparing unit and time delay predicting unit.Wherein, M additive operation unit F A
mfor receiving, operand is inputted and carry out additive operation output, and register cell is with totalizer FA
i-1the carry signal of output is for input, in order to produce the reservation state Cout_Preserved of carry signal.Comparing unit is to totalizer FA
i-1the current state Cout_Present of the carry signal of output and reservation state Cout_Preserved compare to produce transfer state CompSignal.In the time delay predicting unit, using i to the i+n position in operand and described transfer state CompSignal as input, judge according to the logical operation that i to the i+n position is carried out whether the current operation number exists the situation of carry propagation output carry to select signal Carry_sel, then, count A based on shifting state CompSignal and part current operation, whether the XOR computing of B predicts the clock outer to pending additive operation allocation.
In addition, in one embodiment, totalizer also comprises selector switch, it take current state Cout_Present and to retain state Cout_Preserved be input, the carry select signal Carry_sel of take is selecting side, and when no-carry is propagated, selecting side is controlled and selected current state Cout_Present to be exported, when carry propagation is arranged, using in first clock and retain state Cout_Preserved as totalizer FA
icarry signal exported, after current state Cout_Present is stable, the time delay predicting unit judges to retain state Cout_Preserved as totalizer FA based on shifting state CompSignal
ithe prediction of carry signal whether accurate, if accurately, calculate and as usual carry out, if inaccurate, select the current state Cout_Present of described carry signal as output, simultaneously, the time delay predicting unit is sent the signal of enabling time delay, and gives the outer clock of arithmetic operation allocation to re-start computing.
The 32 bit serial totalizers of below take are described the present invention in more detail as example.
As shown in Figure 3, the Variable delay totalizer PTSP that has shown the current state of based on data and transfer state.In this totalizer, i is that 13, n gets 0,1,2,3,4.Therefore, the input signal of predicting unit is current input signal A
13, A
14, A
15, A
16, A
17, and B
13, B
14, B
15, B
16, B
17, comprise 1 transfer of bits state CompSignal simultaneously.Shifting state CompSignal is by the 12nd full adder FA
12carry output signals compare with original signal after 1 bit trigger and to obtain.In the present embodiment, time delay predicting unit output single-bit signal Enable and Carry_Tmp, the former is used for locking output and output register, and the latter is used for selecting to send to full adder FA
13carry signal.Here, can claim that single-bit signal Enable is latch signal.
When
the time, mean that current input signal is not the 13rd to 17 situations that form carry propagation.Now, the critical path of totalizer is broken into two sections, and Enable and Carry_Tmp signal are set to high level, send FA to
13carry signal be current FA
12output carry signal Cout_Present, in a clock, whole calculating is accomplished.
When
the time, Carry_Tmp is set to low level, FA
13the carry signal carry signal Cout_Preserved that selects previous state to carry over.That is, now carry signal is guessed.In the first clock period, due to the Cout_Preserved signal, in steady state (SS), therefore, whole totalizer is broken into two sections at the 12nd place equally, in the time of a clock before and after two sections additions can stability Calculation out.At first clock end, new Cout_Present can settle out, if now the CompSignal signal is low level, the conjecture that is illustrated in first clock is correct, in this case, Enable is set to high level, and whole calculating does not need to recalculate, and a clock just can draw correct result.
But, if now CompSignal is high level, mean that the conjecture in early stage is wrong, now the Enable signal is set to low level, and the input and output register is latched, and the Carry_Tmp signal is set to low level, FA simultaneously
13obtain current correct carry input signal, whole calculating like this needs an extra clock period could correctly calculate complete.
Be compared to the ECIP totalizer, the present invention has not only considered that the current state of input data, to the exciting of critical path, considered the reservation state of carry digit simultaneously.In the ECIP circuit structure, if predicting unit detects the state of carry propagation, circuit will think that the computing of current data needs two clock period.Obviously this practice is also improper in actual operation, can cause clock redundancy to a certain extent.
As shown in Figure 4, if do not consider the continuity of calculating, according to the circuit structure of ECIP, computing for the second time is bound to be regarded as long critical path excited state by the time delay predicting unit, thereby can distribute two clocks to whole totalizer.
But, if consider the continuity of computing, although computing for the second time has the characteristics of carry propagation, due to after computing for the first time stablizes, its carry-out bit value equates just with operation result for the second time.Therefore in actual operation, computing for the second time only needs a clock just can obtain correct result.The present invention has utilized this phenomenon exactly, after carry-out bit is retained by register, the computing that excites long critical path is done to further prediction, eliminated part clock redundancy, thereby make totalizer consume lower energy under the prerequisite of calculating a certain amount of data.
Fig. 5 produces the particular circuit configurations of carry select signal Carry_Sel in the time delay predicting unit, this structure has important effect in the realization of whole totalizer.
This adder circuit structure has been considered the current state of input data simultaneously and has been shifted state on the formation of time delay predicting unit.New structure has been removed the redundancy clock expense produced due to the correlativity between data in the actual operation.When handled input data variation is comparatively slow, as calculated the data that gathered from the temperature sensing net, owing between the input data, having in this case more strong correlativity, the clock redundancy of therefore eliminating by the present invention can be more, and the energy of consumption will be lower.Simultaneously, in the ECIP circuit structure, for the excitation probability that guarantees long critical path remains on less scope, have at least the input of 5 full adders to be admitted to prediction module.This constraint makes the ECIP circuit structure more arrive larger difficulty when the short bit adder of design, and long prediction bit makes the amplitude of lower voltage or frequency upgrading limited.In the present invention, owing to having considered this factor of transfer state, make the full adder number of sending into the time delay predicting unit be reduced to below 3 or 3, for designing short bit adder, provide good strategy, make its lower voltage or frequency upgrading amplitude that further raising be arranged.
According to characteristics of the present invention, can be by its called after PTSP(Present and Transitional State Prediction, referred to as PTSP) totalizer.For the low-power consumption Variable delay totalizer more proposed by the invention characteristic of property with respect to conventional serial totalizer and ECIP totalizer, we have adopted SMIC65nm technique, use circuit simulation tools HSPICE to carry out emulation relatively and analyzed three kinds of different circuit structures.
Specific environment and correlation parameter that table 1 is emulation.In emulation testing, we have compared the conventional serial totalizer, ECIP totalizer and PTSP totalizer of the present invention.In test, at first adopt Matlab to generate random input data, then by emulation tool HSPICE, measure power consumption and energy.
Table 1 simulated environment and correlation parameter
| Operating voltage | 1.2V |
| Temperature | 25℃ |
| Capacitive load | 0.004PF |
| Clock frequency | 250MHz |
| Process modeling | TT |
Table 2 has been listed three kinds of energy (unit is a joule J) that totalizer consumes after 5000 random inputs of emulation, has listed file names with and has had the energy that different prediction bit number totalizers consume.From simulation result, along with reducing of prediction bit number, PTSP Variable delay totalizer is than ECIP totalizer consumption energy still less, and its chief reason is that the time delay predicting unit after improving has been eliminated a large amount of clock redundancies.With conventional adders, compare, due to PTSP is in operation original critical path can be broken into to two sections, so can the decrease supply voltage, until the time delay of shorter critical path is no more than a clock period, get final product.Because conventional adders does not have the time delay predicting unit, therefore under difference prediction bit number, the energy of its consumption is identical.
Table 2 trigger output terminal Q Time Created and total time delay are relatively
| ? | 4 bit predictions | 3 bit predictions | 2 bit predictions |
| The PTSP totalizer | 5.672e-09J | 5.726e-09J | 5.814e-09J |
| The ECIP totalizer | 5.705e-09J | 6.041e-09J | 6.712e-09J |
| Conventional adders | 16.765e-09J | 16.765e-09J | 16.765e-09J |
Although the disclosed embodiment of the present invention as above, the embodiment that described content just adopts for the ease of understanding the present invention, not in order to limit the present invention.Technician in any the technical field of the invention; under the prerequisite that does not break away from the disclosed spirit and scope of the present invention; can do any modification and variation what implement in form and on details; but protection scope of the present invention, still must be as the criterion with the scope that appending claims was defined.
Claims (9)
1. a Variable delay Forecasting Methodology, is characterized in that, comprises the following steps:
S101, input the operand (A of pending additive operation, B) i to the i+n position in and transfer state (CompSignal), the current state (Cout_Present) of the carry signal of the totalizer output that wherein, described transfer state (CompSignal) is i-1 position correspondence in described operand and reservation state (Cout_Preserved) result relatively of described carry signal;
S102, the situation that whether exists long critical path to be excited according to the logical operation judgement current operation number (A, B) that i to the i+n position is carried out;
S103, based on described transfer state (CompSignal) and part current operation number (A, B) enable signal produced determines whether the clock outer to pending additive operation allocation, produce carry select signal (Carry_sel) simultaneously and determine the carry value of propagating to the totalizer of the i position correspondence in current operation number (A, B).
2. Variable delay Forecasting Methodology as claimed in claim 1, it is characterized in that, when the situation that do not exist long critical path to be excited, select the carry input of described current state (Cout_Present) as i totalizer, the critical path of then totalizer being carried out to computing is divided into two sections since place, i-1 position and carries out.
3. Variable delay Forecasting Methodology as claimed in claim 1, it is characterized in that, when the situation that exists long critical path to be excited, described current state (Cout_Present) is predicted, and adopting the carry input of the carry signal of prediction as i totalizer, the critical path of then totalizer being carried out to computing is divided into two sections since place, i-1 position and carries out.
4. Variable delay Forecasting Methodology as claimed in claim 3, is characterized in that, the reservation state (Cout_Preserved) that the carry signal of described prediction is i-1 position carry signal.
5. Variable delay Forecasting Methodology as claimed in claim 4, it is characterized in that, in described current state (Cout_Present) while stablizing, whether the carry signal of more described prediction and described current state (Cout_Present) be accurate to determine prediction, if so, do not enable time delay, if forecasting inaccuracy is true, enable time delay, give the outer clock of arithmetic operation allocation to re-start computing.
6. Variable delay Forecasting Methodology as claimed in claim 5, is characterized in that, comprises to the outer clock of arithmetic operation allocation and latch input register and the extra clock of output register.
7. Variable delay Forecasting Methodology as claimed in claim 1, is characterized in that, in step S102, if i to the i+n position of described operand (A, B) correspondence is all different, there will be carry propagation, and the logical operation of carrying out is:
8. the Variable delay totalizer based on prediction, is characterized in that, comprising:
M additive operation unit (FA
m), for receiving, operand is inputted and carry out additive operation output;
Register cell, with totalizer FA
i-1the carry signal of output is for inputting to produce the reservation state (Cout_Preserved) of described carry signal;
Comparing unit, to totalizer FA
i-1the current state (Cout_Present) of the carry signal of output compares to produce transfer state (CompSignal) with described reservation state (Cout_Preserved);
The time delay predicting unit, using i to the i+n position in operand and described transfer state (CompSignal) as the input, judge according to the logical operation that i to the i+n position is carried out situation the output carry selection signal (Carry_sel) whether the current operation number exists long critical path to be excited, then, whether the XOR function formed based on described transfer state (CompSignal) and part current operation number (A, B) predicts the clock outer to pending additive operation allocation.
9. Variable delay totalizer as claimed in claim 8, it is characterized in that, also comprise: selector switch, it take described current state (Cout_Present) and described reservation state (Cout_Preserved) is input, the described carry select signal (Carry_sel) of take is selecting side
When long critical path is not excited, described selecting side is controlled and is selected described current state (Cout_Present) to be exported,
When long critical path is excited, using described reservation state (Cout_Preserved) as totalizer FA in first clock
icarry signal exported,
After described current state (Cout_Present) is stable, described time delay predicting unit judges and usings described reservation state (Cout_Preserved) as totalizer FA based on transfer state (CompSignal)
ithe prediction of carry signal whether accurate, if accurately, calculate and as usual carry out, if inaccurate, select the current state (Cout_Present) of described carry signal as output, simultaneously, described time delay predicting unit is sent the signal of enabling time delay, and gives the outer clock of arithmetic operation allocation to re-start computing.
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| CN109062111A (en) * | 2018-08-29 | 2018-12-21 | 郑州云海信息技术有限公司 | A kind of power supply IC and its delay time control device |
| CN110045944A (en) * | 2019-04-23 | 2019-07-23 | 陈新豫 | Novel mimimum adder |
| CN113010144A (en) * | 2021-03-05 | 2021-06-22 | 唐山恒鼎科技有限公司 | 1bit plus-minus device |
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| CN109062111B (en) * | 2018-08-29 | 2021-06-29 | 郑州云海信息技术有限公司 | Power supply IC and time delay control device thereof |
| CN110045944A (en) * | 2019-04-23 | 2019-07-23 | 陈新豫 | Novel mimimum adder |
| CN113010144A (en) * | 2021-03-05 | 2021-06-22 | 唐山恒鼎科技有限公司 | 1bit plus-minus device |
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| CN103488457B (en) | 2016-08-31 |
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