CN115014514A - Integrating circuit and illuminance sensor - Google Patents

Abstract

An integration circuit, comprising: an amplifier having a first input terminal, a second input terminal, and an output terminal, the output terminal generating an output voltage; an integrating capacitor provided between the first input terminal and the output terminal of the amplifier; a first switch provided between a generation source of the current to be detected and the first input terminal of the amplifier; a second switch connected in parallel with the integrating capacitor; a control circuit which controls the states of the first switch and the second switch; and an adjustment circuit including a comparator that compares a comparison voltage corresponding to the output voltage with a predetermined determination voltage and an adjustment current generation circuit that generates an adjustment current, wherein the adjustment circuit is capable of supplying a positive or negative adjustment charge generated by the adjustment current to the first input terminal of the amplifier in accordance with a comparison result of the comparator.

Description

Integrating circuit and illuminance sensor

Technical Field

The present disclosure relates to an integrating circuit and an illuminance sensor.

Background

The integrating circuit used for the illuminance sensor and the like is configured to include an amplifier, an integrating capacitor, and the like. The integration circuit accumulates charges of a current to be detected (for example, a photocurrent generated by a photodiode) generated by a current generation source in an integration capacitor during an integration period, and generates a signal corresponding to the accumulated charges.

Prior art documents: patent document 1 (Japanese patent laid-open publication No. 2011-4327)

In the above-described integrating circuit, noise is generated in the amplifier. Depending on the magnitude of the detection target current, the influence of noise becomes large, and it becomes difficult to obtain a desired signal-to-noise ratio (i.e., accuracy of the integration result deteriorates). In addition, a leakage current may occur in a generation source of the current to be detected. The leakage current also becomes a factor of deterioration in accuracy of the integration result.

Disclosure of Invention

The invention aims to provide an integrating circuit and an illuminance sensor which contribute to the improvement of the accuracy of an integration result.

The disclosed integration circuit has: an amplifier configured to have a first input terminal, a second input terminal, and an output terminal, and to generate an output voltage at the output terminal; an integrating capacitor disposed between the first input terminal and the output terminal of the amplifier; a first switch provided between a generation source of a detection target current and the first input terminal of the amplifier; a second switch connected in parallel with the integrating capacitor; a control circuit configured to control states of the first switch and the second switch; and an adjustment circuit configured to include a comparator configured to compare a comparison voltage corresponding to the output voltage with a predetermined determination voltage, and an adjustment current generation circuit configured to generate an adjustment current, wherein the adjustment circuit is capable of supplying positive or negative adjustment charge generated by the adjustment current to the first input terminal of the amplifier in accordance with a comparison result of the comparator.

According to the present disclosure, an integration circuit and an illuminance sensor that contribute to improvement in accuracy of an integration result can be provided.

Drawings

Fig. 1 is a configuration diagram of an illuminance sensor having a basic configuration according to an embodiment of the present disclosure.

Fig. 2 is a configuration diagram of the illuminance sensor of fig. 1 in a first connection mode using a photodiode.

Fig. 3 is a configuration diagram of the illuminance sensor of fig. 1 in a case where a second connection method of a photodiode is employed.

Fig. 4 is a simplified diagram showing an output signal of an amplifier for an illuminance sensor having a basic configuration.

Fig. 5A, 5B, and 5C are waveform diagrams of a reference example of an illuminance sensor having a basic configuration.

Fig. 6 relates to example EX1_ a belonging to the first embodiment of the present disclosure, and is a configuration diagram of an illuminance sensor.

Fig. 7 relates to example EX1_ a pertaining to the first embodiment of the present disclosure, and is a diagram for explaining the operation of the adjustment circuit.

Fig. 8 relates to example EX1_ a belonging to the first embodiment of the present disclosure, and is a diagram showing the state of each switch and the output waveform of the amplifier (first case).

Fig. 9 relates to example EX1_ a pertaining to the first embodiment of the present disclosure, and is a diagram showing the state of each switch and the output waveform of the amplifier (second case).

Fig. 10 relates to example EX1_ a belonging to the first embodiment of the present disclosure, which is a diagram for comparing the waveforms of fig. 8 (first case) and fig. 9 (second case).

Fig. 11A, 11B, and 11C are diagrams for explaining the influence of noise at the end of integration.

Fig. 12 relates to example EX1_ B belonging to the first embodiment of the present disclosure, and is a configuration diagram of an illuminance sensor.

Fig. 13 relates to example EX1_ B pertaining to the first embodiment of the present disclosure, and is a diagram showing a relationship between an integration period and the state of each switch.

Fig. 14A, 14B, and 14C relate to example EX1_ B belonging to the first embodiment of the present disclosure, and are diagrams showing the state of each switch and the output waveform of the amplifier in the vicinity of the end of the integration period.

Fig. 15 relates to example EX1_ C belonging to the first embodiment of the present disclosure, and is a configuration diagram of an adjustment current generation circuit.

Fig. 16 is an explanatory diagram of an operation of the adjustment current generation circuit of fig. 15.

Fig. 17 relates to example EX1_ D pertaining to the first embodiment of the present disclosure, and is a diagram showing a modified structure of the illuminance sensor of fig. 6.

Fig. 18 relates to example EX1_ D pertaining to the first embodiment of the present disclosure, and is a diagram showing a modified structure of the illuminance sensor of fig. 12.

Fig. 19 relates to example EX1_ D pertaining to the first embodiment of the present disclosure, and is a diagram showing the state of each switch and the output waveform of the amplifier in the illuminance sensor of fig. 17 or 18.

Fig. 20 relates to example EX1_ F pertaining to the first embodiment of the present disclosure, which is an external view of a smartphone.

Fig. 21 is a structural diagram of an illuminance sensor of a comparative example, which is referred to in the second embodiment of the present disclosure.

Fig. 22 is an explanatory view of the operation of the illuminance sensor of the comparative example.

Fig. 23 relates to example EX2_ a belonging to the second embodiment of the present disclosure, and is a structural diagram of an illuminance sensor.

Fig. 24 relates to example EX2_ a pertaining to the second embodiment of the present disclosure, and is a state transition diagram of each switch in the illuminance sensor.

Fig. 25 relates to example EX2_ B belonging to the second embodiment of the present disclosure, and is a structural diagram of an illuminance sensor.

Fig. 26 relates to example EX2_ B belonging to the second embodiment of the present disclosure, and is a timing chart of an integration operation in an illuminance sensor.

Fig. 27 is a structural diagram of an illuminance sensor according to a third embodiment of the present disclosure.

Detailed Description

Hereinafter, examples of embodiments of the present disclosure will be specifically described with reference to the drawings. In the drawings referred to, the same components are denoted by the same reference numerals, and the overlapping description of the same components is omitted in principle. In the present specification, for the sake of simplifying the description, information, signals, physical quantities, elements, parts, and the like may be referred to by describing symbols or signs referring to the information, signals, physical quantities, elements, parts, and the like, and names of the information, signals, physical quantities, elements, parts, and the like corresponding to the symbols or signs may be omitted or abbreviated. For example, the integration capacitor referred to by "13" described later (see fig. 1) may be referred to as the integration capacitor 13, and may be referred to as the capacitor 13, but all of them refer to the same component.

First, several terms used in the description of the embodiments of the present disclosure will be described. A line refers to a wiring that propagates or applies an electrical signal. Ground has a potential of 0V (zero volts) as a reference. The 0V potential is sometimes referred to as ground potential. In the embodiment of the present disclosure, a voltage shown without particularly providing a reference represents a potential seen from the ground.

An arbitrary switch described later can be formed of 1 or more MOSFETs (metal-oxide-semiconductor field-effect transistors). The arbitrary switch has first and second terminals and a control terminal, and is turned ON (ON) or OFF (OFF) in response to a control signal applied to the control terminal. One of the first terminal and the second terminal of an arbitrary switch is sometimes referred to as one end of the switch, and the other is sometimes referred to as the other end of the switch. When a switch of interest is turned on, the first and second terminals of the switch of interest are turned on, and signal transmission (charge transfer) via the switch of interest is realized. When a switch of interest is in an off state, the first and second terminals of the switch of interest are in a non-conductive state (blocking state), and signal transmission (charge transfer) via the switch of interest is not possible. Hereinafter, a period during which any switch is turned on may be referred to as an on-period, and a period during which the switch is turned off may be referred to as an off-period. In some cases, switching from the off state to the on state is represented as on (turn on) and switching from the on state to the off state is represented as off (turn off) for any switch. The time at which the switch is turned on may be referred to as an on time, and the time at which the switch is turned off may be referred to as an off time.

< first embodiment >

A first embodiment of the present disclosure will be explained. Fig. 1 shows a configuration of an illuminance sensor 1 as an illuminance sensor having a basic configuration. The illuminance sensor 1 includes: a photodiode 11, an amplifier (operational amplifier) 12, an integrating capacitor 13, a control circuit 14, a detection circuit 15, switches SW1 and SW2, and reference potential terminals 31 and 32. The reference potential Vref having a predetermined dc potential is commonly applied to the reference potential terminals 31 and 32. The reference potential Vref has a positive dc potential. Further, the reference potential may be replaced with the reference voltage. The reference potential terminals 31 and 32 may be understood as a common terminal.

The photodiode 11 generates a photocurrent Ip (the photocurrent Ip is not shown in fig. 1) corresponding to the amount of incident light. The incident light amount is the light amount of light incident to the photodiode 11, and is also the light amount of light incident to the illuminance sensor 1.

The switches SW1 and SW2 are switches (bus switches) capable of transmitting analog signals. The control circuit 14 supplies control signals CNT1 and CNT2 to control terminals of the switches SW1 and SW2, thereby individually controlling states (on/off states) of the switches SW1 and SW 2.

The amplifier 12 has: an inverting input terminal, a non-inverting input terminal, and an output terminal. The non-inverting input terminal of the amplifier 12 is connected to the reference potential terminal 32. Therefore, the reference potential Vref is applied to the non-inverting input terminal of the amplifier 12. The integrating capacitor 13 is provided between the inverting input terminal of the amplifier 12 and the output terminal of the amplifier 12, and the switch SW2 is connected in parallel with the integrating capacitor 13. More specifically, one end of the integration capacitor 13, one end of the switch SW2, and the inverting input terminal of the amplifier 12 are commonly connected to the input line LN1, and the other end of the integration capacitor 13, the other end of the switch SW2, and the output terminal of the amplifier 12 are commonly connected to the output line LN 2. The output voltage Vout of the amplifier 12 is output from the output terminal of the amplifier 12. In other words, the amplifier 12 generates the output voltage Vout at its output terminal.

The detection circuit 15 detects illuminance, which is a detection target of the illuminance sensor 1, from the output voltage Vout, and generates and outputs an illuminance sensing signal Sout indicating a detection result of the illuminance. The illuminance, which is the detection target of the illuminance sensor 1, is a physical quantity proportional to the amount of incident light of the photodiode 11.

A switch SW1 is provided between the input line LN1 and the photodiode 11. The connection method of the photodiode 11 includes a first connection method and a second connection method.

The illuminance sensor 1A in fig. 2 is the illuminance sensor 1 in which the first connection method is adopted for the photodiode 11. In the first connection method, the anode of the photodiode 11 is connected to the reference potential terminal 31, the cathode of the photodiode 11 is connected to one end of the switch SW1, and the other end of the switch SW1 is connected to the input line LN 1.

The illuminance sensor 1B in fig. 3 is the illuminance sensor 1 in which the photodiode 11 employs the second connection method. In the second connection method, the cathode of the photodiode 11 is connected to the reference potential terminal 31, the anode of the photodiode 11 is connected to one end of the switch SW1, and the other end of the switch SW1 is connected to the input line LN 1.

The direction of the photocurrent Ip generated by the photodiode 11 is a direction from the cathode toward the anode of the photodiode 11. Therefore, in the first connection scheme, in the on section of the switch SW1, a photocurrent Ip (positive charge) flows in a direction from the input line LN1 toward the photodiode 11 through the switch SW1 (that is, in the on section of the switch SW1, the photocurrent Ip is generated in a direction in which the potential of the inverting input terminal of the amplifier 12 decreases). Therefore, in the first connection method, if the switch SW1 is turned on and the switch SW2 is turned off, the output voltage Vout rises with the passage of time due to the action of the photocurrent Ip and the amplifier 12. In contrast, in the second connection mode, in the on section of the switch SW1, a photocurrent Ip (positive charge) flows in a direction from the photodiode 11 through the switch SW1 toward the input line LN1 (that is, in the on section of the switch SW1, the photocurrent Ip is generated in a direction in which the potential of the inverting input terminal of the amplifier 12 rises). Therefore, in the second connection mode, if the switch SW1 is turned on and the switch SW2 is turned off, the output voltage Vout decreases with time by the action of the photocurrent Ip and the amplifier 12.

The detection circuit 15 detects the amount of change in the output voltage Vout during the integration period started after the switch SW2 is turned off, and detects the illuminance on the basis of the detected amount of change. A signal indicating the magnitude of the detected illuminance is generated and output as an illuminance sensing signal Sout. The larger the amount of change in the output voltage Vout during the integration period, the larger the detection value of the illuminance, and the smaller the amount of change in the output voltage Vout during the integration period, the smaller the detection value of the illuminance.

[ reference example ]

The operation of the reference example will be described with reference to fig. 4. In the reference example, the illuminance sensor 1A itself shown in fig. 2 is used. In the reference example, starting from an initial state in which both the switches SW1 and SW2 are on, the switch SW2 is turned off while the switch SW1 is kept on, and then, when a certain integration time has elapsed, the switch SW1 is turned off. In the reference example, the period from the off time of the switch SW2 to the off time of the switch SW1 is an integration period, and the illuminance is detected from the amount of change in the output voltage Vout (equivalent to Δ Vout in fig. 4) in the integration period.

That is, in the illuminance sensor 1A, an integrating circuit having the amplifier 12, the integrating capacitor 13, and the switches SW1 and SW2 is configured. Then, first, while the switch SW1 is turned on and the switch SW2 is turned on, the accumulated charge of the integration capacitor 13 is discharged, thereby initializing the output voltage value (the value of the output voltage Vout) of the integration circuit. When the switch SW2 is turned off while the switch SW1 is kept on, the charge generated by the photocurrent Ip generated by the photodiode 11 is accumulated in the integration capacitor 13. The illuminance can be detected by the output voltage Vout corresponding to the amount of charge accumulated in the integrating capacitor 13 during the integration period.

In fig. 4, the waveform of the output voltage Vout is simplified, and in practice, noise caused by noise generation in the amplifier 12 is superimposed on the output voltage Vout.The resulting noise of the amplifier 12 can be represented by input switching noise, which is now considered to be superimposed on the input signal to the inverting input terminal of the amplifier 12. In addition, with Δ V _NOISE Which represents the maximum value of the magnitude of the input conversion noise. Then, the input conversion noise of the amplifier 12 at the off timing of the switch SW2 is from "+ Δ V _NOISE To Δ V _NOISE "is not limited to the above range.

In fig. 5A, a broken-line waveform 910 indicates a waveform of the output voltage Vout of the illuminance sensor 1A in the first case. Solid line waveform 910 _LPF A waveform obtained by low-pass filtering the waveform 910 is shown. The first case is where the input conversion noise of the amplifier 12 at the time of turning off of the switch SW2 is "+ Δ V _NOISE "in the case of the same. In fig. 5B, a broken-line waveform 920 represents a waveform of the output voltage Vout of the illuminance sensor 1A in the second case. Solid line waveform 920 _LPF A waveform obtained by low-pass filtering the waveform 920 is shown. The second condition is that the input switching noise of amplifier 12 at the moment of turn-off of switch SW2 is "- Δ V _NOISE "in the case of the same. In FIG. 5C, waveforms 910, 920, 910 are shown _LPF And 920 _LPF And (4) displaying in an overlapping mode.

In the first case, the reason is "+ Δ V _NOISE "the output voltage Vout sharply falls after the switch SW2 is turned off, and then the output voltage Vout gradually rises due to the photocurrent Ip. In the second case, the factor "- Δ V _NOISE "after the switch SW2 is turned off, the output voltage Vout rises sharply, and then the output voltage Vout gradually rises due to the photocurrent Ip. That is, the input conversion noise is amplified by the gain (C1/C2), and AND (C1/C2) and Δ V are generated between the first and second states in the output voltage Vout after the start of the integration period _NOISE Proportional difference. Here, C1 represents the capacitance value of the parasitic capacitance formed between the anode and cathode of the photodiode 11, and C2 represents the capacitance value of the integrating capacitor 13.

As a result, in the reference example, the variation amount of the output voltage Vout in the integration period is Δ Vout1 and Δ Vout2 in the first and second cases, respectively, and "Δ Vout1 < Δ Vout 2" holds. That is, the detection result of the illuminance in the first case and the second case generates a difference. The larger the difference, the worse the illuminance detection accuracy. The higher the detection sensitivity of the illuminance (i.e., the smaller the C2), or the larger the parasitic capacitance of the photodiode 11 (i.e., the smaller the C1), the larger the influence of the noise.

Example EX1_ A

The first embodiment includes examples EX1_ A to EX1_ F. The configuration and operation of the illuminance sensor capable of reducing the influence of the noise described above will be described in embodiment EX1_ a. Fig. 6 shows a configuration of an illuminance sensor 2 according to example EX1_ a. The illuminance sensor 2 has a configuration in which the adjustment circuit 50 is added to the illuminance sensor 1 having the above-described basic configuration. Therefore, the illuminance sensor 2 has, similarly to the illuminance sensor 1 having the basic configuration: the connection relationship and functions of the photodiode 11, the amplifier (operational amplifier) 12, the integrating capacitor 13, the control circuit 14, the detection circuit 15, the switches SW1 and SW2, and the reference potential terminals 31 and 32 are as described above. In the illuminance sensor 2, the photodiode 11 is connected in a first connection method corresponding to fig. 2. That is, in the illuminance sensor 2, the anode of the photodiode 11 is connected to the reference potential terminal 31, the cathode of the photodiode 11 is connected to one end of the switch SW1, and the other end of the switch SW1 is connected to the input line LN 1.

The adjustment circuit 50 is a circuit for adjusting the start timing of the integration period, and includes: a low-pass filter 51, a comparator 52, a latch circuit 53, an adjustment current generation circuit 54, and a switch (adjustment switch) SWa.

The low-pass filter 51 performs low-pass processing for passing a low-frequency component of the output voltage Vout and attenuating a high-frequency component of the output voltage Vout, and generates the output voltage Vout subjected to the low-pass processing as a comparison voltage Vout'. The comparison voltage Vout' is input to the comparator 52. Specifically, the low-pass filter 51 includes a resistor 51a and a capacitor 51b, one end of the resistor 51a is connected to an output line LN2 to which the output voltage Vout is applied, the other end of the resistor 51a is connected to one end of the capacitor 51b, and the other end of the capacitor 51b is connected to ground. Thereby, a comparison voltage Vout' is generated at a connection node between the resistor 51a and the capacitor 51 b. However, the configuration of the low-pass filter 51 may be any as long as the effect of the low-pass processing described above can be obtained.

The comparator 52 compares the comparison voltage Vout' with a predetermined determination voltage Vth, and outputs a signal CMPout indicating the high-low relationship thereof. The signal CMPout is a binarized signal having a value of "0" or "1". In the illuminance sensor 2 employing the first connection method (see fig. 2) for the photodiode 11, the determination voltage Vth is higher in potential than the reference potential Vref. The comparator 52 has a function of detecting the timing at which the output voltage Vout exceeds the determination voltage Vth, and the low-pass filter 51 is provided so as not to be easily affected by noise at that timing.

The comparator 52 is a comparator with a hysteresis function. When the comparison voltage Vout' has the reference potential Vref, the value of the signal CMPout is "0". In the process of the potential of the comparison voltage Vout ' rising from the reference potential Vref, the value of the signal CMPout is maintained at "0" when the comparison voltage Vout ' is lower than the determination voltage Vth, and the value of the signal CMPout is "1" when the comparison voltage Vout ' is higher than the determination voltage Vth (see fig. 7). Thereafter, the comparison voltage Vout' is not lower than the determination voltage Vth by the predetermined hysteresis width Δ V _HYS Voltage (Vth- Δ V) _HYS ) Hereinafter, the value of the signal CMPout is maintained at "1", and the voltage Vout' for comparison is the voltage (Vth- Δ V) _HYS ) In the following, the value of the signal CMPout returns to "0". Voltage (Vth- Δ V) _HYS ) Is higher than the reference potential Vref.

The latch circuit 53 latches and holds the value of the output signal CMPout of the comparator 52, and outputs a control signal CNTa corresponding to the held value (hereinafter, referred to as a held value) to the control terminal of the switch SWa. The initial value of the hold value is "0". Referring to fig. 7, the operation of the latch circuit 53 will be described with a state in which the hold value is "0" as a starting point. When the value of signal CMPout changes from "0" to "1" while switch SW2 is in the off state and output voltage Vout is rising, latch circuit 53 switches its holding value from "0" to "1". The latch circuit 53 controls the switch SWa to be in an on state when its own hold value is "0" and controls the switch SWa to be in an off state when its own hold value is "1" by the output of the control signal CNTa. Further, the control signal CNTa is also supplied to the control circuit 14. Therefore, the control circuit 14 can recognize the state of the switch SWa. The control circuit 14 may initialize the holding value of the latch circuit 53 to an initial value "0" at a necessary timing.

The switch SWa is a switch (bus switch) capable of transmitting an analog signal. The switch SWa is provided between the input line LN1 and the adjustment current generation circuit 54, and is turned on or off in accordance with the control signal CNTa supplied from the latch circuit 53.

The adjustment current generation circuit 54 can perform an adjustment charge supply operation of generating the adjustment current Ia and supplying the adjustment charge generated by the adjustment current Ia to the input line LN 1. In the configuration of embodiment EX1_ a, the adjustment charge supplying operation is performed only in the on period of the switch SWa. In the off section of the switch SWa, the adjustment charge supply operation (adjustment charge supply stop operation) is not performed, and there is no charge exchange between the input line LN1 and the adjustment current generation circuit 54. In illuminance sensor 2 in fig. 6, adjustment current Ia flows from input line LN1 through switch SWa toward ground. That is, in the on section of the switch SWa, the adjustment current generation circuit 54 introduces the adjustment current Ia from the input line LN1 in the direction in which the potential of the input line LN1 decreases. Therefore, in illuminance sensor 2 in fig. 6, the polarity of the adjustment charge supplied from adjustment current generation circuit 54 to input line LN1 in the on period of switch SWa is negative.

The illuminance sensor 2 performs the illuminance detection operation described below at any necessary timing. The illuminance sensor 2 may repeatedly perform the illuminance detection operation at a predetermined cycle. The illuminance detection operation will be described with reference to the first and second cases.

First, an illuminance detection operation in the first case will be described with reference to fig. 8. As described above, the first case is that the input conversion noise of the amplifier 12 at the time of turning off of the switch SW2 is "+ Δ V _NOISE "in the case of the same. In fig. 8, a broken-line waveform 510 indicates a waveform of the output voltage Vout of the illuminance sensor 2 in the first case, and a solid-line waveform 510 _LPF A waveform of the contrast voltage Vout' of the illuminance sensor 2 in the first case is shown. In the first case, at time t _A1 Previously, all of the switches SW1, SW2 and SWa were turned on at time t _A1 To this end, the switch SW2 is switched from the ON state to the OFF state, and then, at time t _A2 To this end, the switch SWa is switched from the on state to the off state, and then, at time t _A3 To do this, the switch SW1 is switched from the on state to the off state.

In the illuminance detection operation, initial charging is first performed. During the initial charging, both the switches SW1 and SW2 are in the on state. The initial charging is ended because the switch SW2 is turned off. In the on period of the switch SW2, the accumulated charge of the integration capacitor 13 is discharged, and the dc component of the output voltage Vout converges on the reference potential Vref. At the start time of the illuminance detection operation, the holding value of the latch circuit 53 is initialized to "0", and the switch SWa is maintained in the on state during the initial charging.

In the illuminance detection operation, after the initial charging is performed for a certain period of time, the control circuit 14 turns off the switch SW2 while maintaining the switch SW1 in the on state, thereby ending the initial charging. In the first situation of fig. 8, the time t _A1 Corresponding to the off timing of switch SW 2. In the first situation of fig. 8, at time t _A1 Then, the result is "+ Δ V _NOISE "the output voltage Vout drops sharply due to the input switching noise. Then, at time t when the comparison voltage Vout' reaches the determination voltage Vth _A2 Since the switch SWa is in the on state before, the output voltage Vout and the comparison voltage Vout' gradually rise due to the introduction of the photocurrent Ip from the input line LN1 and the adjustment current Ia from the input line LN 1.

At a time t _A2 For example, the relationship between the comparison voltage Vout ' and the determination voltage Vth is switched from "Vout ' < Vth" to "Vout ' > Vth". Thus, at time t _A2 The switch SWa is turned off. In the on-period of the switch SW1 after the switch SWa is turned off, the voltage Vout and the contrast are outputted only by the introduction of the photocurrent Ip from the input line LN1The voltage Vout' gradually rises.

The control circuit 14 recognizes the turn-off timing of the switch SWa from a control signal CNTa for controlling the state of the switch SWa. In the first case of fig. 8, it is determined that time t is _A2 Is the turn-off instant of the switch SWa. The control circuit 14 sets the integration period according to the off timing of the switch SWa. In the first case, the integration period is the period 515, and the start time and the end time of the integration period 515 are the times t _A2 、t _A3 . The control circuit 14 will switch off the slave switch SWa at time t _A2 The time when the predetermined integration time has elapsed is set as the end time t of the integration period 515 _A3 . The integration time has a predetermined fixed time length. Control circuit 14 ends integration period 515 at time t _A3 Switch SW1 is turned off. In other words, the integration period 515 is ended by turning off the switch SW 1.

The integration period 515 is a period in which the charge generated by the photocurrent Ip is accumulated in the integration capacitor 13, and there is no charge exchange between the integration capacitor 13 and the adjustment current generation circuit 54 in the integration period 515. That is, the amount of change in the output voltage Vout in the integration period 515 depends only on the photocurrent Ip. The detection circuit 15 detects illuminance from the amount of change in the output voltage Vout in the integration period 515, and generates and outputs an illuminance sensing signal Sout indicating the detection result of the illuminance. According to the generation and output of the illuminance sensing signal Sout, the illuminance detection operation is ended.

Next, the illuminance detection operation in the second case will be described with reference to fig. 9. As described above, the second case is where the input switching noise of amplifier 12 at the moment of turn-off of switch SW2 is "- Δ V _NOISE "in the case of the same. In fig. 9, a broken-line waveform 520 represents a waveform of the output voltage Vout of the illuminance sensor 2 in the second case, and a solid-line waveform 520 _LPF A waveform of the voltage Vout' for comparison of the illuminance sensor 2 in the second case is shown. In the second case, at time t _B1 Previously, all of the switches SW1, SW2 and SWa were turned on at time t _B1 To this end, the switch SW2 is switched from the ON state to the OFF state, and then, at time t _B2 For boundary, the switch SWa is switched from the on stateIs in an off state, and thereafter, at time t _B3 To do this, the switch SW1 is switched from the on state to the off state.

As described above, in the illuminance detection operation, initial charging is first performed. During the initial charging, both the switches SW1 and SW2 are in the on state. The initial charging is ended by the switch SW2 being turned off. In the on period of the switch SW2, the accumulated charge of the integration capacitor 13 is discharged, and the dc component of the output voltage Vout converges on the reference potential Vref. At the start time of the illuminance detection operation, the held value of the latch circuit 53 is initialized to "0", and the switch SWa is maintained in the on state during the initial charging.

In the illuminance detection operation, after the initial charging is performed for a certain period of time, the control circuit 14 turns off the switch SW2 while maintaining the switch SW1 in the on state, thereby ending the initial charging. In the second situation of fig. 9, the time t _B1 Corresponding to the off timing of switch SW 2. In the second situation of fig. 9, at time t _B1 Then, due to ". DELTA.V _NOISE "the output voltage Vout rises sharply due to the input switching noise. Then, at time t when the comparison voltage Vout' reaches the determination voltage Vth _B2 Since the switch SWa is in the on state before, the output voltage Vout and the comparison voltage Vout' gradually rise due to the introduction of the photocurrent Ip from the input line LN1 and the adjustment current Ia from the input line LN 1.

At a time t _B2 For example, the relationship between the comparison voltage Vout ' and the determination voltage Vth is switched from "Vout ' < Vth" to "Vout ' > Vth". Thus, at time t _B2 The switch SWa is turned off. In the on-period of the switch SW1 after the switch SWa is turned off, the output voltage Vout and the comparison voltage Vout' gradually rise only by the introduction of the photocurrent Ip from the input line LN 1.

The control circuit 14 recognizes the turn-off timing of the switch SWa from a control signal CNTa for controlling the state of the switch SWa. In the second case of fig. 9, it is determined that time t is _B2 Is the turn-off instant of the switch SWa. The control circuit 14 sets the integration period according to the off timing of the switch SWa. First, theIn the second case, the integration period is the period 525, and the start time and the end time of the integration period 525 are the times t _B2 、t _B3 . The control circuit 14 will switch off the slave switch SWa at time t _B2 The time when the predetermined integration time has elapsed is set as the end time t of the integration period 525 _B3 . The integration time has the fixed time length described above. Therefore, the length of the integration period 515 in the first case of fig. 8 and the length of the integration period 525 in the second case of fig. 9 are the same as each other. The control circuit 14 ends the integration period 525 at time t _B3 Switch SW1 is turned off. In other words, the integration period 525 is ended by turning off the switch SW 1.

The integration period 525 is a period in which the charge generated by the photocurrent Ip is accumulated in the integration capacitor 13, and there is no charge exchange between the integration capacitor 13 and the adjustment current generation circuit 54 in the integration period 525. That is, the amount of change in the output voltage Vout in the integration period 525 depends only on the photocurrent Ip. The detection circuit 15 detects illuminance from the amount of change in the output voltage Vout in the integration period 525, and generates and outputs an illuminance sensing signal Sout indicating the detection result of the illuminance. According to the generation and output of the illuminance sensing signal Sout, the illuminance detection operation is ended.

In fig. 10, waveforms 510 of the comparison voltage Vout' in the first and second cases are shown _LPF And 520 _LPF And (4) displaying in an overlapping mode. In either of the first and second cases, the integration period (515, 525) is started from the time when the high-low relationship between the comparison voltage Vout ' and the determination voltage Vth switches from "Vout ' < Vth" to "Vout ' > Vth". Therefore, the amount of change in the output voltage Vout during the integration period and the illuminance detection result based on the amount of change are not affected by noise generated by the amplifier 12 at the start of the integration period (at the time when the switch SW2 is turned off). Therefore, the detection accuracy of the illuminance is improved in comparison with the reference example (see fig. 5C).

Example EX1_ B

Referring to fig. 11A to 11C, the influence of noise generation by the amplifier 12 at the end of the integration period (at the off time of the switch SW 1) is examined. The dashed waveforms 930 and 940 of FIGS. 11A and 11B relate to the basicThe illuminance sensor 1 (see fig. 1) having the configuration is an example (2 examples) of the waveform of the output voltage Vout when the integration period is ended. Solid line waveform 930 _LPF And 940 _LPF Waveforms 930 and 940 are low-pass filtered and shown, respectively. Waveforms 930 and 940 and waveform 930 in FIG. 11C _LPF And 940 _LPF And (4) displaying in an overlapping mode.

In the illuminance sensor 1 of the basic configuration, noise generated in the amplifier 12 when the switch SW1 is turned off remains in the integrating capacitor 13, and the noise remaining in the integrating capacitor 13 is superimposed on the output voltage Vout. Due to this noise, the output voltage Vout irregularly shifts in the up-down direction (the waveform 930 is obtained, or the waveform 940 is obtained, or is indefinite). This results in deterioration of the detection accuracy of illuminance. Further, the gain of the amplifier 12 decreases due to the off of the switch SW1, and the ac component of the noise decreases, but the dc component of the noise remains in the integrating capacitor 13.

In embodiment EX1_ B, a configuration for reducing the influence of noise at the end of such an integration period will be described. Fig. 12 shows a structure of an illuminance sensor 3 according to example EX1_ B. The illuminance sensor 3 has a configuration in which the noise reduction circuit 60 is added to the illuminance sensor 2 according to the embodiment EX1_ a described above. Therefore, the illuminance sensor 3 has, similarly to the illuminance sensor 1 having the basic configuration: the connection relationship and functions of the photodiode 11, the amplifier (operational amplifier) 12, the integrating capacitor 13, the control circuit 14, the detection circuit 15, the switches SW1 and SW2, and the reference potential terminals 31 and 32 are as described above. The illuminance sensor 3 has the adjustment circuit 50 in the same manner as the illuminance sensor 2 of example EX1_ a, and the configuration and operation of the adjustment circuit 50 are as shown in example EX1_ a. In the illuminance sensor 3, the photodiode 11 is connected in a first connection method corresponding to fig. 2. That is, in the illuminance sensor 3, the anode of the photodiode 11 is connected to the reference potential terminal 31, the cathode of the photodiode 11 is connected to one end of the switch SW1, and the other end of the switch SW1 is connected to the input line LN 1.

The noise reduction circuit 60 functions as a circuit for reducing the influence of noise at the end of the integration period, and the adjustment circuit 50 functions as a circuit for reducing the influence of noise at the start of the integration period. Therefore, the adjustment circuit 50 and the noise reduction circuit 60 may be referred to as a first noise reduction circuit and a second noise reduction circuit, respectively. It is preferable that both the adjustment circuit 50 and the noise reduction circuit 60 are provided in the illuminance sensor, but the adjustment circuit 50 may be deleted from the illuminance sensor 3 only when focusing on noise at the end of the integration period.

The noise reduction circuit 60 has a capacitor (additional capacitor) 61 and a resistor 62, and switches SW3 and SW 4. It is also understood that the reference potential terminal 33 is also included in the components of the noise reduction circuit 60.

The capacitor 61 is provided between the output terminal of the amplifier 12 and a predetermined node 63. That is, one end of the capacitor 61 is connected to the output terminal (therefore, the output line LN2) of the amplifier 12, and the other end of the capacitor 61 is connected to the predetermined node 63. A series circuit of the resistor 62 and the switch SW3 is provided between the reference potential terminal 33 and the node 63. More specifically, one end of the switch SW3 is connected to the node 63, the other end of the switch SW3 is connected to one end of the resistor 62, and the other end of the resistor 62 is connected to the reference potential terminal 33. The reference potential Vref is applied to the reference potential terminal 33 in the same manner as the reference potential terminals 31 and 32. The reference potential terminals 31 to 33 may be common terminals. A switch SW4 is provided between the inverting input terminal of the amplifier 12 (hence, the input line LN1) and the node 63. That is, one end of the switch SW4 is connected to the inverting input terminal (therefore, the input line LN1) of the amplifier 12, and one end of the switch SW4 is connected to the node 63.

Like the switches SW1 and SW2, the switches SW3 and SW4 are switches (bus switches) capable of transmitting analog signals. The control circuit 14 individually controls the states (on/off states) of the switches SW1 to SW4 by supplying control signals CNT1 to CNT4 to control terminals of the switches SW1 to SW 4. The switching timing of on/off of each of the switches SW1 and SW2 is as described in embodiment EX1_ a.

During the illuminance detection operation, the control circuit 14 starts from the time of initial charging (therefore, in the example of fig. 8, from time t) _A1 From the moment t in the example of fig. 9 _B1 From the beginning),when the switch SW1 is switched from the on state to the off state, the switch SW3 is switched to the off state and the switch SW4 is switched to the on state as shown in fig. 13, with the switch SW3 being kept in the on state and the switch SW4 being kept in the off state. Thereafter, switch SW3 may be maintained in the off state and switch SW4 may be maintained in the on state before a new illuminance detection action is performed.

Typically, the turn-off timing of the switch SW1, the turn-off timing of the switch SW3, and the turn-on timing of the switch SW4 may be identical to each other. However, the off timing of the switch SW3 may be advanced or delayed by a predetermined minute time from the off timing of the switch SW1, or alternatively or in addition, the on timing of the switch SW4 may be advanced or delayed by a predetermined minute time from the off timing of the switch SW 1. The off timing of the switch SW3 may be the same as the on timing of the switch SW4, or may be earlier or later than the on timing of the switch SW4 by a predetermined minute time.

The dashed line waveforms 530 and 540 in fig. 14A and 14B relate to the illuminance sensor 3, and are examples (2 examples) of the waveform of the output voltage Vout when the integration period is ended. Solid line waveform 530 _LPF The waveform of the comparison voltage Vout' of the output voltage Vout based on the dotted line waveform 530, and the solid line waveform 540 _LPF A waveform of the comparison voltage Vout' of the output voltage Vout based on the broken-line waveform 540 is shown. In FIG. 14C, waveforms 530 and 540 and waveform 530 _LPF And 540 _LPF And (4) performing superposition representation.

In the on period of the switch SW3, the capacitor 61 and the resistor 62 form a low-pass filter for the voltage across the capacitor 61. That is, in the on period of the switch SW3, a voltage obtained by applying a low-pass process (a low-pass process of passing a low-frequency component in the output voltage Vout and attenuating a high-frequency component in the output voltage Vout) to the output voltage Vout is applied between both ends of the capacitor 61. Therefore, the voltage across the capacitor 61 is less likely to be affected by noise generated by the amplifier 12. At the end of the integration period, the capacitor 61, which is less susceptible to noise generation of the amplifier 12, is connected in parallel with the integrating capacitor 13, whereby noise (offset of the dc component) superimposed on the output voltage Vout becomes small. In this case, the capacitance value of the capacitor 61 can be set large with respect to the capacitance value of the integration capacitor 13, and the noise reduction effect increases as the ratio of the capacitance value of the capacitor 61 to the capacitance value of the integration capacitor 13 increases.

Example EX1_ C

An embodiment EX1_ C is explained. In the illuminance sensor 2 or 3 described above, even if the photocurrent Ip is made almost zero by the action of the adjustment current Ia after the initial charging and before the start of the integration period, the transition from "Vout '< Vth" to "Vout' > Vth" is ensured. Here, the photocurrent Ip is weak (for example, of the order of nA), depending on the application. In addition, in the case of | Ip | < | Ia |, the delay from when the dc component of the output voltage Vout reaches the determination voltage Vth until the supply of the adjustment current Ia is blocked greatly affects the amount of variation of the output voltage Vout (therefore, the illuminance detection result) in the integration period, and therefore, it is necessary to set the magnitude of the adjustment current Ia to the magnitude of the assumed photocurrent Ip.

For example, it is studied to generate an adjustment current Ia of 1nA based on a current of 1 μ a (microampere). In this case, a current mirror circuit including an input side MOSFET and an output side MOSFET is prepared, and the ratio of the source area of the output side MOSFET to the source area of the input side MOSFET is set to 1000: 1, in principle, when the drain current of the input side MOSFET is 1 μ a, a current of 1nA (nanoampere) can be obtained from the output side MOSFET. However, it is generally difficult to improve the accuracy of generating such a minute current (since the current flowing through the MOSFET is too small), and the current obtained from the output side MOSFET may actually be dispersed in a range of 1/100 to 100 times with respect to 1 nA.

In embodiment EX1_ C, a description will be given of a configuration of the adjustment current generation circuit 54 capable of generating a minute current with high accuracy. Fig. 15 shows a structure of the adjustment current generation circuit 100 of EX1_ C according to the embodiment. The adjustment current generation circuit 100 can be used as the adjustment current generation circuit 54 of the embodiment EX1_ a or EX1_ B. The adjustment current generation circuit 100 includes: a capacitor unit 110, a constant current circuit 120, a bias applying terminal 130, and a switch SWb.

The capacitor section 110 has a plurality of capacitors and terminals 115 and 116. The capacitor unit 110 uses a plurality of capacitors, and generates k of current flowing through the terminal 115 at the terminal 116 _C The current is doubled. The terminal 116 is connected to one end of the switch SWa, and the other end of the switch SWa is connected to an inverting input terminal of the amplifier 12 (the amplifier 12 is not shown in fig. 15). That is, the terminal 116 is connected to the inverting input terminal of the amplifier 12 via the switch SWa. The current generated at the terminal 116 (in other words, the current flowing through the terminal 116) corresponds to the adjustment current Ia, and the adjustment current Ia flows from the input line LN1 through the switch SWa toward the terminal 116 only in the on period of the switch SWa.

The ratio k of the current flowing through the terminal 116 to the current flowing through the terminal 115 _C Satisfies "0 < k < 1", and is usually sufficiently smaller than 1. In the example of fig. 15, the capacitor section 110 is formed by a total of 4 capacitors 111 to 114. The connection relationship between the capacitors 111 to 114 and the terminals 115 and 116 will be described in consideration that the two ends of each capacitor are constituted by the first end and the second end. A first end of the capacitor 111 and a first end of the capacitor 112 are commonly connected to the terminal 115, and a second end of the capacitor 111 is connected to ground. The second terminal of the capacitor 112, the first terminal of the capacitor 113, and the first terminal of the capacitor 114 are commonly connected to a node 117. A second terminal of the capacitor 113 is connected to ground. A second terminal of capacitor 114 is connected to terminal 116. In order to make the above ratio k _C The capacitance value of the capacitor 111 is set to be smaller than 1, and the capacitance value of the capacitor 113 is set to be larger than that of the capacitor 114.

The constant current circuit 120 is provided between a node 140 connected to the terminal 115 and ground. The constant current circuit 120 operates to generate a constant current I _CNST And make constant current I _CNST From node 140 toward ground. However, when the potential at the node 140 decreases substantially to 0V, the constant current circuit 120 stops operating (i.e., the constant current I) _CNST No longer flowing). Constant current I _CNST With a fixed constant current value.

The state (on/off state) of the switch SWb is controlled by the control circuit 14. One end of the switch SWb is connected to the node 140, and the other end of the switch SWb is connected to the bias applying terminal 130. A predetermined bias voltage Vbias is applied to the bias applying terminal 130. The bias voltage Vbias has a predetermined positive dc voltage value (e.g., 1.5V).

An example of the value when the target value of the adjustment current Ia is set to 1nA is described. In this case, a constant current I _CNST The capacitance values of the capacitors 111, 112, 113, and 114 are set to 1 μ a, 10pF (picofarad), 0.2pF, 1.8pF, and 0.1pF, respectively. This results in the adjustment current Ia as shown in fig. 16. That is, first, the switch SWb is kept on for a certain time, thereby stabilizing the potentials of the terminals 115 and 116 and the node 117. With this stabilization, the voltage across the capacitor 111 becomes the voltage Vbias. After that, the control circuit 14 turns off the switch SWb. Then, a constant current I of 1 μ A continues for a predetermined time from the turning-off of the switch SWb _CNST When the current flows from the capacitor unit 110 to the ground through the terminal 115 and the constant current circuit 120, a current of 1nA flows from the switch SWa to the capacitor unit 110 through the terminal 116 according to the ratio of capacitance values among the capacitors 111, 112, 113, and 114 (however, the switch SWa is turned on in this case). The current of 1nA flowing through the terminal 116 functions as the adjustment current Ia. In the present numerical example, the adjustment current Ia can be maintained at 1nA until approximately 10 μ s (microseconds) has elapsed from the off time of the switch SWb, but the adjustment current Ia gradually decreases from 1nA to zero after the elapsed time from the off time of the switch SWb exceeds 10 μ s.

In this way, the adjustment current generation circuit 100 of fig. 15 can generate a minute current with higher accuracy than the case of using a current mirror circuit. However, the adjustment current generation circuit 100 of fig. 15 is a time-limited current source capable of generating a constant adjustment current Ia for a limited time. Therefore, the constants of the respective circuit elements can be set so as to be at time t of fig. 8 _A1 And t _A2 A stable adjustment current Ia flows therebetween, and the off timing of the switch SWb is made to coincide with the off timing of the switch SW 2. However, the turn-off timing of the switch SWb may be advanced or delayed by a predetermined minute time from the turn-off timing of the switch SW 2. The switch SWa can be maintained in the on state from a time far before the off time of the switch SWb. Alternatively, the switch SWa may be opened at the same timing as the off timing of the switch SWb, or the switch SWa may be opened at a timing earlier or later by a predetermined minute time than the off timing of the switch SWb.

In short, in the adjustment current generation circuit 100, the constant current I is set to be constant in the on period of the switch SWa _CNST Flowing through the terminal 115, a constant current I is generated at the terminal 116 in the capacitor 110 _CNST The small current is used as the adjustment current Ia. I.e. at constant current I _CNST When the current flows through the terminal 115, a constant current I is generated in the capacitors 111-114 _CNST The corresponding charge movement generates a current corresponding to the charge movement in the capacitors 111 to 114 in the terminal 116 as the adjustment current Ia. The charge (here, negative charge) generated by the generated current at the terminal 116 is supplied to the inverting input terminal of the amplifier 12 through the switch SWa as a control charge.

In the configuration example of fig. 15, the capacitor unit 110 is formed of 4 capacitors 111 to 114, but any capacitor unit may be used as long as the total number of capacitors forming the capacitor unit 110 is 2 or more. The capacitor 110 may include at least capacitors 111 and 112. In the case where the capacitance section 110 is constituted only by the capacitors 111 and 112, the capacitors 113 and 114 are deleted from the capacitance section 110 of fig. 15, and the node 117 is directly connected to the terminal 116. In this case, at a constant current I _CNST When the current flows through the terminal 115, a constant current I is generated in the capacitors 111 and 112 _CNST The corresponding charge transfer generates a current corresponding to the charge transfer of the capacitors 111 and 112 as the adjustment current Ia at the terminal 116

Example EX1_ D

An embodiment EX1_ D will be explained. In embodiments EX1_ a to EX1_ C, the description has been given of the configuration in which the direction of change of the output voltage Vout during the integration period is the rising direction, but the configurations of embodiments EX1_ a to EX1_ C may be modified so that the direction of change of the output voltage Vout during the integration period is the falling direction.

That is, for example, the illuminance sensor 2 in fig. 6 may be modified to the illuminance sensor 2 'in fig. 17, or the illuminance sensor 3 in fig. 12 may be modified to the illuminance sensor 3' in fig. 18.

The difference between the illuminance sensors 2 and 2 'and the difference between the illuminance sensors 3 and 3' include the following first to third differences. The illuminance sensor 2 'has the same configuration and operation as the illuminance sensor 2, and the illuminance sensor 3' has the same configuration and operation as the illuminance sensor 3, except for the first to third different points and the following points accompanying the first to third different points.

As a first difference, a second connection method (see fig. 3) is adopted for the illuminance sensors 2 'and 3', unlike the illuminance sensors 2 and 3. That is, in the illuminance sensors 2 'and 3', the cathode of the photodiode 11 is connected to the reference potential terminal 31, and the anode of the photodiode 11 is connected to one end of the switch SW 1. According to the first difference, in the illuminance sensors 2 'and 3', in the on section of the switch SW1, the photocurrent Ip (positive charge) flows in the direction from the photodiode 11 through the switch SW1 toward the input line LN1 (that is, in the on section of the switch SW1, the photocurrent Ip is generated in the direction in which the potential of the inverting input terminal of the amplifier 12 rises). Therefore, in the illuminance sensors 2 'and 3', if the switch SW1 is turned on and the switch SW2 is turned off, the output voltage Vout decreases with the passage of time due to the photocurrent Ip and the action of the amplifier 12 (except for a transient increase in the output voltage Vout that may occur after the switch SW2 is turned off).

As a second difference, in illuminance sensors 2 'and 3', unlike illuminance sensors 2 and 3, in the on-period of switch SWa, adjustment current Ia flows from adjustment current generation circuit 54 through switch SWa to input line LN 1. That is, the adjustment current generation circuit 54 of the illuminance sensors 2 'and 3' outputs the adjustment current Ia to the input line LN1 in the direction in which the potential of the input line LN1 increases in the on period of the switch SWa. Therefore, in illuminance sensors 2 'and 3', the polarity of the adjustment charge supplied from adjustment current generation circuit 54 to input line LN1 is positive in the on-period of switch SWa.

In order to provide the illuminance sensors 2 'and 3' with the second different point, the input line LN1 is connected to one end of the switch SWa in the illuminance sensors 2 'and 3', and the electric power is adjustedThe current generation circuit 54 is provided between the other end of the switch SWa and a terminal to which a predetermined positive dc voltage is applied. Then, the adjustment current generation circuit 54 in the illuminance sensors 2 'and 3' generates the adjustment current Ia in a direction to increase the potential of the input line LN1, based on the positive dc voltage. When the illuminance sensors 2 'and 3' are formed by applying the configuration shown in example EX1_ C (see fig. 15), the constant current I flows through the terminal 115 in the direction of charging the capacitor 111 in the on interval of the switch SWa _CNST Thereby, a constant current I is generated _CNST K of (a) _C The current that is multiplied and the current that is directed from the terminal 116 through the switch SWa toward the inverting amplification terminal of the amplifier 12 (therefore, the current that is directed in the direction of increasing the potential of the inverting amplification terminal of the amplifier 12) is used as the adjustment current Ia.

As a third difference, the operation of the comparator 52 is different between the illuminance sensors 2 and 3 and the illuminance sensors 2 'and 3'. The comparator 52 of the illuminance sensors 2 'and 3' has a function of detecting the timing at which the output voltage Vout is lower than the determination voltage Vth. In the illuminance sensors 2 'and 3', the potential of the determination voltage Vth is lower than the reference potential Vref (see fig. 19). In the illuminance sensors 2 'and 3', the value of the signal CMPout is "0" when the comparison voltage Vout 'has the reference potential Vref, the value of the signal CMPout is maintained at "0" when the comparison voltage Vout' is higher than the determination voltage Vth while the potential of the comparison voltage Vout 'is decreasing from the reference potential Vref, and the value of the signal CMPout is "1" when the comparison voltage Vout' is lower than the determination voltage Vth. Thereafter, the comparison voltage Vout' is not higher than the determination voltage Vth by the predetermined hysteresis width Δ V _HYS Voltage (Vth + Δ V) _HYS ) As described above, the value of the signal CMPout is maintained at "1", and the voltage Vout' for comparison is the voltage (Vth + Δ V) _HYS ) In the above, the value of the signal CMPout returns to "0". Voltage (Vth + Δ V) _HYS ) Is lower than the reference potential Vref.

According to the third difference, in illuminance sensors 2 'and 3', when the value of signal CMPout changes from "0" to "1" while switch SW2 is turned off to decrease output voltage Vout, the held value of latch circuit 53 switches from "0" to "1" to turn off switch SWa.

The illuminance detection operation by the illuminance sensors 2 'and 3' will be described with reference to fig. 19. In fig. 19, a broken-line waveform 510 ' shows an example of the waveform of the output voltage Vout in the illuminance sensors 2 ' and 3 '. Solid line waveform 510 _LPF ' indicates a waveform of a comparison voltage Vout ' based on the output voltage Vout corresponding to the broken-line waveform 510 '. The illuminance detection operation of the illuminance sensors 2 'and 3' is performed at time t _A1 Previously, all of the switches SW1, SW2 and SWa were turned on at time t _A1 ' As a boundary, the switch SW2 is switched from the ON state to the OFF state, and then at time t _A2 ' As a boundary, the switch SWa is switched from the on state to the off state, and then, at time t _A3 ' As bound, switch SW1 switches from the on state to the off state.

As described above, in the illuminance detection operation, initial charging is first performed. During the initial charging, both the switches SW1 and SW2 are turned on. The initial charging is ended by the switch SW2 being turned off. In the on period of the switch SW2, the accumulated charge of the integration capacitor 13 is discharged, and the dc component of the output voltage Vout converges on the reference potential Vref. At the start time of the illuminance detection operation, the holding value of the latch circuit 53 is initialized to "0", and the switch SWa is maintained in the on state during the initial charging.

During the illuminance detection operation, after the initial charging is performed for a certain period of time, the control circuit 14 turns off the switch SW2 while maintaining the switch SW1 in the on state, thereby ending the initial charging. In the example of fig. 19, time t _A1 ' corresponds to the turning-off timing of the switch SW 2. In the example of fig. 19, at time t _A1 After that, the output voltage Vout rises sharply due to the noise generated by the amplifier 12. Then, at time t when the comparison voltage Vout' is lowered to the determination voltage Vth _A2 Before, since the switch SWa is in the on state, the output voltage Vout and the comparison voltage Vout' gradually decrease due to the supply of the photocurrent Ip and the adjustment current Ia to the input line LN 1.

At a time t _A2 'As a boundary, the relationship between the comparison voltage Vout' and the determination voltage Vth is switched from "Vout '> Vth" to "Vout' < Vth". Thus, at time t _A2 ', turn off the switch SWa. In the on-period of the switch SW1 after the switch SWa is turned off, the output voltage Vout and the comparison voltage Vout' gradually decrease only by the supply of the photocurrent Ip to the input line LN 1.

The control circuit 14 recognizes the turn-off timing of the switch SWa from a control signal CNTa for controlling the state of the switch SWa. In the example of fig. 19, it is determined that the time t is _A2 ' is the turn-off instant of the switch SWa. The control circuit 14 sets the integration period according to the off timing of the switch SWa. In the example of fig. 19, the integration period is a period 515 ', and the start time and the end time of the integration period 515' are times t _A2 ’、t _A3 '. The control circuit 14 will switch off the slave switch SWa at time t _A2 ' the time when the predetermined integration time has elapsed is set as the end time t of the integration period 515 _A3 '. As described above, the integration time has a predetermined fixed time length. Control circuit 14 ends the integration period 515' at time t _A3 ' off switch SW 1. In other words, the integration period 515' is ended by turning off the switch SW 1.

The integration period 515 'is a period in which the charge generated by the photocurrent Ip is accumulated in the integration capacitor 13, and there is no charge exchange between the integration capacitor 13 and the adjustment current generation circuit 54 in the integration period 515'. That is, the amount of change in the output voltage Vout in the integration period 515' depends only on the photocurrent Ip. The detection circuit 15 detects illuminance from the amount of change in the output voltage Vout in the integration period 515', and generates and outputs an illuminance sensing signal Sout indicating the illuminance detection result. According to the generation and output of the illuminance sensing signal Sout, the illuminance detection operation is ended.

Hereinafter, the operation of the illuminance sensors 2 and 3 and the operation of the illuminance sensors 2 'and 3' will be described in comparison.

The adjustment circuit 50 (see fig. 6, 12, 8, and 9) in the illuminance sensors 2 and 3 stops supplying the negative adjustment charge to the input line LN1 (and hence the inverting input terminal of the amplifier 12) by turning the adjustment switch SWa on and supplying the negative adjustment charge to the input line LN1 (i.e., by introducing the adjustment current Ia from the inverting input terminal of the amplifier 12) when the relationship between the contrast voltage Vout 'and the determination voltage Vth is "Vout' < Vth" and then turning the adjustment switch SWa off when the relationship between the contrast voltage Vout 'and the determination voltage Vth is "Vout' > Vth" after the switch SW2 is switched from the on state to the off state by the control circuit 14.

The control circuit 14 (see fig. 6, 12, 8, and 9) of the illuminance sensors 2 and 3 sets a period from the time of switching from "Vout '< Vth" to "Vout' > Vth" in the above-described high-low relationship to the time when a predetermined integration time elapses from the switching time as an integration period (515, 525). The control circuit 14 in the illuminance sensors 2 and 3 recognizes the switching timing (t in fig. 8) when the control circuit transitions from the first state in which the switch SW1 and the switch SW2 are both in the on state to the second state in which the switch SW1 is in the on state and the switch SW2 is in the off state _A2 T in FIG. 9 _B2 ) Then, at the time point (t in fig. 8) when the integration time has elapsed from the switching time point _A3 T in FIG. 9 _B3 ) The switch SW1 is switched from the on state to the off state (i.e., the integration period is ended).

The adjustment circuit 50 (see fig. 17, 18, and 19) of the illuminance sensors 2 ' and 3 ' switches the switch SW2 from the on state to the off state by the control circuit 14, and then turns on the adjustment switch SWa when the relationship between the level of the comparison voltage Vout ' and the determination voltage Vth is "Vout ' > Vth", thereby supplying positive adjustment charge to the input line LN1 (i.e., outputting the adjustment current Ia to the inverting input terminal of the amplifier 12), and turns off the adjustment switch SWa when the relationship between the level of the comparison voltage Vout ' and the determination voltage Vth is switched from "Vout ' > Vth" to "Vout ' < Vth", thereby stopping the supply of positive adjustment charge to the input line LN1 (and therefore, the inverting input terminal of the amplifier 12).

Control circuit 14 in illuminance sensors 2 'and 3' (see fig. 17 or 3)Fig. 18 and 19) sets a period from a switching time point from "Vout ' > Vth" to "Vout ' < Vth" in the above-described high-low relationship to a time point at which a predetermined integration time elapses from the switching time point to an integration period (period 515 ' in fig. 19). The control circuit 14 of the illuminance sensors 2 'and 3' recognizes the switching timing (t in fig. 19) when the control circuit transitions from the first state in which the switch SW1 and the switch SW2 are both in the on state to the second state in which the switch SW1 is in the on state and the switch SW2 is in the off state _A2 ') at the time point when the integration time has elapsed since the switching time point (t in fig. 19) _A3 ') switch SW1 from the on state to the off state (i.e., end the integration period).

Example EX1_ E

An embodiment EX1_ E will be explained. In embodiment EX1_ E, a modified technique related to the switch (adjustment switch) SWa will be described. The technique described in embodiment EX1_ E can be applied to embodiments EX1_ A to EX1_ D.

As described above, the adjustment current generation circuit 54 can perform the adjustment charge supply operation of generating the adjustment current Ia and supplying the adjustment charge generated by the adjustment current Ia to the input line LN 1. Here, the arrangement position of the switch SWa can be changed arbitrarily by performing the adjustment charge supply operation (that is, supplying the adjustment charge generated by the adjustment current Ia to the input line LN1) in the on section of the switch SWa and stopping the adjustment charge supply operation (that is, stopping the supply of the adjustment charge generated by the adjustment current Ia to the input line LN1) in the off section of the switch SWa. For example, when the adjustment current generation circuit 100 in fig. 15 is used as the adjustment current generation circuit 54, the switch SWa may be inserted in series between the node 140 and the constant current circuit 120. In this case, the terminal 116 may be directly connected to the inverting input terminal of the amplifier 12 to be constant current I _CNST The operation shown in embodiment EX1_ C is realized by flowing through the node 140 only in the on period of the switch SWa inserted in series between the node 140 and the constant current circuit 120.

In any of the illuminance sensors (2, 3, 2 'or 3') of embodiments EX1_ a to EX1_ D, the switch SWa may be omitted. In this caseNext, the latch circuit 53 may control the on/off operation of the adjustment current generation circuit 54. That is, in any of embodiments EX1_ a to EX1_ D, the adjustment current generation circuit 54 is directly connected to the inverting input terminal of the amplifier 12 without the switch SWa, and the operation of the adjustment current generation circuit 54 is turned on to perform the adjustment charge supply operation when the held value of the latch circuit 53 is "0", whereas the operation of the adjustment current generation circuit 54 is turned off to stop the adjustment charge supply operation when the held value of the latch circuit 53 is "1" (see fig. 7 as appropriate). When the adjustment current generation circuit 100 of fig. 15 is used as the adjustment current generation circuit 54, the switch SWa may be omitted and the terminal 116 may be directly connected to the inverting input terminal of the amplifier 12, and when the hold value of the latch circuit 53 is "0", the operation of the constant current circuit 120 may be turned on to cause the constant current circuit 120 to generate the constant current I _CNST On the other hand, when the holding value of the latch circuit 53 is "1", the operation of the constant current circuit 120 is turned off to stop the constant current I by the constant current circuit 120 _CNST May be generated (i.e., the flow of current between the node 140 and the constant current circuit 120 may be stopped).

Example EX1_ F

An embodiment EX1_ F will be explained. The illuminance sensor (2, 3, 2 ', or 3') described above can be mounted on a smartphone SP including a display DD as shown in fig. 20. In this case, the illuminance sensor (2, 3, 2 ', or 3') can be used for brightness adjustment of the display DD. That is, in the smartphone SP, the luminance of the display DD can be adjusted according to the illuminance sensing signal Sout of the illuminance sensor (2, 3, 2 ', or 3'). In order to improve the design of the smartphone SP, there are many demands for making the optical window for the illuminance sensor (window for taking in external light) inconspicuous, and in many cases, the transmittance of visible light in the optical window is set low in response to the demands. The sensitivity of the illuminance sensor needs to be increased as the transmittance of the optical window is decreased, but when the sensitivity is increased, the influence of noise becomes significant. The illuminance sensor (2, 3, 2 ', or 3') of the present embodiment is extremely advantageous because it has a structure that is less susceptible to noise as described above.

< second embodiment >

A second embodiment of the present disclosure will be explained. Advantageous configurations of the second embodiment are specifically shown in examples EX2_ a and EX2_ B described later, and first, comparative examples for comparison with these examples will be described.

Fig. 21 shows a configuration of an illuminance sensor 901 of a comparative example. As shown in fig. 21, in the illuminance sensor 901 of the comparative example, the cathode of the photodiode 911 is connected to the inverting input terminal of the amplifier 912 through the switch SW911, and the anode of the photodiode 911 is connected to the ground. In the illuminance sensor 901, a parallel circuit of an integration capacitor 913 and a switch SW912 is connected between an output terminal and an inverting input terminal of an amplifier 912, and a reference voltage Vref having a positive dc voltage value (for example, 0.6V) is supplied to a non-inverting input terminal of the amplifier 912. A connection node between the cathode of the photodiode 911 and the switch SW911 is connected to a terminal to which the reference voltage Vref is applied, via the switch SW 911B. In the on-period of the switch SW911, the switch SW911B is controlled to be off, and in the off-period of the switch SW911, the switch SW911B is controlled to be on.

As shown in fig. 22, in the illuminance sensor 901, the integration period is started by turning off the switch SW912 from a state in which both the switches SW911 and SW912 are on, and thereafter, the integration period is ended by turning off the switch SW 911. During the integration period, the output voltage Vo of the amplifier 912 increases in accordance with the photocurrent Ip' generated by the photodiode 911. The illuminance can be detected from the output voltage Vo.

In the illuminance sensor 901 of the comparative example, the operating point of the amplifier 912, which is an integrating amplifier, is the same as the operating point of the photodiode 911. That is, in the integration period, the amplifier 912 operates with the reference voltage Vref as an operating point, and the photodiode 911 operates with the reference voltage Vref applied between the anode and the cathode. During the integration period, when the reference voltage Vref is applied to the photodiode 911 as a bias, a leakage current (dark current) flows in the photodiode 911. The leakage current becomes significant at high temperatures. When the leakage current flows, the presence of the incident light is erroneously recognized even in a blackish black state. Therefore, the leakage current becomes a factor of deterioration in detection accuracy of the illuminance sensor 901.

The following methods were also investigated: a light-shielded photodiode is prepared separately from the photodiode 911, and a difference between an integration result using the photodiode 911 and an integration result using the light-shielded photodiode is obtained, thereby eliminating a leakage current (dark current). However, in this method, it is necessary to separately prepare a light-shielded photodiode, and it is difficult to completely match the leakage current, and hence an erasure may occur. If the bias of the photodiode 911 is set to 0V, the leakage current can be suppressed, but an integrating amplifier that operates with 0V as an operating point cannot be manufactured. Therefore, in the configuration of the illuminance sensor 901 in fig. 21, the bias of the photodiode 911 cannot be set to 0V.

Example EX2_ A

As an example contributing to the reduction of the leakage current, example EX2_ a belonging to the second embodiment will be described. Fig. 23 shows a configuration of an illuminance sensor 6 according to example EX2_ a.

The illuminance sensor 6 includes: the photodiode 11, the amplifier 12, the integrating capacitor 13, the control circuit 14, and the detection circuit 15 include a chopper capacitor 16 and switches SW11 to SW 14. The photodiode 11, the amplifier 12, the integrating capacitor 13, the control circuit 14, and the detection circuit 15 in the illuminance sensor 6 may be the same as the photodiode 11, the amplifier 12, the integrating capacitor 13, the control circuit 14, and the detection circuit 15 in the illuminance sensor (for example, the illuminance sensor 2 in fig. 6) of the first embodiment, and the description of the first embodiment related thereto may be applied to the second embodiment.

However, the control circuit 14 in the illuminance sensor 6 has a function of controlling the switches SW11 to SW 14. That is, the control circuit 14 in the illuminance sensor 6 individually controls the states (on/off states) of the switches SW11 to SW14 by supplying control signals CNT11 to CNT14 to the control terminals of the switches SW11 to SW 14. The switches SW11 to SW14 are switches (bus switches) capable of transmitting analog signals.

A reference potential terminal (in other words, a reference potential point) 32 and a predetermined potential terminal (in other words, a predetermined potential point) 34 are provided at the illuminance sensor 6. A reference potential Vref (e.g., 0.6V) having a predetermined positive dc potential is applied to the reference potential terminal 32. On the other hand, the predetermined potential terminal 34 has a potential of 0V. That is, the predetermined potential terminal 34 corresponds to ground.

The connection relationship of the components of the illuminance sensor 6 will be described. The anode of the photodiode 11 is connected to a predetermined potential terminal 34 (i.e., grounded). The cathode of the photodiode 11 is connected to one end of the switch SW11, and the other end of the switch SW11 is connected to the input line LN1 (predetermined line). One end of the switch SW14 is connected to a node connecting the cathode of the photodiode 11 and the switch SW11, and the other end of the switch SW14 is connected to the predetermined potential terminal 34 (i.e., ground connection). One end of the switch SW13 is connected to the input line LN1, and the other end of the switch SW13 is connected to the predetermined potential terminal 34 (i.e., ground connection).

One end of the integration capacitor 13 is connected to the output terminal of the amplifier 12, and the other end of the integration capacitor 13 is connected to the input line LN 1. One end of the switch SW12 is connected to the output terminal of the amplifier 12, and the other end of the switch SW12 is connected to the inverting input terminal of the amplifier 12. The non-inverting input terminal of the amplifier 12 is connected to the reference potential terminal 32 and receives the reference potential Vref. A chopper capacitor 16 is inserted between the inverting input terminal of the amplifier 12 and the input line LN 1. That is, one end of chopper capacitor 16 is connected to input line LN1, and the other end of chopper capacitor 16 is connected to the inverting input terminal of amplifier 12. Similarly to the first embodiment, in the second embodiment, the output voltage from the output terminal of the amplifier 12 is referred to as an output voltage Vout, and a line connected to the output terminal of the amplifier 12 and transmitting the output voltage Vout is referred to as an output line LN 2. The detection circuit 15 detects illuminance as a detection target of the illuminance sensor 6 from the output voltage Vout, and generates and outputs an illuminance sensing signal Sout indicating a detection result of the illuminance. The illuminance as a detection target of the illuminance sensor 6 is a physical quantity proportional to the incident light amount of the photodiode 11.

The flow of the switching control in the integration sensor 6 will be described with reference to fig. 24. The state 610 shown in fig. 24 is an initial state. In state 610, switch SW11 is open and switches SW 12-SW 14 are closed. In the state 610, the switch SW12 connects the output terminal and the inverting input terminal of the amplifier 12, and therefore, the voltage of the inverting input terminal matches the reference voltage Vref. In addition, in the state 610, the switch SW13 is turned on, and therefore, the potential of the input line LN1 is kept at 0V. Therefore, in the state 610, the charge corresponding to the reference voltage Vref is accumulated in the chopper capacitor 16.

The control circuit 14 starts from the state 610, turns off the switch SW13 and turns off the switch SW12, thereby transitioning from the state 610 to the state 620. The turn-off timing of the switch SW13 and the turn-off timing of the switch SW12 may be substantially the same, but strictly speaking, the switch SW12 may be turned off after a predetermined minute time has elapsed from the turn-off of the switch SW 13. The switch SW12 is turned off to disconnect the inverting input terminal and the output terminal of the amplifier 12, but there is no input/output of electric charge to/from the connection node between the chopper capacitor 16 and the switch SW12, and therefore, even in the state 620, the voltage of the inverting input terminal of the amplifier 12 is maintained at the reference voltage Vref (the same applies to the state 630 described later). Even if the switch SW13 is turned off, the charge corresponding to the reference voltage Vref is stored in the chopper capacitor 16. Therefore, in the state 620, the potential of the input line LN1 is also held at 0V (the same applies to the state 630 described later).

Control circuit 14 then transitions from state 620 to state 630 by turning off switch SW14 and turning on switch SW 11. The turn-off timing of the switch SW14 and the turn-on timing of the switch SW11 may be substantially the same, but strictly speaking, the switch SW11 may be turned on after a predetermined minute time has elapsed from the turn-off of the switch SW 14. In the state 630, since the switch SW11 is turned on and the switches SW12 to SW14 are turned off, the charge of the photocurrent Ip generated by the photodiode 11 is accumulated in the integrating capacitor 13, and the output voltage Vout rises in accordance with the photocurrent Ip.

The control circuit 14 sets the integration period in the on-period of the switch SW11 in the state 630. At this time, the integration period may be started from the opening timing of the switch SW 11. The control circuit 14 turns off the switch SW11 at the time when a predetermined integration time has elapsed from the start time of the integration period, thereby ending the integration period. The integration time may have a predetermined fixed length of time.

The detection circuit 15 detects an integrated value of the photocurrent Ip (the total amount of the photocurrent Ip generated during the integration period) during the integration period from the output voltage Vout during the integration period, and generates and outputs an illuminance sensing signal Sout corresponding to the detected integrated value. The detection circuit 15 has an AD converter (analog-digital converter), and generates an illuminance sensing signal Sout by converting an analog signal indicating the above-described integration value into a digital signal by the AD converter.

According to embodiment EX2_ a, since the integration operation is performed in a state where no bias is applied to the photodiode 11 (that is, in a state where the potential difference between the anode and the cathode of the photodiode 11 is zero), the above-described leakage current (dark current) is suppressed. As a result, in comparison with the comparative example of fig. 21 (particularly, in a high-temperature environment), the detection accuracy of the illuminance sensor is improved.

In embodiment EX2_ a described above, it is assumed that the discharge operation of the accumulated charge of the integration capacitor 13 is not performed during the integration period. Therefore, the detection circuit 15 of embodiment EX2_ a simply obtains the difference voltage between the output voltage Vout at the start time of the integration period and the output voltage Vout at the end time of the integration period, and obtains the amount proportional to the magnitude of the difference voltage as the integral value of the photocurrent Ip in the integration period.

However, one of important characteristics in the illuminance sensor is detection sensitivity. If the variation of the output voltage Vout is large with respect to the same light intensity, the detection sensitivity is improved. Therefore, as one of methods for improving the detection sensitivity, a method of extending the integration time is considered. However, actually, there is an upper limit voltage (hereinafter referred to as a D range upper limit) depending on the power supply voltage and the circuit system in the output voltage Vout, and when the output voltage Vout reaches the D range upper limit, an accurate integration operation cannot be performed. For example, if the power supply voltage is 3V, the output voltage Vout exceeding 3V cannot be obtained regardless of the circuit used. Further, since a voltage margin is required so that a transistor of an output stage of the amplifier 12 does not saturate, a voltage slightly lower than 3V (for example, 2.8V) becomes an upper limit of the D range.

Example EX2_ B

In consideration of the upper limit of the D range, as shown in fig. 25, the discharge circuit 17 may be added to the illuminance sensor 6 of example EX2_ a. Fig. 25 is a configuration diagram of the illuminance sensor 6 according to example EX2_ B, and the illuminance sensor 6 according to example EX2_ B has a configuration in which the discharge circuit 17 is added to the illuminance sensor 6 according to example EX2_ a. In embodiment EX2_ B, the capacitance value C2 of the integration capacitor 13 is variable. The following describes an integration operation using the discharge circuit 17. In addition, in embodiment EX2_ B, matters not particularly described below, and matters described in embodiment EX2_ a are also applicable to embodiment EX2_ B.

Discharge circuit 17 is connected to input line LN 1. The discharge circuit 17 discharges the electric charge stored in the integration capacitor 13 in accordance with the control signal CNT17 supplied thereto. The control signal CNT17 is a binary signal having a value of "0" or "1", and the discharge circuit 17 performs the discharge operation of the integration capacitor 13 when the value of the control signal CNT17 is "1" (specifically, performs the discharge operation of the integration capacitor 13 1 time in response to a change in the value of the control signal CNT17 from "0" to "1"), and stops the discharge operation of the integration capacitor 13 when the value of the control signal CNT17 is "0".

The control circuit 14 and the detection circuit 15 constitute a control block. The control block generates a control signal CNT17 for controlling the discharge circuit 17 using each comparison result of a first comparator that compares the output voltage Vout with the upper limit voltage VH and a second comparator that compares the output voltage Vout with the lower limit voltage VL. Here, "0 < VL < Vref < VH" holds. For example, (VL, Vref, VH) ═ 0.5V, 0.6V, 1.2V. The generation of the control signal CNT17 and the supply of the control signal CNT17 to the discharge circuit 17 may be performed by the control circuit 14 or the detection circuit 15, and hereinafter, the control circuit 14 may be the main body. The first comparator and the second comparator may be provided to the detection circuit 15. In addition, the detection circuit 15 also has a function of generating the integrated value DATA according to the number of discharges of the integration capacitor 13. The integration value DATA represents an integration value of the photocurrent Ip during integration, and the integration value DATA itself or DATA proportional to the integration value DATA can be used as the illuminance sensing signal Sout.

Fig. 26 is a timing chart of the integrating operation of illuminance sensor 6 according to example EX2_ B. Time t _C2 The previous operation corresponds to a standby period of the illuminance sensor 6. At a time t _C2 Early moment t _C1 The states of the switches SW11 to SW14 correspond to the state 610 in fig. 24. At a time t _C1 To start, the control circuit 14 turns off the switch SW12 after turning off the switch SW13, and then turns on the switch SW11 after turning off the switch SW 14. The switch SW11 is turned on at time t _C2 From time t _C2 The integration period is started.

In addition, the capacitance value C2 of the integration capacitor 13 is variable under the control of the control circuit 14. Hereinafter, the capacitance value is also simply referred to as a capacitance value. At time t described later _C3 Previously, the capacitance value C2 was set to the capacitance value C2a at the time t _C3 To do so, the capacitance value C2 is switched from the capacitance value C2a to the capacitance value C2 b. Here, the capacitance value C2b is set to be m times the capacitance value C2 a. m is greater than 1. For example, m is 32, C2a is 0.5pF and C2b is 16 pF.

At the start time t of the integration period _C2 The output voltage Vout coincides with the reference voltage Vref (noise and offset are ignored). In the standby period of the illuminance sensor 6, the integration value DATA is initialized to zero, and at the start time t of the integration period _C2 Is "DATA ═ 0". By at time t _C2 The switch SW11 is opened, and the output voltage Vout rises from the reference voltage Vref in accordance with the photocurrent Ip. At a time t _C2 Delayed by a predetermined integration time t _C3 The integration period is ended by turning off the switch SW 11. I.e. at time t _C2 And t _C3 The period in between corresponds to the integration period.

During the integration, the control signal CNT17 has a value of "0" as long as "Vout < VH". During the integration period, the control circuit 14 sets the value of the control signal CNT17 to "1" for a very short time every time the output voltage Vout reaches the upper limit voltage VH. In response to this, the discharge circuit 17 performs a discharge operation of the integration capacitor 13 every time the output voltage Vout reaches the upper limit voltage VH during the integration period. In the 1-time discharging operation, the integration capacitor 13 is discharged with a charge amount corresponding to "C2 a × (VH-Vref)". Since the integration period is "C2 ═ C2 a" (e.g., 0.5pf), the output voltage Vout is reduced from the upper limit voltage VH to the reference voltage Vref by 1 discharge operation. The integration operation in the integration period is particularly referred to as a uniform discharge operation.

The integration value DATA is incremented by 1 each time the uniform discharge operation is performed. In the example of fig. 26, since the uniform discharge operation is performed 3 times in the integration period, the end time t of the integration period is _C3 Becomes "DATA ═ 3".

At the end of the integration period t _C3 Thereafter, under the control of the control circuit 14, the discharge circuit 17 repeats the discharge operation until the output voltage Vout becomes lower than the lower limit voltage VL. The discharge operation performed after the integration period is ended is particularly referred to as a step discharge operation. In the example of fig. 26, the time t is shorter than the time t _C3 Delayed time t _C4 As a boundary, the state "Vout ≧ VL" is transited from the state "Vout ≧ VL" to the state "Vout < VL". Thus, time t _C3 And t _C4 The period between the two electrodes corresponds to a stage discharge period during which a stage discharge operation is performed. During the stage discharge, all of the switches SW11 to SW14 are turned off (however, the switch SW14 may be turned on). After the stage discharge period is completed, the control circuit 14 can return the states of the switches SW111 to SW14 to the state 610 in fig. 24 at an arbitrary timing.

As described above, at time t _C3 For this reason, the capacitance value C2 is switched from the capacitance value C2a to the capacitance value C2b, and thus "C2 ═ C2b ═ m × C2 a" is obtained during the step discharge. On the other hand, the discharge charge amount "C2 a × (VH-Vref)" in the 1-time discharge operation is the same between the batch discharge operation and the stage discharge operation. Therefore, the output voltage Vout decreases "(VH-Vref)/m" every time the stage discharge operation is performed. For example, if VH is 1.2V, Vref 0.6V and m is 32, the output voltage Vout decreases by about 18.8mV each time the stage discharge operation is performed, as compared with "0.6V/32 ≈ 18.8 mV". Such a stage discharge operation is repeated until time t when output voltage Vout becomes lower than lower limit voltage VL _C4 Until now.

The integrated value DATA is added with "1/m" every time the phase discharge operation is performed. Therefore, as shown in fig. 26, if the step discharge operation (n is an integer) is performed n times in the step discharge period after the 3 times of the uniform discharge operation in the integration period, the step discharge operation is performed at time t _C4 The "DATA ═ 3+ (n/m)". If such a collective discharge operation and a step discharge operation are used, the detection sensitivity can be increased according to the extension of the integration period without being limited by the upper limit of the D range, and the resolution of the integrated value DATA can be increased because the decimal point or less of the integrated value DATA can be measured.

In addition, the integration period cannot be extended without limitation in practice due to restrictions on the application. For example, in an irradiation sensor for a smart phone, it is necessary to complete an integration operation in about 10 to 100 μ s.

< third embodiment >

A third embodiment of the present disclosure will be explained. The first embodiment and the second embodiment described above can be combined, and the structure of the combination will be described in the third embodiment.

Fig. 27 shows a configuration of an illuminance sensor 8 according to a third embodiment. The illuminance sensor 8 corresponds to a combination of the configuration of example EX1_ a (fig. 6) belonging to the first embodiment and the configuration of example EX2_ a (fig. 23) belonging to the second embodiment. The illuminance sensor 8 is configured by adding the adjustment circuit 50 to the illuminance sensor 6 (fig. 23) of example EX2_ a. The configuration of the illuminance sensor 8 is the same as that of the illuminance sensor 6 (fig. 23) of example EX2_ a, except for the addition of the adjustment circuit 50. In illuminance sensor 8, adjustment circuit 50 is connected to input line LN 1. That is, the adjustment circuit 50 supplies the adjustment charge generated by the adjustment current Ia to the input line LN1, which is common between the first and third embodiments. However, in the illuminance sensor (see fig. 6) of the first embodiment, the input line LN1 is directly connected to the inverting input terminal of the amplifier 12, whereas in the illuminance sensor 8 of the third embodiment, the chopper capacitor 16 is inserted between the input line LN1 and the inverting input terminal of the amplifier 12 in accordance with the technique of the second embodiment.

In the illuminance sensor 8 of fig. 27, the states of the switches SW11 to SW14 are also controlled in the order shown in the second embodiment. That is, for example, the control circuit 14 in the illuminance sensor 8 turns off the switch SW12 after turning off the switch SW13, and then turns on the switch SW11 after turning off the switch SW14, with the state 610 of fig. 24 as a starting point.

However, in illuminance sensor 8, the integration period is not started from the time when switch SW11 is turned on, but the time when the high-low relationship between voltage Vout ' and Vth is switched from "Vout ' < Vth" to "Vout ' > Vth" by the rise of output voltage Vout thereafter is set as the start time of the integration period. The integration period is ended at the time when a predetermined integration time has elapsed from the time of switching from "Vout '< Vth" to "Vout' > Vth". For example, the control circuit 14 may set the start time and the end time of the integration period based on the output signal CNTa of the latch circuit 53, as in the first embodiment.

The supply of the adjustment charge (negative adjustment charge in the configuration example of fig. 27) to the input line LN1 by the adjustment circuit 50 is started before the states of the switches SW11 to S14 reach the state 630 of fig. 24 (for example, at the time point of the state 610 or 620). Alternatively, the supply of the adjustment charge to the input line LN1 by the adjustment circuit 50 may be started from the time point when the state 630 is shifted by the opening of the switch SW 11. Thereafter, at the time of switching from "Vout '< Vth" to "Vout' > Vth" (i.e., at the start time of the integration period), the supply of the adjustment charge to the input line LN1 by the adjustment circuit 50 is stopped. The detection circuit 15 of the third embodiment detects an integrated value of the photocurrent Ip (the total amount of the photocurrent Ip generated during the integration period) during the integration period from the output voltage Vout during the integration period, and generates and outputs an illuminance sensing signal Sout corresponding to the detected integrated value, as in the first and second embodiments.

Here, the illuminance sensor 8 in which the configuration of example EX1_ a (fig. 6) and the configuration of example EX2_ a (fig. 23) are combined is shown, but any example belonging to the first embodiment and any example belonging to the second embodiment may be combined.

< fourth embodiment >

A fourth embodiment of the present disclosure will be explained. In the fourth embodiment, an application example, a modification example, or a supplementary item to the first to third embodiments will be described. The illuminance sensor shown in the fourth embodiment without reference signs can be understood to mean any of the illuminance sensors shown in the first to third embodiments.

The illuminance sensors (6, 8) according to the second and third embodiments can be mounted on a smartphone SP (see fig. 20) including a display DD, as with the illuminance sensor (2, 3, 2 ', or 3') described in the first embodiment, and the illuminance sensors (6, 8) can be used for adjusting the luminance of the display DD.

However, any of the illuminance sensors according to the embodiments can be applied to and mounted on any device that requires illuminance detection. The arbitrary device here includes, for example, an electronic device, and examples of the electronic device include a mobile phone classified as a smartphone, a mobile phone not classified as a smartphone, an information terminal, a personal computer, a tablet computer, a game machine, a camera device, and the like.

In the illuminance sensor, the photodiode 11 is a source of generation of a current to be detected, and the current to be detected is a photocurrent Ip. The illuminance sensor detects illuminance from the total amount of detection target current (photocurrent Ip) generated during integration. The illuminance sensor described above incorporates an integration circuit. It can be considered that the integrating circuit is configured by the remaining portion excluding the photodiode 11 from the illuminance sensor.

The integration circuit of the present disclosure can also be applied to a sensor device that detects an arbitrary physical quantity. The illuminance sensor is an example of a sensor device. The sensor device may also be a temperature sensor, for example. In this case, the physical quantity is a temperature to be detected by the temperature sensor. A circuit element that generates a current corresponding to temperature (for example, a current obtained by current-converting a forward voltage of PN junction of a semiconductor) may be provided in the temperature sensor, and the generated current may be treated as a current to be detected.

The application range of the integration circuit of the present disclosure is not limited to the sensor device, and the integration circuit can be applied to any device.

The integrating circuit and the illuminance sensor disclosed in the present disclosure can be formed in the form of a semiconductor integrated circuit. The semiconductor integrated circuit is sealed in a housing (package) made of resin, thereby forming a semiconductor device.

The embodiments of the present disclosure can be modified in various ways as appropriate within the scope of the technical idea shown in the claims. The above embodiments are merely examples of the embodiments of the present disclosure, and the meanings of the terms of the present disclosure and the respective constituent elements are not limited to the contents described in the above embodiments. The specific numerical values shown in the above description are merely examples, and it is needless to say that they can be changed to various numerical values.

< appendage >

The technical idea embodied in the above-described embodiment will be considered.

The integration circuit of the present disclosure is an integration circuit (first structure) having: an amplifier configured to have a first input terminal, a second input terminal, and an output terminal, and to generate an output voltage at the output terminal; an integrating capacitor disposed between the first input terminal and the output terminal of the amplifier; a first switch provided between a generation source of a detection target current and the first input terminal of the amplifier; a second switch connected in parallel with the integrating capacitor; a control circuit configured to control states of the first switch and the second switch; and an adjustment circuit configured to include a comparator configured to compare a comparison voltage corresponding to the output voltage with a predetermined determination voltage, and an adjustment current generation circuit configured to generate an adjustment current, wherein the adjustment circuit is capable of supplying positive or negative adjustment charge generated by the adjustment current to the first input terminal of the amplifier in accordance with a comparison result of the comparator.

In the integration circuit of the first configuration (the second configuration), the adjustment circuit may supply the adjustment electric charge to the first input terminal when a high-low relationship between the comparison voltage and the determination voltage is in a first relationship after the control circuit switches the second switch from the on state to the off state, and the adjustment circuit may stop supplying the adjustment electric charge to the first input terminal when the high-low relationship between the comparison voltage and the determination voltage is in a second relationship opposite to the first relationship.

In the integration circuit having the second configuration, the integration circuit may further have a configuration (third configuration) in which: a detection circuit configured to detect a change amount of the output voltage during an integration period, wherein the control circuit sets the following period as the integration period: the high-low relationship is a period from a switching time point of the first relationship to the second relationship to a time point when a predetermined integration time has elapsed from the switching time point.

In the integration circuit according to the third configuration, the control circuit may be configured to switch the first switch from the on state to the off state when the integration time elapses from the switching time after the switching time elapses after a transition from a first state in which both the first switch and the second switch are in the on state to a second state in which the first switch is in the on state and the second switch is in the off state (a fourth configuration).

In the integration circuit according to any one of the first to fourth configurations described above, a configuration (a fifth configuration) may be adopted in which the integration circuit further includes: an additional capacitor provided between the output terminal of the amplifier and a predetermined node; a series circuit of a resistor and a third switch, which is provided between a reference potential terminal to which a predetermined reference potential is applied and the predetermined node; and a fourth switch provided between the first input terminal of the amplifier and the predetermined node.

In the integration circuit of the third or fourth configuration, a configuration (sixth configuration) may be such that the integration circuit further includes: an additional capacitor provided between the output terminal of the amplifier and a predetermined node; a series circuit of a resistor and a third switch, which is provided between a reference potential terminal to which a predetermined reference potential is applied and the predetermined node; and a fourth switch provided between the first input terminal of the amplifier and the predetermined node, wherein the control circuit keeps the third switch in an on state and keeps the fourth switch in an off state from before the start of the integration period, and then switches the third switch in an off state and switches the fourth switch in an on state when the first switch is switched from the on state to the off state.

In the integration circuit according to the fifth or sixth configuration, the capacitance value of the additional capacitor may be larger than the capacitance value of the integration capacitor (seventh configuration).

In the integration circuit according to any one of the first to seventh configurations, the adjustment current generation circuit may have a configuration (eighth configuration) in which: a constant current circuit configured to generate a constant current; and a capacitance unit having a first terminal and a second terminal, the capacitance unit having a plurality of capacitors, the constant current flowing through the first terminal in a section where the adjustment charge is supplied to the first input terminal, the capacitance unit causing the second terminal to generate a current smaller than the constant current as the adjustment current in accordance with the constant current in the first terminal, and thereby supplying the adjustment charge generated by the adjustment current to the first input terminal through the second terminal.

In the integration circuit according to the eighth configuration, the plurality of capacitors may include at least a first capacitor and a second capacitor, the second capacitor may have a smaller capacitance value than the first capacitor, one end of each of the first capacitor and the second capacitor may be commonly connected to the first terminal, when the constant current flows through the first terminal, charge transfer corresponding to the constant current may occur in the first capacitor and the second capacitor, and a current corresponding to the charge transfer may occur in the second terminal as the adjustment current (a ninth configuration).

The integration circuit according to any one of the first to ninth configurations described above may be configured as follows (tenth configuration), when the detection object current is generated in a direction in which the potential of the first input terminal of the amplifier decreases in an on section of the first switch, the adjustment charge has a negative polarity, the adjustment current generation circuit generates the adjustment current in a direction in which a potential of the first input terminal decreases in a section in which the adjustment charge is supplied to the first input terminal, when the current to be detected is generated in a direction in which the potential of the first input terminal of the amplifier increases in the on section of the first switch, the adjustment charge has a positive polarity, and the adjustment current generation circuit generates the adjustment current in a direction in which a potential of the first input terminal rises in a section in which the adjustment charge is supplied to the first input terminal.

In the integration circuit according to any one of the first to tenth configurations described above, the adjustment circuit may have a configuration (eleventh configuration) in which: and a low-pass filter configured to generate the contrast voltage from the output voltage.

In the integration circuit according to any one of the first to eleventh configurations, a generation source of the detection target current may be a photodiode (twelfth configuration).

The illuminance sensor of the present disclosure has a structure (thirteenth structure) including: the integration circuit according to any one of the first to twelfth configurations; and a photodiode as a generation source of the detection target current, the photodiode generating the detection target current corresponding to an amount of incident light between the photodiode and the first input terminal of the amplifier when the first switch is in an on state.

Another integration circuit of the present disclosure is a structure (fourteenth structure) having: an amplifier having a first input terminal, a second input terminal, and an output terminal; a first switch provided between a generation source of the detection target current and a predetermined line; a second switch disposed between the first input terminal and the output terminal of the amplifier; an integration capacitor provided between the output terminal of the amplifier and the predetermined line; a chopping capacitor provided between the predetermined line and the first input terminal of the amplifier; a third switch provided between a predetermined potential terminal having a predetermined potential different from a potential of the second input terminal of the amplifier and the predetermined line; a fourth switch provided between a connection node between the generation source of the detection object current and the first switch and the predetermined potential terminal; and a control circuit that controls states of the first to fourth switches.

In the integration circuit according to any one of the fourteenth and fifteenth configurations, starting from a state in which the first switch is off and the second to fourth switches are on, the control circuit may turn off the fourth switch and turn on the first switch after turning off the third switch and turning off the second switch.

In the integration circuit according to any one of the fifteenth configurations described above, the control circuit may turn off the second switch after the third switch is turned off, and then turn on the first switch after the fourth switch is turned off, starting from the state where the first switch is turned off and the second to fourth switches are turned on (a sixteenth configuration).

In the integration circuit according to any one of the fifteenth and sixteenth configurations described above, a configuration (seventeenth configuration) may be adopted in which the integration circuit further includes: and a detection circuit configured to detect an integrated value of the current to be detected during an integration period based on an output voltage from an output terminal of the amplifier during the integration period, wherein the control circuit sets the integration period during an on period of the first switch.

In the integration circuit according to any one of the fourteenth to seventeenth configurations described above, a generation source of the detection target current may be provided between the first switch and the predetermined potential terminal (eighteenth configuration).

Another illuminance sensor of the present disclosure has a configuration (nineteenth configuration) including: the integrating circuit according to any one of the fourteenth to eighteenth configurations; and a photodiode as a generation source of the detection object current.

Claims (19)

1. An integration circuit, comprising:

an amplifier configured to have a first input terminal, a second input terminal, and an output terminal, and to generate an output voltage at the output terminal;

an integrating capacitor disposed between the first input terminal and the output terminal of the amplifier;

a first switch provided between a generation source of a detection target current and the first input terminal of the amplifier;

a second switch connected in parallel with the integrating capacitor;

a control circuit configured to control states of the first switch and the second switch; and

and an adjustment circuit configured to include a comparator configured to compare a comparison voltage corresponding to the output voltage with a predetermined determination voltage, and an adjustment current generation circuit configured to generate an adjustment current, wherein the adjustment circuit is capable of supplying a positive or negative adjustment charge generated by the adjustment current to the first input terminal of the amplifier in accordance with a comparison result of the comparator.

2. The integration circuit of claim 1,

the adjustment circuit supplies the adjustment electric charge to the first input terminal when a high-low relationship between the comparison voltage and the determination voltage is in a first relationship after the second switch is switched from the on state to the off state by the control circuit, and stops supplying the adjustment electric charge to the first input terminal when the high-low relationship between the comparison voltage and the determination voltage is switched to a second relationship opposite to the first relationship.

3. The integration circuit of claim 2,

the integration circuit further includes: a detection circuit configured to detect a change amount of the output voltage during an integration period,

the control circuit sets the following period as the integration period: the high-low relationship is a period from a switching time point of the first relationship to the second relationship to a time point when a predetermined integration time has elapsed since the switching time point.

4. The integration circuit of claim 3,

the control circuit switches the first switch from the on state to the off state when the integration time elapses from the switching time after the switching time elapses after a transition from a first state in which the first switch and the second switch are both in the on state to a second state in which the first switch is in the on state and the second switch is in the off state.

5. The integration circuit according to any one of claims 1 to 4,

the integration circuit further includes:

an additional capacitor provided between the output terminal of the amplifier and a predetermined node;

a series circuit of a resistor and a third switch, which is provided between a reference potential terminal to which a predetermined reference potential is applied and the predetermined node; and

a fourth switch disposed between the first input terminal of the amplifier and the predetermined node.

6. The integration circuit of claim 3 or 4,

the integration circuit further includes:

an additional capacitor provided between the output terminal of the amplifier and a predetermined node;

a series circuit of a resistor and a third switch, which is provided between a reference potential terminal to which a predetermined reference potential is applied and the predetermined node; and

a fourth switch disposed between the first input terminal of the amplifier and the predetermined node,

the control circuit keeps the third switch in an on state and the fourth switch in an off state from before the start of the integration period, and then switches the third switch in an off state and the fourth switch in an on state when the first switch is switched from the on state to the off state.

7. The integration circuit of claim 5 or 6,

the capacitance value of the additional capacitor is larger than the capacitance value of the integration capacitor.

8. The integration circuit according to any one of claims 1 to 7,

the adjustment current generation circuit includes:

a constant current circuit configured to generate a constant current; and

a capacitor section having a first terminal and a second terminal and having a plurality of capacitors,

in a section in which the adjustment charge is supplied to the first input terminal, the constant current flows through the first terminal, and the capacitance section causes the second terminal to generate a current smaller than the constant current as the adjustment current in accordance with the constant current in the first terminal, whereby the adjustment charge generated by the adjustment current is supplied to the first input terminal through the second terminal.

9. The integration circuit of claim 8,

the plurality of capacitors includes at least a first capacitor and a second capacitor having a smaller electrostatic capacitance value than the first capacitor,

one end of each of the first capacitor and the second capacitor is commonly connected to the first terminal,

when the constant current flows through the first terminal, charge transfer corresponding to the constant current is generated in the first capacitor and the second capacitor, and a current corresponding to the charge transfer is generated as the adjustment current in the second terminal.

10. The integration circuit according to any one of claims 1 to 9,

the adjustment charge has a negative polarity when the detection target current is generated in a direction in which a potential of the first input terminal of the amplifier decreases in an on section of the first switch, the adjustment current generation circuit generates the adjustment current in the direction in which the potential of the first input terminal decreases in a section in which the adjustment charge is supplied to the first input terminal,

the adjustment electric charge has a positive polarity when the detection target current is generated in a direction in which a potential of the first input terminal of the amplifier rises in an on section of the first switch, and the adjustment current generation circuit generates the adjustment current in the direction in which the potential of the first input terminal rises in a section in which the adjustment electric charge is supplied to the first input terminal.

11. The integration circuit according to any one of claims 1 to 10,

the adjustment circuit has: and a low-pass filter configured to generate the comparison voltage from the output voltage.

12. The integration circuit according to any one of claims 1 to 11,

the generation source of the detection object current is a photodiode.

13. An illuminance sensor, comprising:

the integration circuit of any one of claims 1 to 12; and

a photodiode as a generation source of the detection object current,

when the first switch is in an on state, the photodiode generates the detection target current corresponding to an amount of incident light between the photodiode and the first input terminal of the amplifier.

14. An integration circuit, comprising:

an amplifier having a first input terminal, a second input terminal, and an output terminal;

a first switch provided between a generation source of the detection target current and a predetermined line;

a second switch disposed between the first input terminal and the output terminal of the amplifier;

an integrating capacitor provided between the output terminal of the amplifier and the predetermined line;

a chopping capacitor provided between the predetermined line and the first input terminal of the amplifier;

a third switch provided between a predetermined potential terminal having a predetermined potential different from a potential of the second input terminal of the amplifier and the predetermined line;

a fourth switch provided between a connection node between the generation source of the detection object current and the first switch and the predetermined potential terminal; and

and a control circuit for controlling the states of the first to fourth switches.

15. The integration circuit of claim 14,

the control circuit turns off the fourth switch and opens the first switch after turning off the third switch and turning off the second switch, starting from a state where the first switch is turned off and the second to fourth switches are turned on.

16. The integration circuit of claim 15,

the control circuit turns off the second switch after turning off the third switch, and then turns on the first switch after turning off the fourth switch, starting from the state where the first switch is turned off and the second to fourth switches are turned on.

17. The integration circuit of claim 15 or 16,

the integration circuit further includes: a detection circuit configured to detect an integrated value of the current to be detected during an integration period based on an output voltage from an output terminal of the amplifier during the integration period,

the control circuit sets the integration period during an on period of the first switch.

18. The integration circuit according to any one of claims 14 to 17,

the generation source of the detection object current is provided between the first switch and the predetermined potential terminal.

19. An illuminance sensor, comprising:

the integration circuit of any one of claims 14 to 18; and

a photodiode as a generation source of the detection object current.

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