JP2022134704A - Integration circuit and illumination sensor - Google Patents

Abstract

To reduce an influence of a noise in an integration circuit.SOLUTION: An integration circuit comprises: an amplifier that includes a first input terminal, a second input terminal, and an output terminal, and generates an output voltage in the output terminal; an integration capacitor that is provided between the first input terminal of the amplifier and the output terminal; a first switch that is provided between a generation source of a detection object current and the first input terminal of the amplifier; a second switch that is connected in parallel to the integration capacitor; a control circuit that controls a state of the first switch and the second switch; and an adjustment circuit that includes a comparator comparing a comparison voltage in accordance with the output voltage with a predetermined determination voltage and an adjustment current generation circuit that generates an adjustment current, and can supply a positive or negative adjustment charge by the adjustment current in accordance with a comparison result of the comparator to the first input terminal of the amplifier.SELECTED DRAWING: Figure 6

Description

The present disclosure relates to integration circuits and illuminance sensors.

An integrating circuit used for an illuminance sensor or the like includes an amplifier, an integrating capacitor, and the like. The integration circuit accumulates the charge of the detection target current (for example, the photocurrent generated by the photodiode) generated by the current generation source in the integration capacitor during the integration period, and generates a signal corresponding to the accumulated charge.

Japanese Unexamined Patent Application Publication No. 2011-4327

Noise occurs in the amplifier in the above integrating circuit. Depending on the magnitude of the current to be detected, the influence of noise increases, making it difficult to obtain a desired signal-to-noise ratio (that is, the precision of the integration result deteriorates). In addition, leakage current may occur at the source of the current to be detected. Leakage current is also a factor that degrades the accuracy of integration results.

An object of the present disclosure is to provide an integration circuit and an illuminance sensor that contribute to improving the accuracy of integration results.

An integration circuit according to the present disclosure includes an amplifier that has a first input terminal, a second input terminal, and an output terminal, and generates an output voltage at the output terminal; an integrating capacitor provided between; a first switch provided between a source of current to be detected and the first input terminal of the amplifier; and a second switch connected in parallel to the integrating capacitor. , a control circuit for controlling states of the first switch and the second switch, a comparator for comparing a comparison voltage corresponding to the output voltage with a predetermined judgment voltage, and an adjustment current generation circuit for generating an adjustment current. and an adjustment circuit capable of supplying positive or negative adjustment charge from the adjustment current to the first input terminal of the amplifier according to the comparison result of the comparator (first configuration) be.

In the integration circuit according to the first configuration, the adjustment circuit adjusts the level relationship between the comparison voltage and the determination voltage to the first level after the control circuit switches the second switch from the ON state to the OFF state. When there is one relationship, the adjustment charge is supplied to the first input terminal, and when the level relationship between the comparison voltage and the determination voltage is switched to the second relationship opposite to the first relationship, the first input terminal. The configuration (second configuration) may be such that the supply of the adjustment charge to is stopped.

The integration circuit according to the second configuration further includes a detection circuit that detects the amount of change in the output voltage during the integration period, wherein the control circuit switches the high-low relationship from the first relationship to the second relationship. A configuration (a third configuration) may be employed in which a period from the timing to the timing when a predetermined integration time elapses from the switching timing is set as the integration period.

In the integration circuit according to the third configuration, the control circuit is arranged such that the first switch is turned on and the second switch is turned off from a first state in which both the first switch and the second switch are turned on. A configuration (fourth configuration) in which the first switch is switched from the ON state to the OFF state after the transition to the second state as the state, and after the switching timing has passed and the integration time has elapsed from the switching timing. It can be.

In the integration circuit according to any one of the first to fourth configurations, an additional capacitor provided between the output terminal of the amplifier and a predetermined node, a reference potential terminal to which a predetermined reference potential is applied, and the predetermined node and a series circuit of a resistor and a third switch provided between and a fourth switch provided between the first input terminal of the amplifier and the predetermined node (fifth configuration).

In the integration circuit according to the third or fourth configuration, an additional capacitor provided between the output terminal of the amplifier and a predetermined node, and between a reference potential terminal to which a predetermined reference potential is applied and the predetermined node and a fourth switch provided between the first input terminal of the amplifier and the predetermined node, wherein the control circuit controls the integration Keeping the third switch in the ON state and the fourth switch in the OFF state from before the start of the period, and thereafter, when switching the first switch from the ON state to the OFF state, the third switch is turned OFF and the A configuration (sixth configuration) in which the fourth switch is turned on may be employed.

In the integration circuit according to the fifth or sixth configuration, the capacitance value of the additional capacitor may be larger than the capacitance value of the integration capacitor (seventh configuration).

In the integration circuit according to any one of the first to seventh configurations, the adjustment current generation circuit has a constant current circuit that generates a constant current, a first terminal and a second terminal, and is composed of a plurality of capacitors. a capacitance unit, wherein the constant current flows through the first terminal in a period in which the adjustment charge is supplied to the first input terminal, and the capacitance unit is based on the constant current at the first terminal, A configuration (eighth configuration) in which a current smaller than the constant current is generated at the second terminal as the adjustment current, thereby supplying the adjustment charge from the adjustment current to the first input terminal through the second terminal. It can be.

In the integration circuit according to the eighth configuration, the plurality of capacitors includes at least a first capacitor and a second capacitor having a capacitance value smaller than that of the first capacitor, and Each one end is connected in common to the first terminal, and when the constant current flows through the first terminal, movement of electric charge corresponding to the constant current occurs in the first and second capacitors, and the movement of electric charge may be generated at the second terminal as the adjustment current (ninth configuration).

With respect to the integration circuit according to any one of the first to ninth configurations, when the current to be detected is generated in the direction in which the potential of the first input terminal of the amplifier decreases during the ON period of the first switch, , the adjustment charge has a negative polarity, and the adjustment current generation circuit supplies the adjustment current in a direction in which the potential of the first input terminal decreases in a period in which the adjustment charge is supplied to the first input terminal. and when the current to be detected is generated in a direction in which the potential of the first input terminal of the amplifier rises during the ON period of the first switch, the adjustment charge has a positive polarity and the The adjustment current generation circuit may be configured to generate the adjustment current in a direction in which the potential of the first input terminal rises in a period during which the adjustment charge is supplied to the first input terminal (a tenth configuration). .

In the integration circuit according to any one of the first to tenth configurations, the adjustment circuit may have a configuration (eleventh configuration) that includes a low-pass filter that generates the comparison voltage from the output voltage.

In the integrating circuit according to any one of the first to eleventh configurations, a photodiode may be used as the source of the current to be detected (twelfth configuration).

An illuminance sensor according to the present disclosure includes an integrating circuit according to any one of the first to twelfth configurations, and a photodiode as a source of the detection target current, the photodiode being the first switch. is in an ON state, the current to be detected is generated between the photodiode and the first input terminal of the amplifier according to the amount of incident light (a thirteenth configuration).

Another integration circuit according to the present disclosure includes an amplifier having a first input terminal, a second input terminal, and an output terminal, a first switch provided between a current source to be detected and a predetermined line, and the amplifier a second switch provided between said first input terminal and said output terminal of said amplifier; an integrating capacitor provided between said output terminal of said amplifier and said predetermined line; A chopper capacitor provided between the first input terminal, a predetermined potential terminal having a predetermined potential different from the potential of the second input terminal of the amplifier, and the predetermined line. A fourth switch provided between three switches, a connection node between the source of the current to be detected and the first switch, and the predetermined potential terminal, and controls states of the first to fourth switches. and a control circuit for performing the above (fourteenth configuration).

In the integration circuit according to any one of the fourteenth configurations, the control circuit turns off the third switch starting from a state in which the first switch is off and the second to fourth switches are on, and After turning off the second switch, the fourth switch may be turned off and the first switch may be turned on (a fifteenth configuration).

In the integration circuit according to any one of the fifteenth configurations, the control circuit turns off the third switch starting from the state in which the first switch is off and the second to fourth switches are on. After that, the second switch is turned off, and after that, the fourth switch is turned off, and then the first switch is turned on (a sixteenth configuration).

The integration circuit according to any one of the fifteenth and sixteenth configurations above further includes a detection circuit for detecting an integrated value of the current to be detected during the integration period based on the output voltage from the output terminal of the amplifier during the integration period. The control circuit may be configured to set the integration period during the ON period of the first switch (17th configuration).

In the integration circuit according to any one of the fourteenth to seventeenth configurations, the generation source of the current to be detected is provided between the first switch and the predetermined potential terminal (eighteenth configuration). can be

Another illuminance sensor according to the present disclosure includes an integration circuit according to any one of the fourteenth to eighteenth configurations, and a photodiode as a generation source of the current to be detected (nineteenth configuration). be.

According to the present disclosure, it is possible to provide an integrating circuit and an illuminance sensor that contribute to improving the accuracy of integration results.

1 is a configuration diagram of an illuminance sensor according to the basic configuration of an embodiment of the present disclosure; FIG. 2 is a configuration diagram when a first connection mode of photodiodes is adopted in the illuminance sensor of FIG. 1; FIG. 2 is a configuration diagram when a second connection mode of photodiodes is adopted in the illuminance sensor of FIG. 1. FIG. FIG. 4 is a diagram showing a simplified output signal of an amplifier in the illuminance sensor according to the basic configuration; FIG. 4 is a waveform diagram according to a reference example of an illuminance sensor according to a basic configuration; FIG. 10 is a configuration diagram of an illuminance sensor according to Example EX1_A belonging to the first embodiment of the present disclosure; FIG. 10 is a diagram for explaining the operation of an adjustment circuit according to example EX1_A belonging to the first embodiment of the present disclosure; FIG. 10 is a diagram showing the state of each switch and the output waveform of an amplifier (first case) according to Example EX1_A belonging to the first embodiment of the present disclosure; FIG. 10 is a diagram showing the state of each switch and the output waveform of an amplifier (second case) according to example EX1_A belonging to the first embodiment of the present disclosure; FIG. 10 is a diagram for comparing the waveform of FIG. 8 (first case) and the waveform of FIG. 9 (second case) according to example EX1_A belonging to the first embodiment of the present disclosure; FIG. 10 is a diagram for explaining the influence of noise at the end of integration; FIG. 10 is a configuration diagram of an illuminance sensor according to Example EX1_B belonging to the first embodiment of the present disclosure; FIG. 10 is a diagram showing the relationship between the integration period and the state of each switch, according to Example EX1_B belonging to the first embodiment of the present disclosure; FIG. 10 is a diagram showing the state of each switch and the output waveform of the amplifier near the end of the integration period, according to example EX1_B belonging to the first embodiment of the present disclosure; FIG. 10 is a configuration diagram of an adjustment current generation circuit according to Example EX1_C belonging to the first embodiment of the present disclosure; FIG. 16 is an operation explanatory diagram of the adjustment current generation circuit of FIG. 15; FIG. 7 is a diagram showing a modified configuration of the illuminance sensor of FIG. 6, according to example EX1_D belonging to the first embodiment of the present disclosure; FIG. 13 is a diagram showing a modified configuration of the illuminance sensor of FIG. 12, according to example EX1_D belonging to the first embodiment of the present disclosure; FIG. 19 is a diagram showing the state of each switch and the output waveform of the amplifier in the illuminance sensor of FIG. 17 or 18, relating to Example EX1_D belonging to the first embodiment of the present disclosure; FIG. 10 is an external view of a smartphone according to Example EX1_F belonging to the first embodiment of the present disclosure; FIG. 7 is a configuration diagram of an illuminance sensor according to a comparative example, which is referred to in the second embodiment of the present disclosure; FIG. 10 is an operation explanatory diagram of an illuminance sensor according to a comparative example; FIG. 11 is a configuration diagram of an illuminance sensor according to example EX2_A belonging to the second embodiment of the present disclosure; FIG. 10 is a state transition diagram of each switch in an illuminance sensor, according to example EX2_A belonging to the second embodiment of the present disclosure. FIG. 10 is a configuration diagram of an illuminance sensor according to example EX2_B belonging to the second embodiment of the present disclosure; FIG. 10 is a timing chart of integration operation in an illuminance sensor according to example EX2_B belonging to the second embodiment of the present disclosure; FIG. FIG. 11 is a configuration diagram of an illuminance sensor according to a third embodiment of the present disclosure;

Hereinafter, examples of embodiments of the present disclosure will be specifically described with reference to the drawings. In each figure referred to, the same parts are denoted by the same reference numerals, and redundant descriptions of the same parts are omitted in principle. In this specification, for simplification of description, by describing symbols or codes that refer to information, signals, physical quantities, elements or parts, etc., information, signals, physical quantities, elements or parts corresponding to the symbols or codes are used. etc. may be omitted or abbreviated. For example, the integrating capacitor referenced by "13" below (see FIG. 1) may be written as integrating capacitor 13 or abbreviated as capacitor 13, but they are all the same. Point.

First, an explanation is provided for some terms used in describing embodiments of the present disclosure. Lines refer to wires through which electrical signals are propagated or applied. The ground has a reference potential of 0V (zero volts). A potential of 0 V is sometimes referred to as a ground potential. In embodiments of the present disclosure, voltages shown without specific reference represent potentials as seen from ground.

Any switch to be described later can be composed of one or more MOSFETs (metal-oxide-semiconductor field-effect transistors). Any switch has first and second terminals and a control terminal and is turned on or off depending on a control signal applied to the control terminal. One of the first and second terminals of any switch may be referred to as one end of the switch and the other as the other end of the switch. When a switch of interest is in an ON state, there is conduction between the first and second terminals of the switch of interest, allowing signal propagation (transfer of charge) through the switch of interest. When a certain switch of interest is in an off state, the first and second terminals of the switch of interest are in a non-conducting state (blocking state), and signal propagation (transfer of charge) through the switch of interest is disabled. becomes. Hereinafter, with respect to any switch, the period during which the switch is in an ON state may be referred to as an ON period, and the period during which the switch is in an OFF state may be referred to as an OFF period. Also, for any switch, switching from an off state to an on state may be expressed as turn-on, and switching from an on state to an off state may be expressed as turn-off. Also, the timing at which the switch is turned on is sometimes referred to as turn-on timing, and the timing at which the switch is turned off is sometimes referred to as turn-off timing.

<<First Embodiment>>
A first embodiment according to the present disclosure will be described. FIG. 1 shows the configuration of an illuminance sensor 1, which is an illuminance sensor having a basic configuration. The illuminance sensor 1 includes a photodiode 11, an amplifier (operational amplifier) 12, an integrating capacitor 13, a control circuit 14, a detection circuit 15, switches SW1 and SW2, and reference potential terminals 31 and 32. A reference potential Vref having a predetermined DC potential is commonly applied to the reference potential terminals 31 and 32 . The reference potential Vref has a positive DC potential. Note that the reference potential may be replaced with the reference voltage. It may be understood that the reference potential terminals 31 and 32 are common terminals.

The photodiode 11 generates a photocurrent Ip corresponding to the amount of incident light (the photocurrent Ip is not shown in FIG. 1). The amount of incident light is the amount of light incident on the photodiode 11 and also the amount of light incident on the illuminance sensor 1 .

The switches SW1 and SW2 are switches (bus switches) capable of propagating analog signals. The control circuit 14 individually controls the states (on/off states) of the switches SW1 and SW2 by supplying control signals CNT1 and CNT2 to the control terminals of the switches SW1 and SW2.

Amplifier 12 has an inverting input terminal, a non-inverting input terminal, and an output terminal. The non-inverting input terminal of amplifier 12 is connected to reference potential terminal 32 . Therefore, the reference potential Vref is applied to the non-inverting input terminal of the amplifier 12 . The integration capacitor 13 is provided between the inverting input terminal of the amplifier 12 and the output terminal of the amplifier 12, and the switch SW2 is connected in parallel to the integration capacitor 13. FIG. More specifically, one end of the integrating capacitor 13, one end of the switch SW2, and the inverting input terminal of the amplifier 12 are commonly connected by an input line LN1, and the other end of the integrating capacitor 13, the other end of the switch SW2, and the other end of the amplifier 12 are connected. The output terminal is commonly connected to the output line LN2. An output voltage Vout of the amplifier 12 is output from the output terminal of the amplifier 12 . In other words, amplifier 12 produces an output voltage Vout at its output terminal.

The detection circuit 15 detects the illuminance, which is the detection target of the illuminance sensor 1, according to the output voltage Vout, and generates and outputs an illuminance sense signal Sout representing the illuminance detection result. The illuminance to be detected by the illuminance sensor 1 is a physical quantity proportional to the amount of light incident on the photodiode 11 .

A switch SW1 is provided between the input line LN1 and the photodiode 11 . As the connection mode of the photodiode 11, there are a first connection mode and a second connection mode.

The illuminance sensor 1A in FIG. 2 is the illuminance sensor 1 when the photodiode 11 adopts the first connection mode. In the first connection mode, the anode of the photodiode 11 is connected to the reference potential terminal 31, the cathode of the photodiode 11 is connected to one end of the switch SW1, and the other end of the switch SW1 is connected to the input line LN1.

The illuminance sensor 1B in FIG. 3 is the illuminance sensor 1 when the photodiode 11 adopts the second connection mode. In the second connection mode, the cathode of photodiode 11 is connected to reference potential terminal 31, the anode of photodiode 11 is connected to one end of switch SW1, and the other end of switch SW1 is connected to input line LN1.

The direction of the photocurrent Ip generated by the photodiode 11 is from the cathode to the anode of the photodiode 11 . Therefore, in the first connection mode, the photocurrent Ip (positive charge) flows from the input line LN1 through the switch SW1 toward the photodiode 11 during the ON period of the switch SW1 (that is, the positive charge of the amplifier 12 during the ON period of the switch SW1). A photocurrent Ip is generated in the direction in which the potential of the inverting input terminal decreases). Therefore, in the first connection mode, if the switch SW1 is on and the switch SW2 is off, the photocurrent Ip and the action of the amplifier 12 increase the output voltage Vout over time. Conversely, in the second connection mode, the photocurrent Ip (positive charge) flows from the photodiode 11 through the switch SW1 in the ON period of the switch SW1 toward the input line LN1 (that is, the amplifier 12 in the ON period of the switch SW1). A photocurrent Ip is generated in the direction in which the potential of the inverting input terminal of is increased). Therefore, in the second connection mode, if the switch SW1 is on and the switch SW2 is off, the photocurrent Ip and the action of the amplifier 12 cause the output voltage Vout to decrease over time.

The detection circuit 15 detects the amount of change in the output voltage Vout during the integration period starting after the switch SW2 is turned off, and detects the illuminance based on the detected amount of change. A signal indicating the magnitude of the detected illuminance is generated and output as the illuminance sense signal Sout. The larger the amount of change in the output voltage Vout during the integration period, the larger the illuminance detection value, and the smaller the amount of change in the output voltage Vout during the integration period, the smaller the illuminance detection value.

[Reference example]
The operation according to the reference example will be described with reference to FIG. In the reference example, the illuminance sensor 1A itself shown in FIG. 2 is used. In the reference example, starting from an initial state in which both the switches SW1 and SW2 are turned on, the switch SW2 is turned off while keeping the switch SW1 on, and after a certain integration time has elapsed, the switch SW1 is turned off. In the reference example, the period from the turn-off timing of the switch SW2 to the turn-off timing of the switch SW1 is the integration period, and the illuminance is detected based on the amount of change in the output voltage Vout (corresponding to ΔVout in FIG. 4) during the integration period.

That is, the illuminance sensor 1A constitutes an integrating circuit having an amplifier 12, an integrating capacitor 13, and switches SW1 and SW2. First, the output voltage value (the value of the output voltage Vout) of the integration circuit is initialized by discharging the charge accumulated in the integration capacitor 13 during the period in which the switch SW2 is turned on while the switch SW1 is turned on. After that, when the switch SW2 is turned off while the switch SW1 is kept on, the charge due to the photocurrent Ip generated in the photodiode 11 is accumulated in the integrating capacitor 13. FIG. The illuminance can be detected from the output voltage Vout corresponding to the amount of charge accumulated in the integration capacitor 13 during the integration period.

In FIG. 4, the waveform of the output voltage Vout is shown in a simplified form, and in reality noise originating from the noise generated in the amplifier 12 is superimposed on the output voltage Vout. The noise generated by the amplifier 12 can be represented by the input-equivalent noise, and now it is assumed that the input-equivalent noise is superimposed on the input signal to the inverting input terminal of the amplifier 12 . ΔV _NOISE represents the maximum value of input-equivalent noise. Then, the input conversion noise of the amplifier 12 at the turn-off timing of the switch SW2 is indefinite in the range from "+ΔV _NOISE " to "-ΔV _NOISE ".

In FIG. 5A, a dashed waveform 910 represents the waveform of the output voltage Vout of the illuminance sensor 1A in the first case. The solid waveform 910 _LPF represents the waveform obtained by low-pass filtering waveform 910 . The first case is a case where the input conversion noise of the amplifier 12 at the turn-off timing of the switch SW2 is "+ΔV _NOISE ". In FIG. 5B, a dashed waveform 920 represents the waveform of the output voltage Vout of the illuminance sensor 1A in the second case. Solid waveform 920 _LPF represents the waveform obtained by low-pass filtering waveform 920 . The second case is a case where the input conversion noise of the amplifier 12 at the turn-off timing of the switch SW2 is "-ΔV _NOISE ". FIG. 5(c) shows waveforms 910, 920, 910 _LPF and 920 _LPF superimposed.

In the first case, due to input conversion noise of “+ΔV _NOISE ”, the output voltage Vout sharply drops immediately after the switch SW2 is turned off, and thereafter the output voltage Vout gradually rises due to the photocurrent Ip. In the second case, the output voltage Vout sharply rises immediately after the switch SW2 is turned off due to input conversion noise of “−ΔV _NOISE ”, and then the output voltage Vout gradually rises due to the photocurrent Ip. . That is, the input-referred noise is amplified by the gain (C1/C2), and the difference in the output voltage Vout immediately after the start of the integration period is proportional to (C1/C2) and ΔV _NOISE between the first and second cases. occur. Here, C1 represents the capacitance value of the parasitic capacitance formed between the anode and cathode of the photodiode 11, and C2 represents the capacitance value of the integration capacitor 13.

As a result, in the reference example, the amount of change in the output voltage Vout during the integration period is ΔVout1 and ΔVout2 in the first and second cases, respectively, and "ΔVout1<ΔVout2" is established. In other words, there is a difference in the illuminance detection result between the first case and the second case. The greater the difference, the worse the illuminance detection accuracy. The higher the illuminance detection sensitivity (that is, the smaller C2 is) or the larger the parasitic capacitance of the photodiode 11 (that is, the smaller C1), the greater the influence of noise.

[Example EX1_A]
The first embodiment includes examples EX1_A through EX1_F. The configuration and operation of an illuminance sensor capable of reducing the influence of noise will be described in Example EX1_A. FIG. 6 shows the configuration of the illuminance sensor 2 according to Example EX1_A. The illuminance sensor 2 has a configuration obtained by adding an adjustment circuit 50 to the illuminance sensor 1 having the basic configuration described above. Therefore, the illuminance sensor 2 includes a photodiode 11, an amplifier (operational amplifier) 12, an integrating capacitor 13, a control circuit 14, a detection circuit 15, switches SW1 and SW2, and a reference potential, similarly to the illuminance sensor 1 according to the basic configuration. terminals 31 and 32, the connection relationship and function of which are as described above. Further, in the illuminance sensor 2, the first connection mode corresponding to FIG. 2 is adopted for the photodiode 11. As shown in FIG. That is, in the illuminance sensor 2, the anode of the photodiode 11 is connected to the reference potential terminal 31, the cathode of the photodiode 11 is connected to one end of the switch SW1, and the other end of the switch SW1 is connected to the input line LN1.

The adjustment circuit 50 is a circuit for adjusting the start timing of the integration period, and includes a low-pass filter 51, a comparator 52, a latch circuit 53, an adjustment current generation circuit 54, a switch ((adjustment switch) SWa, Prepare.

The low-pass filter 51 performs low-pass processing to pass low-frequency components in the output voltage Vout and attenuate high-frequency components in the output voltage Vout. is generated as a comparison voltage Vout'. A comparison voltage Vout' is input to the comparator 52 . Specifically, the low-pass filter 51 has a resistor 51a and a capacitor 51b, one end of the resistor 51a is connected to the output line LN2 to which the output voltage Vout is applied, the other end of the resistor 51a is connected to one end of the capacitor 51b, and , the other end of the capacitor 51b is connected to the ground. As a result, a comparison voltage Vout' is generated at the connection node between the resistor 51a and the capacitor 51b. However, the configuration of the low-pass filter 51 is arbitrary as long as the effect of the low-pass processing described above can be obtained.

A comparator 52 compares the comparison voltage Vout' with a predetermined determination voltage Vth, and outputs a signal CMPout indicating the level relationship between them. Signal CMPout is a binary signal having a value of "0" or "1". In the illuminance sensor 2 adopting the first connection mode (see FIG. 2) for the photodiode 11, the potential of the determination voltage Vth is higher than the reference potential Vref. The comparator 52 has a function of detecting the timing when the output voltage Vout exceeds the determination voltage Vth, and the low-pass filter 51 is provided to make the timing less susceptible to noise.

A comparator 52 is a comparator with a hysteresis function. When the comparison voltage Vout' has the reference potential Vref, the value of the signal CMPout is "0". In the process in which the potential of the voltage for comparison Vout' rises from the reference potential Vref, when the voltage for comparison Vout' is lower than the determination voltage Vth, the value of the signal CMPout is maintained at "0" and the voltage for comparison Vout' rises to the determination voltage Vth. When it becomes higher, the value of the signal CMPout becomes "1" (see FIG. 7). Thereafter, the value of the signal CMPout is maintained at "1" and the comparison voltage Vout' is kept at "1" unless the comparison voltage Vout' becomes equal to or lower than the voltage (Vth-ΔV _HYS ) lower than the determination voltage Vth by the predetermined hysteresis width ΔV _HYS . becomes equal to or less than the voltage (Vth-ΔV _HYS ), the value of the signal CMPout returns to "0". The potential of the voltage (Vth-ΔV _HYS ) is higher than the reference potential Vref.

The latch circuit 53 latches and holds the value of the output signal CMPout of the comparator 52, and outputs a control signal CNTa corresponding to the held value (hereinafter referred to as held value) to the control terminal of the switch SWa. The initial value of the held value is "0". Referring to FIG. 7, the operation of the latch circuit 53 will be described starting from the state where the held value is "0". When the value of the signal CMPout changes from "0" to "1" in the process of increasing the output voltage Vout by turning off the switch SW2, the latch circuit 53 changes its holding value from "0" to "1". ”. Through the output of the control signal CNTa, the latch circuit 53 controls the switch SWa to the ON state when the value held by itself is "0", and controls the switch SWa to the OFF state when the value held by itself is "1". do. Note that the control signal CNTa is also supplied to the control circuit 14 . Therefore, the control circuit 14 can recognize the state of the switch SWa. Also, the control circuit 14 may initialize the value held by the latch circuit 53 to the initial value "0" at a necessary timing.

The switch SWa is a switch (bus switch) capable of propagating an analog signal. The switch SWa is provided between the input line LN1 and the adjustment current generation circuit 54, and is turned on or off according to the control signal CNTa supplied from the latch circuit 53. FIG.

The adjustment current generation circuit 54 can perform an adjustment charge supply operation of generating an adjustment current Ia and supplying adjustment charges from the adjustment current Ia to the input line LN1. In the configuration according to Example EX1_A, the adjustment charge supply operation is performed only during the ON period of the switch SWa. In the off period of the switch SWa, the adjustment charge supply operation is not executed (the adjustment charge supply operation is stopped), and no charge is exchanged between the input line LN1 and the adjustment current generation circuit 54. FIG. In the illuminance sensor 2 of FIG. 6, the adjustment current Ia flows from the input line LN1 to the ground through the switch SWa. In other words, during the ON period of the switch SWa, the adjustment current generating circuit 54 draws the adjustment current Ia from the input line LN1 in a direction in which the potential of the input line LN1 decreases. Therefore, in the illuminance sensor 2 of FIG. 6, the polarity of the adjustment charge supplied from the adjustment current generation circuit 54 to the input line LN1 during the ON period of the switch SWa is negative.

The illuminance sensor 2 performs the following illuminance detection operation at any required timing. The illuminance sensor 2 may repeatedly perform the illuminance detection operation at a predetermined cycle. The illuminance detection operation will be described by focusing on the first case and the second case described above.

First, the illuminance detection operation in the first case will be described with reference to FIG. In the first case, as described above, the input conversion noise of the amplifier 12 at the turn-off timing of the switch SW2 is "+ΔV _NOISE ". In FIG. 8, a broken-line waveform 510 represents the waveform of the output voltage Vout of the illuminance sensor 2 in the first case, and a solid-line waveform _510LPF represents the waveform of the comparison voltage Vout' of the illuminance sensor 2 in the first case. In the first case, the switches SW1, SW2, and SWa are all in the ON state before the timing _tA1 , the switch SW2 switches from the ON state to the OFF state at the timing _tA1 , and then the switch SWa at the timing _tA2 . is switched from the on state to the off state, and thereafter, the switch SW1 is switched from the on state to the off state at timing _tA3 .

In the illuminance detection operation, initial charging is performed first. During the initial charging period, the switches SW1 and SW2 are both turned on. The initial charging ends when the switch SW2 is turned off. During the ON period of the switch SW2, the accumulated charge in the integration capacitor 13 is discharged, and the DC component of the output voltage Vout converges to the reference potential Vref. At the start of the illuminance detection operation, the value held by the latch circuit 53 is initialized to "0", and the switch SWa is maintained in the ON state during the initial charging period.

In the illuminance detection operation, the control circuit 14 performs initial charging for a certain period of time, and then turns off the switch SW2 while maintaining the switch SW1 in the ON state, thereby ending the initial charging. In the first case of FIG. 8, the timing t _A1 corresponds to the turn-off timing of the switch SW2. In the first case of FIG. 8, immediately after the timing t _A1 , the output voltage Vout sharply drops due to the input conversion noise of “+ΔV _NOISE ”. After that, the switch SWa is in the ON state until the timing _tA2 when the comparison voltage Vout' reaches the determination voltage Vth. The output voltage Vout and the comparison voltage Vout' gradually rise.

At the timing _tA2 , the level relationship between the comparison voltage Vout' and the determination voltage Vth switches from "Vout'<Vth" to "Vout'>Vth". Therefore, the switch SWa is turned off at timing _tA2 . In the on period of the switch SW1 after the switch SWa is turned off, the output voltage Vout and the comparison voltage Vout' gradually increase only based on the drawing of the photocurrent Ip from the input line LN1.

The control circuit 14 recognizes the turn-off timing of the switch SWa based on the control signal CNTa for controlling the state of the switch SWa. In the first case of FIG. 8, it is determined that the timing _tA2 is the turn-off timing of the switch SWa. The control circuit 14 sets the integration period based on the turn-off timing of the switch SWa. The integration period in the first case is period 515, and the start timing and end timing of integration period 515 are timings t _A2 and t _A3 , respectively. The control circuit 14 sets the end timing t _A3 of the integration period 515 to the timing when a predetermined integration time has elapsed from the turn-off timing t _A2 of the switch SWa. The integration time has a predetermined fixed length of time. The control circuit 14 turns off the switch SW1 at the end timing t _A3 of the integration period 515 . In other words, the integration period 515 is ended by turning off the switch SW1.

The integration period 515 is a period for accumulating the charge due to the photocurrent Ip in the integration capacitor 13. During the integration period 515, no charge is exchanged between the integration capacitor 13 and the adjustment current generation circuit . That is, the amount of change in the output voltage Vout during the integration period 515 depends only on the photocurrent Ip. The detection circuit 15 detects illuminance based on the amount of change in the output voltage Vout during the integration period 515, and generates and outputs an illuminance sense signal Sout representing the illuminance detection result. The illuminance detection operation ends with the generation and output of the illuminance sense signal Sout.

Next, the illuminance detection operation in the second case will be described with reference to FIG. In the second case, as described above, the input equivalent noise of the amplifier 12 at the turn-off timing of the switch SW2 is "-ΔV _NOISE ". In FIG. 9, the broken line waveform 520 represents the waveform of the output voltage Vout of the illuminance sensor 2 in the second case, and the solid line waveform _520LPF represents the waveform of the comparison voltage Vout' of the illuminance sensor 2 in the second case. In the second case, the switches SW1, SW2, and SWa are all in the ON state before the timing _tB1 , the switch SW2 is switched from the ON state to the OFF state at the timing _tB1 , and then the switch SWa at the timing _tB2 . is switched from the ON state to the OFF state, and thereafter, the switch SW1 is switched from the ON state to the OFF state at timing _tB3 .

As described above, in the illuminance detection operation, initial charging is performed first. During the initial charging period, the switches SW1 and SW2 are both turned on. The initial charging ends when the switch SW2 is turned off. During the ON period of the switch SW2, the accumulated charge in the integration capacitor 13 is discharged, and the DC component of the output voltage Vout converges to the reference potential Vref. At the start of the illuminance detection operation, the value held by the latch circuit 53 is initialized to "0", and the switch SWa is maintained in the ON state during the initial charging period.

In the illuminance detection operation, the control circuit 14 performs initial charging for a certain period of time, and then turns off the switch SW2 while maintaining the switch SW1 in the ON state, thereby ending the initial charging. In the second case of FIG. 9, the timing t _B1 corresponds to the turn-off timing of the switch SW2. In the second case of FIG. 9, immediately after the timing t _B1 , the output voltage Vout sharply rises due to input conversion noise of “−ΔV _NOISE ”. After that, until the timing _tB2 when the comparison voltage Vout' reaches the determination voltage Vth, the switch SWa is in the ON state. The output voltage Vout and the comparison voltage Vout' gradually rise.

At the timing _tB2 , the level relationship between the comparison voltage Vout' and the determination voltage Vth switches from "Vout'<Vth" to "Vout'>Vth". Therefore, the switch SWa is turned off at timing _tB2 . In the on period of the switch SW1 after the switch SWa is turned off, the output voltage Vout and the comparison voltage Vout' gradually increase only based on the drawing of the photocurrent Ip from the input line LN1.

The control circuit 14 recognizes the turn-off timing of the switch SWa based on the control signal CNTa for controlling the state of the switch SWa. In the second case of FIG. 9, it is determined that the timing _tB2 is the turn-off timing of the switch SWa. The control circuit 14 sets the integration period based on the turn-off timing of the switch SWa. The integration period in the second case is a period 525, and the start timing and end timing of the integration period 525 are timings _tB2 and _tB3 , respectively. The control circuit 14 sets the end timing t _B3 of the integration period 525 to the timing when a predetermined integration time has elapsed from the turn-off timing t _B2 of the switch SWa. The integration time has a fixed length of time as described above. Therefore, the length of integration period 515 in the first case of FIG. 8 and the length of integration period 525 in the second case of FIG. 9 are the same. The control circuit 14 turns off the switch SW1 at the end timing t _B3 of the integration period 525 . In other words, the integration period 525 is ended by turning off the switch SW1.

The integration period 525 is a period for accumulating charges from the photocurrent Ip in the integration capacitor 13. During the integration period 525, no charges are exchanged between the integration capacitor 13 and the adjustment current generating circuit . That is, the amount of change in the output voltage Vout during the integration period 525 depends only on the photocurrent Ip. The detection circuit 15 detects illuminance based on the amount of change in the output voltage Vout during the integration period 525, and generates and outputs an illuminance sense signal Sout representing the illuminance detection result. The illuminance detection operation ends with the generation and output of the illuminance sense signal Sout.

FIG. 10 shows superimposed waveforms 510 _LPF and 520 _LPF of the comparison voltage Vout' in the first and second cases. In any of the first and second cases, the integration period (515, 525) starts from the timing when the level relationship between the comparison voltage Vout' and the determination voltage Vth switches from "Vout'<Vth" to "Vout'>Vth". is started. Therefore, the amount of change in the output voltage Vout during the integration period and the illuminance detection result based on the amount of change are not affected by the noise generated by the amplifier 12 at the start of the integration period (the turn-off timing of the switch SW2). . Therefore, the illuminance detection accuracy is improved in comparison with the reference example (see FIG. 5(c)).

[Example EX1_B]
With reference to FIGS. 11(a) to 11(c), the effect of noise generated by the amplifier 12 at the end of the integration period (turn-off timing of the switch SW1) will be examined. Broken-line waveforms 930 and 940 in FIGS. 11A and 11B relate to the illuminance sensor 1 (see FIG. 1) according to the basic configuration, and are examples of waveforms of the output voltage Vout when the integration period ends (two examples ). Solid waveforms 930 _LPF and 940 _LPF represent waveforms obtained by low-pass filtering waveforms 930 and 940, respectively. Waveforms 930 and 940 and waveforms _930LPF and _940LPF are shown superimposed in FIG. 11(c).

In the illuminance sensor 1 according to the basic configuration, the noise generated by the amplifier 12 when the switch SW1 is turned off remains in the integration capacitor 13, and the noise remaining in the integration capacitor 13 is superimposed on the output voltage Vout. This noise causes the output voltage Vout to shift irregularly in the vertical direction (whether the waveform 930 is obtained or the waveform 940 is obtained is uncertain). This leads to deterioration in the accuracy of illuminance detection. Turning off the switch SW1 reduces the gain associated with the amplifier 12, reducing the AC component of the noise, but leaving the DC component of the noise in the integrating capacitor 13. FIG.

A configuration for reducing the influence of noise at the end of such an integration period will be described in Example EX1_B. FIG. 12 shows the configuration of the illuminance sensor 3 according to Example EX1_B. The illuminance sensor 3 has a configuration in which a noise reduction circuit 60 is added to the illuminance sensor 2 according to Example EX1_A described above. Therefore, the illuminance sensor 3 includes a photodiode 11, an amplifier (operational amplifier) 12, an integrating capacitor 13, a control circuit 14, a detection circuit 15, switches SW1 and SW2, and a reference potential, similarly to the illuminance sensor 1 according to the basic configuration. terminals 31 and 32, the connection relationship and function of which are as described above. Further, the illuminance sensor 3 includes an adjustment circuit 50, similarly to the illuminance sensor 2 according to Example EX1_A, and the configuration and operation of the adjustment circuit 50 are as shown in Example EX1_A. Further, in the illuminance sensor 3, the first connection mode corresponding to FIG. 2 is adopted for the photodiode 11. As shown in FIG. That is, in the illuminance sensor 3, the anode of the photodiode 11 is connected to the reference potential terminal 31, the cathode of the photodiode 11 is connected to one end of the switch SW1, and the other end of the switch SW1 is connected to the input line LN1.

The noise reduction circuit 60 functions as a circuit for reducing the effects of noise at the end of the integration period, and the adjustment circuit 50 functions as a circuit for reducing the effects of noise at the start of the integration period. Therefore, the adjustment circuit 50 and the noise reduction circuit 60 can also be called first and second noise reduction circuits, respectively. Although it is preferable to provide both the adjustment circuit 50 and the noise reduction circuit 60 in the illuminance sensor, it is also possible to eliminate the adjustment circuit 50 from the illuminance sensor 3 when focusing only on the noise at the end of the integration period. .

The noise reduction circuit 60 includes a capacitor (additional capacitor) 61, a resistor 62, and switches SW3 and SW4. It can also be understood that the reference potential terminal 33 is also included in the components of the noise reduction circuit 60 .

Capacitor 61 is provided between the output terminal of amplifier 12 and a predetermined node 63 . That is, one end of the capacitor 61 is connected to the output terminal of the amplifier 12 (thus the output line LN2), and the other end of the capacitor 61 is connected to a predetermined node 63. FIG. A series circuit of a resistor 62 and a switch SW3 is provided between the reference potential terminal 33 and the node 63 . More specifically, one end of the switch SW3 is connected to the node 63, the other end of the switch SW3 is connected to one end of the resistor 62, and the other end of the resistor 62 is connected to the reference potential terminal 33. Like the reference potential terminals 31 and 32, the reference potential Vref is applied to the reference potential terminal 33. FIG. Incidentally, the reference potential terminals 31 to 33 may be understood as common terminals. A switch SW4 is provided between the inverting input terminal of amplifier 12 (and thus input line LN1) and node 63; That is, one end of the switch SW4 is connected to the inverting input terminal of the amplifier 12 (therefore, the input line LN1), and one end of the switch SW4 is connected to the node 63. FIG.

The switches SW3 and SW4, like the switches SW1 and SW2, are switches (bus switches) capable of propagating analog signals. The control circuit 14 individually controls the states (on/off states) of the switches SW1 to SW4 by supplying control signals CNT1 to CNT4 to the control terminals of the switches SW1 to SW4. The on/off switching timings of the switches SW1 and SW2 are as described in the embodiment EX1_A.

In the illuminance detection operation, the control circuit 14 turns on the switch SW3 from the time the initial charging is performed (therefore, from before the timing t _A1 in the example of FIG. 8 and from before the timing t _B1 in the example of FIG. 9). The switch SW4 is kept in the ON state and the switch SW4 is kept in the OFF state, and as shown in FIG. 13, when the switch SW1 is switched from the ON state to the OFF state, the switch SW3 is switched to the OFF state and the switch SW4 is switched to the ON state. After that, the switch SW3 may be maintained in the OFF state and the switch SW4 in the ON state until a new illuminance detection operation is performed.

Typically, the turn-off timing of the switch SW1, the turn-off timing of the switch SW3, and the turn-on timing of the switch SW4 may be the same. However, the turn-off timing of the switch SW3 may be before or after the turn-off timing of the switch SW1 by a predetermined minute time. It may be before or after the timing by a predetermined minute time. The turn-off timing of the switch SW3 may be the same as the turn-on timing of the switch SW4, or may precede or follow the turn-on timing of the switch SW4 by a predetermined minute time.

Broken-line waveforms 530 and 540 in FIGS. 14A and 14B are examples (two examples) of waveforms of the output voltage Vout when the integration period ends, relating to the illuminance sensor 3 . A solid line waveform 530 _LPF represents the waveform of the comparison voltage Vout' based on the output voltage Vout by the dashed line waveform 530, and a solid line waveform _540LPF represents the waveform of the comparison voltage Vout' based on the output voltage Vout by the dashed line waveform 540. Waveforms 530 and 540 and waveforms _530LPF and _540LPF are shown superimposed in FIG. 14(c).

During the ON period of the switch SW3, the capacitor 61 and the resistor 62 form a low-pass filter for the voltage across the capacitor 61. FIG. In other words, in the ON period of the switch SW3, the output voltage Vout is subjected to low-pass processing (low-pass processing for passing low-frequency components in the output voltage Vout and attenuating high-frequency components in the output voltage Vout). A voltage is applied across capacitor 61 . Therefore, the voltage across the capacitor 61 is less susceptible to noise generated by the amplifier 12 . At the end of the integration period, the capacitor 61, which is less susceptible to noise generated by the amplifier 12, is connected in parallel with the integration capacitor 13, thereby reducing noise (DC component shift) superimposed on the output voltage Vout. At this time, the capacitance value of the capacitor 61 can be set larger than the capacitance value of the integrating capacitor 13, and the ratio of the capacitance value of the capacitor 61 to the capacitance value of the integrating capacitor 13 can be set to The more it is increased, the greater the noise reduction effect.

[Example EX1_C]
Example EX1_C will be described. In the illuminance sensor 2 or 3 described above, after the initial charge, even if the photocurrent Ip is almost zero due to the action of the adjustment current Ia before the integration period starts, "Vout'<Vth" to "Vout'> A transition to Vth" is ensured. Here, although depending on the application, the photocurrent Ip is weak (for example, nA order). Further, when |Ip|<<|Ia|, the delay from when the DC component of the output voltage Vout reaches the determination voltage Vth to when the supply of the adjustment current Ia is cut off is the fluctuation of the output voltage Vout during the integration period. It is necessary to set the magnitude of the adjustment current Ia to approximately the magnitude of the expected photocurrent Ip, because the magnitude of the adjustment current Ia greatly affects the amount (therefore, the detection result of the illuminance).

For example, consider generating an adjustment current Ia of 1 nA based on a current of 1 μA (microampere). In this case, by preparing a current mirror circuit consisting of an input-side MOSFET and an output-side MOSFET and setting the ratio of the source area of the output-side MOSFET to the source area of the input-side MOSFET to 1000:1, in principle, the input When the drain current of the side MOSFET is 1 μA, a current of 1 nA (nanoampere) can be extracted from the output side MOSFET. However, it is generally difficult to improve the accuracy of generating such a minute current (because the current flowing through the MOSFET is too small), and the current taken out from the output-side MOSFET is actually 1/100 to 100 times that of 1 nA. It may fluctuate in the range.

In Example EX1_C, the configuration of the adjustment current generating circuit 54 capable of generating minute current with high accuracy will be described. FIG. 15 shows the configuration of the adjustment current generating circuit 100 according to Example EX1_C. The adjustment current generation circuit 100 can be used as the adjustment current generation circuit 54 of the embodiment EX1_A or EX1_B. The adjustment current generation circuit 100 includes a capacitance section 110, a constant current circuit 120, a bias application terminal 130, and a switch SWb.

The capacitive section 110 has a plurality of capacitors and terminals 115 and 116 . Capacitance unit 110 uses a plurality of capacitors to generate at terminal 116 a current obtained by multiplying the current flowing through terminal 115 by _kC . Terminal 116 is connected to one end of switch SWa, and the other end of switch SWa is connected to the inverting input terminal of amplifier 12 (amplifier 12 is not shown in FIG. 15). That is, the terminal 116 is connected to the inverting input terminal of the amplifier 12 via the switch SWa. The current generated at the terminal 116 (in other words, the current flowing through the terminal 116) corresponds to the adjustment current Ia, and the adjustment current Ia flows from the input line LN1 to the terminal 116 through the switch SWa only during the ON period of the switch SWa.

A ratio kC of the current flowing through the terminal 116 to the current flowing through the terminal 115 satisfies " ₀ <k<1" and is usually sufficiently smaller than one. In the example of FIG. 15, the capacitive section 110 is formed by a total of four capacitors 111-114. The connection relationship between the capacitors 111 to 114 and the terminals 115 and 116 will be described assuming that each capacitor has a first end and a second end. A first end of capacitor 111 and a first end of capacitor 112 are commonly connected to terminal 115, and a second end of capacitor 111 is connected to ground. A second end of capacitor 112 , a first end of capacitor 113 , and a first end of capacitor 114 are connected together at node 117 . A second end of capacitor 113 is connected to ground. A second end of capacitor 114 is connected to terminal 116 . In order to make the above ratio _kC smaller than 1, the capacitance value of capacitor 111 is set to be greater than the capacitance value of capacitor 112, and the capacitance value of capacitor 113 is set to be greater than the capacitance value of capacitor 114. set greater than the value.

Constant current circuit 120 is provided between node 140 connected to terminal 115 and the ground. Constant current circuit 120 operates to generate a constant current I _CNST and to flow constant current I _CNST from node 140 to ground. However, when the potential at node 140 drops to substantially 0V, constant current circuit 120 stops operating (ie, constant current I _CNST no longer flows). Constant current I _CNST has a fixed constant current value.

The state (on/off state) of the switch SWb is controlled by the control circuit 14 . One end of the switch SWb is connected to the node 140 and the other end of the switch SWb is connected to the bias application terminal 130 . A predetermined bias voltage Vbias is applied to the bias application terminal 130 . The bias voltage Vbias has a predetermined positive DC voltage value (eg 1.5V).

Numerical examples when the target value of the adjustment current Ia is set to 1 nA will be given. In this case, the magnitude of the constant current I _CNST is set to 1 μA and the capacitance values of capacitors 111, 112, 113 and 114 are set to 10 pF (picofarad), 0.2 pF, 1.8 pF and 0.1 pF, respectively. set to Thereby, an adjustment current Ia as shown in FIG. 16 is obtained. That is, first, the potentials of the terminals 115 and 116 and the node 117 are stabilized by keeping the switch SWb on for a certain period of time. Due to this stabilization, the voltage across the capacitor 111 becomes the voltage Vbias. After that, the control circuit 14 turns off the switch SWb. Then, a constant current I _CNST of 1 μA flows from the capacitor 110 through the terminal 115 and the constant current circuit 120 toward the ground continuously for a predetermined time immediately after the switch SWb is turned off. , a current of 1 nA flows through the terminal 116 from the switch SWa toward the capacitance unit 110 (assuming that the switch SWa is on at this time). A current of 1 nA flowing through this terminal 116 functions as an adjustment current Ia. In this numerical example, the adjustment current Ia can be maintained at 1 nA until about 10 μs (microseconds) have passed since the turn-off timing of the switch SWb. The adjustment current Ia gradually decreases from 1 nA and finally becomes zero.

In this manner, the adjustment current generating circuit 100 of FIG. 15 can generate a minute current with higher precision than when using a current mirror circuit. However, the adjustment current generating circuit 100 of FIG. 15 is a timed current source capable of generating a constant adjustment current Ia for a limited time. Therefore, it is preferable to set the constant of each circuit element so that a stable adjustment current Ia flows between the timings t _A1 and t _A2 in FIG. 8, and match the turn-off timing of the switch SWb with the turn-off timing of the switch SW2. However, the turn-off timing of the switch SWb may be before or after the turn-off timing of the switch SW2 by a predetermined minute time. The switch SWa may be maintained in the ON state long before the turn-off timing of the switch SWb. Alternatively, the switch SWa may be turned on at the same timing as the turn-off timing of the switch SWb, or may be turned on at a timing before or after the turn-off timing of the switch SWb by a predetermined minute time.

In any case, in the regulated current generation circuit 100, the constant current I _CNST flows through the terminal 115 during the ON period of the switch SWa, and as a result, the capacitance section 110 generates a current smaller than the constant current I _CNST at the terminal 116 as the regulated current Ia. Let In other words, when the constant current I _CNST flows through the terminal 115, the capacitors 111 to 114 move charges according to the constant current I _CNST , and the current corresponding to the charge moves in the capacitors 111 to 114 is the adjustment current Ia. It will occur at terminal 116 . Then, the charge (negative charge here) generated by the current generated at the terminal 116 is supplied to the inverting input terminal of the amplifier 12 through the switch SWa as the adjustment charge.

In the configuration example of FIG. 15, the capacitive section 110 is formed by four capacitors 111 to 114, but the total number of capacitors forming the capacitive section 110 is arbitrary as long as it is two or more. Capacitor section 110 may include at least capacitors 111 and 112 . When the capacitance section 110 is composed only of the capacitors 111 and 112, the capacitors 113 and 114 are removed from the capacitance section 110 of FIG. 15, and the node 117 is directly connected to the terminal 116. In this case, when a constant current I _CNST flows through terminal 115, a charge transfer corresponding to the constant current I _CNST occurs in capacitors 111 and 112, and the current corresponding to the charge transfer in capacitors 111 and 112 is adjusted. It will appear at terminal 116 as current Ia.

[Example EX1_D]
Example EX1_D will be described. In Examples EX1_A to EX1_C, the configuration in which the output voltage Vout changes in the increasing direction during the integration period has been described. may be transformed.

That is, for example, the illuminance sensor 2 of FIG. 6 may be transformed into the illuminance sensor 2' of FIG. 17, and the illuminance sensor 3 of FIG. 12 may be transformed into the illuminance sensor 3' of FIG.

Differences between the illuminance sensors 2 and 2' and differences between the illuminance sensors 3 and 3' include the following first to third differences. The configuration and operation of the illuminance sensor 2' are the same as those of the illuminance sensor 2, except for the first to third differences and the points shown below accompanying the first to third differences, and the illuminance sensor 3' is the same as the illuminance sensor 3 in configuration and operation.

The first difference is that unlike the illumination sensors 2 and 3, the illumination sensors 2' and 3' employ the second connection mode (see FIG. 3). That is, in the illuminance sensors 2' and 3', the cathode of the photodiode 11 is connected to the reference potential terminal 31, and the anode of the photodiode 11 is connected to one end of the switch SW1. Based on the first difference, in the illuminance sensors 2′ and 3′, the photocurrent Ip (positive charge) flows from the photodiode 11 through the switch SW1 toward the input line LN1 during the ON period of the switch SW1 (that is, the switch A photocurrent Ip is generated in the direction in which the potential of the inverting input terminal of the amplifier 12 rises during the ON period of SW1). Therefore, in the illuminance sensors 2' and 3', if the switch SW1 is on and the switch SW2 is off, the output voltage Vout decreases over time due to the action of the photocurrent Ip and the amplifier 12 (however, the switch SW2 is turned off). excluding the transient rise in the output voltage Vout that may occur immediately after turn-off).

As a second difference, unlike the illuminance sensors 2 and 3, in the illuminance sensors 2′ and 3′, the adjustment current Ia flows from the adjustment current generation circuit 54 through the switch SWa toward the input line LN1 during the ON period of the switch SWa. . That is, the adjustment current generation circuit 54 associated with the illuminance sensors 2' and 3' outputs the adjustment current Ia to the input line LN1 in the direction in which the potential of the input line LN1 rises during the ON period of the switch SWa. Therefore, in the illuminance sensors 2' and 3', the polarity of the adjustment charge supplied from the adjustment current generation circuit 54 to the input line LN1 during the ON period of the switch SWa is positive.

In the illuminance sensors 2' and 3', the input line LN1 is connected to one end of the switch SWa, and the adjustment current generating circuit 54 is It is provided between the other end of the switch SWa and a terminal to which a predetermined positive DC voltage is applied. Then, the adjustment current generating circuit 54 in the illuminance sensors 2' and 3' generates an adjustment current Ia directed to increase the potential of the input line LN1 based on the positive DC voltage. When the illuminance sensors 2' and 3' are formed by applying the configuration shown in Example EX1_C (see FIG. 15), a constant current I _CNST , which is k _C times the constant current I _CNST and flows from the terminal 116 through the switch SWa to the inverting amplifier terminal of the amplifier 12 (thus increasing the potential of the inverting amplifier terminal of the amplifier 12). current) is generated as the adjustment current Ia.

As a third difference, the operation of the comparator 52 differs between the illuminance sensors 2 and 3 and the illuminance sensors 2' and 3'. The comparator 52 associated with the illuminance sensors 2' and 3' has a function of detecting the timing when the output voltage Vout falls below the determination voltage Vth. In the illuminance sensors 2' and 3', the potential of the determination voltage Vth is lower than the reference potential Vref (see FIG. 19). In the illuminance sensors 2' and 3', when the comparison voltage Vout' has the reference potential Vref, the value of the signal CMPout is "0" and the potential of the comparison voltage Vout' drops from the reference potential Vref. In the process, when the voltage for comparison Vout' is higher than the determination voltage Vth, the value of the signal CMPout is kept at "0", and when the voltage for comparison Vout' is lower than the determination voltage Vth, the value of the signal CMPout becomes "1". Thereafter, the value of the signal CMPout is maintained at "1" unless the comparison voltage Vout' becomes equal to or higher than the voltage (Vth+ΔV _HYS ) higher than the determination voltage Vth by the predetermined hysteresis width ΔV _HYS , and the comparison voltage Vout' When it becomes (Vth+ΔV _HYS ) or more, the value of the signal CMPout returns to "0". The potential of the voltage (Vth+ΔV _HYS ) is lower than the reference potential Vref.

Based on the third difference, in the illuminance sensors 2' and 3', the value of the signal CMPout changed from "0" to "1" in the process in which the switch SW2 was turned off and the output voltage Vout decreased. At this time, the value held in the latch circuit 53 is switched from "0" to "1" and the switch SWa is turned off.

The illuminance detection operation of the illuminance sensors 2' and 3' will be described with reference to FIG. In FIG. 19, a dashed line waveform 510' represents an example of the waveform of the output voltage Vout in the illuminance sensors 2' and 3'. A solid line waveform 510 _LPF ' represents the waveform of the comparison voltage Vout' based on the output voltage Vout corresponding to the dashed line waveform 510'. Regarding the illuminance detection operation of the illuminance sensors 2' and 3', the switches SW1, SW2, and SWa are all in the ON state before the timing t _A1 ', and the switch SW2 is switched from the ON state to the OFF state at the timing t _A1 ', After that, the switch SWa switches from the on state to the off state at the timing t _A2 ′, and the switch SW1 switches from the on state to the off state at the timing t _A3 ′.

As described above, in the illuminance detection operation, initial charging is performed first. During the initial charging period, the switches SW1 and SW2 are both turned on. The initial charging ends when the switch SW2 is turned off. During the ON period of the switch SW2, the accumulated charge in the integration capacitor 13 is discharged, and the DC component of the output voltage Vout converges to the reference potential Vref. At the start of the illuminance detection operation, the value held by the latch circuit 53 is initialized to "0", and the switch SWa is maintained in the ON state during the initial charging period.

In the illuminance detection operation, the control circuit 14 performs initial charging for a certain period of time, and then turns off the switch SW2 while maintaining the switch SW1 in the ON state, thereby ending the initial charging. In the example of FIG. 19, the timing t _A1 ′ corresponds to the turn-off timing of the switch SW2. In the example of FIG. 19, immediately after the timing t _A1 ′, the output voltage Vout sharply rises due to the noise generated by the amplifier 12 . After that, the switch SWa is in the ON state until the timing t _A2 ' when the comparison voltage Vout' drops to the determination voltage Vth. The operating voltage Vout' gradually decreases.

At the timing t _A2 ′, the level relationship between the comparison voltage Vout′ and the determination voltage Vth switches from “Vout′>Vth” to “Vout′<Vth”. Therefore, the switch SWa is turned off at the timing t _A2 '. During the on period of the switch SW1 after the switch SWa is turned off, the output voltage Vout and the comparison voltage Vout' gradually decrease based only on the supply of the photocurrent Ip to the input line LN1.

The control circuit 14 recognizes the turn-off timing of the switch SWa based on the control signal CNTa for controlling the state of the switch SWa. In the example of FIG. 19, the timing t _A2 ′ is determined to be the turn-off timing of the switch SWa. The control circuit 14 sets the integration period based on the turn-off timing of the switch SWa. The integration period in the example of FIG. 19 is a period 515', and the start timing and end timing of the integration period 515' are timings t _A2 ' and t _A3 ', respectively. The control circuit 14 sets the end timing t _A3 ' of the integration period 515' to the timing when a predetermined integration time has elapsed from the turn-off timing t _A2 ' of the switch SWa. As mentioned above, the integration time has a predetermined fixed length of time. The control circuit 14 turns off the switch SW1 at the end timing t _A3 ' of the integration period 515'. In other words, turning off switch SW1 terminates the integration period 515'.

The integration period 515 ′ is a period for accumulating charges from the photocurrent Ip in the integration capacitor 13 , and there is no exchange of charges between the integration capacitor 13 and the adjustment current generating circuit 54 during the integration period 515 ′. That is, the amount of change in the output voltage Vout during the integration period 515' depends only on the photocurrent Ip. The detection circuit 15 detects illuminance based on the amount of change in the output voltage Vout during the integration period 515', and generates and outputs an illuminance sense signal Sout representing the illuminance detection result. The illuminance detection operation ends with the generation and output of the illuminance sense signal Sout.

A comparative description of the operation of the illumination sensors 2 and 3 and the operation of the illumination sensors 2' and 3' is provided below.

After the switch SW2 is switched from the on state to the off state by the control circuit 14, the adjustment circuit 50 in the illuminance sensors 2 and 3 (see FIGS. 6 or 12 and 8 or 9) adjusts the comparison voltage Vout' and When the level relationship with the determination voltage Vth is "Vout'<Vth", the adjustment switch SWa is turned on to supply negative adjustment charge to the input line LN1 (that is, the adjustment current Ia from the inverting input terminal of the amplifier 12). ), and when the level relationship between the comparison voltage Vout′ and the judgment voltage Vth switches from “Vout′<Vth” to “Vout′>Vth”, the input line LN1 (and thus the amplifier 12) is turned off.

The control circuit 14 in the illuminance sensors 2 and 3 (see FIG. 6 or 12 and FIG. 8 or 9) determines the corresponding A period from the switching timing to the timing when a predetermined integration time has elapsed is set as an integration period (515, 525). After the control circuit 14 in the illuminance sensors 2 and 3 transitions from the first state in which both the switches SW1 and SW2 are on to the second state in which the switch SW1 is on and the switch SW2 is off. , when the switching timing (t _A2 in FIG. 8, t _B2 in FIG. 9) is recognized, the switch SW1 is turned on at the timing (t A3 in FIG. 8, t _B3 in FIG. 9) after the integration time has elapsed from the switching timing (t _A3 in FIG. 8, t B3 in FIG. 9). to the off state (ie, terminate the integration period).

After the switch SW2 is switched from the on state to the off state by the control circuit 14, the adjustment circuit 50 in the illuminance sensors 2′ and 3′ (see FIG. 17 or FIGS. 18 and 19) determines the comparison voltage Vout′. When the level relationship with the voltage Vth is "Vout'>Vth", the positive adjustment charge is supplied to the input line LN1 by turning on the adjustment switch SWa (that is, the adjustment current Ia is supplied to the inverting input terminal of the amplifier 12). output), and when the level relationship between the comparison voltage Vout′ and the judgment voltage Vth switches from “Vout′>Vth” to “Vout′<Vth”, the adjustment switch SWa is turned off to turn off the input line LN1 (therefore, the amplifier 12) is turned off.

The control circuit 14 in the illuminance sensors 2′ and 3′ (see FIG. 17 or FIGS. 18 and 19) controls the timing of switching from “Vout′>Vth” to “Vout′<Vth” in the level relationship. A period from the timing to the timing when the predetermined integration time has passed is set as the integration period (period 515′ in FIG. 19). The control circuit 14 in the illuminance sensors 2' and 3' causes the switch SW1 and the switch SW2 to transition from a first state in which both the switches SW1 and SW2 are on to a second state in which the switch SW1 is on and the switch SW2 is off. After that, when the switching timing ( _{t A2} ' in FIG. 19) is recognized, the switch SW1 is switched from the ON state to the OFF state (that is, integration end the period).

[Example EX1_E]
Example EX1_E will be described. In Example EX1_E, a modified technique related to the switch (adjustment switch) SWa will be described. The techniques described in Example EX1_E are applicable to Examples EX1_A to EX1_D.

As described above, the adjustment current generation circuit 54 can perform the adjustment charge supply operation of generating the adjustment current Ia and supplying the adjustment charge from the adjustment current Ia to the input line LN1. Here, while the adjustment charge supply operation is performed during the ON period of the switch SWa (that is, the adjustment charge by the adjustment current Ia is supplied to the input line LN1), the adjustment charge supply operation is stopped during the OFF period of the switch SWa. (that is, the supply of the adjustment charge to the input line LN1 by the adjustment current Ia is stopped), the arrangement position of the switch SWa can be arbitrarily changed. For example, when the adjustment current generation circuit 100 of FIG. 15 is used as the adjustment current generation circuit 54, a switch SWa may be inserted in series between the node 140 and the constant current circuit 120. In this case, the terminal 116 may be directly connected to the inverting input terminal of the amplifier 12, and the constant current I _CNST will flow through the node 140 only during the ON period of the switch SWa inserted in series between the node 140 and the constant current circuit 120. As a result, the operation shown in Example EX1_C is realized.

The switch SWa may be omitted in any illuminance sensor (2, 3, 2' or 3') according to the embodiments EX1_A to EX1_D. In this case, the latch circuit 53 may control ON/OFF of the adjustment current generation circuit 54 . That is, in any one of the embodiments EX1_A to EX1_D, the switch SWa is omitted and the adjustment current generation circuit 54 is directly connected to the inverting input terminal of the amplifier 12, and the adjustment is performed when the value held by the latch circuit 53 is "0". While the operation of the current generation circuit 54 is turned on to perform the adjustment charge supply operation, when the value held by the latch circuit 53 is "1", the operation of the adjustment current generation circuit 54 is turned off to stop the adjustment charge supply operation. (See FIG. 7 where appropriate). 15 is used as the adjustment current generation circuit 54, the switch SWa is omitted and the terminal 116 is directly connected to the inverting input terminal of the amplifier 12, while the value held by the latch circuit 53 is When the value is "0", the operation of the constant current circuit 120 is turned on to cause the constant current circuit 120 to generate the constant current _ICNST . It may be turned off to stop constant current circuit 120 from generating constant current I _CNST (ie, to stop current flow between node 140 and constant current circuit 120).

[Example EX1_F]
Example EX1_F will be described. The illuminance sensor (2, 3, 2' or 3') described above can be installed in a smartphone SP including a display DD as shown in FIG. At this time, an illuminance sensor (2, 3, 2' or 3') can be used for luminance adjustment of the display DD. That is, the smartphone SP can adjust the luminance of the display DD based on the illuminance sense signal Sout of the illuminance sensor (2, 3, 2' or 3'). In order to improve the design of smartphone SPs, there have been many requests to make the optical window for the illuminance sensor (a window that takes in external light) inconspicuous. There are many. As the transmittance of the optical window decreases, it becomes necessary to increase the sensitivity of the illuminance sensor. The illuminance sensor (2, 3, 2' or 3') according to this embodiment is extremely useful because it has a configuration that is less susceptible to noise as described above.

<<Second Embodiment>>
A second embodiment according to the present disclosure will be described. A beneficial configuration in the second embodiment will be specifically shown in examples EX2_A and EX2_B described later, but first, a comparative example for comparison with those examples will be described.

FIG. 21 shows the configuration of an illuminance sensor 901 according to a comparative example. As shown in FIG. 21, in the illuminance sensor 901 according to the comparative example, the cathode of the photodiode 911 is connected to the inverting input terminal of the amplifier 912 through the switch SW911, and the anode of the photodiode 911 is grounded. In the illuminance sensor 901, a parallel circuit of an integrating capacitor 913 and a switch SW912 is connected between an output terminal and an inverting input terminal of an amplifier 912, and a positive DC voltage value (for example, 0.6 V) is applied to the non-inverting input terminal of the amplifier 912. is supplied with a reference voltage Vref. A connection node between the cathode of the photodiode 911 and the switch SW911 is connected to a terminal to which the reference voltage Vref is applied via the switch SW911B. The switch SW911B is controlled to be off during the on period of the switch SW911, and the switch SW911B is controlled to be on during the off period of the switch SW911.

As shown in FIG. 22, in the illuminance sensor 901, the integration period is started by turning off the switch SW912 while both the switches SW911 and SW912 are on, and then the integration period is ended by turning off the switch SW911. During the integration period, the output voltage Vo of the amplifier 912 increases according to the photocurrent Ip' generated by the photodiode 911. FIG. Illuminance detection can be performed based on this output voltage Vo.

In the illuminance sensor 901 according to the comparative example, the operating point of the amplifier 912, which is an integrating amplifier, and the operating point of the photodiode 911 are the same. That is, during the integration period, the amplifier 912 operates with the reference voltage Vref as the operating point, and the photodiode 911 operates with the reference voltage Vref applied between the anode and the cathode. When the reference voltage Vref is applied as a bias to the photodiode 911 during the integration period, a leakage current (dark current) flows through the photodiode 911 . Leakage current becomes significant at high temperatures. If a leak current flows, it is erroneously recognized as if there is incident light even in a dark state. Therefore, the leak current becomes a factor of deterioration of the detection accuracy of the illuminance sensor 901 .

A light-shielded photodiode is prepared separately from the photodiode 911, and leakage current (dark current) is canceled by taking the difference between the integration result using the photodiode 911 and the integration result using the light-shielded photodiode. A method of doing so will also be considered. However, in this method, it is necessary to separately prepare a light-shielded photodiode, and in addition, since it is difficult to perfectly match the leakage current, cancellation leakage may occur. Leakage current can be suppressed by setting the bias of the photodiode 911 to 0V, but an integrating amplifier that operates with 0V as the operating point cannot be created. Therefore, in the configuration of the illuminance sensor 901 in FIG. 21, the bias of the photodiode 911 cannot be set to 0V.

[Example EX2_A]
Example EX2_A belonging to the second embodiment will be described as an example that contributes to the reduction of the leakage current. FIG. 23 shows the configuration of the illuminance sensor 6 according to Example EX2_A.

The illuminance sensor 6 includes a photodiode 11, an amplifier 12, an integrating capacitor 13, a control circuit 14, a detection circuit 15, a chopper capacitor 16 and switches SW11 to SW14. The photodiode 11, the amplifier 12, the integrating capacitor 13, the control circuit 14, and the detection circuit 15 in the illuminance sensor 6 are the photodiode 11, the amplifier 12, the integrating They may be the same as the capacitor 13, the control circuit 14 and the detection circuit 15, and the description of the first embodiment regarding them also applies to the second embodiment.

However, the control circuit 14 in the illuminance sensor 6 has a function of controlling the switches SW11 to SW14. That is, the control circuit 14 in the illuminance sensor 6 individually controls the states (on/off states) of the switches SW11 to SW14 by supplying control signals CNT11 to CNT14 to the control terminals of the switches SW11 to SW14. The switches SW11 to SW14 are switches (bus switches) capable of propagating analog signals.

The illuminance sensor 6 is provided with a reference potential terminal (in other words, a reference potential point) 32 and a predetermined potential terminal (in other words, a predetermined potential point) 34 . A reference potential Vref (for example, 0.6 V) having a predetermined positive DC potential is applied to the reference potential terminal 32 . On the other hand, the predetermined potential terminal 34 has a potential of 0V. That is, the predetermined potential terminal 34 corresponds to ground.

The connection relationship of the constituent elements of the illuminance sensor 6 will be described. The anode of the photodiode 11 is connected to the predetermined potential terminal 34 (that is, grounded). The cathode of the photodiode 11 is connected to one end of the switch SW11, and the other end of the switch SW11 is connected to the input line LN1 (predetermined line). One end of the switch SW14 is connected to the node where the cathode of the photodiode 11 and the switch SW11 are connected, and the other end of the switch SW14 is connected to the predetermined potential terminal 34 (that is, grounded). One end of the switch SW13 is connected to the input line LN1, and the other end of the switch SW13 is connected to the predetermined potential terminal 34 (that is, grounded).

One end of the integrating capacitor 13 is connected to the output terminal of the amplifier 12, and the other end of the integrating capacitor 13 is connected to the input line LN1. One end of the switch SW12 is connected to the output terminal of the amplifier 12 and the other end of the switch SW12 is connected to the inverting input terminal of the amplifier 12 . The non-inverting input terminal of amplifier 12 is connected to reference potential terminal 32 for receiving reference potential Vref. A chopper capacitor 16 is inserted between the inverting input terminal of amplifier 12 and input line LN1. That is, one end of the chopper capacitor 16 is connected to the input line LN 1 and the other end of the chopper capacitor 16 is connected to the inverting input terminal of the amplifier 12 . As in the first embodiment, also in the second embodiment, the output voltage from the output terminal of the amplifier 12 is referred to as the output voltage Vout, and the wiring connected to the output terminal of the amplifier 12 to propagate the output voltage Vout is referred to as the output line LN2. called. The detection circuit 15 detects the illuminance, which is the detection target of the illuminance sensor 6, based on the output voltage Vout, and generates and outputs an illuminance sense signal Sout representing the illuminance detection result. The illuminance to be detected by the illuminance sensor 6 is a physical quantity proportional to the amount of light incident on the photodiode 11 .

The flow of switch control in the integration sensor 6 will be described with reference to FIG. State 610 shown in FIG. 24 is the initial state. In state 610, switch SW11 is off and switches SW12-SW14 are on. In the state 610, the output terminal and the inverting input terminal of the amplifier 12 are connected through the switch SW12, so the voltage of the inverting input terminal matches the reference voltage Vref. Also, in the state 610, the potential of the input line LN1 is kept at 0 V because the switch SW13 is on. Therefore, in state 610, chopper capacitor 16 is charged with reference voltage Vref.

Starting from the state 610, the control circuit 14 turns off the switch SW13 and turns off the switch SW12, thereby transitioning from the state 610 to the state 620. FIG. The turn-off timing of the switch SW13 and the turn-off timing of the switch SW12 may be substantially the same, but strictly speaking, it is preferable to turn off the switch SW12 after a predetermined minute time elapses after turning off the switch SW13. When the switch SW12 is turned off, the inverting input terminal and the output terminal of the amplifier 12 are disconnected. is kept at the reference voltage Vref (the same applies to state 630, which will be described later). Even if the switch SW13 is turned off, the electric charge corresponding to the reference voltage Vref is still accumulated in the chopper capacitor 16 . Therefore, the potential of the input line LN1 is kept at 0 V even in state 620 (the same applies to state 630, which will be described later).

After that, the control circuit 14 causes the state 620 to transition to the state 630 by turning off the switch SW14 and turning on the switch SW11. The turn-off timing of the switch SW14 and the turn-on timing of the switch SW11 may be substantially the same, but strictly speaking, the switch SW11 should be turned on after a predetermined minute time has passed since the switch SW14 was turned off. In the state 630, since the switch SW11 is on and the switches SW12 to SW14 are off, the charge due to the photocurrent Ip generated in the photodiode 11 is accumulated in the integration capacitor 13, and the output voltage Vout changes according to the photocurrent Ip. and rise.

The control circuit 14 sets the integration period during the ON period of the switch SW11 in the state 630. FIG. At this time, the integration period may be started from the turn-on timing of the switch SW11. The control circuit 14 ends the integration period by turning off the switch SW11 at the timing when a predetermined integration time has elapsed from the start timing of the integration period. The integration time may have a predetermined fixed length of time.

The detection circuit 15 detects the integrated value of the photocurrent Ip during the integration period (the total amount of the photocurrent Ip generated during the integration period) based on the output voltage Vout during the integration period, and outputs an illuminance sense signal corresponding to the detected integrated value. Generate and output Sout. The detection circuit 15 has an AD converter (analog-digital converter), and converts the analog signal representing the integrated value into a digital signal by the AD converter to generate an illuminance sense signal Sout.

According to the embodiment EX2_A, since the integration operation is performed in a state in which no bias is applied to the photodiode 11 (that is, a state in which the potential difference between the anode and cathode of the photodiode 11 is zero), the leak current (dark current) is suppressed. As a result, compared with the comparative example of FIG. 21, the detection accuracy of the illuminance sensor is improved (especially in a high temperature environment).

It should be noted that in the above-described embodiment EX2_A, it is assumed that the operation of discharging the charge accumulated in the integration capacitor 13 is not performed during the integration period. Therefore, the detection circuit 15 according to the embodiment EX2_A simply obtains the difference voltage between the output voltage Vout at the start timing of the integration period and the output voltage Vout at the end timing of the integration period, and is proportional to the magnitude of the difference voltage. Quantity is determined as the integrated value of the photocurrent Ip over the integration period.

By the way, one of the important characteristics of an illuminance sensor is detection sensitivity. If the change in the output voltage Vout increases with respect to the same intensity of light, the detection sensitivity increases. Therefore, one method of increasing the detection sensitivity is to lengthen the integration time. However, in reality, the output voltage Vout has an upper limit voltage (hereinafter referred to as the upper limit of the D range) that depends on the power supply voltage and the circuit system. . For example, if the power supply voltage is 3V, an output voltage Vout exceeding 3V cannot be obtained using any circuit. Also, since it is necessary to provide a voltage margin so that the transistors in the output stage of the amplifier 12 do not saturate, a voltage slightly lower than 3 V (for example, 2.8 V) is the upper limit of the D range.

[Example EX2_B]
Considering the upper limit of the D range, as shown in FIG. 25, a discharge circuit 17 may be added to the illuminance sensor 6 according to Example EX2_A. FIG. 25 is a configuration diagram of the illuminance sensor 6 according to Example EX2_B, and the illuminance sensor 6 according to Example EX2_B has a configuration in which a discharging circuit 17 is added to the illuminance sensor 6 according to Example EX2_A. Further, in Example EX2_B, the capacitance value C2 of the integrating capacitor 13 is variable. The integration operation using the discharge circuit 17 will be described below. In Example EX2_B, matters described in Example EX2_A also apply to Example EX2_B, unless otherwise specified.

Discharge circuit 17 is connected to input line LN1. The discharge circuit 17 discharges the charge accumulated in the integration capacitor 13 according to the control signal CNT17 supplied to itself. The control signal CNT17 is a binary signal that takes a value of "0" or "1", and the discharge circuit 17 discharges the integration capacitor 13 when the value of the control signal CNT17 is "1" (details , the integrating capacitor 13 is discharged once in response to the change of the value of the control signal CNT17 from "0" to "1"), and when the value of the control signal CNT17 is "0", the integrating capacitor 13 discharge operation is stopped.

A control block is composed of the control circuit 14 and the detection circuit 15 . The control block controls the discharge circuit 17 using the comparison results of a first comparator that compares the output voltage Vout with the upper limit voltage VH and a second comparator that compares the output voltage Vout with the lower limit voltage VL. A control signal CNT17 is generated. Here, "0<VL<Vref<VH" is established. For example, (VL, Vref, VH)=(0.5V, 0.6V, 1.2V). Although either the control circuit 14 or the detection circuit 15 may be the subject of generation of the control signal CNT17 and supply of the control signal CNT17 to the discharge circuit 17, in the following description it is assumed that the subject is the control circuit 14. . The first comparator and the second comparator may be provided in the detection circuit 15 . The detection circuit 15 also has a function of generating integration value data DATA based on the number of times the integration capacitor 13 is discharged. The integrated value data DATA represents the integrated value of the photocurrent Ip in the integration period, and the integrated value data DATA itself or data proportional to the integrated value data DATA can be used as the illuminance sense signal Sout.

FIG. 26 is a timing chart of integration operation by the illuminance sensor 6 according to Example EX2_B. The period before timing _tC2 corresponds to the standby period of the illuminance sensor 6 . At timing t _C1 before timing t _C2 , the states of the switches SW11 to SW14 match state 610 in FIG. Starting from timing _tC1 , the control circuit 14 turns off the switch SW13, turns off the switch SW12, and then turns off the switch SW14 and then turns on the switch SW11. The turn-on timing of the switch SW11 is the timing _tC2 , and the integration period starts from the timing _tC2 .

Also, the capacitance value C2 of the integration capacitor 13 is made variable under the control of the control circuit 14 . Hereinafter, the capacitance value is also simply referred to as the capacitance value. The capacitance value C2 is set to the capacitance value C2a before timing _tC3 , which will be described later, and the capacitance value C2 is switched from the capacitance value C2a to the capacitance value C2b at the timing _tC3 . Here, the capacitance value C2b is set to m times the capacitance value C2a. m is greater than one. For example, m=32, C2a=0.5 pF and C2b=16 pF.

At the integration period start timing _tC2 , the output voltage Vout matches the reference voltage Vref (noise and offset are ignored). Further, the integrated value data DATA is initialized to zero during the standby period of the illuminance sensor 6, and "DATA=0" at the start timing _tC2 of the integration period. As the switch SW11 is turned on at timing _tC2 , the output voltage Vout rises from the reference voltage Vref based on the photocurrent Ip. The integration period ends when the switch SW11 is turned off at a timing _tC3 after a predetermined integration time from the timing _tC2 . That is, the period between timings _tC2 and _tC3 corresponds to the integration period.

During the integration period, the control signal CNT17 has a value of "0" as long as "Vout<VH". During the integration period, every time the output voltage Vout reaches the upper limit voltage VH, the control circuit 14 sets the value of the control signal CNT17 to "1" for a minute time. In response to this, the discharge circuit 17 discharges the integration capacitor 13 each time the output voltage Vout reaches the upper limit voltage VH during the integration period. One discharge operation discharges the integration capacitor 13 by a charge amount corresponding to “C2a×(VH−Vref)”. Since "C2=C2a" (for example, 0.5 pf) during the integration period, the output voltage Vout drops from the upper limit voltage VH to the reference voltage Vref by one discharge operation. The integration operation during the integration period is particularly called a batch discharge operation.

The integrated value data DATA is incremented by 1 each time the batch discharge operation is performed. In the example of FIG. 26, since three batch discharge operations are performed within the integration period, "DATA=3" is set at the end timing _tC3 of the integration period.

After the integration period end timing _tC3 , the discharge circuit 17 repeats the discharge operation under the control of the control circuit 14 until the output voltage Vout falls below the lower limit voltage VL. A discharge operation that is performed after the integration period ends is particularly referred to as a stepped discharge operation. In the example of FIG. 26, the state of "Vout≧VL" transitions to the state of "Vout<VL" at timing _tC4 after timing _tC3 . Therefore, the period between the timings _tC3 and _tC4 corresponds to the staged discharge period during which the staged discharge operation is performed. All of the switches SW11 to SW14 are off during the stepped discharge period (however, the switch SW14 may be on). After the gradual discharge period ends, the control circuit 14 can return the state of the switches SW111 to SW14 to the state 610 of FIG. 24 at any timing.

As described above, the capacitance value C2 is switched from the capacitance value C2a to the capacitance value C2b at the timing _tC3 . On the other hand, the discharge charge amount “C2a×(VH−Vref)” in one discharge operation is the same between the batch discharge operation and the stepped discharge operation. Therefore, the output voltage Vout decreases by "(VH-Vref)/m" each time the stepped discharge operation is performed. For example, if VH=1.2V, Vref=0.6V, and m=32, the output voltage Vout is about 18V every time the stepped discharge operation is performed, according to "0.6V/32≈18.8mV". .8 mV. Such a stepwise discharge operation is repeated until timing _tC4 at which the output voltage Vout falls below the lower limit voltage VL.

The integrated value data DATA is added by "1/m" each time the stepped discharge operation is performed. Therefore, as shown in FIG. 26, if the stepped discharge operation is performed n times in the stepped discharge period (n is an integer) after the batch discharge operation is performed three times in the integration period, the timing t _{At C4} , "DATA=3+(n/m)". By using such a batch discharge operation and a stepwise discharge operation, it is possible to increase the detection sensitivity by the length of the integration period without being restricted by the upper limit of the D range, and to measure the integral value data DATA after the decimal point. Therefore, it is possible to improve the resolution of the integral value data DATA.

In practice, however, the integration period cannot be lengthened indefinitely due to application restrictions and the like. For example, in a lighting sensor for a smart phone, it is necessary to complete the integral action in about 10 to 100 μs.

<<Third Embodiment>>
A third embodiment according to the present disclosure will be described. The above-described first embodiment and second embodiment can be combined, and the configuration related to this combination will be described in the third embodiment.

FIG. 27 shows the configuration of the illuminance sensor 8 according to the third embodiment. The illuminance sensor 8 corresponds to a combination of the configuration of the example EX1_A belonging to the first embodiment (FIG. 6) and the configuration of the example EX2_A belonging to the second embodiment (FIG. 23). The illuminance sensor 8 is configured by adding the adjustment circuit 50 to the illuminance sensor 6 (FIG. 23) according to Example EX2_A. Except for the addition of the adjustment circuit 50, the configuration of the illuminance sensor 8 is the same as the configuration of the illuminance sensor 6 (FIG. 23) according to Example EX2_A. In the illuminance sensor 8, the adjustment circuit 50 is connected to the input line LN1. That is, it is common to the first and third embodiments that the adjustment circuit 50 supplies the adjustment charge by the adjustment current Ia to the input line LN1. However, in the illuminance sensor according to the first embodiment (see FIG. 6), the input line LN1 is directly connected to the inverting input terminal of the amplifier 12, whereas in the illuminance sensor 8 according to the third embodiment, the second embodiment Chopper capacitor 16 is inserted between input line LN1 and the inverting input terminal of amplifier 12, according to the technique of the embodiment.

In the illuminance sensor 8 of FIG. 27 as well, the states of the switches SW11 to SW14 are controlled in the order shown in the second embodiment. That is, for example, the control circuit 14 in the illuminance sensor 8 turns off the switch SW13, turns off the switch SW12, and then turns off the switch SW14 and then turns on the switch SW11, starting from the state 610 in FIG.

However, in the illuminance sensor 8, the integration period is not started from the turn-on timing of the switch SW11. >Vth” is set as the start timing of the integration period. Then, the integration period ends when a predetermined integration time elapses from the timing of switching from "Vout'<Vth" to "Vout'>Vth". For example, like the first embodiment, the control circuit 14 may set the start timing and end timing of the integration period based on the output signal CNTa of the latch circuit 53 .

Supply of the adjustment charge (negative adjustment charge in the configuration example of FIG. 27) to the input line LN1 by the adjustment circuit 50 is started before the states of the switches SW11 to S14 reach the state 630 in FIG. 610 or 620). Alternatively, the supply of adjustment charges to the input line LN1 by the adjustment circuit 50 may be started at the timing of transition to the state 630 by turning on the switch SW11. After that, at the timing when "Vout'<Vth" is switched to "Vout'>Vth" (that is, at the start timing of the integration period), the adjustment circuit 50 stops supplying the adjustment charge to the input line LN1. As in the first and second embodiments, the detection circuit 15 according to the third embodiment detects the integrated value of the photocurrent Ip during the integration period (photocurrent Ip generated during the integration period) based on the output voltage Vout during the integration period. is detected, and an illuminance sense signal Sout corresponding to the detected integrated value is generated and output.

Although the illuminance sensor 8 combining the configuration of Example EX1_A (FIG. 6) and the configuration of Example EX2_A (FIG. 23) is shown here, any example belonging to the first embodiment and the second embodiment It is also possible to combine with any embodiment belonging to .

<<Fourth Embodiment>>
A fourth embodiment according to the present disclosure will be described. In the fourth embodiment, application examples, modifications, or supplements to the first to third embodiments will be described. The illuminance sensors shown in the fourth embodiment without reference numerals may be understood to refer to any of the illuminance sensors shown in the first to third embodiments.

The illuminance sensors (6, 8) according to the second and third embodiments are also installed in the smartphone SP including the display DD, like the illuminance sensors (2, 3, 2' or 3') shown in the first embodiment. (see FIG. 20), and the illuminance sensor (6, 8) can be used for brightness adjustment of the display DD.

However, any illuminance sensor according to each embodiment can be applied and installed in any device that requires illuminance detection. Any device here includes, for example, electronic devices, and examples of electronic devices include mobile phones classified as smartphones, mobile phones not classified as smartphones, information terminals, personal computers, tablets, game machines, camera devices, and the like. be done.

In the illuminance sensor, the photodiode 11 is the source of the current to be detected, and the current to be detected is the photocurrent Ip. The illuminance sensor performs illuminance detection based on the total amount of current to be detected (photocurrent Ip) generated during the integration period. The illuminance sensor described above includes an integrating circuit. It can be considered that the illuminance sensor described above except for the photodiode 11 constitutes an integrating circuit.

The integration circuit according to the present disclosure can also be applied to sensor devices that detect arbitrary physical quantities. An illuminance sensor is an example of a sensor device. For example, the sensor device may be a temperature sensor. In this case, the physical quantity is the temperature to be detected by the temperature sensor. A temperature sensor may be provided with a circuit element that generates a current corresponding to temperature (for example, a current obtained by current-converting the forward voltage of a PN junction of a semiconductor), and the generated current may be handled as a current to be detected.

Furthermore, the scope of application of the integrating circuit according to the present disclosure is not limited to sensor devices, and can be applied to any device.

The integration circuit and the illuminance sensor according to the present disclosure can be formed in the form of semiconductor integrated circuits. A semiconductor device is configured by enclosing the semiconductor integrated circuit in a housing (package) made of resin.

The embodiments of the present disclosure can be appropriately modified in various ways within the scope of the technical idea indicated in the scope of claims. The above embodiments are merely examples of the embodiments of the present disclosure, and the meanings of the terms of the present disclosure and each constituent element are not limited to those described in the above embodiments. The specific numerical values given in the above description are merely examples and can of course be changed to various numerical values.

1, 2, 3, 2', 3', 6, 8 illumination sensor 11 photodiode 12 amplifier 13 integration capacitor 14 control circuit 15 detection circuit 16 chopper capacitor 50 adjustment circuit 51 low-pass filter 52 comparator 53 latch circuit 54 adjustment current generation Circuit 60 Noise reduction circuit 61 Capacitor (additional capacitor)
62 resistor 100 adjustment current generation circuit 110 capacitors 111 to 114 capacitors 115 and 116 terminals 120 constant current circuit 130 bias application terminals SW1 to SW4, SWa, SWb, SW11 to SW14 switches

Claims (19)

an amplifier having a first input terminal, a second input terminal and an output terminal for producing an output voltage at the output terminal;
an integrating capacitor provided between the first input terminal and the output terminal of the amplifier;
a first switch provided between a source of current to be detected and the first input terminal of the amplifier;
a second switch connected in parallel with the integration capacitor;
a control circuit that controls states of the first switch and the second switch;
A comparator that compares a comparison voltage corresponding to the output voltage with a predetermined judgment voltage, and an adjustment current generation circuit that generates an adjustment current. and a conditioning circuit capable of supplying a negative conditioning charge to said first input terminal of said amplifier. After the second switch is switched from the ON state to the OFF state by the control circuit, the adjustment circuit adjusts the adjustment charge to the first state when the magnitude relationship between the comparison voltage and the determination voltage is in the first relationship. 1 input terminal, and when the level relationship between the comparison voltage and the determination voltage switches to a second relationship opposite to the first relationship, the supply of the adjustment charge to the first input terminal is stopped; The integration circuit according to claim 1. further comprising a detection circuit that detects the amount of change in the output voltage during the integration period;
The control circuit sets, as the integration period, a period from timing of switching from the first relationship to the second relationship of the level relationship to timing when a predetermined integration time has elapsed from the switching timing. 3. The integration circuit according to 2. The control circuit causes a transition from a first state in which both the first switch and the second switch are on to a second state in which the first switch is on and the second switch is off. 4 . The integrating circuit according to claim 3 , wherein after the switching timing, the first switch is switched from the ON state to the OFF state when the integration time elapses from the switching timing. an additional capacitor provided between the output terminal of the amplifier and a predetermined node;
a series circuit of a resistor and a third switch provided between a reference potential terminal to which a predetermined reference potential is applied and the predetermined node;
5. The integration circuit according to claim 1, further comprising a fourth switch provided between said first input terminal of said amplifier and said predetermined node. an additional capacitor provided between the output terminal of the amplifier and a predetermined node;
a series circuit of a resistor and a third switch provided between a reference potential terminal to which a predetermined reference potential is applied and the predetermined node;
a fourth switch provided between the first input terminal of the amplifier and the predetermined node;
The control circuit keeps the third switch on and the fourth switch off before the start of the integration period, and thereafter, when switching the first switch from the on state to the off state, keeps the third switch on. 5. An integration circuit as claimed in claim 3 or 4, switching a switch to the off state and the fourth switch to the on state. 7. The integration circuit according to claim 5, wherein the capacitance value of said additional capacitor is greater than the capacitance value of said integration capacitor. The adjustment current generation circuit has a constant current circuit that generates a constant current, and a capacitance section that has a first terminal and a second terminal and is composed of a plurality of capacitors,
The constant current flows through the first terminal in a section in which the adjustment charge is supplied to the first input terminal, and the capacitance unit supplies a current smaller than the constant current based on the constant current at the first terminal. 8. The integrating circuit according to claim 1, wherein said adjustment current is generated at said second terminal as said adjustment current so that said adjustment charge due to said adjustment current is supplied to said first input terminal through said second terminal. the plurality of capacitors includes at least a first capacitor and a second capacitor having a smaller capacitance value than the first capacitor;
one end of each of the first and second capacitors is commonly connected to the first terminal;
When the constant current flows through the first terminal, charge movement corresponding to the constant current occurs in the first and second capacitors, and a current corresponding to the charge movement is the adjusted current at the second terminal. 9. The integrator circuit of claim 8, wherein the integrator circuit occurs at . When the current to be detected is generated in a direction in which the potential of the first input terminal of the amplifier decreases during the ON period of the first switch, the adjustment charge has a negative polarity to generate the adjustment current. a circuit for generating the adjustment current in a direction in which the potential of the first input terminal decreases in a section in which the adjustment charge is supplied to the first input terminal;
When the current to be detected is generated in a direction in which the potential of the first input terminal of the amplifier rises during the ON period of the first switch, the adjustment charge has a positive polarity to generate the adjustment current. 10. The integration circuit according to claim 1, wherein the circuit generates the adjustment current in a direction in which the potential of the first input terminal rises during the supply period of the adjustment charge to the first input terminal. 11. The integration circuit according to claim 1, wherein said adjustment circuit has a low-pass filter for generating said comparison voltage from said output voltage. 12. The integration circuit according to claim 1, wherein said current source to be detected is a photodiode. an integrating circuit according to any one of claims 1 to 12;
a photodiode as a source of the current to be detected,
The illuminance sensor, wherein the photodiode generates the current to be detected according to the amount of incident light between the photodiode and the first input terminal of the amplifier when the first switch is in an ON state. an amplifier having a first input terminal, a second input terminal and an output terminal;
a first switch provided between the source of the current to be detected and the predetermined line;
a second switch provided between the first input terminal and the output terminal of the amplifier;
an integrating capacitor provided between the output terminal of the amplifier and the predetermined line;
a chopper capacitor provided between the predetermined line and the first input terminal of the amplifier;
a third switch provided between a predetermined potential terminal having a predetermined potential different from the potential of the second input terminal of the amplifier and the predetermined line;
a fourth switch provided between a connection node between the source of the current to be detected and the first switch and the predetermined potential terminal;
and a control circuit that controls states of the first to fourth switches. The control circuit turns off the third switch, turns off the second switch, and then turns off the fourth switch, starting from a state in which the first switch is off and the second to fourth switches are on. and turn on the first switch. The control circuit turns off the third switch, turns off the second switch, and then turns off the second switch, starting from the state in which the first switch is off and the second to fourth switches are on. 16. The integrator circuit of claim 15, wherein four switches are turned off before the first switch is turned on. further comprising a detection circuit for detecting an integrated value of the current to be detected during the integration period based on the output voltage from the output terminal of the amplifier during the integration period;
17. The integration circuit according to claim 15, wherein said control circuit sets said integration period during an ON period of said first switch. 18. The integration circuit according to claim 14, wherein said detection target current generation source is provided between said first switch and said predetermined potential terminal. an integrating circuit according to any one of claims 14 to 18;
and a photodiode as a source of the current to be detected.

Images