CN115005842A - Frequency-modulated brain-computer interface chip input impedance enhancing method and system - Google Patents
Frequency-modulated brain-computer interface chip input impedance enhancing method and system Download PDFInfo
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- CN115005842A CN115005842A CN202210947840.3A CN202210947840A CN115005842A CN 115005842 A CN115005842 A CN 115005842A CN 202210947840 A CN202210947840 A CN 202210947840A CN 115005842 A CN115005842 A CN 115005842A
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- A—HUMAN NECESSITIES
- A61—MEDICAL OR VETERINARY SCIENCE; HYGIENE
- A61B—DIAGNOSIS; SURGERY; IDENTIFICATION
- A61B5/00—Measuring for diagnostic purposes; Identification of persons
- A61B5/24—Detecting, measuring or recording bioelectric or biomagnetic signals of the body or parts thereof
- A61B5/316—Modalities, i.e. specific diagnostic methods
- A61B5/369—Electroencephalography [EEG]
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- A—HUMAN NECESSITIES
- A61—MEDICAL OR VETERINARY SCIENCE; HYGIENE
- A61B—DIAGNOSIS; SURGERY; IDENTIFICATION
- A61B5/00—Measuring for diagnostic purposes; Identification of persons
- A61B5/24—Detecting, measuring or recording bioelectric or biomagnetic signals of the body or parts thereof
- A61B5/25—Bioelectric electrodes therefor
- A61B5/251—Means for maintaining electrode contact with the body
- A61B5/256—Wearable electrodes, e.g. having straps or bands
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- A—HUMAN NECESSITIES
- A61—MEDICAL OR VETERINARY SCIENCE; HYGIENE
- A61B—DIAGNOSIS; SURGERY; IDENTIFICATION
- A61B5/00—Measuring for diagnostic purposes; Identification of persons
- A61B5/24—Detecting, measuring or recording bioelectric or biomagnetic signals of the body or parts thereof
- A61B5/25—Bioelectric electrodes therefor
- A61B5/279—Bioelectric electrodes therefor specially adapted for particular uses
- A61B5/291—Bioelectric electrodes therefor specially adapted for particular uses for electroencephalography [EEG]
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- A—HUMAN NECESSITIES
- A61—MEDICAL OR VETERINARY SCIENCE; HYGIENE
- A61B—DIAGNOSIS; SURGERY; IDENTIFICATION
- A61B5/00—Measuring for diagnostic purposes; Identification of persons
- A61B5/24—Detecting, measuring or recording bioelectric or biomagnetic signals of the body or parts thereof
- A61B5/30—Input circuits therefor
- A61B5/307—Input circuits therefor specially adapted for particular uses
- A61B5/31—Input circuits therefor specially adapted for particular uses for electroencephalography [EEG]
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- A—HUMAN NECESSITIES
- A61—MEDICAL OR VETERINARY SCIENCE; HYGIENE
- A61B—DIAGNOSIS; SURGERY; IDENTIFICATION
- A61B5/00—Measuring for diagnostic purposes; Identification of persons
- A61B5/72—Signal processing specially adapted for physiological signals or for diagnostic purposes
- A61B5/7203—Signal processing specially adapted for physiological signals or for diagnostic purposes for noise prevention, reduction or removal
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- A—HUMAN NECESSITIES
- A61—MEDICAL OR VETERINARY SCIENCE; HYGIENE
- A61B—DIAGNOSIS; SURGERY; IDENTIFICATION
- A61B5/00—Measuring for diagnostic purposes; Identification of persons
- A61B5/72—Signal processing specially adapted for physiological signals or for diagnostic purposes
- A61B5/7225—Details of analog processing, e.g. isolation amplifier, gain or sensitivity adjustment, filtering, baseline or drift compensation
Abstract
The invention discloses a method and a system for enhancing the input impedance of a frequency-modulated brain-computer interface chip, which comprises the following steps: step S1: calibrating by changing the control voltage of the frequency adjusting channel, and setting the frequency obtained after calibration as the working frequency; step S2: carrying out chopper modulation on the acquired electroencephalogram signal to obtain a chopper-modulated electroencephalogram signal; step S3: amplifying the chopped wave modulated electroencephalogram signal through a chip amplifier module to obtain an amplified electroencephalogram signal; step S4: performing signal demodulation on the amplified electroencephalogram signal to obtain an original electroencephalogram signal; step S5: the original electroencephalogram signal passes through a low-pass filter to obtain an electroencephalogram analog signal; step S6: the electroencephalogram analog signal is converted into a discrete digital signal through an analog-to-digital converter. According to the invention, the chopping frequency is finely adjusted, the input current is controlled, the input impedance of the input end is maximized, the process error is overcome, the problem of accurate matching is solved, and the wearable electroencephalogram acquisition system is suitable for the wearable electroencephalogram acquisition system.
Description
Technical Field
The invention relates to the technical field of integrated circuit design, in particular to a method and a system for enhancing the input impedance of a frequency-modulated brain-computer interface chip.
Background
The brain-computer interface is an communication and control channel established between the human brain and a computer or other electronic equipment, is a direct connection channel established between the brain and external equipment, and through the channel, a human body can express ideas or operate the equipment directly through the brain, so that the capability of communicating with the outside or controlling the external environment of a patient with serious physical disability is effectively enhanced, and the life quality of the patient is greatly improved.
The brain-computer interface technology is a cross technology relating to multiple subjects of neuroscience, signal detection, signal processing, mode recognition and the like, and is used as a system engineering. Is a key core technology for comprehensively analyzing and knowing the brain, and is an important tool for the most advanced research of the international brain science.
In a traditional wearable electroencephalogram signal acquisition device, a dry electrode is used for signal acquisition, the input impedance of the dry electrode is megaohm level, an impedance enhancement loop is generally needed, but the capacitance value of a capacitor on the impedance enhancement loop is the same as that of an input capacitor, and is only about 10 fF. Due to the limitation of the semiconductor integration process at the present stage, the process error generated in the chip manufacturing process is inevitable. The brain-computer interface chip has high requirement on the accuracy of capacitance value of the capacitor, and the influence of tiny process errors on a chip circuit is not negligible. How to counteract the influence brought by process error, the accuracy of furthest improvement signal acquisition chip becomes the research difficulty.
Based on the background, the invention designs a method and a system for enhancing the input impedance of a frequency-modulated brain-computer interface chip.
Disclosure of Invention
In order to solve the technical problems, the invention provides a method and a system for enhancing the input impedance of a frequency-modulated brain-computer interface chip.
The technical scheme adopted by the invention is as follows:
a frequency-modulated brain-computer interface chip input impedance enhancement method comprises the following steps:
step S1: calibrating the chopping frequency of the chopping modulation unit and the chopping demodulation unit by changing the control voltage of the frequency adjusting circuit, and setting the frequency obtained after calibration as the working frequency of the chopping modulation unit and the chopping demodulation unit;
step S2: the dry active electrode worn outside the cranium and provided with electroencephalogram signal acquisition equipment transmits the acquired electroencephalogram signals to a chopping modulation unit through a signal acquisition channel for chopping modulation to obtain chopping modulated electroencephalogram signals;
step S3: amplifying the chopped wave modulated electroencephalogram signal through a chip amplifier module to obtain an amplified electroencephalogram signal;
step S4: carrying out signal demodulation on the amplified electroencephalogram signal through a chopping demodulation unit, and demodulating the amplified electroencephalogram signal to an original signal frequency band to obtain an original electroencephalogram signal;
step S5: filtering harmonic noise of the original electroencephalogram signal through a low-pass filter to obtain an electroencephalogram analog signal;
step S6: and converting the amplitude and the time continuous electroencephalogram analog signal into a discrete digital signal through an analog-to-digital converter.
Furthermore, an impedance enhancement loop is arranged at the input end of the chopping modulation unit and the output end of the chopping demodulation unit, and the impedance enhancement loop is composed of two impedance enhancement capacitors.
Further, the impedance boosting capacitance is 10 fF.
Furthermore, the chip amplifier module comprises a fixed gain amplifier, two sets of input capacitors, two sets of feedback capacitors and two sets of pseudo resistors, wherein the output end of the chopping modulation unit is connected with the two sets of input capacitors, the output end of the input capacitor is connected with the fixed gain amplifier, the output end of the fixed gain amplifier is connected with the chopping demodulation unit, the two ends of the fixed gain amplifier are also connected with the feedback capacitors, and the other end of the feedback capacitors is connected with the pseudo resistors.
Further, the gain of the fixed gain amplifier is designed to be 40dB, the bandwidth is 30 khz, the input capacitance is 1pF, the feedback capacitance is 10fF, and the pseudo resistance is 100G ohms.
Further, the chopping frequency of the chopper modulation unit and the chopping demodulation frequency of the chopper demodulation unit are the same.
Furthermore, the frequency adjusting path is composed of a voltage control oscillator and inverter drives, the output end of the voltage control oscillator is sequentially connected with the four inverter drives in series, and the output end of the last inverter drive is respectively connected with the chopping wave modulating unit and the chopping wave demodulating unit.
Further, the cut-off frequency of the low-pass filtering in the step S5 is 200 hz.
Further, the precision of the analog-to-digital converter in the step S6 is 10 bits.
The invention also provides a frequency-modulated brain-computer interface chip input impedance enhancing system which comprises a signal acquisition path and a frequency adjusting path, wherein the signal acquisition path is sequentially provided with a chopping modulation unit, a chip amplifier module, a chopping demodulation unit, a low-pass filter and an analog-to-digital converter, the frequency adjusting path is sequentially provided with a voltage control oscillator and four inverter drives, and the output end of the last inverter drive is respectively connected with the chopping modulation unit and the chopping demodulation unit; an impedance enhancement loop is arranged at the input end of the chopping modulation unit and the output end of the chopping demodulation unit;
the device comprises a chopping modulation unit, a control unit and a control unit, wherein the chopping modulation unit is used for carrying out chopping modulation on an electroencephalogram signal collected by a dry active electrode worn outside the cranium and carrying electroencephalogram signal collection equipment to obtain a chopping modulated electroencephalogram signal;
the chip amplifier module is used for amplifying the chopped wave modulated electroencephalogram signal to obtain an amplified electroencephalogram signal;
the chopping demodulation unit is used for demodulating the amplified electroencephalogram signal to an original signal frequency band to obtain an original electroencephalogram signal;
the low-pass filter is used for filtering the harmonic noise of the original electroencephalogram signal to obtain an electroencephalogram analog signal;
the analog-to-digital converter is used for converting the electroencephalogram analog signal with continuous amplitude and time into a discrete digital signal;
the voltage control oscillator and the four inverters are used for driving and adjusting the control voltage of the frequency adjusting path to finely adjust the chopping frequency of the chopping modulation unit and the chopping demodulation unit;
and the impedance enhancement loop is used for improving the input impedance on the signal acquisition path.
The invention has the beneficial effects that: the invention provides a method and a system for enhancing input impedance of a frequency-modulated brain-computer interface chip, which aim at the problem that a feedback capacitor in a traditional impedance enhancement loop is easily influenced by process errors. The technology needs to perform input impedance calibration once before acquisition, then sets the frequency obtained after calibration as chopping working frequency, and performs subsequent signal acquisition-chopping modulation-amplification-chopping demodulation-low-pass filtering-analog-to-digital conversion at the frequency. According to the invention, the chopping frequency is finely adjusted, the input current is controlled, the input impedance of the input end is maximized, the process error is overcome, the accurate matching problem is solved, and the wearable electroencephalogram acquisition system is suitable for the wearable electroencephalogram acquisition system.
Drawings
FIG. 1 is a flow chart of a method for enhancing input impedance of a frequency-modulated brain-computer interface chip according to the present invention;
FIG. 2 is a schematic diagram of a frequency-modulated input impedance enhancement system for a brain-computer interface chip according to the present invention;
FIG. 3 is a circuit diagram according to an embodiment of the present invention.
Detailed Description
The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the invention, its application, or uses. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
See FIG. 1
A frequency-modulated brain-computer interface chip input impedance enhancement method comprises the following steps:
step S1: calibrating the chopping frequency of the chopping modulation unit and the chopping demodulation unit by changing the control voltage of the frequency adjusting circuit, and setting the frequency obtained after calibration as the working frequency of the chopping modulation unit and the chopping demodulation unit; the frequency adjusting channel is composed of a voltage control oscillator and inverter drives, the output end of the voltage control oscillator is sequentially connected with the four inverter drives in series, and the output end of the last inverter drive is respectively connected with the chopping wave modulating unit and the chopping wave demodulating unit.
Step S2: the dry active electrode worn outside the cranium and provided with electroencephalogram signal acquisition equipment transmits the acquired electroencephalogram signals to a chopping modulation unit through a signal acquisition channel for chopping modulation to obtain chopping modulated electroencephalogram signals;
step S3: amplifying the chopped wave modulated electroencephalogram signal through a chip amplifier module to obtain an amplified electroencephalogram signal; the chip amplifier module comprises a fixed gain amplifier, two groups of input capacitors, two groups of feedback capacitors and two groups of pseudo resistors, wherein the output end of the chopping modulation unit is connected with the two groups of input capacitors, the output end of the input capacitor is connected with the fixed gain amplifier, the output end of the fixed gain amplifier is connected with the chopping demodulation unit, the two ends of the fixed gain amplifier are also connected with the feedback capacitors, and the other end of the feedback capacitors is connected with the pseudo resistors; the gain design of fixed gain amplifier is 40dB, and the bandwidth is 30 khz, input capacitance is 1pF, feedback capacitance is 10fF, pseudo resistance is 100G ohm.
Step S4: demodulating the amplified electroencephalogram signal to an original signal frequency band through a chopping demodulation unit to obtain an original electroencephalogram signal;
step S5: filtering harmonic noise of the original electroencephalogram signal through a low-pass filter to obtain an electroencephalogram analog signal; the cut-off frequency of the low-pass filtering is 200 hz.
Step S6: converting the electroencephalogram analog signal with continuous amplitude and time into a discrete digital signal through an analog-to-digital converter; the precision of the analog-to-digital converter is 10 Bit.
And the input end of the chopping modulation unit and the output end of the chopping demodulation unit are provided with an impedance enhancement loop, and the impedance enhancement loop is composed of two impedance boosting capacitors.
The impedance boosting capacitance is 10 fF.
The chopping frequency of the chopping modulation unit is the same as the chopping demodulation frequency of the chopping demodulation unit.
See FIG. 2
A brain-computer interface chip input impedance enhancement system adopting frequency modulation comprises a signal acquisition path and a frequency adjustment path, wherein a chopping modulation unit, a chip amplifier module, a chopping demodulation unit, a low-pass filter and an analog-to-digital converter are sequentially arranged on the signal acquisition path, a voltage control oscillator and four inverter drives are sequentially arranged on the frequency adjustment path, and the output end of the last inverter drive is respectively connected with the chopping modulation unit and the chopping demodulation unit; an impedance enhancement loop is arranged at the input end of the chopping modulation unit and the output end of the chopping demodulation unit;
the device comprises a chopping modulation unit, a control unit and a control unit, wherein the chopping modulation unit is used for carrying out chopping modulation on an electroencephalogram signal collected by a dry active electrode which is worn outside the cranium and carries electroencephalogram signal collection equipment to obtain a chopping modulated electroencephalogram signal;
the chip amplifier module is used for amplifying the chopped wave modulation electroencephalogram signal to obtain an amplified electroencephalogram signal;
the chopping demodulation unit is used for demodulating the amplified electroencephalogram signal to an original signal frequency band to obtain an original electroencephalogram signal;
the low-pass filter is used for filtering the harmonic noise of the original electroencephalogram signal to obtain an electroencephalogram analog signal;
the analog-to-digital converter is used for converting the electroencephalogram analog signal with continuous amplitude and time into a discrete digital signal;
the voltage control oscillator and the four inverters are used for driving and adjusting the control voltage of the frequency adjusting path to finely adjust the chopping frequency of the chopping modulation unit and the chopping demodulation unit;
and the impedance enhancement loop is used for improving the input impedance on the signal acquisition path.
Example (b):
see FIG. 3:
step S1: a sine input signal with certain frequency and amplitude is connected into a signal acquisition channel, and the control voltage V of the frequency adjustment channel is changed cal Trimming the chopping frequency of the chopping modulation unit and the chopping demodulation unit, and recording different control voltages V in the trimming process cal Lower output signal amplitude V pk Finally, the control voltage V when the amplitude of the output signal is maximum cal Setting the frequency obtained after calibration as the working frequency of the chopping modulation unit and the chopping demodulation unit as the working voltage of the chopping modulation unit and the chopping demodulation unit; the frequency adjusting path is composed of a voltage control oscillator VCO and an inverter drive, and the output end of the voltage control oscillator VCO is sequentially connected in seriesThe output end of the last inverter drive is respectively connected with the chopper modulation unit and the chopper demodulation unit, and the frequency of the chopper control signal generated by the voltage control oscillator VCO is controlled by a control voltage V cal Determined by regulating the control voltage V cal Changing the clock control signal V of a chopper modulation unit and a chopper demodulation unit CLK 。
And the input end of the chopping modulation unit and the output end of the chopping demodulation unit are provided with an impedance enhancement loop, and the impedance enhancement loop is composed of two impedance boosting capacitors.
Because the electrode impedance of the dry active electrode is in megaohm level, an impedance enhancing loop is arranged at the input end of the chopping modulation unit and the output end of the chopping demodulation unit to improve the input impedance, so that the signal distortion caused by the high electrode impedance of the signal at the electrode input end is avoided, and the impedance enhancing loop is formed by two impedance boosting capacitors C with the size of 10fF IBL1 、C IBL2 And (4) forming. When the feedback current I flows through the impedance enhancement loop IBL And an input current I in When the amplitudes are the same, they can cancel each other, i.e. the amplitude values are equal
Thus, the equivalent gain of the circuit can be expressed as:
when the current I is fed back IBL And an input current I in When the amplitudes are the same, the input end of the signal acquisition path can be used as the input current I in The input impedance of the signal acquisition path is 0, i.e. the input impedance of the signal acquisition path is infinite under the ideal condition, so the impedance enhancement loop improves the input impedance of the signal acquisition path end in such a way.
In order to ensure that the feedback current and the input current have the same amplitude as much as possible, a feedback capacitor C is required fb1,2 And C IBL1,2 The same size, all 10fF, but the on-chip capacitor is integratedThe circuit preparation process can not be completely consistent due to process errors, and the capacitance mismatching problem caused by the process errors is serious due to the small capacitance amplitude (10 fF). Input impedance Z of the circuit in The expression of (a) should be:
because the on-chip capacitor size is difficult to calibrate, the chopping frequency f can be finely adjusted c Then the input impedance Z is trimmed in The input current and the feedback current are equal and mutually offset, so that the process error is overcome, and the problem of accurate matching is solved.
Control voltage V through frequency regulation path cal The chopping frequency is adjusted to 4kHz, and then a sinusoidal input signal V with 10 Hz frequency and 100 microvolts amplitude is applied test A signal acquisition channel is accessed, because the gain of a fixed gain amplifier A1 is designed to be 40dB, when the input impedance Z of the circuit is in Maximum time, maximum output voltage V under ideal conditions out At 10 mv. Control voltage V through fine tuning frequency regulation path cal, Recording the output voltage V out At different control voltages V cal Magnitude of the condition when the output voltage V out At maximum amplitude, the input impedance Z is at this time in The control voltage V at the time is recorded when the maximum value is reached cal And keeping the calibration unchanged, and finishing the calibration.
The frequency f obtained after calibration c Setting the frequency as the working frequency to collect the EEG signal V in1 And the input end is connected to the signal acquisition channel.
Step S2: the dry active electrode worn outside the skull and provided with the electroencephalogram signal acquisition equipment acquires the electroencephalogram signal V in1 The signals are transmitted to a chopping modulation unit through a signal acquisition path to carry out chopping modulation, namely, the acquired electroencephalogram signals V are subjected to chopping modulation through two phases in1 Performing chopping modulation to a chopping frequency to avoid noise at low frequency part of the chip amplifier moduleClock control signal V generated by rate adjustment path CLK Determining to obtain a chopped wave modulation electroencephalogram signal;
step S3: amplifying the chopped wave modulated electroencephalogram signal through a chip amplifier module to obtain an amplified electroencephalogram signal; the chip amplifier module comprises a fixed gain amplifier A1 and two groups of input capacitors C in1 、C in2 Two sets of feedback capacitors C fb1 、C fb2 And two sets of dummy resistors R fb1 、R fb2 The output end of the chopping modulation unit is connected with two groups of input capacitors C in1 、C in2 Said input capacitance C in1 、C in2 Is connected with the fixed gain amplifier a1, the output end of the fixed gain amplifier a1 is connected with the chopper demodulation unit, and two ends of the fixed gain amplifier a1 are also connected with the feedback capacitor C fb1 、C fb2 Said feedback capacitance C fb1 、C fb2 Is connected with the dummy resistor R at the other end fb1 、R fb2 (ii) a The DC bias is formed by two pseudo resistors R with the size of 100G ohm and arranged between the input end and the output end of a fixed gain amplifier A1 fb1 、R fb2 Providing; the gain of the fixed gain amplifier A1 is designed to be 40dB, the bandwidth is 30 khz, and the input capacitor C in1 、C in2 Is 1pF, the feedback capacitance C fb1 、C fb2 Is 10fF, the pseudo resistance R fb1 、R fb2 Is 100G ohms. The expression of the gain of the chip amplifier module should be:
step S4: demodulating the amplified electroencephalogram signal to an original signal frequency band through a chopping demodulation unit to obtain an original electroencephalogram signal; the chopping demodulation process and the chopping modulation process are carried out by the same clock signal V CLK And (5) controlling.
Step S5: filtering harmonic noise of the original electroencephalogram signal through a low-pass filter to obtain an electroencephalogram analog signal; the cut-off frequency of the low-pass filtering is 200 hz.
The output signal of the chopping demodulation unit contains high-frequency harmonic noise, and the signal is transmitted to a low-pass filter to filter various harmonic noise, so that the acquired electroencephalogram analog signal is left.
Step S6: converting the electroencephalogram analog signal with continuous amplitude and time into a discrete digital signal through an analog-to-digital converter; the precision of the analog-to-digital converter is 10 Bit.
Aiming at the problem that a feedback capacitor in a traditional impedance loop is susceptible to process errors, a sinusoidal signal with certain frequency and amplitude is firstly connected into a signal acquisition channel, input control voltage of a voltage control oscillator of a frequency adjustment channel is changed to calibrate and fine-tune chopping frequency, and then current at the input end of the signal acquisition channel is changed, so that the technical goal of maximizing input impedance of the signal acquisition channel is achieved, and the input impedance of a circuit is adjusted to the maximum value. The technology needs to calibrate input impedance for one time before acquisition, then sets the frequency obtained after calibration as chopping working frequency, and performs subsequent signal acquisition-chopping modulation-amplification-chopping demodulation-low-pass filtering-analog-to-digital conversion operation at the frequency. According to the invention, the chopping frequency is finely adjusted, the input current is controlled, the input impedance of the input end is maximized, the process error is overcome, the problem of accurate matching is solved, and the wearable electroencephalogram acquisition system is suitable for the wearable electroencephalogram acquisition system.
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (10)
1. A frequency-modulated brain-computer interface chip input impedance enhancement method is characterized by comprising the following steps:
step S1: calibrating the chopping frequency of the chopping modulation unit and the chopping demodulation unit by changing the control voltage of the frequency adjusting circuit, and setting the frequency obtained after calibration as the working frequency of the chopping modulation unit and the chopping demodulation unit;
step S2: the dry active electrode worn outside the cranium and provided with electroencephalogram signal acquisition equipment transmits the acquired electroencephalogram signals to a chopping modulation unit through a signal acquisition channel for chopping modulation to obtain chopping modulated electroencephalogram signals;
step S3: amplifying the chopped wave modulated electroencephalogram signal through a chip amplifier module to obtain an amplified electroencephalogram signal;
step S4: demodulating the amplified electroencephalogram signal to an original signal frequency band through a chopping demodulation unit to obtain an original electroencephalogram signal;
step S5: filtering harmonic noise of the original electroencephalogram signal through a low-pass filter to obtain an electroencephalogram analog signal;
step S6: and converting the amplitude and the time continuous electroencephalogram analog signal into a discrete digital signal through an analog-to-digital converter.
2. The method according to claim 1, wherein an impedance boosting loop is provided at an input terminal of the chopper modulation unit and an output terminal of the chopper demodulation unit, and the impedance boosting loop is composed of two impedance boosting capacitors.
3. The method according to claim 2, wherein the impedance boosting capacitor is 10 fF.
4. The method according to claim 1, wherein the chip amplifier module comprises a fixed gain amplifier, two sets of input capacitors, two sets of feedback capacitors, and two sets of pseudo resistors, an output terminal of the chopper modulation unit is connected to the two sets of input capacitors, an output terminal of the input capacitor is connected to the fixed gain amplifier, an output terminal of the fixed gain amplifier is connected to the chopper demodulation unit, two ends of the fixed gain amplifier are further connected to the feedback capacitors, and the other end of the feedback capacitors is connected to the pseudo resistors.
5. The method of claim 4 wherein the gain of the fixed gain amplifier is designed to be 40dB, the bandwidth is 30 khz, the input capacitance is 1pF, the feedback capacitance is 10fF, and the pseudo resistance is 100 Gohms.
6. The method according to claim 1, wherein the chopping frequency of the chopper modulation unit is the same as the chopping demodulation frequency of the chopper demodulation unit.
7. The method according to claim 1, wherein the frequency modulation path comprises a voltage-controlled oscillator and inverter drivers, an output terminal of the voltage-controlled oscillator is sequentially connected in series with four inverter drivers, and an output terminal of the last inverter driver is respectively connected to the chopper modulation unit and the chopper demodulation unit.
8. The method as claimed in claim 1, wherein the cut-off frequency of the low-pass filtering in step S5 is 200 hz.
9. The method as claimed in claim 1, wherein the precision of the analog-to-digital converter in step S6 is 10 Bit.
10. A frequency-modulated brain-computer interface chip input impedance enhancement system is characterized by comprising a signal acquisition path and a frequency adjustment path, wherein a chopping modulation unit, a chip amplifier module, a chopping demodulation unit, a low-pass filter and an analog-to-digital converter are sequentially arranged on the signal acquisition path, a voltage control oscillator and four inverter drives are sequentially arranged on the frequency adjustment path, and the output end of the last inverter drive is respectively connected with the chopping modulation unit and the chopping demodulation unit; an impedance enhancement loop is arranged at the input end of the chopping modulation unit and the output end of the chopping demodulation unit;
the device comprises a chopping modulation unit, a control unit and a control unit, wherein the chopping modulation unit is used for carrying out chopping modulation on an electroencephalogram signal collected by a dry active electrode which is worn outside the cranium and carries electroencephalogram signal collection equipment to obtain a chopping modulated electroencephalogram signal;
the chip amplifier module is used for amplifying the chopped wave modulated electroencephalogram signal to obtain an amplified electroencephalogram signal;
the chopping demodulation unit is used for demodulating the amplified electroencephalogram signal to an original signal frequency band to obtain an original electroencephalogram signal;
the low-pass filter is used for filtering the harmonic noise of the original electroencephalogram signal to obtain an electroencephalogram analog signal;
the analog-to-digital converter is used for converting the electroencephalogram analog signal with continuous amplitude and time into a discrete digital signal;
the voltage control oscillator and the four inverters are used for driving and adjusting the control voltage of the frequency adjusting path to finely adjust the chopping frequency of the chopping modulation unit and the chopping demodulation unit;
and the impedance enhancement loop is used for improving the input impedance on the signal acquisition path.
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| CN116942169A (en) * | 2023-09-21 | 2023-10-27 | 之江实验室 | Miniaturized brain-computer signal amplifier and brain-computer interface chip system |
| CN117017308A (en) * | 2023-10-09 | 2023-11-10 | 之江实验室 | Slow wave neural signal amplifying circuit |
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