CN115001911A - High-speed FTN signal iterative equalization method and system based on FPGA - Google Patents
High-speed FTN signal iterative equalization method and system based on FPGA Download PDFInfo
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Abstract
The invention belongs to the technical field of wireless communication, and relates to a high-speed FTN signal iterative equalization system and method based on an FPGA. By adopting a partitioned data structure and a simplified iterative equalization algorithm and through a separated feedforward and feedback structure, the complexity is obviously reduced while the system performance is ensured; the processing speed and the throughput are improved through a parallel structure and a pipeline processing mode; all the computing requirements in the system are integrated, the computing modules are realized by using uniform interfaces and architectures, and a large amount of hardware resources are saved by multiplexing the general computing modules.
Description
Technical Field
The invention belongs to the technical field of wireless communication, and relates to a high-speed FTN signal iterative equalization system and method based on an FPGA.
Background
In recent years, the rapid development of 5G technology has made mobile access technology, which is dedicated to the internet of everything, one of the important internet access forms, and more communication systems are deployed in miniaturized terminal devices with limited power. Therefore, embedded devices with high performance and low power consumption are becoming a research hotspot in engineering applications. Among them, a signal processing system designed based on FPGA is the most widespread solution. Meanwhile, the problem that the frequency spectrum resources are increasingly tense is brought about by the interconnection of everything, and the transmission speed and the communication quality of signals are seriously influenced. In such a background, the Faster-Than-Nyquist transmission technique (FTN) having higher spectral efficiency and channel capacity has attracted a wide attention in the field of wireless communication. In 1975, Mazo proposed the super-nyquist theorem and demonstrated that when signals were transmitted in an additive white gaussian noise channel at a rate that exceeded the nyquist rate by 25%, the minimum euclidean distance between the signals remained unchanged and the error performance was not affected. This conclusion breaks the constraints of orthogonal transmission and demonstrates the feasibility of non-orthogonal transmission, thus yielding an FTN transmission technique. The FTN transmission breaks through the limitation of Nyquist rate by reducing the symbol transmission interval, has higher frequency spectrum efficiency and channel capacity compared with the traditional orthogonal system, but also introduces ISI, so that the FTN signal detection is more difficult, and the complexity of a receiver is greatly improved. Meanwhile, logic and storage resources in the FPGA chip are limited, so that certain technical difficulties still exist in realizing the super-Nyquist transmission on the FPGA.
Since the FTN theory is proposed, new equalization algorithms suitable for the FTN system are proposed, such as a truncated viterbi algorithm, an Ungerboeck observation model-based M-BCJR algorithm, a successive interference cancellation algorithm, a weighting factor graph-based Turbo equalization algorithm, and the like, which reduce complexity or improve bit error rate performance to some extent, but are still not easy to implement in hardware. To solve the problem of large equalization calculation amount, sugiura et al in japan proposes a scheme of applying a frequency domain equalization technique to an FTN transmission system, truncates ISI introduced by FTN by adding a cyclic prefix, calculates a frequency domain equalization coefficient by using an MMSE criterion, can effectively reduce calculation amount, and is very easy to implement hardware. However, when the equalization coefficient is calculated, only ISI introduced by the FTN is considered and influence of an actual channel is not considered, so that the error code performance is poor, and a good error code rate can be obtained by additional channel coding.
In the same year, Ganhao et al introduced an Iterative Block Decision Feedback Equalizer (IBDFE) into the FTN transmission system, which algorithm demapped the symbols during each iteration, thereby calculating and simultaneously updating the filter coefficients and the feedback compensation amount for the next iteration. This approach significantly improves the bit error rate performance of the receiver but also increases the complexity of the system. After that, xu yang et al propose a simplified IBDFE algorithm on this basis, introduce the variance of the symbol in error of decision by considering the error relationship between the symbol after decision and the transmitted symbol, and artificially set the bit error rate and the optimal signal-to-noise ratio, thereby simplifying the calculation of the filter coefficient to a certain extent, but the distance is easy to implement by hardware and still has a certain gap.
Disclosure of Invention
The technical problem to be solved by the invention is as follows: the method and the system can effectively reduce the complexity while ensuring the performance, are easy to deploy in FPGA-based miniaturized equipment, improve the throughput of data processing through a parallel processing technology and meet the requirement of high speed.
The technical solution of the invention is as follows:
a high-speed FTN signal iterative equalization method based on FPGA comprises the following steps:
the data block is obtained by dividing an original symbol sequence to be sent according to every N symbols;
the cyclic prefix refers to adding the first 2v symbols of the data block to the end of the data block, so as to form a group of data with the length of N +2 v;
the data block r to be processed is parallel N-path data, and is processed by taking the parallel N-path data block as a unit in the subsequent step;
the iteration frequency l refers to the frequency of iteration processing in the subsequent steps, and the value of the iteration frequency l is more than 0;
step 3, performing N-point Fast Fourier Transform (FFT) on the data block R to obtain R;
step 4, judging the iteration number of the current processing process, and if the iteration number l is equal to 0, namely the first iteration, executing step 4.1; otherwise, if the iteration times l is more than 0, executing the step 4.2;
step 4.1, frequency domain equalization, namely performing frequency domain equalization on the data block R output in the step 3 according to the formula (1) to obtain Y:
Y＝R·W (1)
wherein W represents an equalization coefficient, and the element W (i) thereof is calculated by the following equations (2) to (5):
λ＝F(g 1 ) (3)
wherein N is 0 Representing the noise power, P the signal power, F (-) the Fourier transform, h s (t) and h r (t) representing FTN signal shaping filter coefficients and matched filter coefficients, respectively;
step 4.2, calculating a feedback compensation coefficient, and performing compensation correction on the data Y obtained in the step 4.1 after the frequency domain equalization in the first iteration according to the formula (6) to obtain U (l) ：
U (l) ＝Y+Z (l) (6)
Wherein, U (l) Representing the feedback compensated data block in the ith iteration,
representing the frequency domain version of the symbol sequence after remapping in the l-th iteration,
represents the compensation coefficient given by the feedback compensation coefficient calculation module in the 1 st iteration, and the element thereof
Can be calculated from the equations (6) to (8):
in the formula (I), the compound is shown in the specification,
representing the correlation coefficients of the decided symbol sequence and the original symbol sequence,
is the energy of the decided symbol sequence. In fact, the decision operation has been greatly reduced
Error from the original symbol sequence, thus taking into account
The practical significance of (a) is,
is far greater than
Therefore, the method is simplified according to the following formula, and the resource consumption of complex division is reduced:
Step 6, judging whether the current process finishes iteration, namely whether the iteration times reach a preset value, and outputting u if the iteration is finished (l) Is the final result after iterative equalization; otherwise, the current iteration times l is added with 1 and is obtained after remapping
The remapping refers to remapping a bit sequence obtained after the symbol sequence is subjected to hard decision into a symbol sequence according to the modulation mode of the bit sequence;
after remapping
Performing FFT to obtain
And step 4 is re-executed.
A system for realizing high-speed FTN signal iterative equalization based on FPGA comprises a preprocessing module, a parallel FFT computing unit, a frequency domain equalization module, a parallel complex multiplication computing unit, a data cache module, a parallel IFFT computing module, a feedback compensation parameter computing module, a remapping module and an output module;
the preprocessing module is used for preprocessing an input symbol sequence of the high-speed FTN signal iterative equalization system, performing serial-parallel conversion on each group of data with the length of N +2v, and removing cyclic prefixes of v symbols before and after each group of data to obtain parallel N paths of data blocks r to be processed. In addition, in order to meet the requirements of processing in the subsequent modules, a tag needs to be constructed for the data block r. The binary format of the tag is [ b ] 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 ]Wherein [ b ] 2 b 1 b 0 ]Representing the current number of iterations of the data block, is set to [000 ] in the pre-processing module]And represents the 0 th iteration. [ b ] a 5 b 4 b 3 ]The label indicating the data block is used for distinguishing different data blocks, and the data block can be used as an address to cache in a subsequent module; the identification is updated in the preprocessing module with a counter, i.e. for each prepared data block to be processed b 5 b 4 b 3 ]Plus 1. [ b ] a 7 b 6 ]For marking the data flow direction in the system, the value is set to [00 ] in the preprocessing module]. The preprocessing module transfers the data block r and the label thereof as output to the parallel FFT computing unit. Finally, in order to meet the requirement of pipeline processing of the system, the preprocessing module also needs to provide a uniform driving enable for the rest of the system so as to ensure the coordinated stepping among the modules of the system.
The parallel FFT computing unit is used for meeting the requirement of the system for executing parallel FFT computation in a multiplexing mode and consists of an FFT multiplexer, an N-path parallel FFT calculator and an FFT result distributor. The FFT multiplexer monitors FFT calculation calling requests from the preprocessing module, the parallel IFFT calculation module and the remapping module and transmits the requests to the FFT calculator through a data bus; the FFT calculator adopts a base-2 algorithm to complete specific FFT calculation, and transmits a calculation result to the FFT result distributor; FFT result allocator pass check [ b 7 b 6 ]To determine the data source and flow direction, so as to output the FFT calculation result to the parallel IFFT calculation module,A parallel complex multiplication unit or a feedback compensation parameter calculation module.
The frequency domain equalization module receives the input data block R from the parallel FFT computing unit and calls the parallel complex multiplication unit to execute the computation of the formula (1). The frequency domain equalization coefficient W obtained by the formula (2) - (5) is stored in the module, and after the data block R is received, the frequency domain equalization coefficient W and the frequency domain equalization coefficient W are output to the parallel complex multiplication unit.
The parallel complex multiplication computing unit is used for meeting the requirement of a system for executing parallel complex multiplication computation in a multiplexing mode, and is similar to the parallel FFT computing unit, and the unit is composed of a complex multiplication multiplexer, an N-path parallel complex multiplication calculator and a multiplication result distributor. The complex multiplication multiplexer monitors a complex multiplication calculation call request from the frequency domain equalization module and the feedback compensation parameter calculation module and transmits the call request to the N paths of parallel complex multipliers through a data bus; n paths of parallel complex multipliers complete specific complex multiplication calculation; multiply result allocator pass check [ b 7 b 6 ]To determine the data source and flow direction, so as to output the complex multiplication result to the data buffer module or the feedback compensation parameter calculation module.
The data cache module is used for caching data needed in an iterative process by packaging an RAM (random access memory), and specifically, the module judges the iteration times [ b ] of an input data block label 2 b 1 b 0 ]If 0, i.e. the data block is the result Y of the frequency domain equalization obtained in the 0 th iteration, the data block is labeled with its label [ b ] 5 b 4 b 3 ]Buffered for address into RAM, otherwise labeled with input data block [ b ] 5 b 4 b 3 ]Taking the corresponding data from RAM for the address and adding it to the input data, the result U (l) And outputting the signals to a parallel IFFT calculation module.
The parallel IFFT computing module is configured to perform parallel IFFT computing on the input from the data caching module, and because the IFFT and the FFT have the same computing structure, the parallel IFFT computing is implemented by invoking the parallel FFT computing unit. Specifically, the parallel IFFT module pairs the input data blocks U (l) Taking and sharingThe data block is output to the parallel FFT computing unit after the yoke, and the label [ b ] of the data block is modified 7 b 6 ]To indicate its data source and flow direction. Finally, after receiving the calculation result returned by the parallel FFT calculation unit, the conjugate is taken again and the label is modified to be used as the output u (l) And the data is transmitted to a remapping module and an output module.
The feedback compensation elaboration calculation module is used for receiving the outputs from the parallel FFT calculation unit and the parallel complex multiplication unit and executing the formulas (6) to (8) to calculate the compensation parameters in each iteration process, and comprises a parallel real number multiplier, a parallel real number divider, a FIFO, a RAM, a parallel complex number divider and a multiplexer. Wherein, for the input from the parallel FFT computing unit, firstly, the label [ b ] is judged 2 b 1 b 0 ]If 0, the input data block is the FFT result R of the system input R, and the FFT result R is sent to a parallel complex divider to calculate R (n)/lambda (n) and the result is according to the label [ b ] 5 b 4 b 3 ]Storing in RAM; otherwise, the input data block is
The following three operations will be performed: passes to the multiplexer together with the results of the R (n)/lambda (n) calculations taken from the RAM to request invocation of the parallel complex multiplication unit calculation
Passes to the multiplexer along with its own conjugate to request invocation of parallel complex multiplication unit computations
According to its label [ b 5 b 4 b 3 ]Stored in the FIFO for use by subsequent processes. For the inputs from the parallel complex multiplication units are respectively
And
the average is calculated by a parallel real number multiplier and a parallel real number divider
While fetching from the FIFO in the previous iteration
And sent to the parameter calculation multiplexer together. Finally, the parameter calculation multiplexer will process the request and output the data to the parallel complex multiplication unit through the bus.
The remapping module is used for detecting the input data block u from the parallel IFFT computing module (l) Determining whether the iteration is finished, if not, adding 1 to the iteration number, and obtaining a bit sequence according to the modulation mode and then remapping the bit sequence into a symbol sequence
Otherwise, no operation is performed on the data block.
The output module is used for detecting the input data block u from the parallel IFFT calculation module (l) Determining whether the iteration is finished or not, if so, removing the label of the iteration, and simultaneously performing parallel-serial conversion to output a final high-speed FTN signal iteration equalization result; otherwise, the module does nothing.
Advantageous effects
1. By adopting a partitioned data structure and a simplified iterative equalization algorithm and through a separated feedforward and feedback structure, the complexity is obviously reduced while the system performance is ensured;
2. the processing speed and the throughput are improved through a parallel structure and a pipeline processing mode;
3. all the computing requirements in the system are integrated, the computing modules are realized by using uniform interfaces and architectures, and a large amount of hardware resources are saved by multiplexing the general computing modules.
4. The structure of the existing iterative equalization algorithm is changed, the original iterative updating process is separated into two parts of an independent feedforward loop and an independent feedback loop, and the iterative updating structure and complexity are simplified; the formula of the existing iterative equalization algorithm is reasonably approximated, so that the system performance is ensured, and the calculated amount is obviously reduced;
5. the processing speed and the throughput are improved through a parallel structure and a pipeline processing mode;
6. all the computing requirements in the device are integrated, each computing module is realized by using a uniform interface and architecture, and the same computing module is shared for the same computing process in all the steps in a time-sharing multiplexing mode, so that a large amount of hardware logic resources are saved.
Drawings
FIG. 1 is a flow chart of a high-speed FTN signal iterative equalization FPGA implementation method according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of an algorithm structure according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of a high-speed FTN signal iterative equalization system based on an FPGA according to an embodiment of the present invention;
FIG. 4 is a schematic structural diagram of an input pre-processing module according to an embodiment of the present invention;
fig. 5 is a schematic structural diagram of a feedback compensation parameter calculation module according to an embodiment of the present invention.
Detailed Description
In order to make the technical solutions better understood by those skilled in the art, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application.
The invention provides a high-speed FTN signal iterative equalization method based on FPGA and a realization device thereof, as shown in figure 1, the structure thereof comprises the following parts:
and a preprocessing module. The module is used for preprocessing an input symbol sequence, and comprises the steps of partitioning, removing cyclic prefix and adding an address label so as to meet the processing requirements of subsequent modules and steps.
And a parallel FFT computing unit. The unit consists of a multiplexer, a parallel FFT calculator and a distributor, and is used for performing parallel FFT conversion on input data in a mode of multiplexing hardware logic resources.
And a frequency domain equalization module. And realizing the frequency domain equalization of the data blocks.
A parallel complex multiplication unit. Similar to the FFT computation unit, a parallel N-way complex multiplication is implemented.
And a feedback compensation parameter calculation module. The function of the module is to calculate the feedback compensation coefficient of iterative equalization, wherein some complex multiplication calculation needs to use a complex multiplication unit.
And a data caching module. The module is used for caching data required in the subsequent iteration process.
And a remapping module. The module is used for carrying out hard decision on data which does not complete iteration according to the modulation mode of the data to obtain a bit sequence, then remapping the bit sequence into a symbol sequence and sending the symbol sequence to the next iteration process.
And an output module. The module is used for detecting whether the iteration times are reached or not and recovering the original data sequence to be output in a format.
The implementation device can be used for implementing high-speed FTN signal iterative equalization, and the modules can be implemented based on FPGA and connected through a uniform data interface. To better illustrate its working principle, implementation-specific parameters first need to be determined. The implementation structure of the high-speed nyquist system iteration balance is described in detail by taking the length N of the data block as 128, the length v of the cyclic prefix as 8, the number p of the input parallel paths as 8 and the iteration number l as 3 into consideration comprehensively for the bit error rate performance of the system and the hardware conditions such as clock frequency, logic resources and the like of the mainstream FPGA at present. It should be noted that the structural parameters in the present embodiment are merely preferred implementations, and the corresponding parameters may be adjusted according to specific application scenarios to achieve the intended efficacy and purpose.
The flow chart of the FPGA implementation method for iterative equalization of the high-speed FTN signal provided by the invention is shown in figure 2, the algorithm structure is shown in figure 3, and the FPGA implementation method comprises the following steps:
step one, preprocessing an input symbol sequence. A received parallel 8-way symbol sequence is shown in fig. 4, where each set of data includes a valid data symbol of length 128 and a cyclic prefix of length 16. It should be noted that, the subsequent process is performed with a data block with a length of 128, so that the input symbol sequence needs to be converted from serial to parallel and 8 symbols before and after the input symbol sequence are removed. Specifically, the preprocessing module and the subsequent module use the same clock signal, the serial-to-parallel conversion adopts a FIFO structure, and the parallel 8-way input data is buffered into the parallel 128-way data block every clock cycle under the condition that the data enable is effective, as shown in fig. 4. The assignment of the registers requires a delay of one clock cycle. Also, using a counter as a control, the counter value is incremented by 1 every clock cycle and reset every 18 clock cycles. When the counter accumulates to 17 th clock cycle, the data blocks of the 128 parallel paths are the valid data to be processed, the output data enable is set to be valid at the moment, and the output data enable is invalid at the rest of time.
Because the hardware implementation method provided by the invention adopts a pipeline processing mode, a plurality of unprocessed data blocks exist in the system at each moment. Also, there are many multiplexed logic resources and feedback loops in the implementation structure due to the iterative processing required. For the above two reasons, it is necessary to add a corresponding tag to each data block as a distinction and to be able to mark the number of iterations. Specifically, the format of the data block tag is [ b ] 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 ]Wherein:
[b 2 b 1 b 0 ]representing the current number of iterations of the data block, the value is set to [000 ] in the pre-processing module]And represents the 0 th iteration. [ b ] a 5 b 4 b 3 ]The identifier of the data block is represented, and the data block can be cached as an address in a subsequent module; the identification is updated in the preprocessing module with a counter, i.e. for each valid data block ready b 5 b 4 b 3 ]Plus 1. [ b ] a 7 b 6 ]For marking the data flow direction in the multiplexing module, the value is set to [00 ] in the preprocessing module]. It should be noted that the data block label will be as follows in the subsequent data processingThe setting needs to be modified; in addition, as can be seen from the introduction and analysis of the subsequent steps and modules, the tag format provided in the embodiment of the present invention can unambiguously and uniquely identify the data blocks of each stage in the system.
Finally, the preprocessing module needs to delay the input data enable by one clock cycle as the driving enable of the subsequent module. Because it is necessary to ensure that the multiplexing module does not have a plurality of valid data blocks colliding at any time when the input symbol sequence continuously enters the pipeline, it is necessary to strictly control the output delay of each module and ensure the cooperative stepping among the modules. Under the control of the unified drive enable, the delay between the modules is kept fixed, and the valid data is marked through the data enable.
In summary, the ports of all subsequent modules in the embodiments of the present invention are composed of a clock signal, a driving enable, and a plurality of input/output interfaces, where each input/output interface includes a data enable, a tag, and 128 parallel data.
And step two, frequency domain equalization. The data is first FFT transformed before frequency domain equalization. As shown in fig. 1, the output of the preprocessing module first enters the FFT multiplexer, which receives the inputs of the different modules and selects a set of valid inputs as outputs to be delivered to the bus according to the data enable of the input interface, which introduces a processing delay of 1 clock cycle. The data to be calculated will then be passed via the bus to the 128-point FFT calculation module. The FFT module adopts a radix-2-butterfly operation structure and is realized in a recursive mode, and the processing delay is 12 clock cycles. The data after completing FFT calculation will enter the distributor, which will be according to [ b ] of the label 7 b 6 ]The bits direct the data on the bus to different destination modules for subsequent processing, specifically [00 ]]Output from port 1, [01 ]]Output from port 2. It should be noted that the distributor is implemented by using combinational logic, and there is no processing delay. Multiplexing of the FFT computation modules is achieved by introducing multiplexers, distributors and utilizing bus connections.
Tag of data block [ b ] in feed forward frequency domain equalization stage 7 b 6 ]Is [0 ]0]The following calculation is performed by entering the multiplication module through port 1 of the distributor:
Y＝R·W (1)
wherein, the element W (i) of the equalization coefficient W can be calculated by the following formulas (2) to (5):
λ＝F(g 1 ) (3)
in the formula, N 0 Representing the noise power, P the signal power, F (-) the Fourier transform, h s (t) and h r (t) represents FTN shaping filter coefficients and matched filter coefficients, respectively. Since the feed forward frequency domain equalization coefficient is not updated during processing and can be pre-calculated, this coefficient can be stored directly in the distributor and output from port 1 together with the data block R. Obviously, the input interface of the complex multiplication unit needs to be widened by 128 data to satisfy the parallel entry of two multipliers.
Meanwhile, the complex multiplication unit has a similar structure to the FFT computation unit to realize a multiplexing function. Where the parallel multiplier performs parallel computations by calling 128 complex multiplicative IP-cores, with a processing delay of 1 clock cycle. Label b of data block Y after frequency domain equalization 7 b 6 ]Is still [00 ]]The distributor of the complex multiplication unit sends the output of the port 2 to the data buffer module.
And step three, calculating a feedback compensation coefficient, and compensating and correcting the received data. First, the data buffer module passes the input data block Z (l) The number of iterations of the label of (1) is judged:
is the first one0 iterations, i.e. l ═ b 2 b 1 b 0 ]＝[000]Then the input to the data buffer module is the result of the frequency domain equalization (i.e., Z) (l) Y), when Y is passed to the module output port and the number of iterations is increased by 1, i.e. U (l+1) Y; at the same time, Y is labeled according to its label [ b ] 5 b 4 b 3 ]As addresses, to be stored in RAM for use in subsequent iteration processes. And then skip subsequent content of this step.
If not, the data cache module will pass tag b 5 b 4 b 3 ]The data block Y after frequency domain equalization (i.e. iteration 0) is taken out from RAM and is processed according to U (l+1) ＝Y+Z (l) And (5) compensating and outputting. Wherein the content of the first and second substances,
representing the symbol sequence after the decision of the l-th iteration,
representing the compensation coefficient given by the feedback compensation coefficient calculation module in the first iteration, the elements of which
Can be calculated from the equations (6) to (8):
in the formula (I), the compound is shown in the specification,
representing a decided symbol sequence and an original symbol sequenceThe correlation coefficient of (a) is calculated,
is the energy of the decided symbol sequence.
In the course of the specific implementation,
the feedback compensation parameter is obtained through a feedback compensation parameter calculation module. As shown in fig. 1, two input ports of the feedback compensation parameter calculating module are respectively connected to the output port 1 of the FFT calculating unit distributor and the output port 2 of the complex multiplication unit distributor, and one output port is connected to the input of the complex multiplication unit multiplexer.
Specifically, as shown in fig. 5, the feedback compensation parameter calculation module first determines the number of iterations for the data block from port 1 of the FFT distributor through the tag to distinguish between R and R
In the frequency domain equalization stage, the original data block R which is subjected to FFT conversion is sent to an 8-path parallel complex divider to be executed (7)
And (4) calculating. It should be noted that the complex divider consumes a large amount of hardware resources, and cannot realize high-parallelism computation. But the result of this calculation is not used in the next iteration and each data block R is calculated only once, which allows for a relatively sufficient processing delay for the calculation, which can be done over a period of time with a small number of parallel dividers. In summary, in the embodiment of the present invention, the 8-channel parallel complex divider is adopted to sequentially calculate the 128-channel data blocks, and the processing process occupies 16 clock cycles of the divider and is not greater than the effective data output cycle of the preprocessing module, so that no conflict is caused. The parallel complex divider implementation is shown in fig. 5, and the total processing delay is 18 clock cycles by adding the input and output assignment process. Data for performing division calculations
Will be stored as addresses in RAM by tag for use in subsequent iterations.
In the iteration stage, the last iteration result
The following three operations will be performed:
(1) and taken out of RAM
Output together;
(2) after delaying 2 clock cycles, outputting the result which is conjugated with the delay time;
(3) and storing the data into the FIFO for use by subsequent processes.
The output of the above operation will modify the data Block tag [ b ] 7 b 6 ]Is [01 ]]Then, the complex multiplication unit is fed to perform the calculation of the formula (7) and the formula (8). The distributor of complex multiplication unit distinguishes the label [ b ] 7 b 6 ]The calculation result is sent back to the feedback compensation parameter calculation module through the port 2. It should be noted that, by delaying operation (2) for two clock cycles, the calculation result output from port 1 occupies 2 consecutive clock cycles, and the former is
The latter is
This simplifies the control logic. The feedback compensation parameter calculation module receives the feedback compensation parameter firstly
Thereafter, a 128-way parallel multiplication computation in equation (9) is performed because the set of multipliers for the computation is fixed and the processing delay is 1 clock cycle, the result of which is exactly the same as
Simultaneously send into 32 parallel pathsThe real number divider performs division calculation in the formula (9) to obtain compensation coefficient
The 32-way parallel real divider and the 8-way parallel complex divider have the same structure, and the processing delay is 6 clock cycles. In addition, it outputs read control signal to fetch from FIFO
And
output to the complex multiplication unit together to calculate the compensation quantity Z (l) And is sent to the data buffer module through the distributor port 1.
Step four, compensating the data block U (l+1) And sending the signal to an IFFT module for inverse fast Fourier transform. The FFT has the same calculation structure as the IFFT according to the characteristics of the fast fourier transform, i.e., x (N) ═ conj (FFT (conj (x (k)))/N. Therefore, in the specific implementation process, the IFFT module can receive the received data U (l+1) Taking the conjugate and modifying the tag [ b ] 7 b 6 ]Is [01 ]]And then sent to an FFT calculating unit for calculation. The calculation result is sent back to the IFFT module again through the port 2 of the FFT calculation unit distributor, and then the conjugate is taken to obtain the inverse transformed data u (l+1) And output to decision module and output module, while recovering label [ b ] 7 b 6 ]Is [00 ]]. It should be noted that the IFFT module is implemented by combinational logic, and there is no processing delay. In this way, the FFT and the IFFT share the same calculation module, and a large amount of hardware resources are saved.
Step five, the output module and the judgment module can judge the current data block u (l+1) Whether the number of iterations is greater than the expected number of iterations:
if the number of the data blocks is larger than the preset number, the output module executes the operation opposite to that of the input preprocessing module, namely label removal and parallel-serial conversion, and finally the data blocks quit iteration and output detection symbol sequences; the decision block does not take any action.
If not, the output module does not take any operation; the decision module divides the data block u into two (l+1) Making hard decision and remapping it into data block s (l+1) And sending the signal to an FFT module for calculation to obtain
And continuing to execute the third step and carrying out next iteration.
It should be noted that, in order to ensure that the input bus of the multiplexing module does not have data collision (i.e. a plurality of data blocks occupy one bus at the same time), taking a data block as an example, it must ensure that the output cycle (18 in this embodiment) of the preprocessing module is not repeated at all times that the data block occupies each bus during the complete iteration process. For example, assuming that a certain data block is output from the preprocessing module at the 0 th time, it will occupy the bus of the FFT computation unit at the 1 st, 18 th, 32 th, 65 th, 79 th, and 112 th times, and therefore, in one iteration cycle, the bus will be occupied at the times of (1,18,32,65,79,112) mod 18 being (1,0,14,11,7,4), and there is no collision. Other buses are similar. If a conflict occurs, the processing delay of each module needs to be properly adjusted to satisfy the above condition, and specifically, the processing delay of the ip core may be adjusted by adding a register buffer or changing.
Therefore, the FPGA hardware realization of the high-speed FTN signal iterative equalization is completed, and the invention has the advantages that: by adopting a partitioned data structure and an iterative equalization algorithm and separating a feedforward structure and a feedback structure, the complexity is obviously reduced while the system performance is ensured; the processing speed and the throughput are improved through a parallel structure and a pipeline processing mode; all the computing requirements in the system are integrated, each computing module is realized by using a uniform interface and a uniform framework, and a large amount of hardware resources are saved in a multiplexing mode.
In summary, although the embodiments of the present invention have been described with reference to specific structural parameters and accompanying drawings, the scope of the present invention is not limited thereto. For those skilled in the art, without departing from the principle and idea of the present invention, several modifications of the structure parameters may be made in combination with specific application scenarios, which should also be considered as falling within the protection scope of the present invention.
Claims (10)
1. A high-speed FTN signal iterative equalization method based on FPGA is characterized by comprising the following steps:
step 1, grouping original symbol sequences to be sent and then sending the symbol sequences, wherein each group of data comprises a data block with the length of N and a cyclic prefix with the length of 2 v;
step 2, preprocessing the received symbol sequence, removing cyclic prefixes of v symbols before and after each group of data, performing serial-parallel conversion to obtain a data block r to be processed, and finally initializing the iteration number l of the data block to be 0;
step 3, performing N-point fast Fourier transform on the data block R to obtain R;
step 4, judging the iteration number of the current processing process, and if the iteration number l is equal to 0, namely the first iteration, executing step 4.1; otherwise, if the iteration times l is more than 0, executing the step 4.2;
step 4.1, frequency domain equalization, namely performing frequency domain equalization on the data block R output in the step 3 according to the formula (1) to obtain Y:
Y＝R·W (1)
wherein W represents an equalization coefficient, and the element W (i) thereof is calculated by the following equations (2) to (5):
λ＝F(g 1 ) (3)
wherein, N 0 Representing noise power, P representsSignal power, F (-) represents Fourier transform, h s (t) and h r (t) representing FTN signal shaping filter coefficients and matched filter coefficients, respectively;
step 4.2, calculating a feedback compensation coefficient, and compensating and correcting the data Y after the frequency domain equalization in the first iteration obtained in the step 4.1 according to the formula (6) to obtain U (l) ：
U (l) ＝Y+Z (l) (6)
Wherein, U (l) Representing the feedback compensated data block in the ith iteration,
representing the frequency domain version of the symbol sequence after remapping in the l-th iteration,
represents the compensation coefficient given by the feedback compensation coefficient calculation module in the 1 st iteration, and the element thereof
Can be calculated from the equations (7) to (9):
in the formula (I), the compound is shown in the specification,
representing the correlation coefficients of the decided symbol sequence and the original symbol sequence,
is the energy of the symbol sequence after the decision;
step 5, for U (l) Fast inverse Fourier transform is carried out to obtain u (l) ；
Step 6, judging whether the current process finishes iteration, namely whether the iteration times reach a preset value, and outputting u if the iteration is finished (l) Is the final result after iterative equalization; otherwise, adding 1 to the current iteration number l and obtaining the current iteration number after remapping
2. The high-speed FTN signal iterative equalization method based on FPGA according to claim 1, characterized in that:
in the step 1, the data block is obtained by dividing the original symbol sequence to be sent according to every N symbols; the cyclic prefix refers to a group of data having a length of N +2v, which is formed by adding the first 2v symbols of a data block to the end of the data block.
3. The FPGA-based high-speed FTN signal iterative equalization method according to claim 2, characterized in that:
in step 2, the data block r to be processed is parallel N-way data.
4. The FPGA-based high-speed FTN signal iterative equalization method of claim 3, characterized in that:
in the step 5, in the 0 th iteration process, U (0) Obtained directly from the frequency domain equalization of step 4.1, i.e. U (0) ＝Y。
5. The high-speed FTN signal iterative equalization method based on FPGA according to claim 4, characterized in that:
in the step 6, the remapping refers to remapping the bit sequence obtained by performing hard decision on the symbol sequence into the symbol sequence according to the modulation mode of the bit sequence.
6. The FPGA-based high-speed FTN signal iterative equalization method according to any one of claims 1-5, characterized in that:
after remapping
Performing FFT to obtain
And step 4 is re-executed.
7. A system for realizing high-speed FTN signal iterative equalization based on FPGA is characterized in that: the system comprises a preprocessing module, a parallel FFT (fast Fourier transform) computing unit, a frequency domain balancing module, a parallel complex multiplication computing unit, a data caching module, a parallel IFFT (inverse fast Fourier transform) computing module, a feedback compensation parameter computing module, a remapping module and an output module;
the preprocessing module is used for preprocessing an input symbol sequence of the high-speed FTN signal iterative equalization system, performing serial-parallel conversion on each group of data with the length of N +2v, and removing cyclic prefixes of v symbols before and after each group of data to obtain parallel N paths of data blocks r to be processed;
the parallel FFT computing unit comprises an FFT multiplexer, an N-path parallel FFT calculator and an FFT result distributor, wherein the FFT multiplexer monitors FFT computing calling requests from the preprocessing module, the parallel IFFT computing module and the remapping module and transmits the requests to the FFT calculator through a data bus; the FFT calculator adopts a base-2 algorithm to complete specific FFT calculation, and transmits a calculation result to the FFT result distributor; FFT result allocator pass check [ b 7 b 6 ]To determine the data source and flow direction, so as to output the FFT calculation result to the parallel IThe FFT calculation module, the parallel complex multiplication unit or the feedback compensation parameter calculation module;
the frequency domain equalization module receives an input data block R from the parallel FFT computing unit and calls the parallel complex multiplication unit to perform the computation of the formula (1), the frequency domain equalization coefficient W obtained by the pre-computation of the formulas (2) to (5) is stored in the frequency domain equalization module, and the frequency domain equalization coefficient W are output to the parallel complex multiplication computing unit after the data block R is received;
the parallel complex multiplication computing unit comprises a complex multiplication multiplexer, an N-path parallel complex multiplication calculator and a multiplication result distributor, wherein the complex multiplication multiplexer monitors complex multiplication computing call requests from the frequency domain balancing module and the feedback compensation parameter computing module and transmits the complex multiplication computing call requests to the N-path parallel complex multiplication units through a data bus; n paths of parallel complex multipliers complete specific complex multiplication calculation; multiply result allocator pass check [ b 7 b 6 ]To determine the data source and flow direction, so as to output the complex multiplication result to the data buffer module or the feedback compensation parameter calculation module;
the data caching module is used for caching data required in the iterative process through packaging an RAM;
the parallel IFFT calculation module is used for performing parallel IFFT calculation on the input from the data caching module;
the feedback compensation parameter calculation module is used for receiving the output from the parallel FFT calculation unit and the parallel complex multiplication unit and executing the formulas (6) to (8) to calculate the compensation parameter in each iteration process, the module comprises a parallel real number multiplier, a parallel real number divider, a FIFO, a RAM, a parallel complex number divider and a parameter calculation multiplexer, and for the input from the parallel FFT calculation unit, firstly, the label [ b ] of the input is judged by judging the label [ b ] of the input 2 b 1 b 0 ]If 0, the input data block is the FFT result R of the system input R, and the FFT result R is sent to a parallel complex divider to calculate R (n)/lambda (n) and the result is according to the label [ b ] 5 b 4 b 3 ]Storing in a RAM; otherwise, the input data block is
The following three operations will be performed: passes to the multiplexer together with the results of the R (n)/lambda (n) calculations taken from the RAM to request invocation of the parallel complex multiplication unit calculation
Passes to the multiplexer along with its own conjugate to request invocation of parallel complex multiplication unit computations
According to its label [ b 5 b 4 b 3 ]Stored in FIFO, for inputs from parallel complex multiplication units respectively
And
after averaging, the average value is calculated by a parallel real number multiplier and a parallel real number divider
While fetching from the FIFO in the previous iteration
And sending the data to a parameter calculation multiplexer, and finally, outputting the processing request to a parallel complex multiplication unit by the parameter calculation multiplexer through a bus;
the remapping module is used for detecting the input data block u from the parallel IFFT computing module (l) Determining whether the iteration is finished, if not, adding 1 to the iteration number, and obtaining a bit sequence according to the modulation mode and then remapping the bit sequence into a symbol sequence
Otherwise, no operation is carried out on the data block;
the output module is used for detecting the input data block u from the parallel IFFT calculation module (l) Determining whether the iteration is finished or not, if so, removing the label of the iteration, and simultaneously performing parallel-serial conversion to output a final high-speed FTN signal iteration equalization result; otherwise, the module does nothing.
8. The FPGA-based high-speed FTN signal iterative equalization system of claim 7, further comprising:
the preprocessing module also constructs a label for the data block r, and the binary format of the label is [ b ] 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 ]Wherein, [ b ] 2 b 1 b 0 ]Representing the current number of iterations of the data block, is set to [000 ] in the pre-processing module]Represents the 0 th iteration, [ b ] 5 b 4 b 3 ]The reference numbers representing the data blocks are used to distinguish the different data blocks, and the identification is updated in the preprocessing module by means of a counter, i.e. for each data block to be processed [ b ] every time a data block is ready 5 b 4 b 3 ]Plus 1, [ b ] is added to the value of 7 b 6 ]For marking the data flow direction in the system, the value is set to [00 ] in the preprocessing module]And finally, the preprocessing module also needs to provide a uniform driving enable for the rest parts of the system so as to ensure the coordination stepping among all the modules of the system.
9. The FPGA-based high-speed FTN signal iterative equalization system of claim 7 or 8, characterized in that:
the data cache module judges the iteration times [ b ] of the input data block label through the packaging RAM 2 b 1 b 0 ]If it is 0, i.e. the data block is the result Y of the frequency domain equalization obtained in the 0 th iteration, the data block is labeled with its label b 5 b 4 b 3 ]Buffer address toIn RAM, otherwise labeled with input data block [ b ] 5 b 4 b 3 ]For the address-taking of the corresponding data from the RAM and adding the input data, the result U (l) And outputting the signals to a parallel IFFT calculation module.
10. The FPGA-based high-speed FTN signal iterative equalization system of claim 7 or 8, characterized in that:
the parallel IFFT computing module is used for inputting a data block U (l) The conjugate is taken and output to a parallel FFT computing unit, and meanwhile, the label [ b ] of the data block needs to be modified 7 b 6 ]To indicate the data source and flow direction, and finally, after receiving the calculation result returned by the parallel FFT calculation unit, taking conjugation again and modifying the label as output u (l) And the data is transmitted to a remapping module and an output module.
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