CN107623926A - Communication means, server and base station equipment - Google Patents

Abstract

Embodiment of the disclosure is related to communication means, server and base station equipment.Propose a kind of centralization processing scheme based on high-speed treating apparatus and general processor.The program is implemented the processing of part physical layer by high-speed treating apparatus, and other physical layer process are implemented by general processor, improve calculating performance, reduce time delay.In addition, it is also proposed that a kind of base station migration scheme based on label.The program adds label in wireless packet, so as to the Hold sticker in physical layer process, consequently facilitating base station migrates, improves the efficiency of centralization processing.

Description

Communication means, server and base station equipment

Technical field

Embodiment of the disclosure is related to the communications field, and relates more specifically to communication means, server and base station equipment.

Background technology

Base station centralization treatment technology is an important wireless communication technology, and it can be brought with low cost, high band The communication of the performances such as wide and low time delay optimization.For example, beyond the clouds in the cordless communication network of wireless access network (RAN) framework, Such as radio-frequency apparatus of remote radio head (RRH) and physical layer (layer 1) equipment can be placed on distal end, these remote equipments after And it is connected by cable, optical cable etc. with Base Band Unit (BBU) pond.By BBU ponds, the BBU of different base station can be concentrated Change management.On the one hand, this maintenance cost for greatling save base station equipment.On the other hand, in BBU ponds, the BBU of different base station Between can carry out high bandwidth and the data transfer of low time delay, this results in the gain in terms of bandwidth and time delay.

In the centralization computing resource pond in such as BBU ponds, more machines can be included, every machine can have multiple Processor, each processor can have multiple cores (core, also referred to as kernel).In order to save the cost of implementation of base station, also carry Base station virtualization technology is gone out.

The content of the invention

In general, embodiment of the disclosure proposes the physical layer process based on high-speed treating apparatus and general processor Method and corresponding equipment, and the method and apparatus of the resource management based on label.

In a first aspect, embodiment of the disclosure provides a kind of communication means.The communication means includes：With base station phase At the server cluster of association, the packet from base station is received；Performed by the high-speed treating apparatus of server cluster for packet The processing of continuous processing level in physical layer process chain；And point through processing is sent to the general processor of server cluster Group, to perform further processing by general processor.

In second aspect, embodiment of the disclosure provides a kind of communication means.The communication means includes：Receive come from The packet of the general processor of the associated server cluster in base station, wherein general processor perform physical layer process for packet The processing of continuous processing level in chain；Performed by the high-speed treating apparatus of server cluster for packet in physical layer process chain The processing of remaining continuous processing level；And send the packet through processing to base station.

In the third aspect, embodiment of the disclosure provides a kind of communication means.The communication means includes：With base station phase At the server cluster of association, the packet from base station is received, packet includes indicating multiple processing included by server cluster The label of a process block in block；And by packet distribution to the process block indicated by label；And by process block to packet Perform physical layer process.

In fourth aspect, embodiment of the disclosure provides a kind of communication means.The communication means includes：With base station phase At the server cluster of association, the packet from the general processor included by server cluster is received；Label is added to packet, The cell that label instruction packet is sent to；Physical layer process is performed to packet by high-speed treating apparatus；And by packet transmission To base station to be sent to terminal device.

At the 5th aspect, embodiment of the disclosure provides a kind of communication means.The communication means includes：Connect in base station Receive the first data from terminal device；Label is added to the first data to form the first packet, and the packet of label instruction first is treated Send the first process block in the destination server and destination server in the server cluster associated with base station extremely；And By the first packet transmission to the first process block.

At the 6th aspect, embodiment of the disclosure provides a kind of server.The server is included at least one high speed Equipment is managed, is configured as：Receive the packet from base station；The place of the continuous processing level in physical layer process chain is performed for packet Reason；And the packet through processing is sent to the general processor of server, to perform further processing by general processor.

At the 7th aspect, embodiment of the disclosure provides a kind of server.The server is included at least one high speed Equipment is managed, is configured as：The packet of the general processor from server is received, wherein general processor performs thing for packet Manage the processing of the continuous processing level in layer process chain；The place of the remaining continuous processing level in physical layer process chain is performed for packet Reason；And send the packet through processing to base station.

In eighth aspect, embodiment of the disclosure provides a kind of server.The server includes：At at least one high speed Equipment is managed, is configured as：The packet from base station is received, packet includes more included by least one high-speed treating apparatus of instruction The label of a process block in individual process block；And by packet distribution to the process block indicated by label；And by process block Physical layer process is performed to packet.

At the 9th aspect, embodiment of the disclosure provides a kind of server.The server includes：At at least one high speed Equipment is managed, is configured as：Receive the packet from the general processor included by server；Label is added to packet, label refers to Show the cell that packet is sent to；Physical layer process is performed to packet；And base station is sent the packet to be sent to terminal Equipment.

At the tenth aspect, embodiment of the disclosure provides a kind of base station equipment.The base station equipment includes：Radio-frequency module, It is configured as：Receive the first data from terminal device；Label is added to the first data to form the first packet, label instruction In destination server and destination server in the server cluster associated with base station equipment that first packet is sent to First process block；And by the first packet transmission to the first process block.

It is their specific realities below in order to which simplified form introduces the selection to concept to provide Summary Applying in mode to be further described.Summary is not intended to identify the key feature or principal character of the disclosure, is also not intended to Limit the scope of the present disclosure.

Brief description of the drawings

Disclosure exemplary embodiment is described in more detail in conjunction with the accompanying drawings, the disclosure above-mentioned and other Purpose, feature and advantage will be apparent, wherein, in disclosure exemplary embodiment, identical reference number is usual Represent same parts.

Fig. 1 shows the example context that can implement embodiment of the disclosure；

Fig. 2 shows the block diagram of Long Term Evolution (LTE) uplink processing flow according to prior art；

Fig. 3 shows the block diagram of the LTE downlink handling processes according to prior art；

Fig. 4 show in accordance with an embodiment of the present disclosure frame is focused on based on high-speed treating apparatus and general processor The block diagram of structure；

Fig. 5 shows the block diagram of uplink processing flow in accordance with an embodiment of the present disclosure；

Fig. 6 shows the flow chart of communication means in accordance with an embodiment of the present disclosure；

Fig. 7 shows the flow chart of communication means in accordance with an embodiment of the present disclosure；

Fig. 8 shows the block diagram of the server cluster for resource management according to prior art；

Fig. 9 shows the frame format of the communication protocol based on label in accordance with an embodiment of the present disclosure；

Figure 10 shows the block diagram of the basic framework of FPGA in accordance with an embodiment of the present disclosure；

Figure 11 shows the block diagram of the framework of packet switch in accordance with an embodiment of the present disclosure；

Figure 12 shows the flow chart of communication means in accordance with an embodiment of the present disclosure；

Figure 13 shows the flow chart of communication means in accordance with an embodiment of the present disclosure；

Figure 14 shows the flow chart of communication means in accordance with an embodiment of the present disclosure；

Figure 15 shows the block diagram of server in accordance with an embodiment of the present disclosure；

Figure 16 shows the block diagram of server in accordance with an embodiment of the present disclosure；

Figure 17 shows the block diagram of server in accordance with an embodiment of the present disclosure；

Figure 18 shows the block diagram of server in accordance with an embodiment of the present disclosure；And

Figure 19 shows the block diagram of base station equipment in accordance with an embodiment of the present disclosure.

Embodiment

The principle of the disclosure is described referring now to some example embodiments.It should be appreciated that these embodiments are described only It is in order that those skilled in the art better understood when and then realize the disclosure, and not limit the disclosure in any way Scope.

Term " terminal device " as used herein is to refer to any terminal device with base station communication.As an example, eventually End equipment can include mobile terminal (MT), subscriber stations (SS), portable subscriber platform (PSS), mobile station (MS) or access eventually Hold (AT).

Term " comprising " as used herein and its deformation are that opening includes, i.e., " include but is not limited to ".Term "based" It is " being based at least partially on ".Term " one embodiment " expression " at least one embodiment "；Term " another embodiment " represents " at least one further embodiment ".The related definition of other terms provides in will be described below.

Fig. 1 shows the communication network 100 that can implement embodiment of the disclosure.Communication network 100 shown in Fig. 1 can be with Including server cluster 102 and base station 104.Base station 104 includes antenna 106 and radio-frequency module 108.It should be appreciated that shown in Fig. 1 The number of base station and server has no intention to limit merely for the sake of illustration purpose.In actual applications, there may be any An appropriate number of base station and server.

Communication between base station 104 and terminal device (not shown) can be implemented according to any appropriate communication protocol, Including but not limited to, the first generation (1G), the second generation (2.5G), the third generation (3G), forth generation (4G) communication protocol, the 5th generation (5G) Communication protocol and/or any other agreement for being currently known or developing in the future.

Base station 104 and terminal device (not shown) can use any appropriate wireless communication technology, include but is not limited to, code Divide multiple access (CDMA), frequency division multiple access (FDMA), time division multiple acess (TDMA), FDD (FDD), time division duplex (TDD), multi input Multi output (MIMO), OFDM (OFDM), and/or any other technology for being currently known or developing in the future.

As shown in figure 1, base station 104 is associated with server cluster 102.For example, base station 104 can pass through cable, optical fiber Communicated to connect Deng with server cluster 102.In centralization processing framework, base station 104 is referred to as Remote Radio Unit (RRU), server cluster 102 is referred to as Base Band Unit (BBU) pond.It is logical between base station 104 and server cluster 104 Letter is properly termed as forward pass (fronthaul).It will be understood that base station 104 and server cluster 102 can realize traditional base on the whole The function of standing.Term " traditional base station " as used herein can represent node B (NodeB or NB), enode b (eNodeB Or eNB), femto base station, the low power nodes of femto base station etc..Accordingly, it should be understood that the disclosure is not being departed from In the case of principle, term used herein " server " and " machine " can exchange, and " BBU ponds " and " server set Group " can also exchange.

In the last few years, the development of general processor was very fast.Such as multi -CPU, multi-core, single-instruction multiple-data stream (SIMD) (SIMD) development of the technology such as caching makes it possible to handle on a serviced device more and on the chip of Large Copacity Individual wireless stack.One advantage of general processor is backwards compatibility, it is ensured that software operates in newly without any change can On the processor of a generation.This smooth upgrade to wireless stack is highly profitable.

Another advantage of general processor is to support virtualization technology.Virtualization technology allows multiple virtual machines (VM) simultaneously Allow on identical physical machine.That is, virtual base station is isolated from each other and easily supports multi-standard to operate on an open platform. Based on context, term " base station " can also refer to this virtual base station.

Due to reasons such as frameworks, although general processor is good at the operation such as scheduling very much, and it is bad to calculate.On the contrary, The specialized hardware processing equipment of field programmable gate array (FPGA) etc is a kind of equipment for being good at calculating, and with relatively low Energy consumption.Therefore, if FPGA combined with general processor, the advantages of respective is made full use of, then can more thing uses up it With, substantially improving performance, reduction system power, and reduce communication delay.

In radio access network, many physical layer process algorithms are computation-intensives.By taking LTE as an example, Turbo decodings It is adapted to FFT/IFFT processing by FPGA processing, and some functions are particularly suitable for being handled by general processor, such as MAC scheduling is calculated Method.Fig. 2 and Fig. 3 respectively illustrates each process level of the up handling processes 200 of LTE and LTE downlink processings flow 300 (stage)。

As shown in Fig. 2 in LTE is up, the packet from radio-frequency module 108 is sent to MAC layer by physical layer process 220, by MAC layer 220, these are further handled.Physical layer process is a kind of chain structure, thus referred to as physical layer process chain or Signal processing chain, process chain (chain) can also be referred to as.As shown in Fig. 2 physical layer process chain up LTE can include Fast Fourier Transform (FFT) (FFT) 206, channel estimation and signal to noise ratio (SNR) estimation 206, equilibrium 210, discrete Fourier transform are inverse Convert (IDFT) 212, demapping 214, Turbo decodings 216 and CRC (CRC) 218.These process levels it is detailed in Appearance is well known in the art, thus is repeated no more.In these process levels, FFT 206, IDFT 212 and Turbo decodings 216 belong to the process level of computation-intensive.

As shown in figure 3, in LTE is descending, the packet from MAC layer 220 is sent to radio-frequency module by physical layer process 108, to be sent to terminal device.Encoded as shown in Fig. 2 physical layer process chain descending LTE can include CRC 306, Turbo 308th, interweave 310, scrambling 312, modulation 314, precoding 316, resource element mapping (RE- mappings) and reference signal insertion (RS Insertion) 318, Fast Fourier Transform (FFT) inverse transformation/cyclic prefix insertion (IFFT/CP) 320.The detailed content of these process levels exists It is known in the art, thus repeats no more.In these process levels, only IFFT/CP 320 belongs to computation-intensive Process level.

It will be appreciated that though describe process chain mainly in combination with LTE herein, the inventive concept of the disclosure can apply to existing Or other communication protocols of exploitation in the future, the disclosure is not limited in this respect.

Because FPGA has higher performance in the case of specific energy consumption, general processor and FPGA combination can be real Now higher performance, lower power consumption and more preferable compatibility.In systems in practice, the physical layer process of computation-intensive can be with It can be completed by FPGA processing, MAC layer etc. by general processor.It is explained in more detail below.

Existing fpga chip can support the physical layer process of up to 6 LTE cells, and an x86CPU core can To support the MAC layer of two cells to handle.Therefore, x86 server with multiple core cpus and a FPGA card can be with Support the wireless stack of multiple cells.With more FPGA cards are inserted, a server can support more cells.

It should be noted that although embodiment of the disclosure describes mainly in combination with FPGA, but it is to be understood that this is only example Property and be not intended to be in any way limiting the scope of the present disclosure.It is any with FPGA with identical or approximate processing characteristic Equipment alternative FPGA or used in combination realizes embodiment of the disclosure.In embodiment of the disclosure, these set It is standby to be properly termed as " high-speed treating apparatus ".

Fig. 4 shows the wireless access planar network architecture 400 based on FPGA and general processor in accordance with an embodiment of the present disclosure Schematic diagram.The framework 400 includes radio-frequency module 108, and it is communicated by server 418 with core net 420.It should be appreciated that to the greatest extent Pipe illustrate only a server 418 in Fig. 4, but shown number has no intention to limit merely for the sake of illustration purpose. In server cluster 102, there may be any an appropriate number of server 418.Can be with the mainboard (not shown) of server 418 Any an appropriate number of processor is installed, each processor there can be any an appropriate number of core, and each core can be with With any an appropriate number of thread.In the example of fig. 4, for purposes of clarity, a processor 414 is illustrate only, its Including 8 cores, i.e. core -0 to core -7.

In addition, server 418 also includes FPGA card 404, it is via PCI Express (PCIe) interface 410 and server 418 root complex (root complex, RC) 412 connect.FPGA card 404 is also via NGFI interfaces 406 and radio-frequency module 402 Connection.All or part of processing of uplink and downlink physical layer process can be completed in FPGA.RC 412 is connect by network Mouth card (NIC) 416 is connected with core net 420.Under the framework 400, FPGA card 404 will compete PCIe bandwidth with NIC card 416, Therefore, it is very important for how reducing requirement of the FPGA card 404 to PCIe bandwidth.

FPGA card 404 can also include multiple process blocks (processing block) 408.Fig. 4 shows 6 processing Block.In certain embodiments, a process block can be the module or unit in FPGA or other equipment.As above institute State, a FPGA card 404 can support the physical layer process of six cells, thus can divide FPGA card 404 for six processing Block, each process block support the processing of a cell.It should be appreciated that number has no intention to limit merely for the sake of illustration purpose System, FPGA card can be divided into any an appropriate number of process block.

Because general processor and FPGA may be used to signal transacting, therefore which physical layer function should be real by FPGA It is now a technical issues that need to address.By taking LTE as an example, in up process chain as shown in Figure 2, FFT 206, IDFT 212 It is adapted to Turbo decodings 216 by FPGA processing, and other physical layer process are adapted to be handled by general processor.It is if so real Apply, signal just toggles between FPGA and general processor, so as to introduce high time delay, reduces systematic function, this is with showing Significantly deviate from for the development trend of communication system.

Therefore, embodiment of the disclosure provides a kind of scheme for solving this problem, this shows in detail in Fig. 5-Fig. 7 Go out.Upstream solution is described in detail with reference to Fig. 5 and Fig. 6.

Fig. 5 shows the schematic diagram of uplink communication flow 500 in accordance with an embodiment of the present disclosure.With Fig. 2 prior art Communication process is compared, and adds PCIe cards 204, and to support FPGA, other each frames are identical with Fig. 2, repeat no more.Fig. 6 is shown The flow chart of uplink communication method 600 in accordance with an embodiment of the present disclosure.In step 602, at server cluster 102, connect Receive the packet from base station 104.As described in Figure 1 on, base station 104 is associated with server cluster 102, such as passes through electricity Cable, light etc. are communicatively coupled.In step 604, physics is performed for the packet by the high-speed treating apparatus in server cluster 102 Layer processing.In certain embodiments, high-speed treating apparatus can be FPGA, and the FPGA can be the server 418 shown in Fig. 4 Interior FPGA card 404.Physical layer process can include the processing of the continuous processing level in physical layer process chain as shown in Figure 5. In step 606, the packet through processing is sent to general processor, to perform further processing by general processor, for example, remaining Physical layer process and the processing such as MAC layer.By the method shown in Fig. 6, in high-speed treating apparatus (for example, FPGA) and general place Only once signal transmission between device is managed, is toggled in the absence of described above between the different disposal level of physical layer Problem, so as to the notable requirement reduced to PCIe bandwidth.

As described above, FPGA etc. high-speed treating apparatus has stronger calculating performance, therefore, can in step 604 To perform the processing of the process level of the computation-intensive in physical layer process chain by FPGA, for example, FFT 206, the and of IDFT 212 Turbo decodings one or more of 216.

In addition, as shown in figure 5, the input output band width of each process level may be different, therefore, this can be utilized Characteristic selects the distribution of process chain.When being migrated from data from FPGA to general processor, processed data speed may Much smaller than inphase/orthogonal (I/Q) data rate.So, PCIe bandwidth is no longer bottleneck.

For example, as shown in figure 5, if MAC layer 220, CRC 218 and Turbo decode 216 these three continuous processing levels logical Implemented with processor, and other remaining process levels are implemented in FPGA, then from from FPGA to general processor memory migration PCIe bandwidth required for data can be 1.818Gbps, this by Turbo decodings 216 input bandwidth (that is, demapping 214 Output bandwidth) determine.If only MAC layer 220 is implemented in general processor, by demodulating data from FPGA to general procedure PCIe bandwidth required for device memory migration can be only 75.376Mbps, this by MAC layer input bandwidth (that is, CRC218 Output bandwidth) determine.PCIe interface I/O handling capacities are too high to influence general processor and FPGA real-time performance, and with Other PCIe devices (Ethernet NIC 416 such as shown in Figure 4) compete PCIe bandwidth.Therefore, it is determined which physical layer Function is implemented to need the bandwidth considerations for considering PCIe in FPGA.In other words, can be performed by FPGA in physical layer process chain Terminate at the processing of the continuous processing level of the process level with small output bandwidth.Further, in certain embodiments, may be used also To perform the processing of all process levels in physical layer process chain by FPGA.So, the process level handled by FPGA has on the whole Small output bandwidth, and include the process level of all computation-intensives.

It will be understood that, there is provided the concrete numerical value of above input output band width is used to illustrating the principle of the disclosure, and it is unrestricted its Scope.In different scenes, each process level can have different input output band widths.

With reference to the flow chart of the downlink communication method 700 of Fig. 7 descriptions in accordance with an embodiment of the present disclosure.In step 702, Packet from general processor is received by the high-speed treating apparatus in server cluster 102.For example, high-speed treating apparatus can be with It is the FPGA card 404 shown in Fig. 4, general processor can be the general processor 414 shown in Fig. 4.The packet now received The processing of the continuous processing level of physical layer process chain can be performed via general processor 414.It will be appreciated that though herein Using the statement of continuous processing level, but general processor can not also perform any physical layer process.In step 704, by height Fast processing equipment performs the processing of the remaining continuous processing level in physical layer process chain for the packet.In other words, such as uplink Road is identical, and two parts of physical layer process level are carried out respectively by FPGA etc. high-speed treating apparatus and general processor Reason so that only occur once to communicate between high-speed treating apparatus and general processor, without the situation toggled.In step Rapid 706, send the packet through processing to base station 104.

Fig. 3 is returned to, it illustrates the descending process chains of LTE.In the downlink, IFFT is unique computation-intensive Processing task.It is similar with up processing, in step 704, the process level (example of computation-intensive in physical layer process chain can be performed Such as, IFFT).Alternatively or additionally, the company on the whole with small input bandwidth in physical layer process chain can be performed The processing of continuous process level.In other words, these continuous processing levels originate in the process level with small input bandwidth.Due to descending chain Road and the processing of up-link are substantially corresponding, thus repeat no more.

In certain embodiments, in the case where the performance of general processor is less than predetermined threshold, by such as FPGA height Fast processing equipment performs the processing of all process levels of physical layer process chain.For example, such case can be general processor Core amounts are less, computing capability deficiency, thus need FPGA to share appropriate work.

In other examples, in the case where the performance of general processor is higher than another predetermined threshold, by such as FPGA High-speed treating apparatus perform physical layer process chain part process level processing.In this case, due to general processor Disposal ability it is stronger, with the processing of executable portion process level, can suitably share the work of high-speed treating apparatus.For example, due to Downlink only has a computation-intensive process level IFFT, and therefore, high-speed treating apparatus can only perform IFFT process levels Processing.

The packet switching arrangement based on label is described below in conjunction with Fig. 8-Figure 14.An as it was previously stated, typical FPGA The physical layer process of six typical cells can be supported.Therefore, FPGA resource can be divided into multiple process blocks, at these Managing block can be with parallel work-flow, and each process block can undertake the peak traffic of a cell.

One feature of mobile service is periodically.Due to reasons such as working time, non-working time, mobile service is shown Go out using the 24 hours periodicity as the cycle.Generally, the processing load in server cluster from 9 points of morning to 11 points at night compared with Height, and it is relatively low at night.During standby time (for example, night), if can be by by all base stations of a machine trustship Move on another machine, idle machines can be closed.

Forward pass interface (NGFI) of future generation is a kind of to be used for agreement just under development.The plan of NGFI agreements supports wireless point Group route, i.e. wireless stream of data can be redirected to new destination-address, example by NGFI equipment based on destination NGFI addresses Such as FPGA.Forward pass interchanger can be used for realizing the function, the wireless I/Q data for being sent to source BBU is redirected to target BBU.NGFI interfaces in the industry cycle extensive discussions, can provide flexible route between BBU ponds and RRU, and using point Forward pass network is revised as multipair Multi net voting by group exchange agreement from point-to-point connection.

NGFI has three logical layers, and introduces specific cluster header to transmit nothing in packet switch forward pass network Line I/O data.However, after packet switch is performed via interchanger, usual header is removed, so as to determine data Various information, therefore the appropriate analysis and scheduling to data can not be provided.Therefore, herein propose one kind and be included in wireless I/ Label in O data packet.The label can with indicating cell, antenna, target machine, target FPGA, target FPGA process blocks, and And label is not removed during physical layer process.

Fig. 8 shows the schematic diagram migrated according to the base station of prior art.As shown in figure 8, BBU ponds 800 include multiple machines Device, i.e. machine 802,804,806 and 808.Machine 802 includes Pooled resources manager, for planning as a whole and dispatching BBU ponds 800 Resource.Machine 804,806 and 808 includes corresponding local resource manager 814,816 and 818 respectively.Local resource manager 814th, 816 and 818 operation conditions that can monitor each machine, and respectively to machine 802 Pooled resources manager 812 periodically Report the state of each machine in ground.Pooled resources manager can make a policy according to the operation conditions of each machine.By Fig. 8 institutes The technology shown is it is known in the art, being thus not described in detail.

Fig. 9 shows a kind of tag format, and the label can be used in NGFI agreements.NFGI agreements are still under development, its The header format of middle NGFI PHY carrier waves layer, NGFI data adaptations layer and NGFI data Layers does not determine yet.As shown in figure 9, NGFI Data Layer service data unit (SDU) includes label and wireless I/Q data.Label can include five fields：Cell ID, antenna ID, target machine ID, target FPGA ID and target process block ID.Cell ID indicates the cell associated with wireless packet, For example, the cell belonging to the packet.Antenna ID indicates the antenna associated with wireless packet, i.e. the packet comes from or gone to Antenna.The target machine that target machine ID instructions move to source base station.In the case where a machine includes multiple FPGA, The FPGA that target FPGA ID instruction packets will be gone to.Target process block ID indicates that the packet is performed by FPGA which process block Processing.

It should be noted that although basically illustrating five fields herein, but in actual applications, not necessarily all need These fields, there are some fields to omit, can also also add some other fields.Below in conjunction with the scene of base station migration Introduce the possible application of these fields.It will be appreciated, however, that the application of these labels can be not limited to following example field Scape.

Figure 10 shows the block diagram of the framework of FPGA 404 in accordance with an embodiment of the present disclosure.The FPGA 404 can include NGFI interfaces 406, distributor/multiplexer 1024, process block 408, label remover/packet assembler 1026 and pci interface 410。

NFGI interfaces 406 are connected with radio-frequency module (for example, Fig. 1 radio-frequency module 108), to receive NFGI packets.Upper In line link, distributor/multiplexer 1024 can be by the packet distribution of removal header to appropriate process block.In downlink In, distributor/multiplexer 1024 is multiplexed the packet from different disposal block, is subsequently sent to NFGI interfaces 406.

For simplicity, three process blocks 418,428 and 438 are shown in Figure 10.It should be appreciated that the number is only Have no intention to limit for illustrative purposes.In Fig. 10, each process block 418,428 and 438 performs cell respectively Uplink and downlink are handled.

In the uplink, label remover/packet assembler 1026 can remove the label of packet, be connect via PCIe Mouth 410 is sent to general processor, to carry out MAC layer processing by general processor.In the downlink, label remover/point Assembling orchestration 1026 can be to packet addition label etc..

The communication means 1200 based on label in up-link is described with reference to Figure 12.As shown in figure 12, in step 1202, at server cluster 102, the packet from base station 104 is received, the packet includes indicating the institute of server cluster 102 Including multiple process blocks in a process block label.In step 1204, by the packet distribution to as indicated by the label Process block.The step can be implemented by distributor/multiplexer 1024 shown in Figure 10.In step 1206, by the processing Block performs physical layer process to the packet.For example, method that can be as shown in Figure 6 is handled the packet.

In certain embodiments, multiple process blocks are included in the FPGA of server cluster 102.For example, such as Figure 10 institutes Show, multiple process blocks 418,428 and 438 are included in FPGA404.

In certain embodiments, label also can indicate that the cell associated with packet, for example, label can also be included such as Cell ID shown in Fig. 9.Communication means 1200 can also include removing label from packet, and packet is stored in and cell pair In the buffering area answered, further processing is performed to send to general processor.In FPGA buffering area and general processor Access between memory can be completed using existing direct memory access (DMA) (DMA) method.

Although two fields of label are only described above in association with Figure 12, it will be appreciated by those skilled in the art that the communication Method 1200 can also utilize all five fields as shown in Figure 9.

Illustrate the communication means 1300 based on label in downlink with reference to Figure 13.As shown in figure 13, in step At 1302, at server cluster 102, the packet of the general processor from server cluster 102 is received.In step 1304, Label is added to packet, label can indicate the cell that packet is sent to, such as cell ID as shown in Figure 9.In step 1306, physical layer process is performed to packet.It is, for example, possible to use the method shown in Fig. 7 carries out physical layer process to packet.In step Rapid 1308, base station 104 is sent the packet to be sent to terminal device.

In certain embodiments, the finger for the antenna being sent to packet can also be added to label in step 1304 Show, such as antenna ID as shown in Figure 9.For example, can to block precoders (for example, precoding level 316 as shown in Figure 3 Implement) after, add antenna ID to the label of the packet.

Although two fields of label are only described above in association with Figure 12, it will be appreciated by those skilled in the art that the communication Method 1200 can also utilize all five fields as shown in Figure 9.

Illustrate to add tagged communication means 1400 in up-link with reference to Figure 14.In step 1402, in base station The data from terminal device are received at 104, for the sake of distinguishing, the data are referred to as the first data.In step 1404, to first Data add label to form the first packet, the server associated with base station 104 that the packet of label instruction first is sent to The first process block in destination server and destination server in cluster 102.In step 1406, by the first packet transmission to One process block.

In certain embodiments, the label of the first packet also indicates the first community associated with the first packet.If the The load reduction of one process block under first threshold (for example, in the case of night), then receive it is related to first community Label is added to form second packet to the second data during the second data of connection.The label can indicate first community and be different from The second processing block of first process block.Load monitoring can be by realizing, to determine above in association with the scheme described by Fig. 8 The load of one process block how to change and can receive the first process block load second processing block.

Alternatively or additionally, Pooled resources manager 812 as shown in Figure 8 can be according to machine ID included in label Packet situation is monitored with FPGA ID.As an example, if 812 packet-based label of Pooled resources manager determines to be sent to certain The number of the packet of individual machine (being indicated by the machine ID of label) is less than certain threshold value, it is determined that needs all negative of the machine Load is moved out, so that the machine leaves unused.Similarly, if machine includes multiple FPGA, difference can be indicated by FPGA ID FPGA.In this case, if 812 packet-based label of Pooled resources manager determines to be sent to some FPGA (by label FPGA ID instructions) the number of packet be less than certain threshold value, it is determined that need to move out all loads of the FPGA so that The FPGA leaves unused.The problem of on load migration between machine and between FPGA, the destination of NGFI agreements can be utilized Realized by routeing address.On the particular content of the program, later reference Figure 11 is described in detail, no longer superfluous herein State.

In certain embodiments, the first process block concurrently handles the first packet and different from the first the 3rd point be grouped Group.The label of first packet and the 3rd packet also indicates respectively to be grouped and the associated first community of the 3rd packet and the with first Two cells.In this case, if the load of the first process block increases on Second Threshold (for example, in situation early in the morning Under), then, can be to the 3rd data when receiving with a three associated data of cell in first community and second community For addition label to form the 3rd packet, the label indicates a cell and the 3rd process block.3rd process block can be idle Process block or light load process block, so as to bear it is associated with first community or second community after The processing of continuous packet.The determination of 3rd process block similarly can be as shown in Figure 8 method determine.

Alternatively or additionally, Pooled resources manager 812 as shown in Figure 8 can be according to machine ID included in label Packet situation is monitored with FPGA ID.As an example, if 812 packet-based label of Pooled resources manager determines to be sent to certain The number of the packet of individual machine (being indicated by the machine ID of label) is higher than certain threshold value (for example, load is too high, time delay increase), then It is determined that need to move out the fractional load associated with some cells of the machine, to reduce the load of the machine.Similarly, such as Fruit machine includes multiple FPGA, then different FPGA can be indicated by FPGA ID.In this case, if Pooled resources The number that 812 packet-based label of manager determines to be sent to some FPGA (being indicated by the FPGA ID of label) packet is higher than Certain threshold value, then it can determine to need to move out all loads of the FPGA, so as to reduce the load of the FPGA, during so as to reduce Prolong.

In certain embodiments, label also can indicate that the target FPGA that packet is sent to, it may for example comprise such as Fig. 9 institutes The target FPGA ID shown.In this case, destination server includes multiple FPGA containing target FPGA, and at first Reason block is one in target FPGA multiple process blocks.Alternatively or additionally, label also can indicate that related to packet The antenna of connection, such as including antenna ID as shown in Figure 9.

For the sake of completeness, the block diagram of the framework of packet switch is described with reference to Figure 11.The framework master of the packet switch Will the routing function based on NGFI agreements, i.e. NGFI equipment can be redirected wireless stream of data based on destination NGFI addresses To new destination-address.NGFI agreements have the address space of their own, and each NGFI equipment is by unique NGFI Location identifies.

If Pooled resources manager 812 first may be used based on base station is migrated above in conjunction with determinations such as the methods described by Fig. 8 To determine target machine and/or target FPGA.The destination NGFI then, these information being added in NGFI protocol headers In location.Therefore, based on destination NGFI addresses, NGFI interchangers 1118 route the packet to corresponding machine and/or FPGA.

Figure 11 shows the comprehensive view 1100 of base station migration in accordance with an embodiment of the present disclosure.The view 1100 includes clothes Business device cluster 102, to put it more simply, illustrate only two servers 418 and 1118.The configuration of server 1118 and server 418 Essentially identical, its internal module has been described in above in conjunction with Fig. 4, therefore repeats no more.Pooled resources manager (does not show Go out) periodically collect the respective server sent by local resource manager (not shown) and/or corresponding FPGA resource and make Use information.If the resource utilization of a server (for example, server 418 as depicted) is less than predetermined threshold, by All base stations of the trustship of server 418 will be assigned to other one or more servers, such as server 1118.Pooled resources Manager will find suitable destination server and/or target FPGA based on the resource using information being collected into and target is handled Block.Then, Pooled resources manager triggering tag update event, and target FPGA NGFI addresses and target process block ID are sent out The packet radio assembler (not shown) being sent at radio-frequency module 108.Packet radio assembler is using new destination NGFI Location and the corresponding packet radio of new Tag Packaging.Packet radio can be redirected to suitable FPGA by interchanger 1108 Processing unit.

However, due to after by NGFI interchangers 1108, removing the header of NGFI agreements, it is only remaining such as Fig. 9 institutes The DL SDU shown, it includes label and I/Q data.In this case, the destination-address in the header of NGFI agreements can not Process block is addressed, the process block ID in label can only be relied on.Migration based on label between process block is above Through being described in detail, here is omitted.

Then, the data forwarding between source base station and target BS is started.Target BS is new on destination server Instantiation base station, it will take over all tasks in source base station.For example, as shown in figure 11, as the institute hosted by server 418 There is source base station to can be switched on server 1118 target BS instantiated.Then, from core net 420 to service The NIC 416 of device 418 S1 downlink paths are also switched to the S1 from core net 420 to the NIC 416 of server 1118 Downlink path, it is achieved thereby that the migration from source base station to target BS.

Communication means based on label described herein causes the Hold sticker in physical layer process, consequently facilitating base station Migration, improve the efficiency of centralization processing.

Figure 15 shows the block diagram of server 418 in accordance with an embodiment of the present disclosure.

As shown in figure 15, server 418 includes at least one high-speed treating apparatus.High-speed treating apparatus includes receiver 1502, it is configured as receiving the packet from base station.For example, receiver 1502 can be NFGI interfaces 406 as shown in Figure 10. High-speed treating apparatus also includes process block 408, the continuous processing level for being configured as performing for packet in physical layer process chain Processing.High-speed treating apparatus can also include transmitter 1506, be configured as sending through place to the general processor of server 418 The packet of reason, to perform further processing by general processor 414.For example, transmitter 1506 can be as shown in Figure 10 PCIe interface 410.

In certain embodiments, performing the processing of the continuous processing level in physical layer process chain includes：Perform at physical layer Manage the processing of the process level of the computation-intensive in chain.In certain embodiments, the continuous processing in physical layer process chain is performed The processing of level includes：Perform the continuous processing level for terminating at the process level with small output bandwidth in physical layer process chain Processing.In certain embodiments, performing the processing of the continuous processing level in physical layer process chain includes：Perform physical layer process chain In all process levels processing.In certain embodiments, high-speed treating apparatus can be field programmable gate array (FPGA), example As shown in fig. 10.

Figure 16 shows the block diagram of server 418 in accordance with an embodiment of the present disclosure.

As shown in figure 16, server 418 includes at least one high-speed treating apparatus.High-speed treating apparatus includes receiver 1602, it is configured as receiving the packet of the general processor from server, wherein general processor performs physics for packet The processing of continuous processing level in layer process chain.For example, receiver 1602 can be as shown in Figure 10 PCIe interface 410.At a high speed Processing equipment also includes process block 408, the remaining continuous processing level for being configured as performing for packet in physical layer process chain Processing.As shown in figure 16, high-speed treating apparatus can also include transmitter 1606, be configured as sending point through processing to base station Group.For example, transmitter 1606 can be NFGI interfaces 406 as shown in Figure 10.

In certain embodiments, performing the processing of the remaining continuous processing level in physical layer process chain includes：Perform physics The process level of computation-intensive in layer process chain.In certain embodiments, the remaining continuous processing in physical layer process chain is performed The processing of level includes：Perform the continuous processing level for originating in the process level with small input bandwidth in physical layer process chain Processing.In certain embodiments, the processing for performing the remaining continuous processing level in physical layer process chain can be included in general place The performance of device is managed less than in the case of the first predetermined threshold, performs the processing of all process levels of physical layer process chain.Alternatively Or additionally, in the case where the performance of general processor is higher than the second predetermined threshold, perform quick Fu of physical layer process chain In leaf transformation inverse transformation (IFFT) process level processing.

In certain embodiments, high-speed treating apparatus can be field programmable gate array (FPGA), such as such as Figure 10 institutes Show.

Figure 17 shows the block diagram of server 418 in accordance with an embodiment of the present disclosure.

As shown in figure 17, server 418 includes at least one high-speed treating apparatus.High-speed treating apparatus includes receiver 1702, it is configured as receiving the packet from base station, packet includes multiple included by least one high-speed treating apparatus of instruction The label of a process block in process block.High-speed treating apparatus can also include distributor 1024, be configured as packet point It is dealt into the process block indicated by label.As shown in figure 17, high-speed treating apparatus can also include process block 408, be configured as pair Packet performs physical layer process.In certain embodiments, high-speed treating apparatus can be field programmable gate array (FPGA), example As shown in fig. 10.

In certain embodiments, label also indicates the cell associated with packet, and at least one high-speed treating apparatus It is additionally configured to：Label is removed from packet；And packet is stored in buffering area corresponding with cell, to send to general Computing device is further handled.

Figure 18 shows the block diagram of server 418 in accordance with an embodiment of the present disclosure.

As shown in figure 18, server 418 includes at least one high-speed treating apparatus.High-speed treating apparatus includes receiver 1802, it is configured as receiving the packet from the general processor included by server.Receiver 1802 can be such as Figure 10 institutes The PCIe interface 410 shown.High-speed treating apparatus also includes assembler 1026, is configured as adding label, label instruction to packet It is grouped the cell being sent to.As shown in figure 18, high-speed treating apparatus also includes process block 408, is configured as performing packet Physical layer process；And transmitter 1808, it is configured as sending the packet to base station to be sent to terminal device.For example, hair It can be NGFI interfaces 406 as shown in Figure 10 to send device 1808.

In certain embodiments, performing physical layer process to packet includes：The day being sent to label addition to packet The instruction of line.In certain embodiments, high-speed treating apparatus can be field programmable gate array (FPGA), such as such as Figure 10 institutes Show.

Figure 19 shows the block diagram of base station equipment 104 in accordance with an embodiment of the present disclosure.Base station equipment includes radio-frequency module. Radio-frequency module includes receiver 1902, is configured as receiving the first data from terminal device；Adder 1904, is configured as Label is added to the first data to form the first packet, and the packet of label instruction first is sent to associated with base station equipment The first process block in destination server and destination server in server cluster；And transmitter 1906, be configured as by First packet transmission to the first process block.

In certain embodiments, the label of the first packet also indicates the first community associated with the first packet, radio frequency mould Block is additionally configured to：In response to the first process block load reduction under first threshold, receive associated with first community Second data；And label is added to form second packet to the second data, label instruction first community and different from first Manage the second processing block of block.

In certain embodiments, the first process block concurrently handles the first packet and different from the first the 3rd point be grouped The label of group, the first packet and the 3rd packet also indicates respectively to be grouped and the associated first community of the 3rd packet and the with first Two cells, radio-frequency module are additionally configured to：Load in response to the first process block increases on Second Threshold, receives and first The 3rd data that a cell in cell and second community is associated；And label is added to form the 3rd point to the 3rd data Group, label indicate a cell and the 3rd process block.

In certain embodiments, label also indicates the targeted cache processing equipment that packet is sent to, wherein destination service Device includes multiple high-speed treating apparatus containing targeted cache processing equipment, and the first process block is targeted cache processing equipment Multiple process blocks in one.Alternatively or additionally, label also indicates the antenna associated with packet.In some embodiments In, it is field programmable gate array (FPGA) that high-speed treating apparatus, which includes,.

Although the principle of the disclosure is described mainly in combination with NFGI agreements herein, but those skilled in the art are easy Understand that these novel concepts can apply in other existing or exploitation in the future communication protocols, the disclosure is not limited this System.It is also understood that although describing the communication means based on label above in conjunction with FPGA, but this method can also be modified to Principle applied to other equipment without departing from the disclosure.

In the case where not departing from the principle of the disclosure, included module can be with server 418 and base station equipment 104 Profit is realized in various manners, including software, hardware, firmware or its any combination.In one embodiment, one or more moulds Block can be realized using software and/or firmware, such as store machine-executable instruction on a storage medium.Except machine can Outside execute instruction or alternatively, some or all of module in server 418 and base station equipment 104 can at least portion Ground is divided to be realized by one or more hardware logic components.It is unrestricted as example, the hardware for the exemplary type that can be used Logic module including being on field programmable gate array (FPGA), application specific integrated circuit (ASIC), application specific standard product (ASSP), piece System (SOC), CPLD (CPLD), etc..

In general, the various example embodiments of the disclosure can in hardware or special circuit, software, logic, or its What implements in combining.Some aspects can be implemented within hardware, and other aspect can by controller, microprocessor or Implement in the firmware or software of other computing devices.When each side of embodiment of the disclosure is illustrated or described as frame When figure, flow chart or other some figures of use represent, it will be understood that square frame described herein, device, system, techniques or methods can Using in terms of as nonrestrictive example in hardware, software, firmware, special circuit or logic, common hardware or controller or other Calculate and implement in equipment, or its some combination.

As an example, embodiment of the disclosure can be described in the context of machine-executable instruction, machine can be held Row instruction is such as included in the program module performed in the device on the true or virtual processor of target.In general, Program module includes routine, program, storehouse, object, class, component, data structure etc., and it performs specific task or realized specific Abstract data structure.In embodiments, the function of program module can merge between described program module or Segmentation.Machine-executable instruction for program module can perform in local or distributed apparatus.In distributed apparatus In, program module can be located locally with both remote medium storages.

For realizing that the computer program code of disclosed method can be write with one or more programming languages.These Computer program code can be supplied to the processing of all-purpose computer, special-purpose computer or other programmable data processing units Device so that program code by computer or other programmable data processing units execution when, cause flow chart and/ Or function/operation is carried out specified in block diagram.Program code can completely on computers, part on computers, conduct Independent software kit, part are on computers and part is held on remote computer or server on the remote computer or completely OK.

In the context of the disclosure, machine readable media can include or store to be used to or be related to instruct to perform system Any tangible medium of the program of system, device or equipment.Machine readable media can be that machine-readable signal medium or machine can Read storage medium.Machine readable media can include but is not limited to electronics, magnetic, it is optical, electromagnetism, infrared or partly lead System system, device or equipment, or its any appropriate combination.The more detailed example of machinable medium includes carrying one Or the electrical connections of multiple conducting wires, portable computer diskette, hard disk, random access memories (RAM), read-only storage (ROM), Erasable Programmable Read Only Memory EPROM (EPROM or flash memory), light storage device, magnetic storage apparatus, or its is any appropriate Combination.

In addition, although operation is depicted with particular order, but this and should not be construed and require this generic operation to show Particular order is completed with sequential order, or performs the operations of all diagrams to obtain expected result.In some cases, it is more Task or parallel processing can be beneficial.Similarly, although discussed above contain some specific implementation details, this is not The scope for limiting any invention or claim is should be interpreted that, and should be interpreted that the specific embodiment to specific invention can be directed to Description.Some features in this specification described in the context of separated embodiment can also combined implementation in single reality Apply in example.Conversely, various features described in the context of single embodiment can also discretely multiple embodiments or Implement in any appropriate sub-portfolio.

Although theme is described with the language specific to architectural feature and/or method action, but it is to be understood that institute The theme limited in attached claim is not limited to above-described special characteristic or action.On the contrary, above-described specific spy Action of seeking peace is disclosed as the exemplary forms for realizing claim.

Claims (42)

1. a kind of communication means, including：

At the server cluster associated with base station, the packet from the base station is received；

By the high-speed treating apparatus of the server cluster for the continuous processing level in the packet execution physical layer process chain Processing；And

To the server cluster general processor send the packet through processing, with by the general processor perform into The processing of one step.

2. communication means according to claim 1, wherein performing the processing bag of the continuous processing level in physical layer process chain Include：

Perform the processing of the process level of the computation-intensive in the physical layer process chain.

3. communication means according to claim 1, wherein performing the processing bag of the continuous processing level in physical layer process chain Include：

Perform the processing of the continuous processing level for terminating at the process level with small output bandwidth in the physical layer process chain.

4. communication means according to claim 1, wherein performing the processing bag of the continuous processing level in physical layer process chain Include：

Perform the processing of all process levels in the physical layer process chain.

5. communication means according to claim 1, wherein the high-speed treating apparatus includes field programmable gate array (FPGA)。

6. a kind of communication means, including：

The packet of the general processor from the server cluster associated with base station is received, wherein the general processor is directed to The packet performs the processing of the continuous processing level in physical layer process chain；

The residue performed by the high-speed treating apparatus of the server cluster for the packet in physical layer process chain is continuous Manage the processing of level；And

The packet through processing is sent to the base station.

7. communication means according to claim 6, wherein performing the place of the remaining continuous processing level in physical layer process chain Reason includes：

Perform the process level of computation-intensive in the physical layer process chain.

8. communication means according to claim 6, wherein performing the place of the remaining continuous processing level in physical layer process chain Reason includes：

Perform the processing of the continuous processing level for originating in the process level with small input bandwidth in the physical layer process chain.

9. communication means according to claim 6, wherein performing the place of the remaining continuous processing level in physical layer process chain Reason includes at least one of following：

In the case where the performance of the general processor is less than the first predetermined threshold, all of the physical layer process chain are performed The processing of process level；And

In the case where the performance of the general processor is higher than the second predetermined threshold, the quick of the physical layer process chain is performed The processing of Fourier transformation inverse transformation (IFFT) process level.

10. communication means according to claim 6, wherein the high-speed treating apparatus includes field programmable gate array (FPGA)。

11. a kind of communication means, including：

At the server cluster associated with base station, the packet from the base station is received, the packet is included described in instruction The label of a process block in multiple process blocks included by server cluster；And

By the packet distribution to the process block indicated by the label；And

Physical layer process is performed to the packet by the process block.

12. communication means according to claim 11, wherein the multiple process block is included in the server cluster In included field programmable gate array (FPGA).

13. communication means according to claim 11, wherein the label also indicates the cell associated with the packet, And the communication means also includes：

The label is removed from the packet；And

The packet is stored in buffering area corresponding with the cell, further place is performed to send to general processor Reason.

14. a kind of communication means, including：

At the server cluster associated with base station, point from the general processor included by the server cluster is received Group；

To the packet addition label, the label instruction is described to be grouped the cell being sent to；

Physical layer process is performed to the packet by high-speed treating apparatus；And

By the packet transmission to the base station to be sent to terminal device.

15. communication means according to claim 14, wherein performing physical layer process to the packet includes：

To label addition to the instruction for being grouped the antenna being sent to.

16. communication means according to claim 14, wherein the high-speed treating apparatus includes field programmable gate array (FPGA)。

17. a kind of communication means, including：

The first data from terminal device are received in base station；

Add label to first data to form the first packet, label instruction first packet be sent to The first process block in destination server and the destination server in the associated server cluster in the base station；And

By first packet transmission to first process block.

18. communication means according to claim 17, wherein the label of first packet also indicates and described first point The associated first community of group, the communication means also include：

In response to first process block load reduction under first threshold,

Receive second data associated with the first community；And

Label is added to second data to form second packet, and the label indicates the first community and different from described The second processing block of first process block.

19. communication means according to claim 17, wherein first process block concurrently handles first packet With the 3rd packet different from the described first packet, the label of first packet and the 3rd packet also indicates respectively and institute The first community and second community that the first packet and the 3rd packet are associated are stated, the communication means also includes：

Load in response to first process block increases on Second Threshold,

Receive threeth data associated with a cell in the first community and the second community；And

Label is added to the 3rd data to form the 3rd packet, and the label indicates one cell and the 3rd processing Block.

20. communication means according to claim 17, wherein the label also indicate it is at least one of following：

It is described to be grouped the targeted cache processing equipment being sent to, wherein the destination server includes containing the targeted cache Multiple high-speed treating apparatus of processing equipment, and first process block is multiple processing of the targeted cache processing equipment One in block；And

The antenna associated with the packet.

21. communication means according to claim 20, wherein the multiple high-speed treating apparatus includes field programmable gate Array (FPGA).

22. a kind of server, including：

At least one high-speed treating apparatus, is configured as：

Receive the packet from base station；

The processing of the continuous processing level in physical layer process chain is performed for the packet；And

The packet through processing is sent to the general processor of the server, it is further to be performed by the general processor Processing.

23. server according to claim 22, wherein performing the processing bag of the continuous processing level in physical layer process chain Include：

Perform the processing of the process level of the computation-intensive in the physical layer process chain.

24. server according to claim 22, wherein performing the processing bag of the continuous processing level in physical layer process chain Include：

Perform the processing of the continuous processing level for terminating at the process level with small output bandwidth in the physical layer process chain.

25. server according to claim 22, wherein performing the processing bag of the continuous processing level in physical layer process chain Include：

Perform the processing of all process levels in the physical layer process chain.

26. server according to claim 22, wherein at least one high-speed treating apparatus includes field-programmable Gate array (FPGA).

27. a kind of server, including：

At least one high-speed treating apparatus, is configured as：

The packet of the general processor from the server is received, wherein the general processor performs thing for the packet Manage the processing of the continuous processing level in layer process chain；

The processing of the remaining continuous processing level in physical layer process chain is performed for the packet；And

The packet through processing is sent to base station.

28. server according to claim 27, wherein performing the place of the remaining continuous processing level in physical layer process chain Reason includes：

Perform the process level of computation-intensive in the physical layer process chain.

29. server according to claim 27, wherein performing the place of the remaining continuous processing level in physical layer process chain Reason includes：

Perform the processing of the continuous processing level for originating in the process level with small input bandwidth in the physical layer process chain.

30. server according to claim 27, wherein performing the place of the remaining continuous processing level in physical layer process chain Reason includes at least one of following：

In the case where the performance of the general processor is less than the first predetermined threshold, all of the physical layer process chain are performed The processing of process level；And

In the case where the performance of the general processor is higher than the second predetermined threshold, the quick of the physical layer process chain is performed The processing of Fourier transformation inverse transformation (IFFT) process level.

31. server according to claim 27, wherein at least one high-speed treating apparatus includes field-programmable Gate array (FPGA).

32. a kind of server, including：

At least one high-speed treating apparatus, is configured as：

The packet from base station is received, the packet includes indicating multiple places included by least one high-speed treating apparatus Manage the label of a process block in block；And

By the packet distribution to the process block indicated by the label；And

Physical layer process is performed to the packet by the process block.

33. server according to claim 32, wherein at least one high-speed treating apparatus includes field-programmable Gate array (FPGA).

34. server according to claim 32, wherein the label also indicates the cell associated with the packet, and And at least one high-speed treating apparatus is additionally configured to：

The label is removed from the packet；And

The packet is stored in buffering area corresponding with the cell, further place is performed to send to general processor Reason.

35. a kind of server, including：

At least one high-speed treating apparatus, is configured as：

Receive the packet from the general processor included by the server；

To the packet addition label, the label instruction is described to be grouped the cell being sent to；

Physical layer process is performed to the packet；And

By the packet transmission to base station to be sent to terminal device.

36. server according to claim 35, wherein performing physical layer process to the packet includes：

To label addition to the instruction for being grouped the antenna being sent to.

37. server according to claim 35, wherein at least one high-speed treating apparatus includes field-programmable Gate array (FPGA).

38. a kind of base station equipment, including：

Radio-frequency module, it is configured as：

Receive the first data from terminal device；

Add label to first data to form the first packet, label instruction first packet be sent to The first process block in destination server and the destination server in the associated server cluster of the base station equipment；With And

By first packet transmission to first process block.

39. the base station equipment according to claim 38, wherein the label of first packet also indicates and described first point The associated first community of group, the radio-frequency module are additionally configured to：

In response to first process block load reduction under first threshold,

Receive second data associated with the first community；And

Label is added to second data to form second packet, and the label indicates the first community and different from described The second processing block of first process block.

40. the base station equipment according to claim 38, wherein first process block concurrently handles first packet With the 3rd packet different from the described first packet, the label of first packet and the 3rd packet also indicates respectively and institute The first community and second community that the first packet and the 3rd packet are associated are stated, the radio-frequency module is additionally configured to：

Load in response to first process block increases on Second Threshold,

Receive threeth data associated with a cell in the first community and the second community；And

Label is added to the 3rd data to form the 3rd packet, and the label indicates one cell and the 3rd processing Block.

41. the base station equipment according to claim 38, wherein the label also indicate it is at least one of following：

It is described to be grouped the targeted cache processing equipment being sent to, wherein the destination server includes containing the targeted cache Multiple high-speed treating apparatus of processing equipment, and first process block is multiple processing of the targeted cache processing equipment One in block；And

The antenna associated with the packet.

42. base station equipment according to claim 41, wherein the multiple high-speed treating apparatus includes field programmable gate Array (FPGA).