CN114285704B - Uplink channel estimation method, chip, system and storage medium - Google Patents
Uplink channel estimation method, chip, system and storage medium Download PDFInfo
- Publication number
- CN114285704B CN114285704B CN202210201623.XA CN202210201623A CN114285704B CN 114285704 B CN114285704 B CN 114285704B CN 202210201623 A CN202210201623 A CN 202210201623A CN 114285704 B CN114285704 B CN 114285704B
- Authority
- CN
- China
- Prior art keywords
- processing
- accelerator
- data
- digital signal
- processing module
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000000034 method Methods 0.000 title claims abstract description 148
- 238000012545 processing Methods 0.000 claims abstract description 938
- 239000011159 matrix material Substances 0.000 claims description 72
- 230000008569 process Effects 0.000 claims description 57
- 238000004891 communication Methods 0.000 claims description 42
- 238000001228 spectrum Methods 0.000 claims description 32
- 238000001914 filtration Methods 0.000 claims description 27
- 230000001629 suppression Effects 0.000 claims description 24
- 230000005540 biological transmission Effects 0.000 claims description 23
- 230000003993 interaction Effects 0.000 claims description 22
- 238000000605 extraction Methods 0.000 claims description 20
- 238000004364 calculation method Methods 0.000 claims description 18
- 238000004590 computer program Methods 0.000 claims description 6
- 239000000126 substance Substances 0.000 claims 1
- 238000005457 optimization Methods 0.000 abstract description 5
- 230000006870 function Effects 0.000 description 19
- 238000010586 diagram Methods 0.000 description 13
- 238000005516 engineering process Methods 0.000 description 6
- 238000013461 design Methods 0.000 description 5
- 230000009471 action Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000012935 Averaging Methods 0.000 description 2
- 238000004458 analytical method Methods 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 238000012937 correction Methods 0.000 description 2
- 238000013507 mapping Methods 0.000 description 2
- 241000168254 Siro Species 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 210000001503 joint Anatomy 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 238000010295 mobile communication Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
- 230000007723 transport mechanism Effects 0.000 description 1
Images
Abstract
The present application relates to an uplink channel estimation method, a chip, a system and a storage medium, wherein the uplink channel estimation method comprises a digital signal processing module and N accelerators, and the execution is as follows: each accelerator in the N accelerators receives parameter information which is correspondingly issued by the digital signal processing module; each accelerator acquires required data to be input according to the received parameter information for processing, and outputs respective processing data and processing parameters; the chip also comprises a digital signal processing module and N accelerators, and the method is executed; the system also comprises a digital signal processing module and N accelerators, and the method is executed; therefore, the uplink channel estimation method, the chip, the system and the storage medium are based on the hardware architecture redesign and the uplink channel estimation process optimization of the uplink channel estimation system, the step process optimization of the channel estimation is integrated into a plurality of accelerators, and the overall efficiency of the uplink channel estimation is greatly improved.
Description
Technical Field
The present application relates to the field of wireless communications technologies, and in particular, to an uplink channel estimation method, a chip, a system, and a storage medium.
Background
Channel estimation is a process of estimating the characteristics of a channel using various states exhibited by a received signal, and channel estimation may be defined as a process of qualitatively studying the influence of the channel on an input signal, and is a mathematical representation of the influence of the channel on the input signal. With the development of wireless communication technology, the fifth generation mobile communication technology (5th generation mobile networks or 5th generation wireless systems, 5G for short) is becoming more and more popular in people's daily life, and channel estimation is an important signal processing technology for an uplink network in a 5G-NR communication system, and is of great importance to the performance of a receiving end.
Generally, a channel estimation method mainly includes a series of processing such as extracting, denoising, and filtering a received signal, and then restoring a signal affected by various noises, attenuations, and the like during transmission back to a source signal. The channel estimation procedure in the related communication system is basically performed based on the formula 'Y = HX + W', where Y is the received signal, H is the channel value, X is the source signal, and W is the noise; since the wireless environment is complex and changeable, the signal will be subjected to various interferences in the process of propagation, when reaching the receiving end, the amplitude, phase and frequency of the signal will be changed greatly, and the receiving end cannot directly know the source user data, so that the Reference Signal (RS) directly known by both the receiving end and the transmitting end is used as the object of channel estimation, and the actual data is deduced reversely. That is, the channel estimation work actually is to estimate the Reference Signal (RS) that is fixedly present in the received signal based on the above formula, obtain the channel estimation result, i.e., 'H' and 'W' in the above formula, and then calculate the actual data therefrom.
Disclosure of Invention
The inventor finds that the processing time delay of a related uplink channel estimation system cannot meet the requirement, the hardware architecture of the uplink channel estimation system is redesigned and the uplink channel estimation process is optimized, the channel estimation step process is optimized and integrated into a plurality of accelerators, a series of processing is carried out on the accelerators based on reference signals, finally, user data, channel value data on the corresponding position of the user data and the inversion result of a noise covariance matrix are extracted from frequency domain data input from the outside, the performance of the system is greatly improved, and better channel estimation efficiency can be obtained.
The application provides an uplink channel estimation method, a chip, a system and a storage medium, which aim to solve the problem of low channel estimation efficiency in the existing uplink channel estimation mode.
In a first aspect, the present application provides an uplink channel estimation method, which is applied to a communication system, where the communication system includes a digital signal processing module and N accelerators, where N is a positive integer greater than 1; the N accelerators and the digital signal processing module execute the steps of: each accelerator in the N accelerators receives the parameter information correspondingly issued by the digital signal processing module; each accelerator acquires required data to be input according to the received parameter information for processing, and outputs respective processing data and processing parameters; processing data output by each accelerator is interacted among the accelerators, and processing parameters output by each accelerator are reported to the digital signal processing module; the data to be input acquired by each accelerator is frequency domain data input externally or processing data output by each accelerator; the parameter information received by each accelerator except the first accelerator in the N accelerators comprises an operation result obtained after the digital signal processing module processes the reported processing parameters; the processing data output from each accelerator includes at least a first processing result after demapping as a channel estimation result, a second processing result after inversion of the noise covariance matrix, and channel value data after demapping.
In a second aspect, the present application further provides a chip, where N accelerators are arranged in the chip, and the chip establishes data transmission interaction with the digital signal processing module; each accelerator in the N accelerators receives the parameter information correspondingly issued by the digital signal processing module; each accelerator acquires required data to be input according to the received parameter information for processing, and outputs respective processing data and processing parameters; processing data output by each accelerator is interacted among the accelerators, and processing parameters output by each accelerator are reported to the digital signal processing module; the data to be input acquired by each accelerator is frequency domain data input externally or processing data output by each accelerator; the parameter information received by each accelerator except the first accelerator in the N accelerators comprises an operation result obtained after the digital signal processing module processes the reported processing parameters; the processing data output from each accelerator includes at least a first processing result after demapping as a channel estimation result, a second processing result after inversion of the noise covariance matrix, and channel value data after demapping.
In a third aspect, the present application further provides a communication system comprising a communication device comprising a digital signal processing module, a channel estimation accelerator, and an equalization accelerator; the channel estimation accelerator comprises N accelerators; the digital signal processing module respectively realizes data transmission interaction with each accelerator and the balance accelerator in the N accelerators, and realizes data transmission interaction between the N accelerators and the balance accelerator; the N accelerators and the digital signal processing module are configured to execute the uplink channel estimation method according to any embodiment of the first aspect, and obtain a first processing result after demapping processing, a second processing result after inversion of a noise covariance matrix, and channel value data after demapping processing, which are channel estimation results; and taking the first processing result, the second processing result and the channel value data as data to be input of the equalization accelerator to perform channel equalization processing to obtain a channel equalization result.
In a fourth aspect, the present application further provides a communication device comprising a digital signal processing module and a chip interacting with the digital signal processing module, the chip comprising a chip implementing the embodiments of the second aspect.
In a fifth aspect, the present application further provides a computer-readable storage medium, where a computer program is stored, and when the computer program is executed by a processor, the method for estimating an uplink channel according to any embodiment of the first aspect is implemented.
The beneficial effect of this application is as follows:
according to the uplink channel estimation method, the digital signal processing module provides parameter information corresponding to N accelerators, the N accelerators perform a series of processing of channel estimation on externally input frequency domain data or processing data output by each accelerator according to respective parameter information under the instruction of the digital signal processing module, and obtain channel estimation results such as a first processing result after demapping, a second processing result of noise covariance matrix inversion and channel value data after demapping, and provide required processing data and/or processing parameters for subsequent channel equalization processing; each of the N accelerators is divided into different functions, processes respective data to be input and outputs respective processing data and processing parameters, so that the digital signal processing module processes the processing data and the processing parameters or instructs other accelerators to acquire the processing data and the processing parameters for processing; according to the uplink channel estimation method, through interaction between the digital signal processing module and the N accelerators, the efficiency of the digital signal processing module can be optimized, the N accelerators are scheduled to realize complex operation processing in the channel estimation processing process, meanwhile, the digital signal processing module also receives data and parameters which are difficult to process by the N accelerators to assist in processing, and the received data of different users are processed in an orderly and parallel mode, so that the overall efficiency of uplink channel estimation is improved, and the overall hardware performance is further improved. The chip based on the embodiment of the application comprises the N accelerators, interacts with the digital signal processing module, and can process data of different users in sequence and in parallel, so that the overall efficiency of uplink channel estimation is improved, and the overall hardware performance is improved. The communication system based on the embodiment of the application can improve the efficiency of the whole channel estimation process. The communication device of the embodiment of the application can also improve the efficiency of the whole channel estimation process.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and together with the description, serve to explain the principles of the invention.
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without inventive exercise.
Fig. 1 is a schematic flowchart of an uplink channel estimation method according to an embodiment of the present application;
fig. 2 is a schematic structural diagram of an application scenario of an uplink channel estimation method according to an embodiment of the present application;
fig. 3 is a schematic processing flow diagram of an accelerator of an uplink channel estimation method according to an embodiment of the present application;
fig. 4 is a schematic processing flow diagram of another accelerator of an uplink channel estimation method according to an embodiment of the present application;
fig. 5 is a schematic processing flow diagram of another accelerator of an uplink channel estimation method according to an embodiment of the present application;
fig. 6 is a schematic structural diagram of a chip according to an embodiment of the present disclosure;
fig. 7 is a schematic structural diagram of a communication system according to an embodiment of the present application;
fig. 8 is a schematic structural diagram of a communication device according to an embodiment of the present application;
fig. 9 is a schematic structural diagram of a computer-readable storage medium according to an embodiment of the present application.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments in the present application without making creative efforts shall fall within the protection scope of the present application.
According to various embodiments of the present Application, the term "module" refers to, but is not limited to, a software or hardware component, such as a software or hardware component based on a Field Programmable Gate Array (FPGA) or an Application Specific Integrated Circuit (ASIC) design to perform some task. The term "couple" and its derivatives refer to any direct or indirect communication between two or more modules, whether or not those modules are in physical contact with one another. The character "/" is inclusive, meaning and/or. Relational terms such as "first" and "second," and the like, may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. The terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element. The phrase "in relation to," and derivatives thereof, means including, being included within, interconnected with, connected to, or connected to, coupled to, or coupled with, communicable, cooperative with, joined with, or joined with, having.
The preferred embodiments are described below with reference to the accompanying drawings.
In a 5G-NR communication system, when receiving transmission data sent by a User Equipment (UE), a communication device needs to perform noise interference analysis, that is, CHannel estimation, on a Physical Uplink Shared CHannel (PUSCH) or a Physical Uplink Control CHannel (PUCCH) in a transmission process on a Reference Signal (RS) in the received air interface transmission data, so as to restore actual user data in the air interface transmission data, so that the communication device can analyze and process the user data subsequently. Generally, a channel estimation method mainly includes a series of processing such as extracting, denoising, and filtering a received signal, and then restoring a signal affected by various noises, attenuations, and the like during transmission back to a source signal. The channel estimation procedure in the related communication system is basically performed based on the formula 'Y = HX + W', where Y is the received signal, H is the channel value, X is the source signal, and W is the noise; since the wireless environment is complex and changeable, the signal will be subjected to various interferences in the process of propagation, when reaching the receiving end, the amplitude, phase and frequency of the signal will be changed greatly, and the receiving end cannot directly know the source user data, so that the Reference Signal (RS) directly known by both the receiving end and the transmitting end is used as the object of channel estimation, and the actual data is deduced reversely. That is, the channel estimation work actually estimates the Reference Signal (RS) that is fixedly present in the received signal based on the above formula, thereby obtaining 'H' and 'W' in the above formula, and then deduces the actual user data therefrom.
Fig. 1 is a schematic flowchart illustrating an uplink channel estimation method according to an embodiment of the present application. Fig. 2 is a schematic structural diagram of an application scenario according to an embodiment of the present application.
The uplink channel estimation method provided by the embodiment of the application is applied to a communication system, the communication system comprises a digital signal processing module and N accelerators, and N is a positive integer greater than 1; the N accelerators and the digital signal processing module execute the following steps:
in step 101, each accelerator of the N accelerators receives parameter information correspondingly issued by the digital signal processing module.
It can be understood that the N accelerators are mainly used for completing the complex data processing of the channel estimation in each flow step under the instruction of a digital signal processing module (DSP); on one hand, the digital signal processing module (DSP) receives the processing progress fed back by the N accelerators to schedule the N accelerators, and on the other hand, the DSP can also receive data and parameters which are difficult to process by the N accelerators to perform assistant operation processing, so that the N accelerators complete the processing of each step flow of channel estimation under the assistance of the digital signal processing module (DSP). The parameter information contains corresponding parameter information required by the accelerator to work, and the parameter information comprises configuration parameters, wherein the configuration parameters comprise but are not limited to a user number, the RB number of the user, the RB position index of the user, the subcarrier number, the RS symbol number and the like; besides the basic configuration parameters, the parameter information may also include operation results obtained by processing the processing data and the processing parameters reported by the accelerators by a digital signal processing module (DSP), such as frequency domain interpolation matrix coefficients, time domain interpolation matrix coefficients, and the like obtained by performing operations according to noise correlation values and power delay spectrum data reported by a certain accelerator.
102, acquiring required data to be input by each accelerator according to the received parameter information, processing the data, and outputting respective processing data and processing parameters; processing data output by each accelerator is interacted among the accelerators, and processing parameters output by each accelerator are reported to the digital signal processing module; the data to be input acquired by each accelerator is frequency domain data input externally or processing data output by each accelerator; the parameter information received by each accelerator except the first accelerator in the N accelerators comprises an operation result obtained after the reported processing parameters are processed by the digital signal processing module; the processing data output from each accelerator includes at least a first processing result after demapping as a channel estimation result, a second processing result after inversion of the noise covariance matrix, and channel value data after demapping.
It should be noted that each of the N accelerators is divided to implement different functions, and by dividing the different functions, the channel estimation process can be simplified to a certain extent, the digital signal processing module (DSP) uses a preset condition as a scheduling interval to implement the enabling operation of each accelerator, such as completing the processing of a symbol data or completing the processing of a user data, and each accelerator performs the enabling operation based on the indication of the digital signal processing module (DSP), thereby implementing the efficient operation of each accelerator. Each accelerator outputs respective processing data and processing parameters after completing operations, and the processing data and the processing parameters both represent operation results obtained after each accelerator performs related function operations on data to be input, so that, relatively speaking, the outputs of the accelerators in the embodiment of the present application are divided into two types: processing data and processing parameters; the space occupied by the processed data relative to the processing parameters is larger, the data transmission interaction is carried out on the processed data among the N accelerators, the acquisition efficiency is improved, and the time delay is reduced; the processing parameters are reported to a digital signal processing module (DSP), and then are issued to the corresponding accelerator by the digital signal processing module (DSP); for example, the processing data may be an operation result obtained after inverse fourier transform, an operation result obtained after demapping, an operation result obtained after noise covariance matrix inversion, a generated local reference sequence, and the like, and the processing parameter may be a frequency offset estimation value obtained after frequency offset estimation processing, a shift factor obtained after inverse fourier transform, a position index address corresponding to each processing data, and the like.
In the step, N accelerators and a digital signal processing module act together to complete a series of operation processing of channel estimation, and finally, processing data and processing parameters related to a user are obtained, and the processing data and the processing parameters can be subjected to subsequent channel equalization processing to restore user data.
Therefore, according to the uplink channel estimation method of the embodiment of the application, the digital signal processing module provides parameter information corresponding to the N accelerators, and the N accelerators perform a series of processing of channel estimation on externally input frequency domain data or processing data output by each accelerator according to respective parameter information under the instruction of the digital signal processing module, and obtain channel estimation results such as a first processing result after demapping, a second processing result of noise covariance matrix inversion, channel value data after demapping, and the like, and provide required processing data and/or processing parameters for subsequent channel equalization processing; each of the N accelerators is divided into different functions, processes respective data to be input and outputs respective processing data and processing parameters, so that the digital signal processing module processes the processing data and the processing parameters or instructs other accelerators to acquire the processing data and the processing parameters for processing; according to the uplink channel estimation method, through interaction between the digital signal processing module and the N accelerators, the efficiency of the digital signal processing module can be optimized, the N accelerators are scheduled to realize complex operation processing in the channel estimation processing process, meanwhile, the digital signal processing module also receives data and parameters which are difficult to process by the N accelerators to assist in processing, and the received data of different users are processed in an orderly and parallel mode, so that the overall efficiency of uplink channel estimation is improved, and the overall hardware performance is further improved. The chip based on the embodiment of the application comprises the N accelerators, interacts with the digital signal processing module, and can process data of different users in sequence and in parallel, so that the overall efficiency of uplink channel estimation is improved, and the overall hardware performance is improved.
To further improve the overall efficiency, referring to fig. 2, in an alternative embodiment, the N accelerators include a first accelerator, a second accelerator, and a third accelerator, and the first accelerator, the second accelerator, the third accelerator, and the digital signal processing module execute the following steps:
step 201, the digital signal processing module issues parameter information of the first accelerator, and schedules the first accelerator for processing by using a symbol as a unit.
Step 202, the digital signal processing module issues the parameter information of the second accelerator, and schedules the second accelerator for processing by taking the user as a unit.
Step 203, the digital signal processing module issues the parameter information of the third accelerator, and schedules the third accelerator for processing by taking the user as a unit.
Step 201 and step 203 show that the digital signal processing module schedules the first accelerator to work by taking the symbol as a unit, so that the first accelerator can start the reading processing of the data when receiving the RS symbol data of one user, and the processing is started without completely receiving all the RS symbol data of the users, thereby achieving the effect of responding in time and processing quickly and shortening the processing time; the digital signal processing module schedules the second accelerator and the third accelerator to work in units of users, so that the second accelerator and the third accelerator perform processing based on data of one user.
Further, in this embodiment of the application, after the N accelerators complete the processing, the completion signal is reported in units of users, so that the digital signal processing module can know the completion condition of the current user data. Specifically, before the digital signal processing module in step 203 issues the parameter information of the third accelerator and schedules the third accelerator for processing by using the user as a unit, the method includes:
step 301, the first accelerator reports a completion signal to the digital processing module in units of users to instruct the digital processing module to schedule the second accelerator or the third accelerator for processing.
Step 302, the second accelerator reports a completion signal to the digital processing module in units of users to instruct the digital processing module to schedule the third accelerator for processing.
The digital signal processing module in step 203 issues parameter information of the third accelerator, and after scheduling the third accelerator for processing by using the user as a unit, the method further includes:
step 303, the third accelerator reports a completion signal to the digital processing module in units of users to instruct the digital processing module to perform processing.
That is, the digital signal processing module issues parameter information to indicate the accelerator to work, the work of scheduling the accelerator is performed by using symbols as scheduling units or using users as scheduling units, and after respective processing is completed, the N accelerators report completion signals to the digital processing module by using users as units. The scheduling unit in the embodiment of the present application may refer to a scheduling interval. Specifically, the digital signal processing module issues parameter information to the first accelerator by taking the symbol as a scheduling unit, so that the reading processing of starting data of the first accelerator can be scheduled when RS symbol data of one user is received, the starting processing is not required to be completed by receiving all RS symbol data of the users, the effect of responding to the data in time and processing rapidly can be achieved, and the processing time can be shortened; after completing the processing of all RS symbol data of a user, the first accelerator reports a completion signal to the digital signal processing module, so that the digital signal processing module can perform correlation processing and schedule the second accelerator and the third accelerator to perform subsequent processing on the data of the user, for example, a user has 2 RS symbol data, the digital signal processing module schedules the first accelerator for 2 times by using the symbol as a scheduling unit, obtains the related data and processing parameters of the user after the first accelerator completes the processing for 2 times, and reports the completion signal to the digital signal processing module. The digital signal processing signal enables the second accelerator and the third accelerator by taking a user as a scheduling unit, and the second accelerator and the third accelerator report to the digital signal processing module after completing all data processing of one user. After the third accelerator completes the processing, some series of processing of channel estimation is completed, and a user-based channel estimation processing result can be obtained by combining the processing data and the processing parameters output by the second accelerator.
In order to further improve the channel estimation efficiency and the overall performance, the hardware architecture and the method flow are re-optimized and designed.
Aspects are re-optimized for the method flow. In an alternative embodiment, fig. 3, 4 and 5 are schematic diagrams illustrating processing flows of several accelerators provided in the embodiment of the present application, and processing flow steps of a first accelerator, a second accelerator and a third accelerator are correspondingly indicated in the embodiment of the present application. As shown in fig. 3, 4 and 5, the primary function of the first accelerator is to perform LS channel estimation processing and frequency offset estimation processing, the secondary accelerator is to perform error correction processing on the input data, the tertiary accelerator is to perform noise suppression and filtering processing based on MMSE rule, and the whole channel estimation process is calculated and processed around the Reference Signal (RS) and based on the formula Y = HX + W to obtain the channel estimation parameters or results of the actual user data. Specifically, the execution of the first accelerator, the second accelerator, the third accelerator and the digital signal processing module further includes the following steps:
step 401, a first accelerator acquires externally input frequency domain data as data to be input, and performs symbol extraction processing, LS channel estimation processing and inverse fourier transform processing to obtain and output first processed data after symbol extraction processing and second processed data after inverse fourier transform processing; wherein the first processed data and the second processed data are respectively related to a reference signal of a user.
Step 402, the second accelerator acquires the first processing data as data to be input, performs time-frequency offset compensation processing and demapping processing, and acquires and outputs third processing data and fourth processing data after demapping processing; wherein the third processed data is related to a reference signal of the user, the fourth processed data is related to user data, and the fourth processed data is output as a first processing result.
Step 403, the third accelerator acquires the second processed data and the third processed data as data to be input, and performs noise interference estimation processing and noise correlation matrix inversion processing to obtain and output fifth processed data after the noise correlation matrix inversion processing; wherein the fifth processed data is output as the second processing result.
With continued reference to fig. 3, for the method flow re-optimization aspect, the executing of the first accelerator, the second accelerator, the third accelerator and the digital signal processing module further includes:
step 501, a first accelerator acquires frequency domain data input from outside as data to be input, and performs symbol scaling, LS channel estimation, frequency offset estimation and inverse fourier transform to obtain and report a first processing parameter to a digital signal processing module; the first processing parameter comprises a scaling factor after the symbol scaling processing, a frequency offset estimation value after the frequency offset estimation processing and a shifting factor after the inverse Fourier transform processing.
Step 502, the digital signal processing module generates parameter information corresponding to the second accelerator or parameter information corresponding to the third accelerator according to the first processing parameter, so as to instruct the second accelerator or the third accelerator to perform processing.
In the above steps 401-403 and 501-502, in the embodiment of the present application, a series of step processing of channel estimation is completed by three accelerators in a labor-sharing manner, so that the method of channel estimation process can be simplified to a great extent, and the situation that the longer the processing flow of the accelerator, the lower the scheduling efficiency of a digital signal processing module (DSP) is avoided; and through the function division of each accelerator, the accelerator can well interact with the digital signal processing module, so that the scheduling efficiency of the digital signal processing module is improved, and the efficiency of the whole channel estimation process is improved. The results output by each accelerator in the embodiment of the application are divided into processing data and processing parameters, and relatively speaking, the space occupied by the processing parameters relative to the processing data in the embodiment of the application is larger, so that the design can optimize the processing efficiency among a digital signal processing module (DSP), each accelerator and each accelerator, and effectively reduce the processing time delay. Data transmission interaction is carried out on the processing data output by the three accelerators among the three accelerators, for example, the second accelerator and the third accelerator can acquire the processing data of the first accelerator as data to be processed according to parameter information sent by a digital signal processing module (DSP), so that the acquisition efficiency is improved, and the time delay is reduced; processing parameters output by the three accelerators are reported to a digital signal processing module (DSP), and are processed by the DSP and then are issued to the corresponding accelerators, so that the fast scheduling efficiency is realized.
In an optional embodiment, with continuing reference to fig. 3, the first accelerator further performs noise estimation processing, mainly to calculate a noise value, and the digital signal processing module may assist in processing some data or parameters that are difficult to process or slow to process in the accelerator, so as to improve the overall efficiency. Specifically, the execution of the first accelerator, the second accelerator, the third accelerator and the digital signal processing module further includes the following steps:
step 601, the first accelerator obtains second processed data after the inverse fourier transform processing, performs noise estimation processing on the second processed data to obtain sixth processed data, and reports the sixth processed data to the digital signal processing module.
Step 602, the digital signal processing module performs noise-related coefficient calculation processing based on the sixth processing data to obtain a second processing parameter, and generates parameter information corresponding to the third accelerator based on the second processing parameter; wherein the second processing parameter is related to the frequency domain interpolation matrix coefficient and the time domain interpolation matrix coefficient.
In the embodiment of the present application, for example, CHannel estimation of a Physical Uplink Shared CHannel (PUSCH) is used, noise estimation processing may be performed based on Power Delay Profile (PDP), inverse fourier transform processing converts current data into time domain data, noise estimation processing is performed after inverse fourier transform processing, and a noise correlation value obtained by the noise estimation processing and the PDP data are reported to a digital signal processing module, and the digital signal processing module performs noise correlation coefficient calculation processing, so that overall processing efficiency can be improved.
In step 601, the first accelerator obtains second processed data after the inverse fourier transform, performs noise estimation processing on the second processed data to obtain sixth processed data, and reports the sixth processed data to the digital signal processing module, which specifically includes the following steps:
and 701, the first accelerator performs power delay spectrum calculation processing on the second processing data to obtain first intermediate data.
Step 702, the first accelerator performs power delay spectrum noise estimation processing and power delay spectrum noise removal processing on the first intermediate data to obtain a noise correlation value and power delay spectrum data.
Step 703, the first accelerator reports the noise correlation value and the power delay spectrum data to the digital signal processing module for processing; and outputting the power time delay spectrum data as sixth processing data.
Furthermore, actual user data may exist in a plurality of RS symbol data, and the first accelerator needs to process all RS symbol data of one user, and needs to perform a combining process when calculating the power delay spectrum of the user. That is, the first accelerator in step 701 performs power delay profile calculation processing on the second processed data to obtain first intermediate data, including the following steps:
step 801, performing power delay spectrum calculation processing on the second processing data to obtain a plurality of second intermediate data; wherein the second intermediate data relates to a reference signal of the user and symbol data of the user.
And step 802, after the last second intermediate data is obtained, merging the second intermediate data to obtain the first intermediate data.
In this embodiment of the present application, the last second intermediate data refers to an operation result obtained by the first accelerator performing power delay spectrum calculation processing on the last symbol data of the user. In the process of calculating the power delay profile, merging may be completed after the last intermediate data is obtained, or merging may be completed after one intermediate data is obtained and merging is completed after the last second intermediate data is obtained, and in order to achieve the same purpose, power delay Profile Data (PDP) corresponding to the user is also obtained.
In an alternative embodiment, there may be a multi-port multiplexing situation, where multi-port multiplexing may be simply understood as that each antenna data is divided into multiple layers, and each layer receives data of different users, so that decoding-division multiplexing (FD-CDM) processing is required to perform decoding-division multiplexing on the data of each port of each antenna. Referring to fig. 3, in this embodiment of the application, the dsp module may instruct the first accelerator whether to perform demultiplexing on the current data, and the first accelerator may perform corresponding processing on the data according to the instruction of the dsp module. Specifically, in the case that the multi-port multiplexing exists, the executing of the first accelerator, the second accelerator, the third accelerator and the digital signal processing module further includes:
step 901, the digital signal processing module generates parameter information corresponding to the first accelerator, where the parameter information corresponding to the first accelerator further includes an identification parameter for indicating the decoding multiplexing processing;
step 902, the first accelerator determines whether to perform decoding multiplexing processing on currently acquired data to be input according to the identification parameter, and according to a determination result, the following two situations, namely step 902a and step 902b, exist, as follows:
step 902a, when the first accelerator determines that the decoding multiplexing processing is required, performing the decoding multiplexing processing on the third intermediate data by using the data after the LS channel estimation processing as the third intermediate data to obtain fourth intermediate data; and performing inverse Fourier transform processing or frequency offset estimation processing on the fourth intermediate data.
In this step, if there is a multi-port multiplexing situation, the data obtained after the LS channel estimation processing is subjected to the addition averaging or subtraction averaging according to different ports. For example, there is two-port multiplexing, and for the first port 0, the following formula is used to calculate:
where r denotes a receiving antenna, k denotes a subcarrier index, l denotes the number of layers,
the channel estimation values obtained after least squares channel estimation are shown.
For the second port 1, the calculation can be made by the following formula:
where r denotes a receiving antenna, k denotes a subcarrier index, l denotes the number of layers,
representing the channel estimate obtained after least squares channel estimation.
And step 902b, under the condition that the first accelerator judges that the decoding division multiplexing processing is not needed, taking the data after the LS channel estimation processing as third intermediate data, and directly performing inverse Fourier transform processing or frequency offset estimation processing on the third intermediate data.
In this step, if there is no multiport multiplexing, the data after LS channel estimation is directly transmitted, and the inverse fourier transform processing and the frequency offset estimation processing are directly performed, which may be calculated by using the following formula:
wherein, the first and the second end of the pipe are connected with each other,
the channel estimation value obtained after least square channel estimation is shown, and p is indicated as a port.
In an optional embodiment, referring to fig. 3, based on consideration of efficiency and processing delay, in the uplink channel estimation method according to the embodiment of the present application, the step of generating the local reference sequence is designed and processed in the first accelerator, the generated local reference sequence is mainly used in the LS channel estimation processing procedure and the noise interference estimation processing procedure, the first accelerator generates and outputs the local reference sequence, and the third accelerator can acquire the local reference sequence for processing without repeated operation, so that the process is more optimized. For the step flow of generating the local reference sequence, specifically, the execution of the first accelerator, the second accelerator, the third accelerator and the digital signal processing module further includes the following steps:
step 1001, the first accelerator generates and outputs a local reference sequence for a third accelerator to obtain and perform noise interference estimation processing.
Step 1002, the first accelerator performs LS channel estimation processing based on the local reference sequence and frequency domain data input from outside.
In an alternative embodiment, referring to fig. 4, the second accelerator performs time-frequency offset compensation and demapping on the input frequency-domain data in addition to the time-frequency offset compensation and demapping on the first processed data after the symbol extraction processing performed by the first accelerator, so as to perform error correction on the reference signal channel and the data segment. The first processed data is actually an operation result extracted based on symbol data where the Reference Signal (RS) is located. Specifically, for the second accelerator, the uplink channel estimation method according to the embodiment of the present application further includes the following steps:
step 1101, the second accelerator acquires frequency domain data input from outside as data to be input, and performs symbol scaling processing, time-frequency offset compensation processing and demapping processing to obtain seventh processed data; wherein the seventh processed data is related to the user data and the seventh processed data is output as the first processing result.
As above, it can be understood that the second accelerator is divided into two processing flows: and one path of data receiving the first processing data of the first accelerator, performing time-frequency offset compensation processing and demapping processing on the first processing data, and dividing Reference Signal (RS) data and user data in the frequency domain data subjected to symbol extraction processing at the time, wherein the Reference Signal (RS) data can be output to a third accelerator for noise estimation processing, and the user data can be output to a subsequent processing flow as a final processing result for channel equalization processing and other steps. And the other path receives frequency domain data (namely IQ data) input from the outside, and performs symbol scaling, time-frequency offset compensation and demapping on the data to obtain user data in the frequency domain data, wherein the user data can also be output to a subsequent processing flow as a final processing result to perform channel equalization processing and other steps. Therefore, the time-frequency offset compensation processing and the demapping processing of the original frequency domain data and the frequency domain data after symbol extraction processing are divided into the same accelerator, the whole step flow is optimized, and the processing efficiency can be effectively improved.
In an alternative embodiment, referring to fig. 2 and 5, the third accelerator may function primarily to filter, noise estimate and user data parsing the second processed data output by the first accelerator, where the second processed data is also substantially channel value data based on the reference signal. Specifically, the execution of the first accelerator, the second accelerator, the third accelerator and the digital signal processing module further includes the following steps:
step 1201, the digital signal processing module calculates to obtain a frequency domain interpolation matrix coefficient and a time domain interpolation matrix coefficient according to the processing data and the processing parameters reported by the first accelerator, and generates parameter information of the third accelerator based on the frequency domain interpolation matrix coefficient and the time domain interpolation matrix coefficient.
And 1202, the third accelerator acquires second processing data as data to be input according to the parameter information of the third accelerator, and performs fourier transform processing, interpolation filtering processing and demapping processing to obtain and output channel value data after demapping processing.
Further, referring to fig. 5, in step 1202, the third accelerator acquires second processing data as data to be input according to parameter information of the third accelerator, and performs fourier transform processing, interpolation filter processing, and demapping processing to obtain and output channel value data after the demapping processing, including:
step 1301, performing time domain channel denoising processing and channel time offset compensation processing on the second processed data to obtain a fifth intermediate result;
step 1302, performing fourier transform processing, time-frequency offset compensation processing, frequency domain noise suppression filtering processing and time domain noise suppression filtering processing on the fifth intermediate result to obtain a sixth intermediate result; wherein the sixth intermediate result is related to a reference signal of the user;
step 1303, performing frequency domain interpolation filtering processing and time domain interpolation filtering processing on the sixth intermediate result to obtain seventh intermediate processing data;
and 1304, performing demapping processing on the seventh intermediate processing data to obtain channel value data subjected to demapping processing.
In this step, the parameter information received by the third accelerator includes configuration parameters required for performing each step in the third accelerator, such as a frequency offset estimation value, a time offset estimation value, a noise-removal position index, a frequency domain interpolation matrix coefficient, a time domain interpolation matrix coefficient, and the like, which are processed by a digital signal processing module (DSP). The third accelerator performs time offset compensation and denoising on the input time domain data after inverse Fourier transform processing, performs Fourier transform processing on the data, converts the time domain data into frequency domain data, facilitates subsequent filtering processing, and the frequency domain data obtained by conversion at this time is actually channel value data based on the reference signal. And performing time-frequency offset noise suppression processing on the data subjected to the FFT operation, wherein the matrix operation is mainly performed on the data obtained after the FFT operation based on the frequency domain interpolation matrix coefficient and the time domain interpolation matrix coefficient, so that the noise suppression filtering operation is completed. Meanwhile, time-frequency domain interpolation filtering processing is continued based on the frequency domain interpolation matrix coefficient and the time domain interpolation matrix coefficient, and the currently obtained channel value data based on the reference signal is restored to the channel value data of the whole resource grid; then, the channel value data of the resource grid is subjected to demapping processing, so that channel value data corresponding to the current user data is obtained, and the channel value data is output to provide required data for subsequent channel equalization processing.
With continued reference to FIG. 5, the third accelerator primary function further includes the computation of a noise covariance matrix test value, i.e., a noise correlation matrix inversion process, on the reference signal based data output by the second accelerator. Further, in this embodiment of the application, after performing, in the step 1302, fourier transform processing, time-frequency offset compensation processing, frequency domain noise suppression filtering processing, and time domain noise suppression filtering processing on the fifth intermediate result to obtain a sixth intermediate result, the following steps are further included:
and 1401, performing noise interference estimation processing on the sixth intermediate result and the third processed data by using the third accelerator to obtain seventh intermediate processed data.
And 1402, the third accelerator performs noise correlation matrix inversion processing on the seventh intermediate processed data to obtain and output fifth processed data.
It can be understood that, after the noise suppression and filtering are completed by the third accelerator, the third accelerator is divided into two paths: one path is subjected to interpolation filtering processing and demapping processing, namely data segment channel interpolation estimation is carried out, and relevant channel value data after interpolation are subjected to demapping on the basis of a user to obtain channel value data corresponding to user data; and the other path performs noise interference estimation and RUU (which refers to a correlation matrix of noise, interference and a vector) inversion calculation, in the noise interference estimation process, a result of the noise interference estimation is obtained based on frequency domain data which is output by the second accelerator and is related to the reference signal, the obtained channel value data of the corresponding user data, and the like, and then the result of the noise interference estimation is used for RUU inversion to obtain an inversion result, that is, fifth processed data after the noise correlation matrix inversion processing is obtained.
Aiming at the optimization of the hardware architecture, the re-optimization of the method flow and the consideration of the transmission delay and the processing efficiency, the operation result output by each accelerator is divided into processing data and processing parameters, relatively speaking, the space occupied by the processing parameters relative to the processing data in the embodiment of the application is larger, the processing data output by each accelerator can be acquired by other accelerators and correspondingly operated, the processing parameters output by each accelerator are uniformly reported to the digital signal processing module, and the processing parameters are processed by the digital signal processing module and then are issued to the corresponding accelerator to correspondingly operate. Therefore, when the hardware architecture is designed, a cache bus module and an enhanced bus module are also arranged in the communication system, so that transmission interaction between the accelerator and between the accelerator and the digital signal processing module can be better optimized, and the processing efficiency is improved.
Specifically, referring to fig. 2, in an alternative embodiment, the communication system is further provided with a cache bus module, and each accelerator of the N accelerators is connected to the cache bus module, so that the processing data output by each accelerator interacts among the accelerators. The N accelerators and the cache bus module are realized based on the field programmable gate array design. Therefore, in step 102, each accelerator acquires required data to be input according to the received parameter information, processes the data, and outputs respective processing data and processing parameters, which includes the following steps:
step 1501, each accelerator acquires the required data to be input from the cache bus module according to the received parameter information, and processes the data to obtain respective processing data.
In step 1502, each accelerator stores its own processing data in the cache bus module for processing by other accelerators.
Furthermore, the communication system is also provided with an enhanced bus module, and each accelerator and the digital signal processing module in the N accelerators are respectively connected with the enhanced bus module so as to realize data transmission interaction between the digital signal processing module and the N accelerators; in step 102, each accelerator acquires required data to be input according to the received parameter information, processes the data, and outputs respective processed data and processing parameters, which includes the following steps:
step 1601, each accelerator acquires the required data to be input according to the parameter information received from the enhanced bus module, and processes the data to obtain processing parameters.
In step 1603, each accelerator reports the processing parameters to the digital signal processing module via the enhanced bus module, so that the digital signal processing module can process the processing parameters.
It should be noted that, when the digital signal processing module receives some data and parameters that are difficult to be processed by the N accelerators for assisting processing, the N accelerators can also report to the digital signal processing module through the enhanced bus module, as in the above application embodiment, the first accelerator can report the noise correlation value and the power delay spectrum data to the digital signal processing module through the enhanced bus module, instruct the digital signal processing module to perform operation to obtain a frequency domain interpolation matrix coefficient, a time domain interpolation matrix coefficient, and the like, and then issue the frequency domain interpolation matrix coefficient and the time domain interpolation matrix coefficient to the corresponding accelerators for processing.
Referring to fig. 2, in an optional embodiment, each of the N accelerators is provided with a receiving module and a parameter reporting module, the receiving module receives an instruction from the digital signal processing module through the enhanced bus module to trigger the accelerator to operate, and the parameter reporting module outputs a processing parameter obtained by computing the accelerator corresponding to the receiving module through the enhanced bus module to the digital signal processing module.
In the embodiment of the present application, N accelerators may be implemented based on the same field programmable gate array design or different field programmable gate array designs, and a cache bus module and an enhanced bus module are simultaneously designed, where the cache bus module may be used to store/call processing data of each accelerator, and the enhanced bus module may establish interaction between the digital signal processing module and the N accelerators. The N accelerators are used as independent hardware accelerators to perform corresponding operation on input data, respective processing data and processing parameters can be generally obtained, and the processing data can be subjected to data transmission interaction among the N accelerators through the arranged cache bus module, so that the acquisition efficiency is improved, and the time delay is reduced; through the arranged enhanced bus module, after the processing of the N accelerators is finished, the processing parameters are reported to a digital signal processing module (DSP) through the enhanced bus by taking a user as a unit, the digital signal processing module (DSP) processes the reported processing parameters to generate parameter information corresponding to the accelerators, and then the parameter information is transmitted to the corresponding accelerators through the enhanced bus module, so that the unified indication of the digital signal processing module is realized, the accelerators perform corresponding operation, and the uplink channel estimation efficiency is improved.
Fig. 6 is a schematic structural diagram of a chip provided in an embodiment of the present application.
Referring to fig. 6, N accelerators are disposed in the chip 600, and the chip 600 and the digital signal processing module 670 establish data transmission interaction; the chip 600 may establish a communication mechanism with the digital signal processing module 670 based on an SIRO protocol interface, the digital signal processing module 670 implements unified indication on N accelerators in the chip 600, the chip 600 receives parameter information issued by the digital signal processing module 670, and each of the N accelerators receives the parameter information issued correspondingly by the digital signal processing module 670; each accelerator acquires required data to be input according to the received parameter information for processing, and outputs respective processing data and processing parameters; the processing data output by each accelerator is interacted among the accelerators, and the processing parameters output by each accelerator are reported to the digital signal processing module 670. The data to be input acquired by each accelerator is frequency domain data input from the outside or processing data output by each accelerator. The parameter information received by each accelerator, except the first accelerator, of the N accelerators includes the operation result of the digital signal processing module 670 after processing the reported processing parameter; the processing data output from each accelerator includes at least a first processing result after demapping as a channel estimation result, a second processing result after inversion of the noise covariance matrix, and channel value data after demapping.
Based on the chip 600 of the embodiment of the present application, N accelerators are divided in the chip 600, and under the instruction of the digital signal processing module 670, the N accelerators perform a series of processing of channel estimation on externally input frequency domain data or processing data output by each accelerator according to respective received parameter information, and obtain a first processing result after demapping processing, a second processing result of noise covariance matrix inversion, and channel estimation results such as channel value data after demapping processing, so as to provide required processing data and/or processing parameters for subsequent channel equalization processing; different functions are divided by each accelerator in the N accelerators, so that the efficiency of the digital signal processing module 670 can be optimized, the complex operation processing in the channel estimation processing process can be realized efficiently, meanwhile, the digital signal processing module 670 can be cooperated with the N accelerators efficiently, the received data of different users can be processed orderly and parallelly, the overall efficiency of uplink channel estimation is improved, and the overall hardware performance is improved.
In an alternative embodiment, the chip 600 may be based on a Field Programmable Gate Array (FPGA) chip or an Application Specific Integrated Circuit (ASIC) chip. The chip 600 may specifically include a first accelerator 610, a second accelerator 620, and a third accelerator 630, where the first accelerator 610 may be configured to perform LS channel estimation processing and frequency offset estimation processing, the second accelerator 620 may be configured to perform de-skew processing on input data, the third accelerator 630 may be configured to perform noise suppression and filtering processing based on MMSE rule, and the method for the chip 600 to implement channel estimation processing mainly surrounds a Reference Signal (RS) and performs calculation and processing based on the formula Y = HX + W to obtain a channel estimation parameter or result of actual user data. Referring to fig. 6, in an alternative embodiment, chip 600 may also include an equalization accelerator 640 for channel equalization processing. In order to realize data transmission interaction among the N accelerators and interaction between the accelerators and the digital signal processing module 670, referring to fig. 6, in an alternative embodiment, a cache bus module 650 and an enhanced bus module 660 are further designed in the chip 600, and the cache bus module 650 is connected with the N accelerators to realize interaction between the accelerators of processing data output by the accelerators; the N accelerators are connected to the digital signal processing module 670 through the enhanced bus module 660 to report the processing parameters output by each accelerator to the digital signal processing module 670. Each optional accelerator is used as an independent hardware accelerator, each accelerator may be provided with a receiving module and a parameter reporting module, which are in butt joint with the outside, and the parameter reporting module of each accelerator outputs processing parameters obtained by the operation of the corresponding accelerator to the digital signal processing module 670 through the enhanced bus.
In an alternative embodiment, the primary functions of the first accelerator 610 are LS channel estimation and frequency offset estimation. The first accelerator 610 schedules the symbol unit, and after completing the symbol data processing of one user amount, the first accelerator 610 reports a user completion signal to the digital signal processing module 670 in the user unit, and instructs the digital signal processing module 670 to schedule the second accelerator 620 and the third accelerator 630. It is understood that the first accelerator 610 mainly implements functions including the following:
Secondly, the data obtained after RS extraction processing is stored in the cache bus module, and LS channel estimation and de-coding multiplexing (FD-CDM) is performed inside the first accelerator 610 to obtain channel value data based on Reference Signals (RS) for each user, each layer, and each port.
Channel value data based on a Reference Signal (RS) is subjected to IFFT processing to convert frequency domain data into a time domain, and then pdp (power Delay profile) calculation processing is performed, and data obtained after IFFT processing is output to a cache bus module for processing by the third accelerator 630.
And fourthly, after the Power Delay Profile is processed by the PDP, the noise correlation value and the PDP Power Delay Profile data can be obtained, reported to the digital signal processing module via the enhanced bus, and processed by the digital signal processing module 670 (DSP) to obtain noise correlation information and filter coefficients, such as a frequency domain interpolation matrix coefficient, a time domain interpolation matrix coefficient, and the like, and sent to the third accelerator 630 via the enhanced bus module to perform corresponding denoising and filtering processing.
Specifically, the first accelerator 610 in the chip may be a functional step of the first accelerator 610 for implementing the channel estimation method according to the embodiment of the application, which may be seen in fig. 3 and the embodiment of the method described above, and based on the same inventive concept, repeated parts are not repeated.
In an alternative embodiment, the secondary accelerator 620 functions primarily to deskew the RS channels and data segments. The scheduling and reporting of the second accelerator 620 are performed in units of users, each time data processing of one user amount is completed, the data processing is reported to the digital signal processing module 670 through the enhanced bus module, and the digital signal processing module 670 schedules the third accelerator 630 to work according to the reporting conditions of the first accelerator 610 and the second accelerator 620, that is, the third accelerator 630 is scheduled to work after the first accelerator 610 and the second accelerator 620 both complete the same user data. It is understood that the flow of steps mainly implemented by the second accelerator 620 is divided into two paths as follows:
firstly, one path of data obtained after RS extraction processing output by the first accelerator 610 is obtained from the cache bus module, time-frequency offset compensation processing is performed, demapping processing is performed based on a Reference Signal (RS) and demapping processing is performed based on user data, and therefore Reference Signal (RS) data and user data in the data obtained after RS extraction processing are divided. Reference Signal (RS) data is stored in the buffer bus module for noise estimation processing after being acquired by the third accelerator 630, and user data is also stored in the buffer bus module for equalization processing by the equalizer accelerator 640.
And secondly, the other path of the data is used for acquiring frequency domain data provided by external input from the buffer bus module, performing symbol scaling, time-frequency offset compensation and demapping processing based on user data on the frequency domain data to obtain user data in the frequency domain data of the external input, and outputting the user data to the balance accelerator 640 for subsequent processing.
Specifically, the second accelerator 620 of the chip may be a functional step of the second accelerator 620 for implementing the channel estimation method in the foregoing application embodiment, which may be referred to fig. 4 and the foregoing method embodiment, and repeated parts are not repeated one by one based on the same inventive concept.
In an alternative embodiment, the third accelerator 630 mainly functions as a noise suppression accelerator based on MMSE rule, and mainly functions to filter, estimate noise and parse user data from the channel values provided by the first accelerator 610. The scheduling and reporting interval of the third accelerator 630 is based on the user, and when the second accelerator 620 and the first accelerator 610 complete the processing of the current user and report the completion signal to the digital signal processing module 670 (DSP) via the enhanced bus module, the digital signal processing module 670 (DSP) will schedule the third accelerator 630 based on the user, and issue the parameter information required by the third accelerator 630 via the enhanced bus module. The third accelerator 630 reports the completion signal to the digital signal processing module 670 (DSP) via the enhanced bus module after completing the current user processing. It is understood that the main functional implementations of the third accelerator 630 include the following:
the third accelerator 630 obtains the IFFT data output by the first accelerator 610 from the buffer bus module for time offset compensation and denoising according to the parameter information sent to the third accelerator by the digital signal processing module 670 (DSP), and performs time-frequency domain conversion by FFT fourier transform processing to facilitate subsequent filtering processing.
Performing time-frequency offset noise suppression on the data after the FFT, wherein the data after the actual IFFT is related to channel value data based on a Reference Signal (RS), and the main flow of the time-frequency offset noise suppression is to perform matrix operation on the data converted by the frequency domain according to a frequency domain noise suppression matrix coefficient and a time domain noise suppression matrix coefficient so as to complete the operation of noise suppression and filtering; the frequency domain noise suppression matrix coefficient and the time domain noise suppression matrix coefficient are obtained by the digital signal processing module 670 receiving the noise correlation value reported by the first accelerator and the PDP power delay spectrum data for operation, and include the parameter information sent to the third accelerator by the digital signal processing module 670 (DSP).
Thirdly, the data after the time-frequency offset noise suppression processing and the data which is obtained from the buffer bus module and is output by the second accelerator and subjected to the demapping processing based on the reference signal are used for noise interference estimation; then, the result of the noise interference estimation is used for performing the RUU calculation inversion, and the result of the RUU calculation inversion is output to the cache bus module for the equalization processing by the equalization accelerator 640;
meanwhile, the data after the time-frequency offset noise suppression processing can continue to carry out time-frequency domain interpolation filtering processing according to the frequency domain interpolation matrix coefficient and the time domain interpolation matrix coefficient so as to restore the channel value data based on the Reference Signal (RS) into the channel value data of the whole resource grid; then, the channel value data of the resource grid is demapped according to the demapping position information indicated by the digital signal processing module 670 (DSP), so as to obtain channel value data corresponding to the user data, and the channel value data is stored in the cache bus module for the subsequent operation of the equalizer accelerator 640.
Specifically, the third accelerator 630 of the chip may be a functional step of the third accelerator 630 for implementing the channel estimation method according to the embodiment of the application, which may be seen in fig. 5 and the embodiment of the method described above, and repeated parts are not repeated one by one based on the same inventive concept.
Thus, in an alternative embodiment, when the N accelerators divide the first accelerator 610, the second accelerator 620 and the third accelerator 630, the chip 600 performs the method as follows:
the first accelerator 610 obtains frequency domain data input from outside as data to be input, and performs symbol extraction processing, LS channel estimation processing, and inverse fourier transform processing to obtain and output first processed data after symbol extraction processing and second processed data after inverse fourier transform processing; wherein the first processed data and the second processed data are respectively related to a reference signal of a user;
the second accelerator 620 acquires the first processed data as data to be input, performs time-frequency offset compensation processing and demapping processing, and acquires and outputs third processed data and fourth processed data after demapping processing; wherein the third processed data is related to a reference signal of a user, the fourth processed data is related to user data, and the fourth processed data is output as a first processing result;
the third accelerator 630 acquires the second processed data and the third processed data as data to be input, performs noise interference estimation processing and noise correlation matrix inversion processing, and obtains and outputs fifth processed data after the noise correlation matrix inversion processing; wherein the fifth processed data is output as the second processing result.
In an optional embodiment, the first accelerator 610 may further obtain externally input frequency domain data as data to be input, perform symbol scaling processing, LS channel estimation processing, frequency offset estimation processing, and inverse fourier transform processing, obtain and report a first processing parameter to the digital signal processing module 670, so that the digital signal processing module 670 generates corresponding parameter information to instruct the second accelerator 620 or the third accelerator 630 to operate; the first processing parameter comprises a scaling factor after the symbol scaling processing, a frequency offset estimation value after the frequency offset estimation processing and a shifting factor after the inverse Fourier transform processing.
In an alternative embodiment, chip 600 also performs the method as follows: the first accelerator 610 obtains second processed data after the inverse fourier transform, performs noise estimation processing on the second processed data to obtain sixth processed data, and reports the sixth processed data to the digital signal processing module 670, so that the digital signal processing module 670 generates parameter information corresponding to the third accelerator 630; the parameter information corresponding to the third accelerator 630 includes information related to the frequency domain interpolation matrix coefficient and the time domain interpolation matrix coefficient.
In an alternative embodiment, chip 600 also performs the method as follows: the first accelerator 610 performs power delay spectrum calculation processing on the second processing data to obtain first intermediate data; the first accelerator 610 performs power delay spectrum noise estimation processing and power delay spectrum noise removal processing on the first intermediate data to obtain a noise correlation value and power delay spectrum data; the first accelerator 610 reports the noise correlation value and the power delay spectrum data to the digital signal processing module 670 for processing; and outputting the power delay spectrum data as sixth processing data.
In respect of the first accelerator 610, the second accelerator 620 and the third accelerator 630 of the chip 600 cooperating with the digital signal processing module 670, in an alternative embodiment the chip 600 further performs the method as follows:
the first accelerator 610 receives the parameter information of the first accelerator 610, which is sent by the digital signal processing module 670, based on the symbol as a unit, and reports a completion signal to the digital processing module based on the user as a unit, so as to instruct the digital processing module to schedule the second accelerator 620 or the third accelerator 630 for processing.
The second accelerator 620 receives the parameter information of the second accelerator 620, which is delivered by the digital signal processing module 670, based on the unit of the user, and reports a completion signal to the digital processing module based on the unit of the user, so as to instruct the digital processing module to schedule the third accelerator 630 for processing.
The third accelerator 630 receives the parameter information of the third accelerator 630, which is sent by the digital signal processing module 670, based on the user as a unit, and reports a completion signal to the digital processing module based on the user as a unit, so as to notify the digital signal processing module 670 that the uplink channel estimation processing of the current user has been completed.
In summary, the chip 600 according to the embodiment of the present application mainly constructs an accelerator group, where N accelerators and digital signal processing modules included in the accelerator group complete a channel estimation process. The chip of the embodiment of the application is divided into the first accelerator 610, the second accelerator 620, and the third accelerator 630, and in brief, after external frequency domain data is input and Reference Signal (RS) data is extracted from the first accelerator, a series of processing is performed on the Reference Signal (RS) data at the three accelerators, and finally, user data extracted from the frequency domain data, channel value data at a user data position, and an RUU inversion result after noise interference estimation are obtained, so that the equalization accelerator can restore user data when transmitting from the externally input frequency domain user data through the data and information. The chip can be used for realizing the functional steps of the N accelerators in the channel estimation method of the embodiment of the application, and the repeated parts of the generated technical effects are not repeated one by one based on the same inventive concept.
Fig. 7 is a schematic structural diagram of a communication system according to an embodiment of the present application.
Referring to fig. 7, a communication system 700 includes a communication device 700 that includes a digital signal processing module 710, a channel estimation accelerator 720, and an equalization accelerator 730; the channel estimation accelerators 720 include N accelerators; the digital signal processing module 710 respectively implements data transmission interaction with each of the N accelerators and the equalizing accelerator, and implements data transmission interaction between the N accelerators and the equalizing accelerator 730; the uplink channel estimation method executed by the N accelerators and the digital signal processing module 710 includes: each accelerator in the N accelerators receives the parameter information correspondingly issued by the digital signal processing module; each accelerator acquires required data to be input according to the received parameter information for processing, and outputs respective processing data and processing parameters; processing data output by each accelerator is interacted among the accelerators, and processing parameters output by each accelerator are reported to the digital signal processing module; the data to be input acquired by each accelerator is frequency domain data input externally or processing data output by each accelerator; except the first accelerator, the parameter information received by each accelerator in the N accelerators comprises an operation result obtained after the digital signal processing module processes the reported processing parameters; the processing data output by each accelerator at least comprises a first processing result after de-mapping processing as a channel estimation result, a second processing result after noise covariance matrix inversion and channel value data after de-mapping processing; and taking the first processing result after demapping, the second processing result after inverting the noise covariance matrix, and the channel value data after demapping as the data to be input of the equalization accelerator 730 to perform channel equalization processing, so as to obtain a channel equalization result. Therefore, the channel estimation and channel equalization processing of the received frequency domain data (IQ data) is realized to obtain the complete data of the user.
The channel estimation Accelerator in the embodiment of the present application may include three accelerators, each Accelerator is used as an independent Hardware Accelerator, and the function of channel estimation in the physical layer is implemented by using three Hardware accelerators (Hardware accelerators), where the three accelerators are respectively a first Accelerator having an LS channel estimation function, a second Accelerator having a time frequency offset compensation function, and a third Accelerator having a noise suppression function based on an MMSE rule; the precondition for the operation of each accelerator is as follows: the digital signal processing module (DSP) 710 and the ARM complete the contents above the MAC layer of the protocol, and the digital signal processing module (DSP) 710 needs to complete the analysis of the output data and information of each accelerator and perform scheduling and parameter configuration on each accelerator. In an alternative embodiment, the channel estimation accelerators in the embodiment of the present application include a first accelerator, a second accelerator, and a third accelerator; the first accelerator, the second accelerator, the third accelerator and the digital signal processing module (DSP) 710 perform the following:
the first accelerator acquires the externally input frequency domain data as data to be input, and performs symbol extraction processing, LS channel estimation processing and inverse Fourier transform processing to obtain and output first processed data after symbol extraction processing and second processed data after inverse Fourier transform processing; wherein the first processed data and the second processed data are respectively related to a reference signal of a user;
the second accelerator acquires the first processing data as data to be input, performs time-frequency offset compensation processing and demapping processing, and obtains and outputs third processing data and fourth processing data after demapping processing; wherein the third processed data is related to a reference signal of a user, the fourth processed data is related to user data, and the fourth processed data is output as the first processing result;
the third accelerator acquires the second processed data and the third processed data as data to be input, and performs noise interference estimation processing and noise correlation matrix inversion processing to obtain and output fifth processed data after the noise correlation matrix inversion processing; wherein the fifth processed data is output as the second processing result.
In an alternative embodiment, the execution of the first accelerator, the second accelerator, the third accelerator and the digital signal processing module (DSP) 710 further includes the following:
the first accelerator acquires the externally input frequency domain data as data to be input, and performs symbol scaling processing, LS channel estimation processing, frequency offset estimation processing and inverse Fourier transform processing to obtain and report a first processing parameter to the digital signal processing module; the first processing parameter comprises a scaling factor after symbol scaling processing, a frequency offset estimation value after frequency offset estimation processing and a shifting factor after inverse Fourier transform processing;
and the digital signal processing module generates parameter information corresponding to the second accelerator or parameter information corresponding to the third accelerator according to the first processing parameter so as to instruct the second accelerator or the third accelerator to process.
In an alternative embodiment, the execution of the first accelerator, the second accelerator, the third accelerator and the digital signal processing module (DSP) 710 further includes the following:
the first accelerator receives parameter information of the first accelerator issued by the digital signal processing module based on the symbol as a unit, and reports a completion signal to the digital processing module based on the user as a unit so as to instruct the digital processing module to schedule the second accelerator or the third accelerator for processing;
the second accelerator receives parameter information of the second accelerator issued by the digital signal processing module based on the user as a unit, and reports a completion signal to the digital processing module based on the user as a unit so as to instruct the digital processing module to schedule a third accelerator for processing;
the third accelerator receives the parameter information of the third accelerator issued by the digital signal processing module based on the user as a unit, and reports a completion signal to the digital processing module based on the user as a unit so as to inform the digital signal processing module that the uplink channel estimation processing of the current user is completed.
In summary, the processing procedure of the communication system 700 according to the embodiment of the present application for the whole channel estimation can be briefly summarized as follows: after external frequency domain data are input and Reference Signal (RS) data are extracted from a first accelerator, a series of processing is carried out on the Reference Signal (RS) data in three accelerators, user data extracted from the frequency domain data, channel value data on the position of the user data and an RUU inversion result after noise interference estimation are finally obtained and then are provided to an equalization accelerator, and the equalization accelerator can restore the user data in the sending process from the externally input frequency domain user data through the data and the information. It should be noted that, the first accelerator, the second accelerator, and the third accelerator in this embodiment of the application may be processing flow steps of the first accelerator, the second accelerator, and the third accelerator in the above method embodiment, which may be referred to in any embodiment of fig. 3 to 5 and the above channel estimation method, and based on the same inventive concept, repeated parts are not repeated one by one.
Fig. 8 is a schematic structural diagram of a communication device according to an embodiment of the present application.
The communication device 800 includes a digital signal processing module 810 and N accelerators 820, and the uplink channel estimation method executed by the digital signal processing module 810 and the N accelerators 820 includes: each accelerator in the N accelerators receives the parameter information correspondingly issued by the digital signal processing module; each accelerator acquires required data to be input according to the received parameter information for processing, and outputs respective processing data and processing parameters; processing data output by each accelerator is interacted among the accelerators, and processing parameters output by each accelerator are reported to the digital signal processing module; the data to be input acquired by each accelerator is frequency domain data input externally or processing data output by each accelerator; the parameter information received by each accelerator except the first accelerator in the N accelerators comprises an operation result obtained after the digital signal processing module processes the reported processing parameters; the processing data output by each accelerator at least includes a first processing result after demapping as a channel estimation result, a second processing result after inversion of the noise covariance matrix, and channel value data after demapping, so that the overall channel estimation flow efficiency of the communication system can be improved.
In an alternative embodiment, the N accelerators may include three, a first accelerator, a second accelerator, and a third accelerator. The first accelerator, the second accelerator, the third accelerator and the digital signal processing module 810 perform the following:
the method comprises the steps that a first accelerator obtains externally input frequency domain data as data to be input, symbol extraction processing, LS channel estimation processing and inverse Fourier transform processing are carried out, and first processed data after symbol extraction processing and second processed data after inverse Fourier transform processing are obtained and output; wherein the first processed data and the second processed data are respectively related to a reference signal of a user.
The second accelerator acquires the first processing data as data to be input, performs time-frequency offset compensation processing and demapping processing to obtain and output third processing data and fourth processing data after demapping processing; wherein the third processed data is related to a reference signal of the user, the fourth processed data is related to user data, and the fourth processed data is output as a first processing result.
The third accelerator acquires the second processing data and the third processing data as data to be input, and carries out noise interference estimation processing and noise correlation matrix inversion processing to obtain and output fifth processing data after the noise correlation matrix inversion processing; wherein the fifth processed data is output as the second processing result.
In an alternative embodiment, the execution of the first accelerator, the second accelerator, the third accelerator and the digital signal processing module 810 further includes the following:
the method comprises the steps that a first accelerator obtains frequency domain data input from outside as data to be input, symbol scaling processing, LS channel estimation processing, frequency offset estimation processing and inverse Fourier transform processing are carried out, and a first processing parameter is obtained and reported to a digital signal processing module; the first processing parameter comprises a scaling factor after symbol scaling processing, a frequency offset estimation value after frequency offset estimation processing and a shifting factor after inverse Fourier transform processing;
and the digital signal processing module generates parameter information corresponding to the second accelerator or parameter information corresponding to the third accelerator according to the first processing parameter so as to instruct the second accelerator or the third accelerator to process.
In an alternative embodiment, the execution of the first accelerator, the second accelerator, the third accelerator and the digital signal processing module 810 further includes the following:
the first accelerator receives parameter information of the first accelerator issued by the digital signal processing module based on the symbol as a unit, and reports a completion signal to the digital processing module based on the user as a unit so as to instruct the digital processing module to schedule the second accelerator or the third accelerator for processing;
the second accelerator receives parameter information of the second accelerator issued by the digital signal processing module based on the user as a unit, and reports a completion signal to the digital processing module based on the user as a unit so as to instruct the digital processing module to schedule a third accelerator for processing;
the third accelerator receives the parameter information of the third accelerator issued by the digital signal processing module based on the user as a unit, and reports a completion signal to the digital processing module based on the user as a unit so as to inform the digital signal processing module that the uplink channel estimation processing of the current user is completed.
In summary, the processing procedure of channel estimation of the communication device in the embodiment of the present application can be briefly summarized as follows: after external frequency domain data are input and Reference Signal (RS) data are extracted from a first accelerator, a series of processing is carried out on the Reference Signal (RS) data in three accelerators, user data extracted from the frequency domain data, channel value data on the position of the user data and an RUU inversion result after noise interference estimation are finally obtained and then are provided to an equalization accelerator, and the equalization accelerator can restore the user data in the sending process from the externally input frequency domain user data through the data and the information. Preferably, the first accelerator, the second accelerator, and the third accelerator included in the communication device in the embodiment of the present application may be configured to execute the steps of the processing flow of the chip in the product embodiment, which may be referred to in any embodiment of fig. 6 and the chip described above (also may be referred to in any embodiment of fig. 3-5 and the channel estimation method described above), and based on the same inventive concept, repeated parts are not described again.
The embodiment of the present application further provides a computer-readable storage medium 900, on which a computer program is stored, and when the computer program is executed by a processor, the steps of the uplink channel estimation method provided in any of the foregoing method embodiments are implemented, which are not described herein again. One of ordinary skill in the art will appreciate that computer-readable media 900 may include computer storage media (or non-transitory media) and communication media (or transitory media). The term computer storage media includes volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data, as is well known to those of ordinary skill in the art. Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, Digital Versatile Disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and which can accessed by a computer. In addition, communication media typically embodies computer readable instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism and includes any information delivery media as known to those skilled in the art.
The foregoing are merely exemplary embodiments of the present invention, which enable those skilled in the art to understand or practice the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (26)
1. An uplink channel estimation method is applied to a communication system, wherein the communication system comprises a digital signal processing module and N accelerators, and N is a positive integer greater than 1; the N accelerators and the digital signal processing module execute the steps of:
each accelerator in the N accelerators receives the parameter information correspondingly issued by the digital signal processing module;
each accelerator acquires required data to be input according to the received parameter information for processing, and outputs respective processing data and processing parameters;
processing data output by each accelerator is interacted among the accelerators, and processing parameters output by each accelerator are reported to the digital signal processing module;
the data to be input acquired by each accelerator is frequency domain data input externally or processing data output by each accelerator;
the parameter information received by each accelerator except the first accelerator in the N accelerators comprises an operation result obtained after the digital signal processing module processes the reported processing parameters;
the processing data output from each accelerator includes at least a first processing result after demapping as a channel estimation result, a second processing result after inversion of the noise covariance matrix, and channel value data after demapping.
2. The method of claim 1, wherein the N accelerators include a first accelerator, a second accelerator, and a third accelerator; the first accelerator, the second accelerator, the third accelerator and the digital signal processing module execute operations comprising:
the first accelerator acquires the externally input frequency domain data as data to be input, and performs symbol extraction processing, LS channel estimation processing and inverse Fourier transform processing to obtain and output first processed data after symbol extraction processing and second processed data after inverse Fourier transform processing; wherein the first processed data and the second processed data are respectively related to a reference signal of a user;
the second accelerator acquires the first processing data as data to be input, performs time-frequency offset compensation processing and demapping processing, and obtains and outputs third processing data and fourth processing data after demapping processing; wherein the third processed data is related to a reference signal of a user, the fourth processed data is related to user data, and the fourth processed data is output as the first processing result;
the third accelerator acquires the second processed data and the third processed data as data to be input, and performs noise interference estimation processing and noise correlation matrix inversion processing to obtain and output fifth processed data after the noise correlation matrix inversion processing; wherein the fifth processed data is output as the second processing result.
3. The method of claim 1, wherein the N accelerators include a first accelerator, a second accelerator, and a third accelerator; the first accelerator, the second accelerator, the third accelerator and the digital signal processing module execute operations comprising:
the first accelerator acquires the externally input frequency domain data as data to be input, and performs symbol scaling processing, LS channel estimation processing, frequency offset estimation processing and inverse Fourier transform processing to obtain and report a first processing parameter to the digital signal processing module; the first processing parameter comprises a scaling factor after symbol scaling processing, a frequency offset estimation value after frequency offset estimation processing and a shifting factor after inverse Fourier transform processing;
and the digital signal processing module generates parameter information corresponding to the second accelerator or parameter information corresponding to the third accelerator according to the first processing parameter so as to instruct the second accelerator or the third accelerator to process.
4. The method of claim 2 or 3, wherein the first accelerator, the second accelerator, the third accelerator, and the digital signal processing module performing further comprise:
the first accelerator obtains second processed data after inverse Fourier transform processing, carries out noise estimation processing on the second processed data to obtain sixth processed data, and reports the sixth processed data to the digital signal processing module;
the digital signal processing module performs noise-related coefficient calculation processing based on the sixth processing data to obtain a second processing parameter, and generates parameter information corresponding to the third accelerator based on the second processing parameter; wherein the second processing parameter is related to a frequency domain interpolation matrix coefficient and a time domain interpolation matrix coefficient.
5. The method of claim 4, wherein the first accelerator obtains second processed data after the inverse fourier transform processing, performs noise estimation processing on the second processed data to obtain sixth processed data, and reports the sixth processed data to the digital signal processing module, and the method comprises:
the first accelerator performs power time delay spectrum calculation processing on the second processing data to obtain first intermediate data;
the first accelerator carries out power time delay spectrum noise estimation processing and power time delay spectrum noise removal processing on the first intermediate data to obtain a noise correlation value and power time delay spectrum data;
the first accelerator reports the noise correlation value and the power time delay spectrum data to the digital signal processing module for processing; and outputting the power time delay spectrum data as the sixth processing data.
6. The method of claim 5, wherein the performing, by the first accelerator, the power-time-delay spectrum calculation processing on the second processed data to obtain first intermediate data comprises:
performing power time delay spectrum calculation processing on the second processing data to obtain a plurality of second intermediate data; wherein the second intermediate data relates to a reference signal of a user, symbol data of the user;
and after the last second intermediate data is obtained, merging the plurality of second intermediate data to obtain the first intermediate data.
7. The method of claim 3, wherein the first accelerator, the second accelerator, the third accelerator, and the digital signal processing module perform further comprising:
the digital signal processing module generates parameter information corresponding to the first accelerator, wherein the parameter information corresponding to the first accelerator further comprises an identification parameter for indicating the decoding multiplexing processing;
the first accelerator judges whether the currently acquired data to be input needs to be subjected to decoding division multiplexing processing or not according to the identification parameters; wherein the content of the first and second substances,
under the condition that the first accelerator judges that decoding division multiplexing processing is needed, data after LS channel estimation processing is used as third intermediate data, and the third intermediate data are subjected to decoding division multiplexing processing to obtain fourth intermediate data; performing the inverse fourier transform processing or the frequency offset estimation processing on the fourth intermediate data; or the like, or, alternatively,
and the first accelerator takes data after LS channel estimation processing as third intermediate data under the condition that the first accelerator judges that the decoding multiplexing processing is not needed, and directly performs the inverse Fourier transform processing or the frequency offset estimation processing on the third intermediate data.
8. The method of claim 2 or 3, wherein the first accelerator, the second accelerator, the third accelerator, and the digital signal processing module performing further comprise:
the first accelerator generates and outputs a local reference sequence for a third accelerator to obtain and carry out noise interference estimation processing;
the first accelerator performs the LS channel estimation processing based on the local reference sequence and the externally input frequency domain data.
9. The method of claim 2 or 3, wherein the first accelerator, the second accelerator, the third accelerator, and the digital signal processing module performing further comprise:
the second accelerator acquires the externally input frequency domain data as data to be input, and performs symbol scaling processing, time-frequency offset compensation processing and demapping processing to obtain seventh processed data; wherein the seventh processed data is related to user data and the seventh processed data is output as the first processing result.
10. The method of claim 2, wherein the first accelerator, the second accelerator, the third accelerator, and the digital signal processing module performing further comprise:
the digital signal processing module calculates to obtain a frequency domain interpolation matrix coefficient and a time domain interpolation matrix coefficient according to processing data and processing parameters reported by the first accelerator, and generates parameter information of the third accelerator based on the frequency domain interpolation matrix coefficient and the time domain interpolation matrix coefficient;
and the third accelerator acquires the second processing data as data to be input according to the parameter information of the third accelerator, and performs Fourier transform processing, interpolation filtering processing and demapping processing to obtain and output the channel value data after the demapping processing.
11. The method of claim 10, wherein the third accelerator acquires the second processing data as data to be input according to parameter information of the third accelerator, and performs fourier transform processing, interpolation filter processing, and demapping processing to obtain and output channel value data after the demapping processing, and includes:
performing time domain channel denoising processing and channel time offset compensation processing on the second processed data to obtain a fifth intermediate result;
performing Fourier transform processing, time-frequency offset compensation processing, frequency domain noise suppression filtering processing and time domain noise suppression filtering processing on the fifth intermediate result to obtain a sixth intermediate result; wherein the sixth intermediate result relates to a reference signal of a user;
performing frequency domain interpolation filtering processing and time domain interpolation filtering processing on the sixth intermediate result to obtain seventh intermediate processing data;
and performing demapping processing on the seventh intermediate processing data to obtain channel value data subjected to demapping processing.
12. The method of claim 11, wherein after performing fourier transform processing, time-frequency offset compensation processing, frequency domain noise suppression filtering processing, and time domain noise suppression filtering processing on the fifth intermediate result to obtain a sixth intermediate result, further comprising:
the third accelerator performs noise interference estimation processing on the sixth intermediate result and the third processed data to obtain seventh intermediate processed data;
and the third accelerator performs noise correlation matrix inversion processing on the seventh intermediate processing data to obtain and output fifth processing data.
13. The method according to claim 1, wherein the communication system is further provided with a cache bus module, and each accelerator of the N accelerators is connected with the cache bus module, so that the processing data output by each accelerator is interacted among the accelerators; the method for processing the data to be input by the accelerators according to the received parameter information includes the following steps:
each accelerator acquires required data to be input from the cache bus module according to the received parameter information to process the data to obtain respective processing data;
and each accelerator respectively stores the respective processing data into the cache bus module so as to be processed by other accelerators.
14. The method of claim 1, wherein the communication system is further provided with an enhanced bus module, and each of the accelerators of the N accelerators and the digital signal processing module are respectively connected with the enhanced bus module to realize data transmission interaction between the digital signal processing module and the N accelerators;
the method for processing the data to be input by the accelerators according to the received parameter information includes the following steps:
each accelerator acquires required data to be input according to the parameter information received from the enhanced bus module respectively and processes the data to be input to obtain processing parameters;
and each accelerator respectively reports respective processing parameters to the digital signal processing module through the enhanced bus module so as to be processed by the digital signal processing module.
15. The method of claim 1, wherein the N accelerators include a first accelerator, a second accelerator, and a third accelerator; the first accelerator, the second accelerator, the third accelerator and the digital signal processing module execute further comprising:
the digital signal processing module issues parameter information of the first accelerator and schedules the first accelerator for processing by taking a symbol as a unit;
the digital signal processing module issues parameter information of the second accelerator and schedules the second accelerator for processing by taking a user as a unit;
and the digital signal processing module issues the parameter information of the third accelerator and schedules the third accelerator for processing by taking a user as a unit.
16. The method of claim 15, wherein before the dsp module issues the parameter information of the third accelerator and schedules the third accelerator for processing in units of users, the method further comprises:
the first accelerator reports a completion signal to the digital processing module by taking a user as a unit so as to instruct the digital processing module to schedule a second accelerator or a third accelerator for processing;
the second accelerator reports a completion signal to the digital processing module by taking a user as a unit so as to instruct the digital processing module to schedule a third accelerator for processing;
the digital signal processing module issues the parameter information of the third accelerator, and after the third accelerator is scheduled to process by taking a user as a unit, the method further includes:
and the third accelerator reports a completion signal to the digital processing module by taking a user as a unit so as to inform the digital signal processing module of finishing the uplink channel estimation processing of the current user.
17. A chip is characterized in that N accelerators are arranged in the chip, and the chip and a digital signal processing module establish data transmission interaction;
each accelerator in the N accelerators receives the parameter information correspondingly issued by the digital signal processing module;
each accelerator acquires required data to be input according to the received parameter information for processing, and outputs respective processing data and processing parameters;
processing data output by each accelerator is interacted among the accelerators, and processing parameters output by each accelerator are reported to the digital signal processing module;
the data to be input acquired by each accelerator is frequency domain data input externally or processing data output by each accelerator;
except the first accelerator, the parameter information received by each accelerator in the N accelerators comprises an operation result obtained after the digital signal processing module processes the reported processing parameters;
the processing data output from each accelerator includes at least a first processing result after demapping as a channel estimation result, a second processing result after inversion of the noise covariance matrix, and channel value data after demapping.
18. The chip of claim 17, in which the N accelerators include a first accelerator, a second accelerator, and a third accelerator;
the first accelerator acquires the externally input frequency domain data as data to be input, and performs symbol extraction processing, LS channel estimation processing and inverse Fourier transform processing to obtain and output first processed data after symbol extraction processing and second processed data after inverse Fourier transform processing; wherein the first processed data and the second processed data are respectively related to a reference signal of a user;
the second accelerator acquires the first processing data as data to be input, performs time-frequency offset compensation processing and demapping processing, and obtains and outputs third processing data and fourth processing data after demapping processing; wherein the third processed data is related to a reference signal of a user, the fourth processed data is related to user data, and the fourth processed data is output as the first processing result;
the third accelerator acquires the second processed data and the third processed data as data to be input, and performs noise interference estimation processing and noise correlation matrix inversion processing to obtain and output fifth processed data after the noise correlation matrix inversion processing; wherein the fifth processed data is output as the second processing result.
19. The chip of claim 17, in which the N accelerators include a first accelerator, a second accelerator, and a third accelerator;
the first accelerator acquires the externally input frequency domain data as data to be input, performs symbol scaling processing, LS channel estimation processing, frequency offset estimation processing and inverse fourier transform processing to obtain and report a first processing parameter to the digital signal processing module, so that the digital signal processing module generates corresponding parameter information to indicate the second accelerator or the third accelerator to work; the first processing parameter includes a scaling factor after the symbol scaling processing, a frequency offset estimation value after the frequency offset estimation processing, and a shift factor after the inverse fourier transform processing.
20. The chip according to claim 18 or 19, characterized in that it further performs the method as follows:
the first accelerator obtains second processed data after inverse Fourier transform processing, noise estimation processing is carried out on the second processed data to obtain sixth processed data, and the sixth processed data are reported to the digital signal processing module, so that the digital signal processing module generates parameter information corresponding to the third accelerator;
wherein the parameter information corresponding to the third accelerator includes information related to a frequency domain interpolation matrix coefficient and a time domain interpolation matrix coefficient.
21. The chip of claim 20, wherein the chip further performs the method as follows:
the first accelerator performs power time delay spectrum calculation processing on the second processing data to obtain first intermediate data;
the first accelerator carries out power time delay spectrum noise estimation processing and power time delay spectrum noise removal processing on the first intermediate data to obtain a noise correlation value and power time delay spectrum data;
the first accelerator reports the noise correlation value and the power time delay spectrum data to the digital signal processing module for processing; and outputting the power time delay spectrum data as the sixth processing data.
22. The chip of claim 17, wherein the N accelerators are provided with a first accelerator, a second accelerator, and a third accelerator; the chip also performs the method as follows:
the first accelerator receives the parameter information of the first accelerator issued by the digital signal processing module based on the symbol as a unit, and reports a completion signal to the digital processing module based on the user as a unit so as to instruct the digital processing module to schedule a second accelerator or a third accelerator for processing;
the second accelerator receives the parameter information of the second accelerator issued by the digital signal processing module based on the unit of the user, and reports a completion signal to the digital processing module based on the unit of the user so as to instruct the digital processing module to schedule a third accelerator for processing;
the third accelerator receives the parameter information of the third accelerator issued by the digital signal processing module based on the unit of the user, and reports a completion signal to the digital processing module based on the unit of the user to inform the digital signal processing module that the uplink channel estimation processing of the current user is completed.
23. The chip of claim 17, wherein a cache bus module and an enhanced bus module are further disposed in the chip; the cache bus module is connected with the N accelerators to realize interaction of processing data output by each accelerator among the accelerators; the N accelerators are connected with the digital signal processing module through the enhanced bus module so as to report processing parameters output by each accelerator to the digital signal processing module.
24. A communication system, comprising a communication device comprising a digital signal processing module, a channel estimation accelerator, and an equalization accelerator; the channel estimation accelerator comprises N accelerators; the digital signal processing module respectively realizes data transmission interaction with each accelerator and the balance accelerator in the N accelerators, and realizes data transmission interaction between the N accelerators and the balance accelerator; the N accelerators and the dsp module are configured to perform the uplink channel estimation method according to any one of claims 1 to 16 to obtain a first processing result after demapping processing, a second processing result after inversion of a noise covariance matrix, and channel value data after demapping processing as a channel estimation result; and taking the first processing result, the second processing result and the channel value data as data to be input of the equalization accelerator to perform channel equalization processing to obtain a channel equalization result.
25. A communication device comprising a digital signal processing module and a chip interacting with the digital signal processing module, the chip comprising a chip for performing any of the claims 17-23.
26. A computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and the computer program is executed by a processor to implement the uplink channel estimation method according to any one of claims 1 to 16.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210201623.XA CN114285704B (en) | 2022-03-03 | 2022-03-03 | Uplink channel estimation method, chip, system and storage medium |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210201623.XA CN114285704B (en) | 2022-03-03 | 2022-03-03 | Uplink channel estimation method, chip, system and storage medium |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN114285704A CN114285704A (en) | 2022-04-05 |
| CN114285704B true CN114285704B (en) | 2022-06-21 |
Family
ID=80882103
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210201623.XA Active CN114285704B (en) | 2022-03-03 | 2022-03-03 | Uplink channel estimation method, chip, system and storage medium |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN114285704B (en) |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| ES2334971T1 (en) * | 2007-02-07 | 2010-03-18 | Nec Corporation | CHANNEL ESTIMATION DEVICE, EQUALIZATION DEVICE AND EQUALIZATION METHOD IN THE ESTIMATE. |
| GB2495959A (en) * | 2011-10-26 | 2013-05-01 | Imagination Tech Ltd | Multi-threaded memory access processor |
| CN104301274A (en) * | 2014-09-03 | 2015-01-21 | 武汉邮电科学研究院 | Uplink channel estimation method and system for multi-user scenes |
| CN107181704B (en) * | 2017-04-12 | 2020-03-10 | 西安电子科技大学 | Low-complexity weighted LS soft iteration mobile channel estimation method |
| CN114070657A (en) * | 2020-08-03 | 2022-02-18 | 华为技术有限公司 | Chip and method for manufacturing the same |
| CN114116557B (en) * | 2021-11-15 | 2024-02-27 | 同济大学 | Channel estimation device and method based on hardware accelerator and digital signal processor |
-
2022
- 2022-03-03 CN CN202210201623.XA patent/CN114285704B/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| CN114285704A (en) | 2022-04-05 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP5513523B2 (en) | Method and apparatus for delay spread compensation | |
| JP6448812B2 (en) | Interference suppression synthesis method, apparatus, and storage medium | |
| US10148463B2 (en) | Method and device for estimating frequency offset | |
| EP2510635A1 (en) | Method and arrangement for improved interference rejection combining | |
| JP2015198449A (en) | Method and device for cancelling narrow band interference in single carrier signal and computer program | |
| WO2016015473A1 (en) | Self-interference channel estimation method and device | |
| JP2009111973A (en) | Method and apparatus for estimating level of interference plus noise, and computer program | |
| WO2010102829A1 (en) | System and method for ofdm reception in the presence of doppler effect based on time domain windowing | |
| US10440720B2 (en) | Co-channel interference cancellation method and apparatus | |
| TWI474627B (en) | Signal processing in wireless communication receivers | |
| WO2014176788A1 (en) | Power control method, device and system | |
| KR102240976B1 (en) | Method and apparatus for frequency domain inter-carrier interference compensation | |
| US20130202022A1 (en) | Method and device for signal processing and applied to microwave communication system | |
| CN114285704B (en) | Uplink channel estimation method, chip, system and storage medium | |
| JP2023524631A (en) | Channel estimation and equalization in OFDM systems | |
| WO2016155548A1 (en) | Electronic device in wireless communications system, wireless communications system, and method | |
| WO2015003388A1 (en) | Clipping method, apparatus and system | |
| US10455079B2 (en) | Effective crosstalk estimation in presence of clipping errors | |
| KR20160121267A (en) | Method and Device for estimating channel in a mobile communication system | |
| JP6507260B2 (en) | Channel estimation method and apparatus, storage medium | |
| CN114285703B (en) | Method, chip, device and storage medium for estimating physical uplink shared channel | |
| JP5241437B2 (en) | Reception device and signal processing method | |
| JP6585565B2 (en) | Communication system and receiving apparatus | |
| JP6395639B2 (en) | Method and apparatus and computer program for canceling narrowband interference in a single carrier signal | |
| CN112311714B (en) | Data frame transmission method and device, electronic equipment and computer readable medium |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| PP01 | Preservation of patent right | ||
| PP01 | Preservation of patent right |
Effective date of registration: 20230207 Granted publication date: 20220621 |
|
| PD01 | Discharge of preservation of patent |
Date of cancellation: 20240402 Granted publication date: 20220621 |