CN114285703B - Method, chip, device and storage medium for estimating physical uplink shared channel - Google Patents
Method, chip, device and storage medium for estimating physical uplink shared channel Download PDFInfo
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Abstract
The application relates to an estimation method, a chip, a device and a storage medium of a physical uplink shared channel, wherein the method comprises the following steps: receiving scheduling information issued by a digital signal processing module by taking a symbol as a scheduling unit, wherein the scheduling information carries configuration parameters based on users; according to the configuration parameters, LS channel estimation processing, inverse Fourier transform processing, frequency offset estimation processing and noise estimation processing are carried out on externally input first frequency domain data, and a processing result is output; the processing result comprises a frequency offset estimation value after frequency offset estimation processing, a shifting factor and first processing data after inverse Fourier transform processing, and a channel correlation value and second processing data after noise estimation processing; reporting completion information to the digital signal processing module by taking a user as a unit so as to enable the digital signal processing module to process; thereby the overall efficiency of the channel estimation can be improved.
Description
Technical Field
The present application relates to the field of wireless communications technologies, and in particular, to a method, a chip, a device, and a storage medium for estimating a physical uplink shared channel.
Background
Channel estimation is a process of estimating the characteristics of a channel using various states exhibited by a received signal, and channel estimation may be defined as a process of qualitatively studying the influence of the channel on an input signal, and is a mathematical representation of the influence of the channel on the input signal. With the development of wireless communication technology, the fifth generation mobile communication technology (5th generation mobile networks or 5th generation wireless systems, 5G for short) is becoming more and more popular in people's daily life, and channel estimation is an important signal processing technology for an uplink network in a 5G-NR communication system, and is of great importance to the performance of a receiving end.
Generally, a channel estimation method mainly includes a series of processing such as extracting, denoising, and filtering a received signal, and then restoring a signal affected by various noises, attenuations, and the like during transmission back to a source signal. The channel estimation procedure in the related communication system is basically performed based on the formula 'Y = HX + W', where Y is the received signal, H is the channel value, X is the source signal, and W is the noise; since the wireless environment is complex and changeable, the signal will be subjected to various interferences in the process of propagation, when reaching the receiving end, the amplitude, phase and frequency of the signal will be changed greatly, and the receiving end cannot directly know the source user data, so that the Reference Signal (RS) directly known by both the receiving end and the transmitting end is used as the object of channel estimation, and the actual data is deduced reversely. That is, the channel estimation work actually estimates the Reference Signal (RS) that is fixedly present in the received signal based on the above formula, thereby obtaining 'H' and 'W' in the above formula, and then deduces the actual data therefrom.
Disclosure of Invention
The inventor finds that the hardware architecture redesign and the flow method re-optimization of the physical uplink shared channel estimation system have a large improvement space for the system performance, and particularly can obtain better channel estimation efficiency when the steps of LS channel estimation, inverse Fourier transform, frequency offset estimation and the like are optimized on input frequency domain data.
The application provides an estimation method, a chip, a device and a storage medium of a physical uplink shared channel, so as to improve the channel estimation efficiency of the related physical uplink shared channel.
In a first aspect, the present application provides a method for estimating a physical uplink shared channel, which is applied to a first accelerator, where the first accelerator performs data transmission interaction with a digital signal processing module and N second accelerators, respectively, where N is a positive integer greater than or equal to 1; the method comprises the following steps:
receiving scheduling information issued by the digital signal processing module by taking a symbol as a scheduling unit, wherein the scheduling information carries configuration parameters based on users;
according to the configuration parameters, LS channel estimation processing, inverse Fourier transform processing, frequency offset estimation processing and noise estimation processing are carried out on externally input first frequency domain data, and processing results are output; wherein, the processing result comprises the frequency offset estimation value after the frequency offset estimation processing, the shift factor and the first processing data after the inverse Fourier transform processing, and the channel correlation value and the second processing data after the noise estimation processing;
and reporting completion information to the digital signal processing module by taking a user as a unit so as to enable the digital signal processing module to process.
In a second aspect, the present application further provides a communication chip, where the communication chip is provided with a first accelerator, the first accelerator performs data transmission interaction with the digital signal processing module and N second accelerators, respectively, where N is a positive integer greater than or equal to 1; the first accelerator comprises a receiving module and a processing module, the processing module is connected with the receiving module, wherein:
the receiving module is used for receiving scheduling information issued by the digital signal processing module by taking a symbol as a scheduling unit, wherein the scheduling information carries configuration parameters based on users;
the processing module is used for performing LS channel estimation processing, inverse Fourier transform processing, frequency offset estimation processing and noise estimation processing on externally input first frequency domain data according to the configuration parameters and outputting processing results; the processing result comprises a frequency offset estimation value after the frequency offset estimation processing, a shift factor and first processing data after the inverse Fourier transform processing, and a channel correlation value and second processing data after the noise estimation processing; and the number of the first and second groups,
the processing module is further configured to report completion information to the digital signal processing module by using a user as a unit, so that the digital signal processing module performs processing.
In a third aspect, the present application further provides a communication apparatus, where the apparatus includes a first accelerator, where the first accelerator performs the method for estimating a physical uplink shared channel according to the first aspect; or, the device comprises a communication chip, and the communication chip is the communication chip according to the second aspect.
In a fourth aspect, the present application further provides a computer-readable storage medium, on which a computer program is stored, where the computer program is executed by a processor to implement the method for estimating a physical uplink shared channel according to the first aspect.
The beneficial effect of this application is as follows:
in the method for estimating a physical uplink shared channel of the embodiment of the application, scheduling information issued by a digital signal processing module with a symbol as a scheduling unit is received, wherein the scheduling information carries configuration parameters based on a user; according to the configuration parameters, LS channel estimation processing, inverse Fourier transform processing, frequency offset estimation processing and noise estimation processing are carried out on externally input first frequency domain data, and processing results are output; wherein, the processing result comprises the frequency offset estimation value after the frequency offset estimation processing, the shift factor and the first processing data after the inverse Fourier transform processing, and the channel correlation value and the second processing data after the noise estimation processing; reporting completion information to the digital signal processing module by taking a user as a unit so as to enable the digital signal processing module to process; therefore, the estimation method can realize that the reading processing of the data can be started when the RS symbol data of one user is received by taking the symbol as a scheduling unit, the processing can be started without completely receiving all the RS symbol data of the users, the effect of responding and processing quickly in time can be achieved, and the processing time is shortened; after processing all RS symbol data of a user, reporting completion information to the digital signal processing module, so that the digital signal processing module can perform relevant processing and schedule other accelerators for subsequent processing; the estimation method processes first frequency domain data input from the outside, then carries out LS channel estimation processing, inverse Fourier transform processing, frequency offset estimation processing and noise estimation processing, outputs a frequency offset estimation value after the frequency offset estimation processing, a shift factor and first processing data after the inverse Fourier transform processing, and a channel correlation value and second processing data after the noise estimation processing, integrates the related steps into an accelerator for processing, can optimize the flow method to the maximum extent, improves the channel estimation efficiency of the physical uplink shared channel, and further improves the overall performance of the system. The communication chip comprises a first accelerator, wherein the first accelerator is provided with a receiving module and a processing module, processes input frequency domain data by taking a symbol as a scheduling unit, reports a processing result by taking a user as a unit, achieves the effect of responding and processing quickly in time, shortens the processing time, optimizes the flow method to the maximum extent, improves the channel estimation efficiency of a physical uplink shared channel, and further improves the overall performance of the system; the communication device of the embodiment of the application, which comprises the estimation method or the communication chip, achieves the effect of timely and rapid response processing, improves the channel estimation efficiency of the physical uplink shared channel, and has good system performance.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and together with the description, serve to explain the principles of the invention.
In order to more clearly illustrate the embodiments or technical solutions in the prior art of the present invention, the drawings used in the description of the embodiments or prior art will be briefly described below, and it is obvious for those skilled in the art that other drawings can be obtained based on these drawings without creative efforts.
Fig. 1 is a schematic flowchart of a method for estimating a physical uplink shared channel according to an embodiment of the present application;
fig. 2 is a schematic flowchart of another method for estimating a physical uplink shared channel according to an embodiment of the present application;
fig. 3 is a schematic flowchart of another method for estimating a physical uplink shared channel according to an embodiment of the present application;
fig. 4 is a schematic structural diagram of a communication chip according to an embodiment of the present disclosure;
fig. 5 is a schematic structural diagram of a first accelerator of a communication chip according to an embodiment of the present application;
fig. 6 is a schematic structural diagram of a communication device according to an embodiment of the present application;
fig. 7 is a schematic structural diagram of a computer-readable storage medium according to an embodiment of the present application.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments in the present application without making creative efforts shall fall within the protection scope of the present application.
According to various embodiments of the present Application, the term "module" refers to, but is not limited to, a software or hardware component, such as a software or hardware component based on a Field Programmable Gate Array (FPGA) or an Application Specific Integrated Circuit (ASIC) design to perform some task. The term "connect" and its derivatives refer to any direct or indirect communication between two or more modules, whether or not those modules are in physical contact with one another. Relational terms such as "first" and "second," and the like, may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. The terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element. The phrase "associated with," and derivatives thereof, means including, being included within, interconnected, connected to, or connected to, coupled to, or coupled with, communicable, cooperative with, joined, or joined with, having,. properties, having, or being in a relationship to, etc.
The preferred embodiments are described below with reference to the accompanying drawings.
In a 5G-NR communication system, when receiving transmission data sent by User Equipment (UE), a small cell equipment needs to perform noise interference analysis in a transmission process on a Reference Signal (RS) in the received air interface transmission data, that is, channel estimation, so as to restore actual user data in the air interface transmission data, so as to facilitate the small cell equipment to perform subsequent analysis processing on the user data. By redesigning the hardware architecture and re-optimizing the flow method of a Physical Uplink Shared CHannel (PUSCH) estimation system, the system performance is greatly improved, and particularly, the steps of LS CHannel estimation, inverse fourier transform, frequency offset estimation and the like are optimized on input frequency domain data, so that better CHannel estimation efficiency can be obtained. The estimation method, the chip, the device and the storage medium of the physical uplink shared channel provided by the embodiment of the application are mainly optimized around steps of LS channel estimation, inverse Fourier transform, frequency offset estimation and the like, and are innovatively designed from aspects of data processing method flow, hardware design and the like, so that the processing efficiency is improved, and further, better channel estimation efficiency is obtained.
Fig. 1 is a schematic flowchart illustrating a method for estimating a physical uplink shared channel according to an embodiment of the present application.
The estimation method of the physical uplink shared channel is applied to a first accelerator, the first accelerator performs data transmission interaction with a digital signal processing module or N second accelerators, and N is a positive integer greater than or equal to 1; the first accelerator of the embodiment of the application can receive data or scheduling information issued by a Digital Signal Processor (DSP), read IQ data for processing based on the scheduling information, and output a frequency offset estimation value after frequency offset estimation processing, a shift factor and first processing data after inverse fourier transform processing, and a channel correlation value and second processing data after noise estimation processing; the processing result output by the first accelerator is provided to a digital Signal processing module or other accelerators, so that the digital Signal processing module can process the channel estimation data and schedule the subsequent accelerators to filter, denoise, interpolate and the like the channel estimation value of the Reference Signal (RS) and the symbol data of the Reference Signal, thereby obtaining the channel estimation value H of the physical uplink shared channel transmission data. As shown in fig. 1, the estimation method of the embodiment of the present application includes the following steps:
It should be noted that, when one ue sends transmission data to the small cell device, the actual user data may exist in multiple RS symbol data. The digital signal processing module issues configuration parameters to schedule the first accelerator to work by taking the symbol as a scheduling unit, namely, when receiving one RS symbol data of a user, the digital signal processing module issues scheduling information to schedule the first accelerator to process; the configuration parameters comprise user-based parameter information, the user-based parameter information comprises but is not limited to a user number, the number of RBs of the user, the RB position index of the user, the number of subcarriers, the number of RS symbols and the like, the first accelerator reads IQ data after receiving the configuration parameters sent by the DSP, the IQ data is first frequency domain data input externally, and data related to the user are extracted from the IQ data according to the user-based parameter information for processing. The RS symbol data in the embodiment of the present application refers to an Orthogonal Frequency Division Multiplexing (OFDM) symbol in which a Reference Signal (RS) is located.
102, according to configuration parameters, performing LS channel estimation processing, inverse Fourier transform processing, frequency offset estimation processing and noise estimation processing on externally input first frequency domain data, and outputting a processing result; the processing result comprises a frequency offset estimation value after frequency offset estimation processing, a shifting factor and first processing data after inverse Fourier transform processing, and a channel correlation value and second processing data after noise estimation processing.
In this step, the processing can be started when receiving one RS symbol data, and the processing is started without completely receiving all RS symbol data of the user. After Least Square (LS) channel estimation processing, frequency domain data after LS channel estimation are processed in two ways. Firstly, Inverse Fourier Transform (IFFT) is carried out, frequency domain data are converted into time domain data, a shifting factor and first processing data after the IFFT are obtained, the first processing data represent the time domain data obtained by the IFFT, the shifting factor is beneficial to subsequent possible time domain-frequency domain conversion processing, and the obtained first processing data are subjected to noise estimation processing to obtain a channel correlation value and second processing data; in an alternative embodiment, the channel correlation value may be a noise value of an associated Power Delay Profile (PDP) and a position index of the associated Power delay profile, and the second processing data may be a resulting Power delay profile or a denoised Power delay profile. And secondly, performing frequency offset estimation processing, namely processing the inter-symbol in the frequency domain data of the user to complete the process of conjugate multiplication and accumulation to obtain a frequency offset estimation result, namely a frequency offset estimation value.
And 103, reporting the completion information to the digital signal processing module by taking the user as a unit so as to enable the digital signal processing module to process.
It can be understood that, when the actual user data exists in a plurality of RS symbol data, the dsp module schedules the first accelerator to work by using the symbol as a scheduling unit, and after all RS symbol data processing of a user is completed, obtains the relevant data and processing parameters of the user, and reports the completion information to the dsp module by using the user as a unit. For example, a user has 2 RS symbol data, the dsp module schedules the first accelerator for 2 times with the symbol as a scheduling unit, and obtains the relevant data and processing parameters of the user after the first accelerator completes 2 times of processing, and then reports the completion information to the dsp module to enable the dsp module to perform subsequent processing. In an optional embodiment, the frequency offset estimation value, the channel correlation value, and the shift factor may be reported to the digital signal processing module as processing parameters, and are sent to other accelerators to implement scheduling after being processed by the digital signal processing module, and meanwhile, the digital signal processing module may also perform noise correlation value calculation and the like according to the channel correlation value and the second processed data, and certainly, in other preferred embodiments, the digital signal processing module and the N accelerators may also be functionally divided by combining related hardware performance and processing delays of each step, so as to achieve optimal system performance, and obtain a channel estimation value H of the final physical uplink shared channel transmission data.
Therefore, by using the estimation method of the physical uplink shared channel of the application embodiment, by using the symbol as the scheduling unit, the reading processing of the data can be started when the RS symbol data of one user is received, the processing can be started without completely receiving all the RS symbol data of the users, the effect of responding to the processing in time and rapidly processing can be achieved, and the processing time is shortened; after processing all RS symbol data of a user, reporting completion information to the digital signal processing module, so that the digital signal processing module can perform relevant processing and schedule other accelerators for subsequent processing; the estimation method processes first frequency domain data input from the outside, then carries out LS channel estimation processing, inverse Fourier transform processing, frequency offset estimation processing and noise estimation processing, outputs a frequency offset estimation value after the frequency offset estimation processing, a shift factor and first processing data after the inverse Fourier transform processing, and a channel correlation value and second processing data after the noise estimation processing, integrates the related steps into an accelerator for processing, can optimize the flow method to the maximum extent, improves the channel estimation efficiency of the physical uplink shared channel, and further improves the overall performance of the system.
Fig. 2 is a flowchart illustrating another method for estimating a physical uplink shared channel according to an embodiment of the present application.
In an alternative embodiment, the LS channel estimation process further includes a symbol scaling process and a symbol extraction process. Specifically, in step 102, before the LS channel estimation processing, the inverse fourier transform processing, the frequency offset estimation processing, and the noise estimation processing are performed on the externally input first frequency domain data according to the configuration parameters, the method further includes:
step 201, according to the configuration parameters, performing symbol scaling processing on the externally input first frequency domain data to obtain and output a scaling factor after symbol scaling processing, so as to be processed by the digital signal processing module or the N second accelerators.
In this step, symbol scaling processing is performed on the obtained IQ data, that is, after Signal Strength (RSSI) measurement and Digital Automatic Gain Control (DAGC) are performed, a scaling factor after symbol scaling processing is obtained and output externally, and when other accelerators are used for processing the IQ data, repeated operation is not required, so that processing time is saved.
202, shifting symbol data in externally input first frequency domain data based on configuration parameters and scaling factors to obtain and output second frequency domain data for a digital signal processing module or N second accelerators to process; wherein the second frequency domain data is associated with a reference signal of the user.
In this step, according to the scaling factor obtained in the previous step, a shift operation is performed on symbol data in IQ data, and corresponding Resource Blocks (RBs) in a frequency domain Resource grid are extracted according to antenna, user and RS symbol modes to obtain second frequency domain data, which is output to facilitate other accelerators to process the same data without repeated operation.
Step 203, extracting effective resource particles from the second frequency domain data as first intermediate data; the first intermediate data is used for LS channel estimation processing, inverse Fourier transform processing, frequency offset estimation processing and noise estimation processing.
In this step, it can be understood that, when the shift processing is performed, the relevant whole Resource Block (RB) is processed, and the channel estimation value of the Reference Signal (RS) is calculated for the effective Resource Element (RE), so that the demapping processing is required, and the effective Resource Element (RE) is extracted according to the effective Reference Signal (RS) index in the current Resource Block (RB) for the subsequent processing.
With reference to fig. 2, after the symbol extraction processing, the step 102 of performing, according to the configuration parameters, LS channel estimation processing, inverse fourier transform processing, frequency offset estimation processing, and noise estimation processing on the externally input first frequency domain data specifically includes the following steps:
step 301, according to the configuration parameters, LS channel estimation processing is performed on the externally input first frequency domain data to obtain second intermediate data.
It is understood that, in the least square channel estimation process, the conjugate multiplication operation is performed on the demapped data and the local reference sequence, and the following formula can be adopted:
wherein the content of the first and second substances,
represents the first intermediate data after the demapping process, that is, the valid Resource Element (RE) data;
representing a local reference sequence, r representing a current receiving antenna, k representing a current subcarrier index, l representing the number of layers of current antenna data, and p representing a current port; local reference sequence
May be generated based on relevant parameters in the 3gPP communication protocol, preferably a local reference sequence
In the generation process, values are taken from the initial position of a partial Bandwidth (BWP).
And 302, performing inverse fourier transform processing on the second intermediate data to obtain and output the shift factor and the first processed data after the inverse fourier transform processing, so that the shift factor and the first processed data are processed by the digital signal processing module or the N second accelerators.
It can be understood that before noise estimation processing, data to be processed needs to be converted from a frequency domain to a time domain, and in the embodiment of the present application, the frequency domain data after LS channel estimation is converted into time domain data by using an inverse fourier transform algorithm, which is beneficial to subsequent noise estimation; and the shifting factor and the first processed data after the inverse Fourier transform are output, so that other accelerators do not need repeated operation when processing the same data and performing Fourier transform processing, and the performance of the whole system is improved.
And step 303, performing noise estimation processing on the first processed data to obtain and output a channel correlation value and second processed data after the noise estimation processing, so that the channel correlation value and the second processed data are provided for processing by the digital signal processing module or the N second accelerators.
In this step, optionally, the noise estimation processing may be implemented by calculating a Power Delay Profile (PDP), the channel correlation value may be a noise value obtained after the noise estimation processing of the Power Delay Profile, the channel correlation value is associated with the noise value, and the second processing data may be Power Delay Profile data obtained after the calculation and combination of the relevant Power Delay profiles, where the Power Delay Profile data is associated with all valid data of the user. Of course, in combination with the actual situation, the noise estimation process may also select other noise estimates to obtain the channel correlation value and the second processed data.
And step 304, performing frequency offset estimation processing on the second intermediate data to obtain and output a frequency offset estimation value after the frequency offset estimation processing, so that the frequency offset estimation value is processed by the digital signal processing module or the N second accelerators.
In this step, the Frequency offset estimation process is actually a process of processing between symbols, and performing conjugate multiplication and accumulation on a sequence of symbol data of adjacent Reference Signals (RSs) related to a user, where the symbol data is associated with Orthogonal Frequency Division Multiplexing (OFDM). In the step, after the LS channel estimation, the frequency domain data after the LS channel estimation is subjected to frequency offset estimation processing, and a frequency offset estimation value is output outwards, so that the processing time is shortened, other accelerators can perform subsequent operation, and the overall efficiency of the system is improved.
Fig. 3 is a flowchart illustrating a method for estimating a physical uplink shared channel according to another embodiment of the present application.
Referring to fig. 3, in the case where multiplexing exists for multiple ports, after the LS channel estimation process, a decoding and division multiplexing process needs to be performed on data for each port of each antenna. It should be noted that the multi-port presence multiplexing is simply understood as that each antenna data is divided into multiple layers, and each layer receives data of different users, so that the decoding-division multiplexing (FD-CDM) process is required at this time. Specifically, in step 301, after the LS channel estimation processing is performed on the externally input first frequency domain data according to the configuration parameters to obtain the second intermediate data, the method further includes the following steps:
It can be understood that, when the digital signal processing module issues the configuration parameter to schedule the first accelerator in the embodiment of the present application to start up, it is already known whether the user needs to perform the decoding multiplexing processing, and when the first accelerator in the embodiment of the present application receives the configuration parameter, it can determine whether the decoding multiplexing processing needs to be performed.
Step 402a, under the condition that it is determined that the second intermediate data needs to be subjected to decoding division multiplexing processing, performing decoding division multiplexing processing on the second intermediate data to obtain third intermediate data; and taking the third intermediate data as new second intermediate data to perform inverse Fourier transform processing and frequency offset estimation processing.
In this step, if there is multi-port multiplexing, for example, there is two-port multiplexing, for the first port 0, the following formula is used for calculation:
where r denotes a receiving antenna, k denotes a subcarrier index, l denotes the number of layers,
the channel estimation values obtained after least squares channel estimation are shown.
For the second port 1, the calculation can be made by the following formula:
where r denotes a receiving antenna, k denotes a subcarrier index, l denotes the number of layers,
the channel estimation values obtained after least squares channel estimation are shown.
And 402b, under the condition that the second intermediate data does not need to be subjected to decoding multiplexing processing, directly performing inverse Fourier transform processing and frequency offset estimation processing on the second intermediate data.
It can be understood that, if the multi-port multiplexing does not exist, the data after the LS channel estimation processing is directly transmitted, and the inverse fourier transform processing and the frequency offset estimation processing are directly performed, which may be calculated by using the following formula:
wherein the content of the first and second substances,
the channel estimation value obtained after least square channel estimation is shown, and p is indicated as a port.
Referring to fig. 3, the noise estimation process may optionally include a PDP calculation process, a PDP noise estimation process, and a PDP noise removal process. In step 301, noise estimation processing is performed on the first processed data to obtain and output a channel correlation value and second processed data after the noise estimation processing, which specifically includes the following steps:
step 501, performing power delay spectrum calculation processing on the first processing data to obtain fourth intermediate data after the power delay spectrum calculation processing.
In this step, first processed data after the IFFT processing is received, the first processed data being associated with each Reference Signal (RS) data; according to the configuration parameters, performing power delay spectrum calculation processing on the first processing data to obtain fifth intermediate data based on the user reference signal; the time delay spectrum calculation processing is that the modular arithmetic is carried out after the IFFT processing; when the data is continuous, and the fifth intermediate data is multiple, after the last fifth intermediate data is obtained, the multiple fifth intermediate data are combined to obtain fourth intermediate data; that is, in the successive processing, a plurality of results of the modulo operation based on the Reference Signal (RS) are obtained and added. After receiving the last data of the user, the result of the addition is output, that is, fourth intermediate data, which may be PDP data that has not been subjected to denoising processing. It is understood that, in an alternative embodiment, if there is multiplexed antenna data divided into layer 0, layer 1, adding means to add and combine OFDM symbols of all layers related to a user, thereby obtaining corresponding PDP data of the user.
Step 502, performing power delay spectrum noise estimation processing and power delay spectrum noise removal processing on the fourth intermediate data to obtain a channel correlation value after the power delay spectrum noise estimation processing and second processed data after the power delay spectrum noise removal processing.
In the step, after obtaining power delay spectrum (PDP) data, the maximum value and position of the PDP may be recorded, and all possible noise values are tried to be added by means of sectional averaging, cyclic sliding averaging, and the like, and then the initial position of the noise section is calculated, and the PDP data is subjected to noise estimation processing, so as to obtain a noise power value as a channel correlation value corresponding to the PDP data and output the noise power value, where the channel correlation value may also be an index including the initial position; in this step, the original PDP data may be denoised, a value considered as noise on the PDP is removed, and the denoised PDP data is obtained as second processing data and output.
Step 503, outputting the channel correlation value and the second processing data for the digital signal processing module or the N second accelerators to process the channel correlation value and the second processing data.
It can be understood that, the channel correlation value and the second processing data output by the noise estimation processing in the embodiment of the present application are provided to the digital signal processing module with stronger data processing capability or other accelerators for performing correlation operation processing, so as to obtain noise correlation information and filter coefficients, such as signal-to-noise ratio (SNR), etc.; the flow of the embodiment of the application is optimized in such a way, so that the time delay of the whole processing can be shortened, and the processing efficiency of the whole system can be improved.
Referring to fig. 3, the first accelerator of the embodiment of the present application further includes a step of generating a local reference sequence. Before performing LS channel estimation processing on externally input first frequency domain data according to configuration parameters to obtain second intermediate data in step 301, the method further includes: generating and outputting a local reference sequence for processing by the digital signal processing module or the N second accelerators according to the configuration parameters; based on the local reference sequence and the externally input first frequency domain data, LS channel estimation processing is carried out to obtain second intermediate data. It can be understood that the generated local reference sequence is output, so that other accelerators can perform subsequent operations, and the overall efficiency of the system is improved.
In an optional embodiment, the first accelerator and the N second accelerators respectively perform data transmission interaction based on the cache bus module; the first accelerator and the digital signal processing module perform data transmission interaction based on the enhanced bus module; the first accelerator or the N second accelerators are respectively realized based on a field programmable logic gate array.
Fig. 4 is a schematic structural diagram of a communication chip according to an embodiment of the present application.
Specifically, a communication chip 400 related to the embodiment of the present application may be designed based on a Field Programmable Gate Array (FPGA) or an application specific integrated circuit, where the communication chip 400 is provided with a first accelerator 401, the first accelerator 401 performs data transmission interaction with a digital signal processing module 402 or N second accelerators 403, respectively, and N is a positive integer greater than or equal to 1; the first accelerator 401 includes a receiving module 4011 and a processing module 4012, and the processing module 4012 is connected to the receiving module 4011, wherein:
a receiving module 4011, configured to receive scheduling information issued by the digital signal processing module 402 using the symbol as a scheduling unit, where the scheduling information carries a configuration parameter based on a user;
a processing module 4012, configured to perform, according to the configuration parameters, LS channel estimation processing, inverse fourier transform processing, frequency offset estimation processing, and noise estimation processing on the externally input first frequency domain data, and output a processing result; the processing result comprises a frequency offset estimation value after frequency offset estimation processing, a shifting factor and first processing data after inverse Fourier transform processing, and a channel correlation value and second processing data after noise estimation processing; and the number of the first and second groups,
the processing module 4012 is further configured to report the completion information to the digital signal processing module by taking the user as a unit, so that the digital signal processing module 402 performs processing according to the processing result, or the digital signal processing module 402 schedules the second accelerator 403 to obtain the processing result for processing.
It can be understood that the receiving module 4011 may receive the configuration parameters sent by the digital signal processing module 402, and transmit the configuration parameters to the processing module 4012, the processing module 4012 schedules the first accelerator 401 to operate according to the configuration parameters, the configuration parameters include user-based parameter information, the user-based parameter information includes, but is not limited to, a user number, a user RB position index, a subcarrier number, an RS symbol number, and the like, after receiving the configuration parameters sent by the DSP, the first accelerator 401 reads IQ data by using the user as a scheduling unit, the IQ data is first frequency domain data externally input, and extracts and processes associated data from the IQ data according to the user-based parameter information.
The processing module 4012 may start processing each time an RS symbol data is received according to the configuration parameters received by the receiving module 4011, and start processing without receiving all RS symbol data of the user. After Least Square (LS) channel estimation processing, frequency domain data after LS channel estimation are processed in two ways. Firstly, Inverse Fourier Transform (IFFT) is carried out, frequency domain data are converted into time domain data, a shifting factor and first processing data after the IFFT are obtained, the first processing data represent the time domain data obtained by the IFFT, the shifting factor is beneficial to subsequent possible time domain-frequency domain conversion processing, and the obtained first processing data are subjected to noise estimation processing to obtain a channel correlation value and second processing data; in an alternative embodiment, the channel correlation value may be a noise value of an associated Power Delay Profile (PDP) and a position index of the associated Power delay profile, and the second processing data may be a resulting Power delay profile or a denoised Power delay profile. And secondly, performing frequency offset estimation processing, namely processing the symbols in the frequency domain data of the user to complete the processes of conjugate multiplication and accumulation to obtain a frequency offset estimation result, namely a frequency offset estimation value.
The processing module 4012 may further output the frequency offset estimation value, the channel correlation value, the shift factor, the first processed data, and the second processed data. In an optional embodiment, the frequency offset estimation value, the channel correlation value, and the shift factor may be reported to the digital signal processing module 402 as processing parameters, and are uniformly issued by the digital signal processing module 402 to other accelerators to implement scheduling, and meanwhile, the digital signal processing module 402 may perform noise correlation value calculation and the like according to the channel correlation value and the second processing data, and of course, in other preferred embodiments, the digital signal processing module 402 and the N accelerators may be functionally divided by combining related hardware performance and processing delays of each step, so as to achieve optimal system performance, and obtain a channel estimation value H of the final physical uplink shared channel transmission data.
It should be noted that, according to the embodiment of the above application, by using symbols as scheduling units, it is possible to start data reading processing each time RS symbol data of one user is received, and start processing without completing all reception of all RS symbol data of the users, so that an effect of processing quickly in time of response can be achieved, and processing time can be shortened; after processing all RS symbol data of a user, reporting completion information to the digital signal processing module, so that the digital signal processing module can perform relevant processing and schedule other accelerators for subsequent processing; the estimation method processes first frequency domain data input from the outside, then carries out LS channel estimation processing, inverse Fourier transform processing, frequency offset estimation processing and noise estimation processing, outputs a frequency offset estimation value after the frequency offset estimation processing, a shift factor and first processing data after the inverse Fourier transform processing, and a channel correlation value and second processing data after the noise estimation processing, integrates the related steps into an accelerator for processing, can optimize the flow method to the maximum extent, improves the channel estimation efficiency of the physical uplink shared channel, and further improves the overall performance of the system.
Fig. 5 is a schematic structural diagram of a first accelerator of a communication chip according to an embodiment of the present disclosure.
Referring to fig. 5, the communication chip 400 of the embodiment of the present application is further provided with a cache bus module 404, the processing module 4012 includes a symbol scaling processing module 40121, a symbol extraction processing module 40122 and an output module 40123, the symbol scaling processing module 40121 is connected to the symbol extraction processing module 40122 and the output module 40123 respectively, and the cache bus module 404 is connected to the symbol scaling processing module 40121 and the symbol extraction processing module 40122 respectively, where:
the symbol scaling processing module 40121 is configured to extract, according to the configuration parameter, first frequency domain data that is externally input from the buffer bus module 404 to perform symbol scaling processing, obtain and output, via the output module 40123, a scaling factor after the symbol scaling processing, so as to be processed by the digital signal processing module 402 or the N second accelerators 403.
A symbol extraction processing module 40122, configured to shift symbol data in the externally input first frequency domain data based on the configuration parameter and the scaling factor, to obtain and output second frequency domain data, so that the digital signal processing module 402 or the N second accelerators 403 perform processing; the second frequency domain data is related to the reference signal of the user, and the second frequency domain data is stored in the cache bus module.
A symbol extraction processing module 40122, further configured to extract effective resource elements for the second frequency domain data as first intermediate data; the first intermediate data is used for LS channel estimation processing, inverse Fourier transform processing, frequency offset estimation processing and noise estimation processing. It can be understood that, the symbol scaling processing module 40121 may perform symbol scaling processing on the IQ data obtained from the buffer bus module 404 according to the configuration parameters Received by the receiving module 4011, that is, after performing Signal Strength (Received Signal Strength Indication (RSSI) measurement and Digital Automatic Gain Control (DAGC), obtain a scaling factor after the symbol scaling processing, and output the scaling factor through the output module 40123, so that when other accelerators process the IQ data, no repeated operation is needed, thereby saving processing time.
The symbol extraction processing module 40122 may perform a shift operation on the symbol data in the IQ data according to the scaling factor obtained by the symbol scaling processing module 40121, extract a corresponding Resource Block (RB) in the frequency domain Resource grid according to the antenna, user and RS symbol modes to obtain second frequency domain data, and associate the second frequency domain data with the reference signal of the user, where the second frequency domain data is output to the cache bus module 404, which is beneficial for other accelerators to process the same data without performing repeated operations.
The symbol extraction processing module 40122 may also process the whole Resource Block (RB) during the shift process, and calculate the channel estimation value of the Reference Signal (RS) to be calculated to be the effective Resource Element (RE), so that the demapping process is required to extract the effective Resource Element (RE) according to the effective Reference Signal (RS) index in the current Resource Block (RB) for the subsequent process.
Referring to fig. 5, the processing module 4012 includes an LS channel estimation processing module 40124, an inverse fourier transform processing module 40125, a noise estimation processing module 40126, and a frequency offset estimation processing module 40127, the LS channel estimation processing module 40124 is respectively connected to the inverse fourier transform processing module 40125 and the frequency offset estimation processing module 40127, the noise estimation processing module 40126 is connected to the inverse fourier transform processing module 40125, and the noise estimation processing module 40126 is connected to the buffer bus module 404, where:
the LS channel estimation processing module 40124 is configured to perform LS channel estimation processing on the externally input first frequency domain data according to the configuration parameter, so as to obtain second intermediate data.
The inverse fourier transform processing module 40125 is configured to perform inverse fourier transform processing on the second intermediate data to obtain and output the shift factor and the first processed data after the inverse fourier transform processing, so that the shift factor and the first processed data are provided for the digital signal processing module 402 or the N second accelerators 403 to process; the first processing data is stored in the cache bus module.
The noise estimation processing module 40126 is configured to perform noise estimation processing on the first processed data, obtain and output a channel correlation value after the noise estimation processing and second processed data, so that the channel correlation value and the second processed data are provided for the digital signal processing module 402 or the N second accelerators 403 to process, where the second processed data is stored in the cache bus module.
The frequency offset estimation processing module 40127 is configured to perform frequency offset estimation processing on the second intermediate data, to obtain and output a frequency offset estimation value after the frequency offset estimation processing, so that the frequency offset estimation value is provided for the digital signal processing module 402 or the N second accelerators 403 to process.
It is to be understood that, in the least square channel estimation process, the LS channel estimation processing module 40124 may perform a conjugate multiplication operation on the first intermediate data after demapping obtained by the symbol extraction processing module 40122 and the local reference sequence, and may use the following formula:
wherein, the first and the second end of the pipe are connected with each other,
represents the first intermediate data after the demapping process, that is, the valid Resource Element (RE) data;
representing a local reference sequence, r representing a current receiving antenna, k representing a current subcarrier index, l representing the number of layers of current antenna data, and p representing a current port; local reference sequence
May be generated based on relevant parameters in the 3gPP communication protocol, preferably a local reference sequence
In the generation process, values are taken from the initial position of a partial Bandwidth (BWP).
The inverse fourier transform processing module 40125 may use an inverse fourier transform algorithm to convert the frequency domain data (i.e., the second intermediate data) obtained by the LS channel estimation processing module 40124 into time domain data, which is beneficial to the subsequent noise estimation; and the shift factor and the first processed data after the inverse Fourier transform processing are output, so that other accelerators do not need repeated operation when processing the same data and performing Fourier transform processing, and the performance of the whole system is improved.
The noise estimation processing module 40126 may perform noise estimation processing on the first processed data obtained by the inverse fourier transform processing module 40125 by calculating a Power Delay Profile (PDP), to obtain and output a channel correlation value after noise estimation processing and second processed data, where the channel correlation value may be a noise value obtained after noise estimation processing of the Power Delay Profile, the channel correlation value is associated with the noise value, the second processed data may be Power Delay Profile data after calculation and combination of the related Power Delay profiles, and the Power Delay Profile data is associated with all valid data of a user. Of course, in combination with the actual situation, the noise estimation process may also select other noise estimates to obtain the channel correlation value and the second processed data.
The Frequency offset estimation processing module 40127 is actually a process of performing conjugate multiplication and accumulation on a sequence of symbol data of adjacent Reference Signals (RSs) related to a user, the symbol data being associated with Orthogonal Frequency Division Multiplexing (OFDM). The frequency offset estimation processing module 40127 may perform frequency offset estimation processing on the frequency domain data obtained by the LS channel estimation processing module 40124, and output a frequency offset estimation value outwards, so as to shorten processing time, facilitate other accelerators to perform subsequent operations, and further improve overall efficiency of the system.
In this embodiment of the application, the noise estimation processing module is connected to the cache bus module, and the noise estimation processing module stores the first processed data into the cache bus module and stores the second processed data into the cache bus module, and of course, the inverse fourier transform module 40125 may also be connected to the cache bus module, so as to directly store the first processed data into the cache bus module.
Referring to fig. 5, the processing module 4012 further includes a de-code division multiplexing processing module 40128, the LS channel estimation processing module 40124 is connected to the inverse fourier transform processing module 40125 and the frequency offset estimation processing module 40127 through a decoding de-multiplexing processing module 40128, and the decoding de-multiplexing processing module 40128 is connected to the buffer bus module 404, where:
the receiving module 4011 is further configured to determine whether to perform decoding multiplexing processing on the second intermediate data according to the configuration parameter; the configuration parameters comprise identification information used for indicating whether the current user carries out decoding multiplexing processing or not;
a de-code division multiplexing processing module 40128, configured to perform decoding division multiplexing processing on the second intermediate data to obtain third intermediate data when it is determined that the decoding division multiplexing processing needs to be performed on the second intermediate data; the third intermediate data is used as new second intermediate data and is respectively transmitted to the inverse fourier transform processing module 40125 and the frequency offset estimation processing module 40127; the third intermediate data is stored in the cache bus module 404; or the like, or, alternatively,
a de-code division multiplexing processing module 40128, configured to transmit the second intermediate data to the inverse fourier transform processing module 40125 and the frequency offset estimation processing module 40127 respectively when it is determined that the second intermediate data does not need to be subjected to the decoding and de-multiplexing processing; the second intermediate data is stored in the cache bus module 404.
It can be understood that the digital signal processing module 402 already knows whether the user needs to perform the demultiplexing/decoding process when the first accelerator 401 of the embodiment of the present application starts to operate according to the configuration parameter. The receiving module 4011 may determine whether the decoding multiplexing processing is required according to the configuration parameter issued by the digital signal processing module 402.
The above-described demultiplexing/decoding module 40128 may perform demultiplexing/decoding processing on the second intermediate data when it is determined that demultiplexing/decoding processing on the second intermediate data is necessary. Specifically, if there is multi-port multiplexing, for example, there is two-port multiplexing, the first port 0 can be calculated by the following formula:
where r denotes a receiving antenna, k denotes a subcarrier index, l denotes the number of layers,
the channel estimation values obtained after least squares channel estimation are shown.
For the second port 1, the calculation can be made by the following formula:
where r denotes a receiving antenna, k denotes a subcarrier index, l denotes the number of layers,
representing the channel estimate obtained after least squares channel estimation.
The above-described demultiplexing processing module 40128 may perform the inverse fourier transform processing and the frequency offset estimation processing on the second intermediate data directly, in a case where it is determined that the demultiplexing processing on the second intermediate data is not necessary. Specifically, if the multi-port multiplexing does not exist, the data after the LS channel estimation processing is directly transmitted through, and the inverse fourier transform processing and the frequency offset estimation processing are directly performed, which may be calculated by using the following formula:
wherein the content of the first and second substances,
and representing the channel estimation value obtained after least square channel estimation, and p is represented as a port.
Referring to fig. 5, the processing module 4012 further includes an output module 40123, the noise estimation processing module 40126 includes a power delay spectrum calculation processing module 401261 (i.e., a PDP calculation module) and a power delay spectrum noise estimation processing module 401262 (i.e., a PDP noise estimation module), the power delay spectrum calculation processing module 401261 is connected to the inverse fourier transform processing module 40125 and the power delay spectrum noise estimation processing module 401262, and the power delay spectrum noise estimation processing module 401262 is connected to the output module 40123; wherein:
and the power delay spectrum calculation processing module 401261 is configured to perform power delay spectrum calculation processing on the first processing data to obtain fourth intermediate data after the power delay spectrum calculation processing, where the fourth intermediate data is stored in the cache bus module 404.
The power delay spectrum noise estimation processing module 401262 is configured to perform power delay spectrum noise estimation processing and power delay spectrum noise removal processing on the fourth intermediate data to obtain a channel correlation value after the power delay spectrum noise estimation processing and second processed data after the power delay spectrum noise removal processing; wherein the channel correlation values and the second processed data are output via the output module 40123 for the digital signal processing module 402 or the N second accelerators 403 to process the channel correlation values and the second processed data.
It can be understood that, the power delay spectrum calculation processing module 401261 may perform power delay spectrum calculation processing on the first processing data of the inverse fourier transform processing module 40125 according to a configuration parameter, so as to obtain fifth intermediate data based on a user reference signal; the time delay spectrum calculation processing is that the modular arithmetic is carried out on the first processing data after the IFFT processing; when the data is continuous, and the fifth intermediate data is multiple, after the last fifth intermediate data is obtained, the multiple fifth intermediate data are combined to obtain fourth intermediate data; that is, in the successive processing, a plurality of results of the modulo operation based on the Reference Signal (RS) are obtained and added. After receiving the last data of the user, the result of the addition is output, that is, fourth intermediate data, which may be PDP data that has not been subjected to denoising processing. It is understood that, in an alternative embodiment, if there is multiplexed antenna data divided into layer 0, layer 1, adding means to add and combine OFDM symbols of all layers related to a user, thereby obtaining corresponding PDP data of the user.
The power delay spectrum noise estimation processing module 401262 may receive the power delay spectrum (PDP) data obtained by the power delay spectrum calculation processing module 401261, record a PDP maximum value and a position thereof, try to add all possible noise values by means of segment averaging, cyclic sliding averaging, and the like, calculate an initial position of a noise segment, perform noise estimation processing on the PDP data, obtain a noise power value as a channel correlation value corresponding to the PDP data and output the channel correlation value, where the channel correlation value may also be an index including the initial position; in this step, the original PDP data may be denoised, a value considered as noise on the PDP is removed, and the denoised PDP data is obtained as second processing data and output. The channel correlation value and the second processing data output by the power delay spectrum noise estimation processing module 401262 are provided to the digital signal processing module 402 with stronger data processing capability or other accelerators for correlation operation processing, so as to obtain noise correlation information and filter coefficients, such as signal-to-noise ratio (SNR); the flow of the embodiment of the application is optimized in such a way, so that the time delay of the whole processing can be shortened, and the processing efficiency of the whole system can be improved.
In an optional embodiment, the power delay spectrum noise estimation processing module 401262 is configured to:
according to the configuration parameters, performing power delay spectrum calculation processing on the first processing data to obtain fifth intermediate data based on the user reference signal, and storing the fifth intermediate data into the cache bus module 404;
when the number of the fifth intermediate data is multiple, after the last fifth intermediate data is obtained, extracting multiple fifth intermediate data from the buffer bus module 404 for merging processing to obtain fourth intermediate data; the fourth intermediate data is stored in the cache bus module 404.
Thus, the power delay profile noise estimation processing module 401262 performs the PDP calculation processing and the multi-port symbol combination processing after receiving the last OFDM symbol of the user, writes the result after the combination processing into the cache bus module 404, and outputs the result to the lower module (i.e., the multiplexing module). If there is a division of the multiplexed antenna data into layer 0 and layer 1, the multi-port symbol combining refers to adding the data of layer 0 and layer 1, that is, adding and combining the OFDM symbols of all layers relating to the user.
In an optional embodiment, the symbol extraction processing module 40122 is further configured to generate a local reference sequence according to the configuration parameters, and output the local reference sequence to the cache bus module 404 for processing by the digital signal processing module 402 or the N second accelerators 403. It can be understood that the generated local reference sequence is output by the symbol extraction processing module 40122, which is beneficial for other accelerators to perform subsequent operations, thereby improving the overall efficiency of the system.
Referring to fig. 5, the communication chip 400 further includes a cache bus module 404 and an enhanced bus module 405; the first accelerator 401 performs data transmission interaction with the N second accelerators 403 based on the cache bus module 404, and the first accelerator 401 performs data transmission interaction with the digital signal processing module 402 based on the enhanced bus module 405; the first accelerator 401 or the N second accelerators 403 are each implemented based on a field programmable gate array.
In addition, as shown in fig. 6, the communication apparatus 600 includes a first accelerator 610, where the first accelerator 610 performs data transmission interaction with a digital signal processing module 620 or N second accelerators 630, and the first accelerator 610, when executing, implements the steps of the method for estimating a physical uplink shared channel according to any one of the foregoing method embodiments; the method specifically comprises the following steps: receiving scheduling information issued by a digital signal processing module by taking a symbol as a scheduling unit, wherein the scheduling information carries configuration parameters based on users; according to the configuration parameters, LS channel estimation processing, inverse Fourier transform processing, frequency offset estimation processing and noise estimation processing are carried out on externally input first frequency domain data, and a processing result is output; the processing result comprises a frequency offset estimation value after frequency offset estimation processing, a shifting factor and first processing data after inverse Fourier transform processing, and a channel correlation value and second processing data after noise estimation processing; and reporting the completion information to the digital signal processing module by taking the user as a unit so as to enable the digital signal processing module to process.
Before the LS channel estimation processing, the inverse fourier transform processing, the frequency offset estimation processing, and the noise estimation processing are performed on the externally input first frequency domain data according to the configuration parameters, the method further includes: according to the configuration parameters, symbol scaling processing is carried out on externally input first frequency domain data to obtain and output scaling factors after symbol scaling processing, so that the scaling factors can be processed by a digital signal processing module or N second accelerators; based on the configuration parameters and the scaling factors, carrying out shift processing on symbol data in externally input first frequency domain data to obtain and output second frequency domain data for processing by a digital signal processing module or N second accelerators; wherein the second frequency domain data is associated with a reference signal of the user; extracting effective resource particles from the second frequency domain data as first intermediate data; the first intermediate data is used for LS channel estimation processing, inverse Fourier transform processing, frequency offset estimation processing and noise estimation processing.
According to the configuration parameters, LS channel estimation processing, inverse Fourier transform processing, frequency offset estimation processing and noise estimation processing are carried out on externally input first frequency domain data, and the method comprises the following steps: according to the configuration parameters, LS channel estimation processing is carried out on externally input first frequency domain data to obtain second intermediate data; performing inverse Fourier transform processing on the second intermediate data to obtain and output the shift factor and the first processed data after the inverse Fourier transform processing for processing by a digital signal processing module or N second accelerators; noise estimation processing is carried out on the first processing data, and a channel correlation value and second processing data after the noise estimation processing are obtained and output for processing by a digital signal processing module or N second accelerators; and performing frequency offset estimation processing on the second intermediate data to obtain and output a frequency offset estimation value after the frequency offset estimation processing, so that the frequency offset estimation value is processed by the digital signal processing module or the N second accelerators.
After the LS channel estimation processing is performed on the externally input first frequency domain data according to the configuration parameters to obtain second intermediate data, the method further includes: judging whether the second intermediate data needs to be subjected to decoding division multiplexing processing or not according to the configuration parameters; the configuration parameters comprise identification information used for indicating whether the current user carries out decoding multiplexing processing or not; under the condition that the second intermediate data needs to be subjected to decoding division multiplexing processing, the second intermediate data is subjected to decoding division multiplexing processing to obtain third intermediate data; taking the third intermediate data as new second intermediate data to perform inverse Fourier transform processing and frequency offset estimation processing; or, when it is determined that the decoding/multiplexing process of the second intermediate data is not necessary, the second intermediate data is directly subjected to the inverse fourier transform process and the frequency offset estimation process.
The noise estimation processing is performed on the first processed data to obtain and output a channel correlation value and second processed data after the noise estimation processing, and the method comprises the following steps: performing power time delay spectrum calculation processing on the first processing data to obtain fourth intermediate data after the power time delay spectrum calculation processing; performing power delay spectrum noise estimation processing and power delay spectrum noise removal processing on the fourth intermediate data to obtain a channel correlation value after the power delay spectrum noise estimation processing and second processing data after the power delay spectrum noise removal processing; and outputting the channel correlation values and the second processing data for the digital signal processing module or the N second accelerators to process the channel correlation values and the second processing data.
Performing power delay spectrum calculation processing on the first processing data to obtain fourth intermediate data after the power delay spectrum calculation processing, including: according to the configuration parameters, performing power delay spectrum calculation processing on the first processing data to obtain fifth intermediate data based on the user reference signal; and when the fifth intermediate data is multiple, after the last fifth intermediate data is obtained, merging the multiple fifth intermediate data to obtain fourth intermediate data.
Before the LS channel estimation processing is performed on the externally input first frequency domain data according to the configuration parameters to obtain the second intermediate data, the method further includes: generating and outputting a local reference sequence for processing by the digital signal processing module or the N second accelerators according to the configuration parameters; based on the local reference sequence and the externally input first frequency domain data, LS channel estimation processing is carried out to obtain second intermediate data.
Besides, the embodiment of the present application provides another communication apparatus, where the communication apparatus 600 includes a communication chip, and the communication chip is a module of the communication chip provided in any one of the foregoing embodiments of the communication chip. The method comprises the following specific steps:
the communication chip is provided with a first accelerator, the first accelerator is respectively in data transmission interaction with the digital signal processing module and N second accelerators, and N is a positive integer greater than or equal to 1; the first accelerator comprises a receiving module and a processing module, the processing module is connected with the receiving module, wherein: the receiving module is used for receiving scheduling information which is issued by the digital signal processing module by taking the symbol as a scheduling unit, and the scheduling information carries configuration parameters based on users; the processing module is used for carrying out LS channel estimation processing, inverse Fourier transform processing, frequency offset estimation processing and noise estimation processing on externally input first frequency domain data according to the configuration parameters and outputting a processing result; the processing result comprises a frequency offset estimation value after frequency offset estimation processing, a shifting factor and first processing data after inverse Fourier transform processing, and a channel correlation value and second processing data after noise estimation processing; and the processing module is also used for reporting the completion information to the digital signal processing module by taking the user as a unit so as to enable the digital signal processing module to process.
In an optional embodiment, the communication chip is further provided with a cache bus module, the processing module includes a symbol scaling processing module, a symbol extraction processing module and an output module, the symbol scaling processing module is respectively connected with the symbol extraction processing module and the output module, and the cache bus module is respectively connected with the symbol scaling processing module and the symbol extraction processing module, wherein: the symbol scaling processing module is used for extracting first frequency domain data input from the external from the buffer bus module according to the configuration parameters to perform symbol scaling processing, obtaining and outputting scaling factors after the symbol scaling processing through the output module so as to be processed by the digital signal processing module or the N second accelerators; the symbol extraction processing module is used for shifting symbol data in externally input first frequency domain data based on the configuration parameters and the scaling factors to obtain and output second frequency domain data for the digital signal processing module or the N second accelerators to process; the second frequency domain data are related to reference signals of users and are stored in the cache bus module; the symbol extraction processing module is further used for extracting effective resource particles from the second frequency domain data as first intermediate data; the first intermediate data is used for LS channel estimation processing, inverse Fourier transform processing, frequency offset estimation processing and noise estimation processing.
In an optional embodiment, the communication chip is further provided with a cache bus module, the processing module includes an LS channel estimation processing module, an inverse fourier transform processing module, a noise estimation processing module, and a frequency offset estimation processing module, the LS channel estimation processing module is respectively connected with the inverse fourier transform processing module and the frequency offset estimation processing module, the noise estimation processing module is connected with the inverse fourier transform processing module, and the noise estimation processing module is connected with the cache bus module, wherein: the LS channel estimation processing module is used for carrying out LS channel estimation processing on externally input first frequency domain data according to the configuration parameters to obtain second intermediate data; the inverse Fourier transform processing module is used for performing inverse Fourier transform processing on the second intermediate data to obtain and output the shift factor and the first processing data after the inverse Fourier transform processing so as to be processed by the digital signal processing module or the N second accelerators; the first processing data are stored in the cache bus module; the noise estimation processing module is used for carrying out noise estimation processing on the first processing data to obtain and output a channel correlation value and second processing data after the noise estimation processing, so that the channel correlation value and the second processing data can be processed by the digital signal processing module or the N second accelerators; the second processing data are stored in the cache bus module; and the frequency offset estimation processing module is used for carrying out frequency offset estimation processing on the second intermediate data to obtain and output a frequency offset estimation value after the frequency offset estimation processing so as to be processed by the digital signal processing module or the N second accelerators.
In an optional embodiment, the processing module further includes a decoding multiplexing processing module, the LS channel estimation processing module is connected to the inverse fourier transform processing module and the frequency offset estimation processing module through the decoding multiplexing processing module, and the decoding multiplexing processing module is connected to the cache bus module, where: the receiving module is further used for judging whether the second intermediate data needs to be subjected to decoding division multiplexing processing or not according to the configuration parameters; the configuration parameters comprise identification information used for indicating whether the current user carries out decoding multiplexing processing or not; the decoding division multiplexing processing module is used for performing decoding division multiplexing processing on the second intermediate data to obtain third intermediate data under the condition that the decoding division multiplexing processing on the second intermediate data is judged to be needed; respectively transmitting the third intermediate data serving as new second intermediate data to an inverse Fourier transform processing module and a frequency offset estimation processing module; the third intermediate data is stored in the cache bus module; or, the decoding multiplexing processing module is configured to respectively transmit the second intermediate data to the inverse fourier transform processing module and the frequency offset estimation processing module under the condition that it is determined that the decoding multiplexing processing on the second intermediate data is not required; and the second intermediate data is stored in the cache bus module.
In an optional embodiment, the processing module further includes an output module, the noise estimation processing module includes a power delay spectrum calculation processing module and a power delay spectrum noise estimation processing module, the power delay spectrum calculation processing module is respectively connected with the inverse fourier transform processing module and the power delay spectrum noise estimation processing module, and the power delay spectrum noise estimation processing module is connected with the output module; wherein: the power time delay spectrum calculation processing module is used for performing power time delay spectrum calculation processing on the first processing data to obtain fourth intermediate data after the power time delay spectrum calculation processing; the fourth intermediate data is stored in the cache bus module; the power delay spectrum noise estimation processing module is used for carrying out power delay spectrum noise estimation processing and power delay spectrum noise removal processing on the fourth intermediate data to obtain a channel correlation value after the power delay spectrum noise estimation processing and second processing data after the power delay spectrum noise removal processing; and the channel correlation value and the second processing data are output through the output module so as to be processed by the digital signal processing module or the N second accelerators.
In an optional embodiment, the power delay spectrum noise estimation processing module is configured to: according to the configuration parameters, performing power delay spectrum calculation processing on the first processing data to obtain fifth intermediate data based on the user reference signal; the fifth intermediate data is stored in the cache bus module; when the number of the fifth intermediate data is multiple, after the last fifth intermediate data is obtained, extracting multiple fifth intermediate data from the buffer bus module to perform merging processing to obtain fourth intermediate data; and storing the fourth intermediate data into the cache bus module.
In an optional embodiment, the symbol extraction processing module is further configured to generate a local reference sequence according to the configuration parameter; wherein, the local reference sequence is stored in the cache bus module; the processing module further comprises an LS channel estimation processing module, and the LS channel estimation processing module is used for carrying out LS channel estimation processing on the basis of the local reference sequence and the externally input first frequency domain data to obtain second intermediate data.
In an optional embodiment, the communication chip further comprises a cache bus module and an enhanced bus module; the first accelerator and the N second accelerators perform data transmission interaction based on the cache bus module respectively, and the first accelerator and the digital signal processing module perform data transmission interaction based on the enhanced bus module; the first accelerator and the N second accelerators are respectively realized based on a field programmable logic gate array.
Besides, an embodiment of the present application further provides a computer-readable storage medium, as shown in fig. 7, a computer program is stored on the computer-readable storage medium 700, and when being executed by the processor 710, the computer program implements the steps of the method for estimating a physical uplink shared channel, provided by any one of the method embodiments described above. One of ordinary skill in the art can appreciate that computer-readable media can include computer storage media (or non-transitory media) and communication media (or transitory media). The term computer storage media includes volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data, as is well known to those of ordinary skill in the art. Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, Digital Versatile Disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and which can accessed by a computer. In addition, communication media typically embodies computer readable instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism and includes any information delivery media as known to those skilled in the art.
The foregoing are merely exemplary embodiments of the present invention, which enable those skilled in the art to understand or practice the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (18)
1. The method for estimating the physical uplink shared channel is characterized by being applied to a first accelerator, wherein the first accelerator performs data transmission interaction with a digital signal processing module and N second accelerators respectively, and N is a positive integer greater than or equal to 1; the method comprises the following steps:
receiving scheduling information issued by the digital signal processing module by taking a symbol as a scheduling unit, wherein the scheduling information carries configuration parameters based on users;
according to the configuration parameters, LS channel estimation processing, inverse Fourier transform processing, frequency offset estimation processing and noise estimation processing are carried out on externally input first frequency domain data, and processing results are output; wherein, the processing result comprises the frequency offset estimation value after the frequency offset estimation processing, the shift factor and the first processing data after the inverse Fourier transform processing, and the channel correlation value and the second processing data after the noise estimation processing;
and reporting completion information to the digital signal processing module by taking a user as a unit so as to enable the digital signal processing module to process.
2. The method of claim 1, wherein before the LS channel estimation process, the inverse fourier transform process, the frequency offset estimation process, and the noise estimation process are performed on the externally input first frequency domain data according to the configuration parameters, the method further comprises:
according to the configuration parameters, symbol scaling processing is carried out on externally input first frequency domain data to obtain and output scaling factors after the symbol scaling processing, so that the scaling factors are processed by the digital signal processing module or the N second accelerators;
based on the configuration parameters and the scaling factors, carrying out shift processing on symbol data in externally input first frequency domain data to obtain and output second frequency domain data for processing by the digital signal processing module or the N second accelerators; wherein the second frequency domain data is associated with a reference signal of a user;
extracting effective resource elements from the second frequency domain data as first intermediate data; wherein the first intermediate data is used for the LS channel estimation processing, the inverse Fourier transform processing, the frequency offset estimation processing, and the noise estimation processing.
3. The method of claim 1, wherein performing the LS channel estimation process, the inverse fourier transform process, the frequency offset estimation process, and the noise estimation process on the externally input first frequency domain data according to the configuration parameters comprises:
according to the configuration parameters, LS channel estimation processing is carried out on externally input first frequency domain data to obtain second intermediate data;
performing inverse Fourier transform processing on the second intermediate data to obtain and output the shift factor and the first processed data after the inverse Fourier transform processing, so as to be processed by the digital signal processing module or the N second accelerators;
performing noise estimation processing on the first processing data to obtain and output a channel correlation value and second processing data after the noise estimation processing, so that the channel correlation value and the second processing data are provided for the digital signal processing module or the N second accelerators to process;
and performing frequency offset estimation processing on the second intermediate data to obtain and output a frequency offset estimation value after the frequency offset estimation processing, so that the digital signal processing module or the N second accelerators can process the frequency offset estimation value.
4. The method of claim 3, wherein after the LS channel estimation process is performed on the externally input first frequency domain data according to the configuration parameters to obtain second intermediate data, the method further comprises:
judging whether the second intermediate data needs to be subjected to decoding division multiplexing processing or not according to the configuration parameters; the configuration parameters comprise identification information used for indicating whether the current user carries out decoding division multiplexing processing or not;
under the condition that the second intermediate data needs to be subjected to decoding division multiplexing processing, the second intermediate data is subjected to decoding division multiplexing processing to obtain third intermediate data; taking the third intermediate data as new second intermediate data to perform the inverse fourier transform processing and the frequency offset estimation processing; or the like, or, alternatively,
and under the condition that the second intermediate data does not need to be subjected to decoding multiplexing processing, directly performing the inverse Fourier transform processing and the frequency offset estimation processing on the second intermediate data.
5. The method of claim 3, wherein performing noise estimation processing on the first processed data to obtain and output the channel correlation value after the noise estimation processing and second processed data comprises:
performing power time delay spectrum calculation processing on the first processing data to obtain fourth intermediate data after the power time delay spectrum calculation processing;
performing power delay spectrum noise estimation processing and power delay spectrum de-noising processing on the fourth intermediate data to obtain a channel correlation value after the power delay spectrum noise estimation processing and second processed data after the power delay spectrum de-noising processing;
outputting the channel correlation value and the second processing data for the digital signal processing module or the N second accelerators to process the channel correlation value and the second processing data.
6. The method according to claim 5, wherein performing power delay profile calculation processing on the first processed data to obtain fourth intermediate data after the power delay profile calculation processing includes:
according to the configuration parameters, performing power time delay spectrum calculation processing on the first processing data to obtain fifth intermediate data based on a user reference signal;
and when the number of the fifth intermediate data is multiple, after the last fifth intermediate data is obtained, merging the multiple fifth intermediate data to obtain fourth intermediate data.
7. The method of claim 3, wherein before the LS channel estimation processing is performed on the externally input first frequency domain data according to the configuration parameters to obtain the second intermediate data, the method further comprises:
generating and outputting a local reference sequence according to the configuration parameters for processing by the digital signal processing module or the N second accelerators;
and performing the LS channel estimation processing based on the local reference sequence and the externally input first frequency domain data to obtain the second intermediate data.
8. The method of claim 1, wherein the first accelerator interacts with the N second accelerators for data transfer based on a cache bus module; the first accelerator and the digital signal processing module perform data transmission interaction based on an enhanced bus module; the first accelerator and the N second accelerators are respectively realized based on a field programmable gate array.
9. A communication chip is characterized in that the communication chip is provided with a first accelerator, the first accelerator performs data transmission interaction with a digital signal processing module and N second accelerators respectively, and N is a positive integer greater than or equal to 1; the first accelerator comprises a receiving module and a processing module, the processing module is connected with the receiving module, wherein:
the receiving module is configured to receive scheduling information issued by the digital signal processing module with a symbol as a scheduling unit, where the scheduling information carries a configuration parameter based on a user;
the processing module is used for performing LS channel estimation processing, inverse Fourier transform processing, frequency offset estimation processing and noise estimation processing on externally input first frequency domain data according to the configuration parameters and outputting processing results; wherein, the processing result comprises the frequency offset estimation value after the frequency offset estimation processing, the shift factor and the first processing data after the inverse Fourier transform processing, and the channel correlation value and the second processing data after the noise estimation processing; and the number of the first and second groups,
the processing module is further configured to report completion information to the digital signal processing module by using a user as a unit, so that the digital signal processing module performs processing.
10. The communication chip according to claim 9, wherein the communication chip is further provided with a cache bus module, the processing module includes a symbol scaling processing module, a symbol extraction processing module and an output module, the symbol scaling processing module is respectively connected with the symbol extraction processing module and the output module, and the cache bus module is respectively connected with the symbol scaling processing module and the symbol extraction processing module, wherein:
the symbol scaling processing module is configured to extract first frequency domain data input from the cache bus module according to the configuration parameter, perform symbol scaling processing, obtain and output a scaling factor after the symbol scaling processing through the output module, so as to be processed by the digital signal processing module or the N second accelerators;
the symbol extraction processing module is configured to shift symbol data in externally input first frequency domain data based on the configuration parameter and the scaling factor to obtain and output second frequency domain data, so that the symbol data is processed by the digital signal processing module or the N second accelerators; the second frequency domain data are related to reference signals of users and stored in the cache bus module;
the symbol extraction processing module is further configured to extract effective resource elements from the second frequency domain data as first intermediate data; wherein the first intermediate data is used for the LS channel estimation processing, the inverse Fourier transform processing, the frequency offset estimation processing, and the noise estimation processing.
11. The communication chip according to claim 9, wherein the communication chip is further provided with a cache bus module, the processing module includes an LS channel estimation processing module, an inverse fourier transform processing module, a noise estimation processing module and a frequency offset estimation processing module, the LS channel estimation processing module is respectively connected with the inverse fourier transform processing module and the frequency offset estimation processing module, the noise estimation processing module is connected with the inverse fourier transform processing module, and the noise estimation processing module is connected with the cache bus module, wherein:
the LS channel estimation processing module is used for carrying out LS channel estimation processing on externally input first frequency domain data according to the configuration parameters to obtain second intermediate data;
the inverse fourier transform processing module is configured to perform inverse fourier transform processing on the second intermediate data to obtain and output the shift factor and the first processed data after the inverse fourier transform processing, so that the shift factor and the first processed data are provided for the digital signal processing module or the N second accelerators to process; the first processing data is stored in the cache bus module;
the noise estimation processing module is configured to perform noise estimation processing on the first processed data to obtain and output a channel correlation value and second processed data after the noise estimation processing, so that the channel correlation value and the second processed data are provided for processing by the digital signal processing module or the N second accelerators; the second processing data is stored into the cache bus module;
and the frequency offset estimation processing module is configured to perform frequency offset estimation processing on the second intermediate data to obtain and output a frequency offset estimation value after the frequency offset estimation processing, so that the digital signal processing module or the N second accelerators can perform processing.
12. The communication chip of claim 11, wherein the processing module further comprises a de-multiplexing processing module, the LS channel estimation processing module is connected to the inverse fourier transform processing module and the frequency offset estimation processing module through the de-multiplexing processing module, respectively, and the de-multiplexing processing module is connected to the cache bus module, wherein:
the receiving module is further configured to determine whether decoding multiplexing processing needs to be performed on the second intermediate data according to the configuration parameter; the configuration parameters comprise identification information used for indicating whether the current user carries out decoding division multiplexing processing or not;
the decoding multiplexing processing module is configured to perform decoding multiplexing processing on the second intermediate data to obtain third intermediate data when it is determined that the decoding multiplexing processing needs to be performed on the second intermediate data; the third intermediate data are used as new second intermediate data and are respectively transmitted to the inverse Fourier transform processing module and the frequency offset estimation processing module; the third intermediate data is stored in the cache bus module; or the like, or, alternatively,
the decoding multiplexing processing module is configured to determine that the second intermediate data is not required to be subjected to decoding multiplexing processing, and transparently transmit the second intermediate data to the inverse fourier transform processing module and the frequency offset estimation processing module respectively; and the second intermediate data is stored into the cache bus module.
13. The communication chip according to claim 11, wherein the processing module further includes an output module, the noise estimation processing module includes a power delay spectrum calculation processing module and a power delay spectrum noise estimation processing module, the power delay spectrum calculation processing module is respectively connected to the inverse fourier transform processing module and the power delay spectrum noise estimation processing module, and the power delay spectrum noise estimation processing module is connected to the output module; wherein:
the power delay spectrum calculation processing module is used for performing power delay spectrum calculation processing on the first processing data to obtain fourth intermediate data after the power delay spectrum calculation processing; the fourth intermediate data is stored in the cache bus module;
the power delay spectrum noise estimation processing module is configured to perform power delay spectrum noise estimation processing and power delay spectrum noise removal processing on the fourth intermediate data to obtain a channel correlation value after the power delay spectrum noise estimation processing and second processing data after the power delay spectrum noise removal processing; wherein the channel correlation values and the second processed data are output via the output module for processing by the digital signal processing module or the N second accelerators.
14. The communication chip of claim 13, wherein the power delay profile estimation processing module is configured to:
according to the configuration parameters, performing power delay spectrum calculation processing on the first processing data to obtain fifth intermediate data based on a user reference signal; the fifth intermediate data is stored into the cache bus module;
when a plurality of fifth intermediate data are obtained, after the last fifth intermediate data are obtained, extracting the plurality of fifth intermediate data from the cache bus module to carry out merging processing, so as to obtain fourth intermediate data; and the fourth intermediate data is stored into the cache bus module.
15. The communication chip according to claim 10, wherein the symbol extraction processing module is further configured to generate a local reference sequence according to the configuration parameter; wherein, the local reference sequence is stored in the cache bus module;
the processing module further includes an LS channel estimation processing module, and the LS channel estimation processing module is configured to perform LS channel estimation processing based on the local reference sequence and the externally input first frequency domain data to obtain second intermediate data.
16. The communication chip of claim 9, further comprising a cache bus module and an enhanced bus module; the first accelerator and the N second accelerators perform data transmission interaction based on a cache bus module respectively, and the first accelerator and the digital signal processing module perform data transmission interaction based on an enhanced bus module; the first accelerator and the N second accelerators are respectively realized based on a field programmable logic gate array.
17. A communication apparatus, characterized in that the apparatus comprises a first accelerator, the first accelerator performing the method for estimating physical uplink shared channel according to any one of claims 1 to 8; or the like, or, alternatively,
the device comprises a communication chip, wherein the communication chip is the communication chip as claimed in any one of claims 9 to 16.
18. A computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and the computer program is executed by a processor to implement the method for estimating a physical uplink shared channel according to any one of claims 1 to 8.
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