CN115000111A - Backside illuminated image sensor and forming method - Google Patents

Backside illuminated image sensor and forming method Download PDF

Info

Publication number
CN115000111A
CN115000111A CN202210694876.5A CN202210694876A CN115000111A CN 115000111 A CN115000111 A CN 115000111A CN 202210694876 A CN202210694876 A CN 202210694876A CN 115000111 A CN115000111 A CN 115000111A
Authority
CN
China
Prior art keywords
dielectric layer
layer
epitaxial
forming
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202210694876.5A
Other languages
Chinese (zh)
Inventor
赵立新
徐涛
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Galaxycore Shanghai Ltd Corp
Original Assignee
Galaxycore Shanghai Ltd Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Galaxycore Shanghai Ltd Corp filed Critical Galaxycore Shanghai Ltd Corp
Priority to CN202210694876.5A priority Critical patent/CN115000111A/en
Publication of CN115000111A publication Critical patent/CN115000111A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • H01L27/14685—Process for coatings or optical elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/1464—Back illuminated imager structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14643—Photodiode arrays; MOS imagers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof

Abstract

The invention provides a back-illuminated image sensor and a forming method thereof.A plurality of epitaxial laminated layers with a plurality of grooves are formed in the front surface of a first substrate, the bottom and at least part of the side wall of each groove are covered with a dielectric layer, and the dielectric layer is used as an etching stop layer and is stopped at the dielectric layer when the first substrate is removed and the epitaxial laminated layers are thinned, so that the etching end point is accurately controlled. The groove extends from the surface of the first epitaxial layer to the first substrate, and the stress of the first epitaxial layer is released, so that warping or deformation caused by the stress is avoided. The interface between the dielectric layer and the first epitaxial layer can adsorb impurity metal ions for isolating the impurity metal ions from the first substrate.

Description

Backside illuminated image sensor and forming method
Technical Field
The invention relates to the technical field of semiconductors, in particular to a back-illuminated image sensor and a forming method.
Background
With the development of image sensing technology, CMOS image sensors are increasingly used in various electronic products instead of CCD image sensors. The CMOS image sensor includes a front-illuminated (FSI) image sensor and a back-illuminated (BSI) image sensor.
In the prior art, after a photosensitive device layer is formed on a first substrate, the first substrate is turned over and bonded with a second substrate, and then the first substrate is removed by grinding and/or wet etching, because the etching selection ratio or the grinding selection ratio is not high, the device stack is damaged, and the performance is reduced.
Therefore, how to provide a method for manufacturing an image sensor to solve the above problems in the prior art is necessary.
Disclosure of Invention
The invention aims to provide a back-illuminated image sensor and a forming method thereof.
In view of the above, the present invention provides a method of forming a backside illuminated image sensor, comprising: and forming an epitaxial lamination layer in which a plurality of grooves are formed on the front surface of the first substrate, wherein a dielectric layer covers the bottom and at least part of the side wall of each groove, and the epitaxial lamination layer is stopped at the dielectric layer when the first substrate is removed and thinned.
Preferably, the groove is used for releasing the stress of the epitaxial stacked layer, and further includes: and removing the dielectric layer.
Preferably, the epitaxial stack includes a first epitaxial layer and a second epitaxial layer stacked, each of the grooves extends from the surface of the first epitaxial layer toward the first substrate, and the second epitaxial layer closes a top of each of the grooves.
Preferably, the second epitaxial layer further covers the remaining sidewalls of each of the grooves.
Preferably, the second epitaxial layer further extends to the bottom of each of the grooves and covers a part of the dielectric layer.
Preferably, the forming of the dielectric layer covering the bottom and at least part of the sidewall of each of the grooves includes: and forming a dielectric layer covering the bottom and the side wall of each groove on the first epitaxial layer, and performing back etching to remove at least the dielectric layer on the first epitaxial layer.
Preferably, the dielectric layer is further recessed and closes the top of each groove.
Preferably, the back etching also at least removes the dielectric layer closing the top of each groove.
Preferably, the dielectric layer includes a first sub-dielectric layer and a second sub-dielectric layer stacked, and the second sub-dielectric layer is recessed and closes the top of each recess.
Preferably, the material of the first sub-dielectric layer includes one of silicon nitride, silicon oxide, silicon carbonitride, silicon carbide and silicon oxynitride, and the material of the second sub-dielectric layer includes another one of silicon nitride, silicon oxide, silicon carbonitride, silicon carbide and silicon oxynitride.
Preferably, before thinning the epitaxial stack, the first substrate is removed and stops on the first epitaxial layer.
Preferably, thinning the epitaxial stack comprises: and thinning the first epitaxial layer and stopping at the dielectric layer.
Preferably, the dielectric layer is removed after stopping on the dielectric layer.
Preferably, after removing the dielectric layer, the first epitaxial layer is removed and the second epitaxial layer is planarized.
Preferably, the thickness of the first epitaxial layer is 0.2-2 μm, and the thickness of the second epitaxial layer is 3-4 μm.
Preferably, before removing the first substrate, a bonding layer is formed on the epitaxial stack and the first substrate is flipped to be bonded to a second substrate.
Another aspect of the present invention provides a front-illuminated image sensor formed using the above-described forming method.
According to the invention, the epitaxial lamination layer provided with a plurality of grooves is formed on the front surface of the first substrate, the bottom and at least part of the side wall of each groove are covered with the dielectric layer, the dielectric layer is used as an etching stop layer, and the dielectric layer is stopped when the first substrate is removed and the epitaxial lamination layer is thinned, so that the etching end point is accurately controlled.
Further, the groove extends from the surface of the first epitaxial layer to the first substrate, so that the stress of the first epitaxial layer is released, and warping or deformation caused by the stress is avoided.
Furthermore, the interface between the dielectric layer and the first epitaxial layer can adsorb impurity metal ions for isolating the impurity metal ions from the first substrate, so that the requirement on the first substrate can be properly reduced.
Drawings
Other features, objects and advantages of the present invention will become more apparent from the following detailed description of non-limiting embodiments thereof, which is to be read in connection with the accompanying drawings.
Fig. 1 to 8 are schematic cross-sectional views illustrating steps of a method for forming a backside illuminated image sensor according to an embodiment of the present invention.
In the drawings, like or similar reference numbers indicate like or similar devices (modules) or steps throughout the different views.
Detailed Description
In order to make the contents of the present invention more clearly understood, the contents of the present invention will be further described with reference to the accompanying drawings. The invention is of course not limited to this particular embodiment, and general alternatives known to those skilled in the art are also covered by the scope of the invention.
In the following detailed description of the embodiments of the present invention, in order to clearly illustrate the structure of the present invention and to facilitate explanation, the structure shown in the drawings is not drawn to a general scale and is partially enlarged, deformed and simplified, so that the present invention should not be construed as limited thereto.
In order to solve the problems in the prior art, the invention forms the epitaxial lamination layer provided with a plurality of grooves in the front surface of the first substrate, the bottom and at least part of the side wall of each groove are covered with the dielectric layer, and the dielectric layer is used as an etching stop layer and is stopped at the dielectric layer when the first substrate is removed and the epitaxial lamination layer is thinned, thereby accurately controlling the etching end point.
A method for forming an image sensor according to the present invention will be described in detail below with reference to the accompanying drawings.
As shown in fig. 1, a first substrate 100 is provided, the first substrate 100 having opposing front (upper as shown) and back (lower as shown) surfaces.
In this embodiment, the material of the first substrate 100 is silicon, and in other embodiments, the material of the first substrate 100 may also be germanium, silicon carbide, gallium arsenide, or indium gallium arsenide.
A first epitaxial layer 101 is formed on the front surface of the first substrate 100, and the first epitaxial layer 101 is patterned to form a plurality of grooves 102.
As shown in fig. 1, the recess 102 extends from the surface of the first epitaxial layer 101 toward the first substrate 100.
Next, as shown in fig. 2, a dielectric layer covering the bottom and sidewalls of each of the grooves 102 is formed on the first epitaxial layer 101.
In this embodiment, a first sub-dielectric layer 103 is formed on the first epitaxial layer 101, and covers the bottom and the sidewall of the groove 102, and the thickness thereof is less than half of the lateral dimension of the groove 102.
The material of the first sub-dielectric layer 103 includes one of silicon nitride, silicon oxide, silicon carbonitride, silicon carbide, and silicon oxynitride, and the interface between the first sub-dielectric layer and the first epitaxial layer may adsorb impurity metal ions for isolating the impurity metal ions from the first substrate 100.
The first sub-dielectric layer 103 may be formed by a thermal oxidation process, a chemical vapor deposition process, an atomic layer deposition process, or the like. For example, the first sub-dielectric layer 103 made of silicon oxide is formed by a thermal oxidation process, which has a characteristic of forming a thick oxide layer in a short time, so that high production efficiency and low production cost can be obtained. Meanwhile, the first sub-dielectric layer 103 with complete appearance and uniform thickness can be formed on the side wall and the bottom of the groove 102 with the larger aspect ratio.
The second sub-dielectric layer 104 is formed on the first sub-dielectric layer 103, and the material thereof includes another one of silicon nitride, silicon oxide, silicon carbonitride, silicon carbide, and silicon oxynitride.
The second sub-dielectric layer 104 may be formed on the first sub-dielectric layer 103 by a deposition process. As shown in fig. 2, the second sub-dielectric layers located on the sidewalls of the two sides of the recess 102 are merged at the top of the recess 102, thereby closing the top of each of the recesses 102.
In this embodiment, the first sub-dielectric layer 103 is made of silicon oxide with better adhesion to the first epitaxial side 101, and the second sub-dielectric layer 104 is made of silicon nitride with better isolation performance.
Due to the large aspect ratio of the groove 102, the second sub-dielectric layer 104 is not enough to completely fill the groove 102, and after a long deposition time, the top surface of the second sub-dielectric layer 104 on the top of the groove 102 is closed, and a hollow cavity 105 is formed inside the groove 102, which is favorable for releasing stress.
In another embodiment, the dielectric layer is a single-layer first sub-dielectric layer 103 or a single-layer second sub-dielectric layer 104, and the dielectric layer does not completely fill the recesses 102 and recesses and closes the top of each recess 102 by prolonging the thermal oxidation time or the deposition time, so as to form a hollow cavity 105 in the recess 102.
And then, etching back to remove the dielectric layer on at least the first epitaxial layer 101. For example, while the dielectric layer on the first epitaxial layer 101 is removed by using the etch-back process, the etch-back process also removes at least the dielectric layer closing the top of each of the grooves 102.
As shown in fig. 3, in the present embodiment, the second sub-dielectric layer 104 and the first epitaxial layer 101 are etched back to a predetermined depth to expose the first epitaxial layer 101, the top of the recess 102 and a portion of the sidewall.
Then, a second epitaxial layer 106 is formed on the first epitaxial layer 101.
As shown in fig. 4, the second epitaxial layer 106 is further filled on top of the recesses 102 and covers the remaining sidewalls of each of the recesses 102. Through the epitaxial growth time of the second epitaxial layer 106, the second epitaxial layer 106 can also extend towards the bottom of each of the grooves 102, i.e., fill the hollow inner walls 105 and cover a part of the dielectric layer.
The conductivity types of the first epitaxial layer 101, the second epitaxial layer 106 and the first substrate 100 are the same, and may all be a first conductivity type or all be a second conductivity type.
The doping concentration of the first epitaxial layer 101 and the second epitaxial layer 106 may be at most 5E15 atoms/cm 3 . The second epitaxyLayer 106 is used to form a number of photosensitive regions (not shown) arranged in an array.
In this embodiment, the first epitaxial layer 101 and the second epitaxial layer 106 have a first conductivity type, and the photosensitive region has a second conductivity type. The thickness of the first epitaxial layer 101 ranges from 0.2 mu m to 2 mu m, and the thickness of the second epitaxial layer 106 ranges from 3 mu m to 4 mu m.
A device stack is then formed on the second epitaxial layer 106, the device stack including a metal interconnect layer (not shown) and a first bonding layer (not shown) on the metal interconnect layer. The metal interconnection layer is provided with a plurality of interconnection structures, and may further include other devices (not shown), such as a passive device stack (not shown) and a radio frequency device (not shown).
The forming method and structure of the device stack may be selected from conventional manufacturing methods, and those skilled in the art may select the device stack according to actual needs by referring to the prior art, which is not described herein again.
As shown in fig. 5, a second substrate 200 is provided, the first substrate 100 is flipped over so that the back surface of the first substrate 100 faces away from the second substrate 200, and the first substrate 100 and the second substrate 200 are bonded.
The second substrate 200 is a carrier wafer (carrier wafer) for carrying and protecting the photosensitive device layer in the subsequent processes of removing the first substrate 100, thinning the first epitaxial layer 101, and others. The second substrate 200 may be a silicon substrate or other suitable substrate, and is not limited herein.
The second substrate 200 is bonded to the surface of the photosensitive device layer on the front side of the first substrate 100 by a bonding process, which may be performed by any method known to those skilled in the art.
As shown in fig. 6, the first substrate 100 is removed from the back surface.
The front surface of the first substrate 100 is covered with the first epitaxial layer 101, and a chemical mechanical polishing process is adopted to remove the first substrate 100 and expose the first epitaxial layer 101, and stop at the dielectric layer at the bottom of the groove.
The dielectric layer is removed as shown in fig. 7.
In this embodiment, the first sub-dielectric layer 103 and the second sub-dielectric layer 104 are removed by an etching process to expose the recess 102.
In this embodiment, as shown in fig. 8, after the dielectric layer is removed, the first epitaxial layer 101 is removed by using a chemical mechanical polishing process, and the second epitaxial layer 106 is thinned until the second epitaxial layer 106 is planarized.
According to the invention, the epitaxial lamination layer provided with a plurality of grooves is formed on the front surface of the first substrate, the bottom and at least part of the side wall of each groove are covered with the dielectric layer, the dielectric layer is used as an etching stop layer, and the dielectric layer is stopped when the first substrate is removed and the epitaxial lamination layer is thinned, so that the etching end point is accurately controlled.
Further, the groove extends from the surface of the first epitaxial layer to the first substrate, so that the stress of the first epitaxial layer is released, and warping or deformation caused by the stress is avoided.
Furthermore, the interface between the dielectric layer and the first epitaxial layer can adsorb impurity metal ions for isolating the impurity metal ions from the first substrate.
It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential attributes thereof. The present embodiments are, therefore, to be considered in all respects as illustrative and not restrictive. Furthermore, it will be obvious that the word "comprising" does not exclude other elements or steps, and the word "a" or "an" does not exclude a plurality. Several elements recited in the apparatus claims may also be embodied by one element. The terms first, second, etc. are used to denote names, but not any particular order.

Claims (17)

1. A method of forming a back-illuminated image sensor, comprising: and forming an epitaxial lamination layer in which a plurality of grooves are formed on the front surface of the first substrate, wherein a dielectric layer covers the bottom and at least part of the side wall of each groove, and the epitaxial lamination layer is stopped at the dielectric layer when the first substrate is removed and thinned.
2. The method of forming of claim 1, wherein the recess is to relieve stress of the epitaxial stack, further comprising: and removing the dielectric layer.
3. The method of forming of claim 2, wherein the epitaxial stack includes a first epitaxial layer and a second epitaxial layer stacked, each of the recesses extending from the first epitaxial layer surface toward the first substrate, the second epitaxial layer closing a top of each of the recesses.
4. The method of forming of claim 3 wherein said second epitaxial layer also covers remaining sidewalls of each of said recesses.
5. The method of forming of claim 4, wherein the second epitaxial layer further extends toward a bottom of each of the recesses and covers a portion of the dielectric layer.
6. The method of claim 3, wherein forming the dielectric layer overlying the bottom and at least a portion of the sidewalls of each of the recesses comprises: and forming a dielectric layer covering the bottom and the side wall of each groove on the first epitaxial layer, and performing back etching to remove at least the dielectric layer on the first epitaxial layer.
7. The method of forming of claim 6, wherein the dielectric layer further recesses and closes a top of each of the recesses.
8. The method of forming of claim 7, wherein the etch back further removes at least the dielectric layer closing the top of each of the recesses.
9. The method of forming of claim 8, wherein the dielectric layer comprises a first sub-dielectric layer and a second sub-dielectric layer stacked, the second sub-dielectric layer recessed and closing a top of each of the recesses.
10. The method of claim 9, wherein the material of the first sub-dielectric layer comprises one of silicon nitride, silicon oxide, silicon carbonitride, silicon carbide, and silicon oxynitride, and the material of the second sub-dielectric layer comprises another one of silicon nitride, silicon oxide, silicon carbonitride, silicon carbide, and silicon oxynitride.
11. The method of forming of claim 3, wherein the first substrate is removed and stops on the first epitaxial layer before the epitaxial stack is thinned.
12. The method of forming of claim 11, wherein thinning the epitaxial stack comprises: and thinning the first epitaxial layer and stopping at the dielectric layer.
13. The method of forming of claim 12, wherein the dielectric layer is removed after stopping on the dielectric layer.
14. The method of forming of claim 13, wherein after removing the dielectric layer, removing the first epitaxial layer and planarizing the second epitaxial layer.
15. The method of forming of claim 3, wherein a thickness of the first epitaxial layer comprises 0.2 μ ι η to 2 μ ι η and a thickness of the second epitaxial layer comprises 3 μ ι η to 4 μ ι η.
16. The method of forming of claim 1, wherein prior to removing the first substrate, forming a bonding layer on the epitaxial stack and flipping the first substrate to bond to a second substrate.
17. A back-illuminated image sensor formed by the method for forming a back-illuminated image sensor according to any one of claims 1 to 16.
CN202210694876.5A 2022-06-20 2022-06-20 Backside illuminated image sensor and forming method Pending CN115000111A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202210694876.5A CN115000111A (en) 2022-06-20 2022-06-20 Backside illuminated image sensor and forming method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202210694876.5A CN115000111A (en) 2022-06-20 2022-06-20 Backside illuminated image sensor and forming method

Publications (1)

Publication Number Publication Date
CN115000111A true CN115000111A (en) 2022-09-02

Family

ID=83035726

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202210694876.5A Pending CN115000111A (en) 2022-06-20 2022-06-20 Backside illuminated image sensor and forming method

Country Status (1)

Country Link
CN (1) CN115000111A (en)

Similar Documents

Publication Publication Date Title
CN107946327B (en) Manufacturing method of back-illuminated CMOS image sensor structure
US11164840B2 (en) Chip interconnection structure, wafer interconnection structure and method for manufacturing the same
CN112185980A (en) Three-dimensional memory and manufacturing method thereof
US9773829B2 (en) Through-semiconductor-via capping layer as etch stop layer
US20200075482A1 (en) Semiconductor device and manufacturing method thereof
US20140357050A1 (en) Method of forming isolating structure and through silicon via
US20200075397A1 (en) Method of forming isolation structure
CN115249719A (en) Image sensor and method of forming image sensor
CN110896046A (en) Shallow trench isolation structure, semiconductor device and preparation method thereof
US10840125B2 (en) Memory structure and method for forming the same
CN107425018B (en) Method for manufacturing semiconductor device
US7067387B2 (en) Method of manufacturing dielectric isolated silicon structure
CN108695239B (en) Semiconductor structure with contact plug and manufacturing method thereof
US6191008B1 (en) Method of forming SOI substrate which includes forming trenches during etching of top semiconductor layer
CN116193858A (en) Three-dimensional memory and preparation method thereof
CN115000111A (en) Backside illuminated image sensor and forming method
WO2006118673A3 (en) Method of forming shallow trench isolation structures in the logic and memory areas
WO2022095799A1 (en) Semiconductor device and method for manufacturing same
US10490441B1 (en) Silicon island structure and method of fabricating same
CN115623790A (en) Semiconductor structure and preparation method thereof
CN115000112A (en) Backside illuminated image sensor and forming method
US6204147B1 (en) Method of manufacturing shallow trench isolation
CN115000110A (en) Backside illuminated image sensor and forming method
US9343477B2 (en) Semiconductor device and method for fabricating the same
US11810786B2 (en) Method for fabricating semiconductor device

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination