CN114995565A

CN114995565A - Short-circuit protection method, circuit and bus driver

Info

Publication number: CN114995565A
Application number: CN202210540904.8A
Authority: CN
Inventors: 不公告发明人
Original assignee: Shenzhen Nanyun Microelectronics Co ltd
Current assignee: Shenzhen Nanyun Microelectronics Co ltd
Priority date: 2022-05-17
Filing date: 2022-05-17
Publication date: 2022-09-02
Anticipated expiration: 2042-05-17
Also published as: CN114995565B

Abstract

The invention discloses a short-circuit protection method, a circuit and a bus driver, wherein the short-circuit protection method comprises the following steps: judging whether the upper branch is conducted or not; when the judgment result is that the upper branch is conducted, the following steps are further executed: comparing the output voltage of the output port of the bus driver with a first short-circuit threshold voltage to obtain a first short-circuit comparison result; comparing the output voltage with a first on-load threshold voltage to obtain a first on-load comparison result; and controlling the current flowing in the upper branch circuit according to the first short circuit comparison result and the first load comparison result, wherein when the upper branch circuit is in a heavy load or a short circuit, the current flowing in the upper branch circuit is determined by different injected currents respectively. The invention can decouple the mutual restriction relationship between the internal resistance of the switching tube and the short-circuit current in the driving circuit and improve the amplitude of the differential driving voltage output by the circuit node on the bus.

Description

Short-circuit protection method, circuit and bus driver

Technical Field

The invention relates to the technical field of bus drivers, in particular to a short-circuit protection method and circuit of a bus driver and the bus driver.

Background

Interface devices for standard data exchange, such as interface chips of RS485, RS232, CAN and the like, are designed to comply with the regulations of the electrical characteristic standard of a corresponding communication protocol, and their bus ports must be able to resist various risks from the bus, especially, their bus drivers must be able to consider not only the situation when the bus drivers are not powered on, but also the situation when the bus drivers are powered on, the output ports of the bus drivers may already be in a conducting or high-resistance state, and whether the bus drivers CAN exit from the current state, and whether signal paths between a power rail, the bus drivers and the bus CAN be opened or closed, so as to ensure that the paths of current flow caused by the risks are controlled, and the bus drivers themselves are not damaged. In addition, the bus driver must also be able to withstand overvoltage events that may occur in certain environments.

Fig. 1 is a schematic diagram of a conventional circuit of a bus driver in the prior art, in which only a driving stage part related to the present invention is shown, including an upper branch circuit, a lower branch circuit, a power supply port VCC, a ground port GND and an output port OUT, one end of the upper branch circuit serving as the power supply port for connecting a power supply rail, the other end of the upper branch circuit and one end of the lower branch circuit being connected together as the output port for outputting an output voltage of the bus driver, and the other end of the lower branch circuit serving as the ground port for grounding; each branch comprises a switch unit and a backflow prevention unit. In fig. 1, the diodes DP and DN are the back-flow prevention units of the upper branch and the lower branch, respectively, and they may be conventional diodes or diodes configured based on a different connection mode from other semiconductor devices for lower voltage drop in the forward conduction condition; the PMOS transistor MP1 and the NMOS transistor N1 are switch units of an upper branch and a lower branch, respectively, and when an actual chip is designed, the switch transistors in each branch may be designed to be connected in parallel by a plurality of switch transistors of the same type, for example, the MOS transistor MP1 is designed to be connected in parallel by two PMOS transistors, and the MOS transistor MN1 is designed to be connected in parallel by two NMOS transistors.

Fig. 2 is a schematic diagram of an application of the bus driver shown in fig. 1 in a bus, where the bus driver includes two buses, and at least one circuit node, where the circuit node is connected to a point a with one of the buses, and connected to a point B with the other bus, and the circuit nodes (a, B) are configured with two bus drivers shown in fig. 1, an output port of a first bus driver is connected to the point a, and an output port of a second bus driver is connected to the point B, and at the same time, only one of the first path and the second path operates, so that the nodes (a, B) will output a differential driving voltage, and thus only one branch will operate when the bus driver in fig. 1 operates.

The protection strategy of a conventional bus driver when the output is overloaded or the output port is short-circuited is generally designed as follows: when the output voltage of the output port is in a high level, namely the P switch tube of the upper branch is conducted, the N switch tube of the lower branch is turned off, and when the output voltage of the output port is too low due to overload or short circuit and is lower than the short-circuit threshold value of the upper branch, the control signal turns off most of the P switch tubes connected with the multiple tubes in parallel, so that the current drawn by the output port from a power supply rail is limited; on the contrary, when the output voltage of the output port is low level, and the output voltage of the output port is too high due to overload or short circuit and is higher than the lower branch short circuit threshold value, the control signal turns off most of the N switch tubes connected in parallel, so that the current flowing into the ground from the output port is limited, and the short circuit protection effect on the bus driver is achieved. However, this method has the following disadvantages:

(1) in order to ensure the amplitude of the differential driving voltage output by the nodes (a, B), the internal resistance of the switch tube is generally designed to be as small as possible during chip design. Before the voltage of the output port reaches the corresponding short-circuit threshold point, the corresponding switch tube enters a saturation region, the lower the internal resistance is, the larger the saturation current is, the saturation current flows to the output port from the power supply rail through an upper branch, or flows to the ground from the output port through a lower branch, so that the temperature rise of the bus driver is obvious, and the reliability is greatly reduced;

(2) when the bus driver is in a short-circuit state, because the conduction number of the driving stage switching tubes is small and the internal resistance is large, the short-circuit recovery point is difficult to reach, for example: the internal resistance of the switching tube in the short-circuit state is designed to be 3 times of the limiting current in the normal state, and the current flowing through the switching tube is required to be reduced to 1/3 in the normal state when the short-circuit state is recovered to the normal state, so that the output voltage of the output port can be recovered to a threshold point, most of the switching tubes are turned on again, and the defect directly results in that the nodes (A and B) cannot provide enough differential driving voltage under the condition that the common mode level output by the bus driver is low and negative.

Applying the schematic diagram with respect to fig. 2, the output voltage at the output port of the bus driver includes: the output voltage VA of the output port of the first bus driver and the output voltage VB of the output port of the second bus driver; the common mode level of the bus driver output refers to: half of the sum of the output voltage of the first bus driver output port and the output voltage of the second bus driver output port, namely (VA + VB)/2; the differential driving voltage output by the nodes (a, B) refers to: the difference between the output voltage of the first bus driver output port and the output voltage of the second bus driver output port, i.e. (VA-VB).

The above-mentioned disadvantage limits the internal resistance of the switching tube to be too small, which in fact limits the load-carrying capacity of the bus driver.

Disclosure of Invention

In view of the above, the technical problem to be solved by the present invention is to provide a driving short-circuit protection method and to solve at least one of the technical problems in the prior art to some extent.

As a first aspect of the present invention, there is provided an embodiment of a short-circuit protection method as follows:

a short-circuit protection method is applied to a bus driver, the bus driver comprises an upper branch circuit and a lower branch circuit, a switch tube in the upper branch circuit is a PMOS tube, a switch tube in the lower branch circuit is an NMOS tube, when the bus driver works normally, only one of the upper branch circuit and the lower branch circuit is conducted, and the short-circuit protection method comprises the following steps:

judging whether the upper branch is conducted or not;

when the judgment result is that the upper branch is conducted, the following steps are further executed:

comparing the output voltage of the output port of the bus driver with a first short-circuit threshold voltage to obtain a first short-circuit comparison result;

comparing the output voltage with a first on-load threshold voltage to obtain a first on-load comparison result;

controlling the current flowing in the upper branch according to the first short circuit comparison result and the first load comparison result, wherein the control logic is as follows:

when the output voltage is less than or equal to the first short-circuit threshold voltage, the current flowing in the upper branch is determined by a first preset current injected into the upper branch;

when the first short-circuit threshold voltage is less than the output voltage and less than or equal to the first loaded threshold voltage, the current flowing in the upper branch is determined by a second preset current injected into the upper branch;

when the first on-load threshold voltage is less than the output voltage and less than or equal to the power supply rail voltage, the current flowing in the upper branch is determined by the driving load of the bus driver;

the first preset current is less than the second preset current.

Further, whether the upper branch is conducted or not is judged according to the high and low of the grid driving signal of the switching tube in the upper branch.

judging whether the lower branch is conducted or not;

when the judgment result is that the lower branch is conducted, the following steps are further executed:

comparing the output voltage of the output port of the bus driver with a second short-circuit threshold voltage to obtain a second short-circuit comparison result;

comparing the output voltage with a second on-load threshold voltage to obtain a second on-load comparison result;

controlling the current flowing in the lower branch according to the second short circuit comparison result and the second on-load comparison result, wherein the control logic is as follows:

when the output voltage is not less than 0 and not more than the second loading threshold voltage, the current flowing in the lower branch is determined by the driving load of the bus driver;

when the second on-load threshold voltage is smaller than the output voltage and smaller than or equal to the second short-circuit threshold voltage, the current flowing in the lower branch is determined by a third preset current injected into the lower branch;

when the second short-circuit threshold voltage is less than the output voltage, the current flowing in the lower branch is determined by a fourth preset current injected into the lower branch;

the third preset current is larger than the fourth preset current.

Further, whether the lower branch is conducted or not is judged according to the high and low of the grid driving signals of the switching tubes in the lower branch.

A short-circuit protection method is applied to a bus driver, the bus driver comprises an upper branch and a lower branch, a switch tube in the upper branch is a PMOS tube, a switch tube in the lower branch is an NMOS tube, when the bus driver works normally, only one of the upper branch and the lower branch is conducted, and the short-circuit protection method comprises the following steps:

judging whether the upper branch is conducted or not;

when the first short-circuit threshold voltage is smaller than the output voltage and smaller than or equal to the first loaded threshold voltage, the current flowing in the upper branch is determined by a second preset current injected into the upper branch;

judging whether the lower branch is conducted or not;

when the second short-circuit threshold voltage is less than the output voltage, the current flowing in the lower branch is determined by a third preset current injected into the lower branch;

the first preset current is less than the second preset current; the third preset current is larger than the fourth preset current.

Further, whether the upper branch is conducted or not is judged according to the high and low of the grid driving signal of the switching tube in the upper branch; and judging whether the lower branch is conducted or not according to the high and low of the grid driving signal of the switching tube in the lower branch.

As a second aspect of the present invention, there is provided an embodiment of a short-circuit protection circuit as follows:

a short-circuit protection circuit is applied to a bus driver, the bus driver comprises an upper branch circuit and a lower branch circuit, a switch tube in the upper branch circuit is a PMOS tube, a switch tube in the lower branch circuit is an NMOS tube, when the bus driver works normally, only one of the upper branch circuit and the lower branch circuit is conducted, and the short-circuit protection circuit comprises a first short-circuit protection unit;

the first short-circuit protection unit includes:

the first judgment unit is used for judging whether the upper branch is conducted or not;

a first executing unit, configured to, when the determination result of the first determining unit is that the upper branch is turned on, further execute the following actions:

the first preset current is less than the second preset current.

Further, the first judging unit judges whether the upper branch is conducted or not according to the high and low of the gate driving signal of the switching tube in the upper branch.

A short-circuit protection circuit is applied to a bus driver, the bus driver comprises an upper branch circuit and a lower branch circuit, a switch tube in the upper branch circuit is a PMOS tube, a switch tube in the lower branch circuit is an NMOS tube, when the bus driver works normally, only one of the upper branch circuit and the lower branch circuit is conducted, and the short-circuit protection circuit comprises:

the positive phase input end of the first comparator is used for inputting the output voltage of the output port of the bus driver, and the negative phase input end of the first comparator is used for inputting the first short-circuit threshold voltage; the setting end of the first comparator is used for inputting a grid driving signal of a switching tube in the upper branch circuit to judge whether the upper branch circuit is conducted; when a grid electrode driving signal of a switching tube in the upper branch circuit is at a high level, the output end of the first comparator is set to be at the high level; when a grid electrode driving signal of a switching tube in the upper branch circuit is in a low level, the output end of the first comparator outputs the first short circuit comparison result;

the input end of the first delay unit is used for receiving the output end level of the first comparator, when the output end level of the first comparator is a high level, the first delay unit is used for shaping and transmitting the high level, and the output end of the first delay unit outputs a corresponding high level; when the output end level of the first comparator is low level, the first delay unit is used for outputting the low level from the output end after first delay time;

the control end of the first voltage control current unit is connected with the output end of the first delay unit, and when the control end of the first voltage control current unit receives a high level, the output end of the first voltage control current unit outputs a first constant current; when the control end of the first voltage control current unit receives a low level, the output end of the first voltage control current unit outputs a second constant current, and the first constant current is larger than the second constant current;

the first current proportion unit comprises a PMOS tube MP2 and a PMS tube MP3, a source electrode of the PMOS tube MP2 and a source electrode of the PMS tube MP3 are connected together and then are used for being connected with a power supply rail, a drain electrode of the PMOS tube MP2, a grid electrode of the PMOS tube MP2 and a grid electrode of the PMS tube MP3 are connected together and then are connected with an output end of the first voltage control current unit, and a drain electrode of the PMOS tube MP3 is used for being connected with an anode of a backflow prevention diode of the upper branch.

As a specific embodiment of the first delay unit, the method includes: a PMOS transistor MP4, an NMOS transistor MN4, a capacitor C1 and a Schmidt inverter SMT 1; the gate of the PMOS transistor MP4 and the gate of the NMOS transistor MN4 are connected together and then serve as the input terminal of the first delay unit, the source of the PMOS transistor MP4 is connected to the power rail, the drain of the PMOS transistor MP4, the drain of the NMOS transistor MN4, one end of the capacitor C1 and the input terminal of the schmitt inverter SMT1 are connected together, the source of the NMOS transistor MN4 and the other end of the capacitor C1 are connected together and then serve as the ground, and the output terminal of the schmitt inverter SMT1 serves as the output terminal of the first delay unit.

As a specific embodiment of the first voltage-controlled current unit, the method includes: a switch tube S1, a first reference current IP1 and a second reference current IP 2; the control end of the switch tube S1 is used as the control end of the first voltage control current unit, one end of the switch tube S1 and one end of the second reference current IP2 are connected together and then used as the output end of the first voltage control current unit, the other end of the switch tube S1 is connected with one end of the first reference current IP1, the other end of the first reference current IP1 is used for inputting a first reference current signal, and the other end of the second reference current IP2 is used for inputting a second reference current signal.

A short-circuit protection circuit is applied to a bus driver, the bus driver comprises an upper branch circuit and a lower branch circuit, a switch tube in the upper branch circuit is a PMOS tube, a switch tube in the lower branch circuit is an NMOS tube, when the bus driver works normally, only one of the upper branch circuit and the lower branch circuit is conducted, and the short-circuit protection circuit comprises a second short-circuit protection unit;

the second short-circuit protection unit includes:

the second judging unit is used for judging whether the lower branch is conducted or not;

a second executing unit, configured to, when the determination result of the second determining unit is that the lower branch is connected, further execute the following actions:

when the second on-load threshold voltage is less than the output voltage and less than or equal to the second short-circuit threshold voltage, the current flowing in the lower branch is determined by a third preset current injected into the lower branch;

the third preset current is larger than the fourth preset current.

Further, the second determining unit determines whether the lower branch is turned on according to the level of the gate driving signal of the switching tube in the lower branch.

a positive phase input end of the second comparator is used for inputting the second short-circuit threshold voltage, and a negative phase input end of the second comparator is used for inputting the output voltage of the output port of the bus driver; the setting end of the second comparator is used for inputting a gate drive signal of a switching tube in the lower branch circuit to judge whether the lower branch circuit is conducted; when the grid driving signal of the switching tube in the lower branch circuit is at a low level, the output end of the second comparator is set to be at a high level; when the grid electrode driving signal of the switching tube in the upper branch circuit is in a high level, the output end of the second comparator outputs the second short circuit comparison result;

the input end of the second delay unit is used for receiving the output end level of the second comparator, when the output end level of the second comparator is high level, the second delay unit is used for shaping and transmitting the high level, and the output end of the second delay unit outputs the corresponding high level; when the level of the output end of the second comparator is low level, the second delay unit is used for outputting the low level from the output end of the second delay unit after the second delay time;

a control end of the second voltage control current unit is connected with an output end of the second delay unit, and when the control end of the second voltage control current unit receives a high level, the output end of the second voltage control current unit outputs a third constant current; when the control end of the second voltage control current unit receives a low level, the output end of the second voltage control current unit outputs a fourth constant current, and the third constant current is larger than the fourth constant current;

the second current proportion unit comprises an NMOS tube MN2 and an NMOS tube MN3, the source electrode of the NMOS tube MN2 and the source electrode of the NMS tube MN3 are connected together and then are grounded, the drain electrode of the NMOS tube MN2, the grid electrode of the NMOS tube MN2 and the grid electrode of the NMS tube MN3 are connected together and then are connected with the output end of the second voltage control current unit, and the drain electrode of the NMOS tube MN3 is connected with the source electrode of the NMOS tube of the lower branch.

As a specific embodiment of the second delay unit, the method includes: a PMOS transistor MP5, an NMOS transistor MN5, a capacitor C2 and a Schmidt inverter SMT 2; the gate of the PMOS transistor MP5 and the gate of the NMOS transistor MN5 are connected together and then serve as the input terminal of the second delay unit, the source of the PMOS transistor MP5 is connected to the power rail, the drain of the PMOS transistor MP5, the drain of the NMOS transistor MN5, one end of the capacitor C2 and the input terminal of the schmitt inverter SMT2 are connected together, the source of the NMOS transistor MN5 and the other end of the capacitor C2 are connected together and then serve as the ground, and the output terminal of the schmitt inverter SMT2 serves as the output terminal of the second delay unit.

As a specific embodiment of the second voltage-controlled current unit, the method includes: a switch tube S2, a third reference current IN1 and a fourth reference current IN 2; the control end of the switch tube S2 is used as the control end of the second voltage-controlled current unit, one end of the switch tube S2 and one end of the fourth reference current IN2 are connected together and then used as the output end of the second voltage-controlled current unit, the other end of the switch tube S2 is connected with one end of the third reference current IN1, the other end of the third reference current IN1 is used for inputting a third reference current signal, and the other end of the fourth reference current IN2 is used for inputting a fourth reference current signal.

A short-circuit protection circuit is applied to a bus driver, the bus driver comprises an upper branch and a lower branch, a switch tube in the upper branch is a PMOS tube, a switch tube in the lower branch is an NMOS tube, when the bus driver works normally, only one of the upper branch and the lower branch is conducted, and the short-circuit protection circuit comprises a first short-circuit protection unit and a second short-circuit protection unit;

the first short-circuit protection unit includes:

the first preset current is less than the second preset current;

the second short-circuit protection unit includes:

the third preset current is larger than the fourth preset current.

Further, the first judging unit judges whether the upper branch circuit is conducted or not according to the high and low of the grid driving signal of the switching tube in the upper branch circuit; the second judging unit judges whether the lower branch is conducted or not according to the height of a grid driving signal of a switching tube in the lower branch.

the positive phase input end of the first comparator is used for inputting the output voltage of the output port of the bus driver, and the negative phase input end of the first comparator is used for inputting the first short-circuit threshold voltage; the setting end of the first comparator is used for inputting a grid driving signal of a switching tube in the upper branch circuit to judge whether the upper branch circuit is conducted; when a grid electrode driving signal of a switching tube in the upper branch circuit is in a high level, the output end of the first comparator is set to be in a high level; when a grid electrode driving signal of a switching tube in the upper branch circuit is in a low level, the output end of the first comparator outputs the first short circuit comparison result;

the first current proportion unit comprises a PMOS (P-channel metal oxide semiconductor) tube MP2 and a PMS tube MP3, a source electrode of the PMOS tube MP2 and a source electrode of the PMS tube MP3 are connected together and then are connected with a power supply rail, a drain electrode of the PMOS tube MP2, a grid electrode of the PMOS tube MP2 and a grid electrode of the PMS tube MP3 are connected together and then are connected with an output end of the first voltage control current unit, and a drain electrode of the PMOS tube MP3 is connected with an anode of a backflow prevention diode of the upper branch;

a positive phase input end of the second comparator is used for inputting the second short-circuit threshold voltage, and a negative phase input end of the second comparator is used for inputting the output voltage; the setting end of the second comparator is used for inputting a gate drive signal of a switching tube in the lower branch circuit to judge whether the lower branch circuit is conducted; when the grid driving signal of the switching tube in the lower branch circuit is at a low level, the output end of the second comparator is set to be at a high level; when the grid electrode driving signal of the switching tube in the upper branch circuit is in a high level, the output end of the second comparator outputs the second short circuit comparison result;

a second voltage control current unit, a control end of the second voltage control current unit being connected to an output end of the second delay unit, and when the control end of the second voltage control current unit receives a high level, the output end of the second voltage control current unit outputs a third constant current; when the control end of the second voltage control current unit receives a low level, the output end of the second voltage control current unit outputs a fourth constant current, and the third constant current is larger than the fourth constant current;

As a specific embodiment of the second delay unit, the method includes: a PMOS tube MP5, an NMOS tube MN5, a capacitor C2 and a Schmidt inverter SMT 2; the gate of the PMOS transistor MP5 and the gate of the NMOS transistor MN5 are connected together and then serve as the input terminal of the second delay unit, the source of the PMOS transistor MP5 is connected to the power rail, the drain of the PMOS transistor MP5, the drain of the NMOS transistor MN5, one end of the capacitor C2 and the input terminal of the schmitt inverter SMT2 are connected together, the source of the NMOS transistor MN5 and the other end of the capacitor C2 are connected together and then serve as the ground, and the output terminal of the schmitt inverter SMT2 serves as the output terminal of the second delay unit.

As a specific embodiment of the second voltage-controlled current unit, the method includes: a switch tube S2, a third reference current IN1 and a fourth reference current IN 2; the control end of the switch tube S2 is used as the control end of the second voltage-controlled current unit, one end of the switch tube S2 and one end of the fourth reference current IN2 are connected together and then used as the output end of the second voltage-controlled current unit, the other end of the switch tube S2 is connected with one end of the third reference current IN1, the other end of the first reference current IP1 is used for inputting a first reference current signal, and the other end of the second reference current IP2 is used for inputting a second reference current signal.

As a third aspect of the present invention, a bus driver embodiment is provided as follows:

a bus driver comprising a short-circuit protection circuit as in any preceding embodiment.

The meaning of the terms:

current sinking: current is input from one end of the device, flows out from the other end of the device and flows to a power supply, and the current is similar to absorbed current and is often called a current sink;

current source: current is input into one end of the device from the power supply rail and flows out from the other end of the device, and the current can be used as an input source signal of other circuits, so the current source is often called as a current source;

the embodiment of the invention at least comprises the following beneficial effects: when the bus driver is overloaded or short-circuited, the current flowing through the upper branch or the lower branch of the bus driver can be reasonably limited by the reference currents with different sizes generated inside, so that the temperature rise of the bus driver can be controlled, the reliability of the bus driver is improved, compared with a control strategy in the prior art that the conduction number of the upper switch tube or the lower switch tube is reduced in parallel, the decoupling between the differential output voltage and the short-circuit current of the bus driver is realized, the two are not restricted with each other, the defect that the current value of the corresponding branch is required to be very low for short-circuit recovery in electrification is avoided, and the load carrying capacity of the bus driver is improved in a wide range of positive and negative common mode output voltages.

Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by the practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.

Drawings

FIG. 1 is a conventional circuit schematic of a prior art bus driver;

FIG. 2 is a schematic diagram of the bus driver of FIG. 1 applied to a bus;

FIG. 3 is a flowchart of a short-circuit protection method according to a first embodiment of the present invention;

fig. 4 is a flowchart of a short-circuit protection method according to a second embodiment of the present invention;

fig. 5 is a flowchart of a short-circuit protection method according to a third embodiment of the present invention;

fig. 6 is a schematic block diagram of a short-circuit protection circuit according to a fourth embodiment of the present invention;

fig. 7 is a schematic diagram of an application of a short-circuit protection circuit in a bus driver according to a fifth embodiment of the present invention;

fig. 8 is a schematic diagram of an application of a short-circuit protection circuit in a bus driver according to a fifth embodiment of the present invention, which provides a specific circuit for all units in fig. 7;

fig. 9 is a schematic block diagram of a short-circuit protection circuit according to a sixth embodiment of the present invention;

fig. 10 is a schematic diagram of an application of a short-circuit protection circuit in a bus driver according to a seventh embodiment of the present invention;

fig. 11 is a schematic diagram of an application of the short-circuit protection circuit in a bus driver according to a seventh embodiment of the present invention, which provides a specific circuit for all units in fig. 10;

fig. 12 is a schematic block diagram of a short-circuit protection circuit according to an eighth embodiment of the present invention;

fig. 13 is a schematic diagram of an application of a short-circuit protection circuit in a bus driver according to a ninth embodiment of the present invention;

fig. 14 is a schematic diagram of an application of the short-circuit protection circuit provided in the ninth embodiment of the present invention in a bus driver, and the diagram provides a specific circuit for all units in fig. 10;

fig. 15 is a waveform diagram illustrating the design of the short-circuit protection delay time according to the present invention.

Detailed Description

It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict. The present application will be described in detail below with reference to the embodiments with reference to the attached drawings.

In order to make the technical solutions better understood by those skilled in the art, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only partial embodiments of the present application, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

It should be noted that the terms "first," "second," and the like in the description and claims of this application and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It should be understood that the data so used may be interchanged under appropriate circumstances such that embodiments of the application described herein may be used. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

It should be understood that in the specification, claims and drawings hereof, when a step is described as continuing to another step, that step may continue directly to that other step, or through a third step to that other step; when an element/unit is described as being "connected" to another element/unit, that element/unit may be "directly connected" to that other element/unit, or "connected" to that other element/unit through a third element/unit.

Furthermore, the drawings of the present disclosure are merely schematic representations, not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and thus, a repetitive description thereof will be omitted. Some of the block diagrams shown in the figures are functional entities and do not necessarily correspond to physically or logically separate entities. These functional entities may be implemented in software, or in one or more hardware modules or integrated circuits, or in different networks and/or processor devices and/or micro-control devices.

First embodiment

Fig. 3 is a flowchart of a short-circuit protection method according to a first embodiment of the present invention, please refer to fig. 3, where the short-circuit protection method according to this embodiment is applied to the bus driver in fig. 1 and fig. 2, the bus driver includes an upper branch and a lower branch, a switching transistor in the upper branch is a PMOS transistor, a switching transistor in the lower branch is an NMOS transistor, and when the bus driver normally operates, only one of the upper branch and the lower branch is connected, and the short-circuit protection method includes the following steps:

s101: judging whether the upper branch is conducted or not;

s1021: comparing the output voltage of the output port of the bus driver with a first short-circuit threshold voltage to obtain a first short-circuit comparison result;

s1022: comparing the output voltage with a first on-load threshold voltage to obtain a first on-load comparison result;

s103: controlling the current flowing in the upper branch according to the first short circuit comparison result and the first load comparison result, wherein the control logic is as follows:

s1041: when the output voltage is less than or equal to a first short-circuit threshold voltage, the current flowing in the upper branch is determined by a first preset current injected into the upper branch;

s1042: when the first short-circuit threshold voltage is less than the output voltage and less than or equal to the first loaded threshold voltage, the current flowing in the upper branch is determined by a second preset current injected into the upper branch;

s1043: when the first load threshold voltage is less than the output voltage and less than or equal to the power supply rail voltage, the current flowing in the upper branch is determined by the driving load of the bus driver;

the first preset current is less than the second preset current.

Steps S1021 and S1022 are performed synchronously, and steps S1041, S1042, and S1043 are one of the specific cases of step S103, that is, when step S103 is performed specifically, only one of steps S1041, S1042, and S1043 is performed.

The short-circuit protection method of the embodiment aims to improve the temperature rise problem and the load carrying capacity problem of the upper branch, and comprises the following three modes:

(1) and (3) a light load mode: at this time, corresponding to step S1043, that is, when the first on-load threshold voltage is less than the output voltage and less than or equal to the power rail voltage, the current flowing through the upper branch is determined by the driving load of the bus driver, in this mode, the load is smaller, the output voltage at the output port of the bus driver is larger, and the nodes a and B can provide sufficient differential driving voltage, so that the current flowing through the upper branch is determined by the driving load of the bus driver;

(2) the heavy load mode: at this time, corresponding to step S1042, that is, the first short-circuit threshold voltage is less than the output voltage and less than or equal to the first on-load threshold voltage, and at this time, the current flowing through the upper branch is determined by the second preset current injected into the upper branch, in this mode, the load is large, the output voltage at the output port of the bus driver is reduced, and the nodes a and B cannot provide sufficient differential driving voltage, in this embodiment, the second preset current is injected into the upper branch, so that the current flowing through the upper branch is determined by the injected second preset current, which not only ensures that the bus driver stage has sufficient capability of driving resistive and capacitive loads, but also limits the current of the upper branch of the driver stage within a controllable range;

(3) short-circuit mode: at this time, corresponding to step S1041, that is, the output voltage is less than or equal to the first short-circuit threshold voltage, and the current flowing through the upper branch is determined by the first preset current injected into the upper branch, in this mode, the load is further increased, or the output port of the bus driver is abnormally short-circuited, so that the output voltage at the output port of the bus driver is lower.

From the above analysis, in this embodiment, when the upper branch has a heavy load or a short circuit, the current flowing through the upper branch is reasonably limited by the reference currents with different magnitudes generated inside, which not only can control the temperature rise of the bus driver and improve the reliability of the bus driver, but also realizes the decoupling between the differential output voltage and the short-circuit current of the bus driver compared with the prior art by reducing the conducting number of the parallel upper switch tubes, so that the two are not restricted with each other, thereby the defect that the current value of the upper branch is required to be very low for the short circuit recovery in the live state does not exist, and the load carrying capacity of the bus driver is improved in the wide range of the positive and negative common mode output voltages.

Further, when step S101 is executed, whether the upper branch is conducted is determined by the high/low of the gate driving signal of the switching tube in the upper branch.

Because the switching tube of the upper branch needs to drive a signal to control the switching on and off of the switching tube, when the upper branch is judged to be switched on, whether the upper branch is switched on is judged according to the level of the gate drive signal of the switching tube in the upper branch, so that the need of adding an additional detection step is avoided.

Second embodiment

Fig. 4 is a flowchart of a short-circuit protection method according to a second embodiment of the present invention, please refer to fig. 4, where the short-circuit protection method according to this embodiment is applied to the bus driver in fig. 1 and fig. 2, the bus driver includes an upper branch and a lower branch, a switching transistor in the upper branch is a PMOS transistor, a switching transistor in the lower branch is an NMOS transistor, and when the bus driver normally operates, only one of the upper branch and the lower branch is connected, and the short-circuit protection method includes the following steps:

s201: judging whether the lower branch is conducted or not;

s2021: comparing the output voltage of the output port of the bus driver with a second short-circuit threshold voltage to obtain a second short-circuit comparison result;

s2022: comparing the output voltage with a second on-load threshold voltage to obtain a second on-load comparison result;

s203: controlling the current flowing in the lower branch according to the second short circuit comparison result and the second on-load comparison result, wherein the control logic is as follows:

s2041: when the output voltage is more than or equal to 0 and less than or equal to a second loaded threshold voltage, the current flowing in the lower branch is determined by the driving load of the bus driver;

s2042: when the second loading threshold voltage is less than the output voltage and less than or equal to the second short-circuit threshold voltage, the current flowing in the lower branch is determined by a third preset current injected into the lower branch;

s2043: when the second short-circuit threshold voltage is smaller than the output voltage, the current flowing in the lower branch is determined by a fourth preset current injected into the lower branch;

the third preset current is larger than the fourth preset current.

Steps S2021 and S2022 are performed synchronously, and steps S2041, S2042 and S2043 are one of specific cases of step S203, that is, only one of steps S2041, S2042 and S2043 is performed when step 203 is performed specifically.

The short-circuit protection method of the embodiment aims to improve the temperature rise problem and the load carrying capacity problem of the lower branch, and is divided into three modes:

(1) and (3) a light load mode: at this time, corresponding to step S2041, that is, when the output voltage is not less than 0 and not more than the second on-load threshold voltage, the current flowing through the lower branch is determined by the driving load of the bus driver, in this mode, the load is small, the output voltage at the output port of the bus driver is small, and the nodes CAN-H and CAN-L CAN provide sufficient differential driving voltage, so that the current flowing through the lower branch is determined by the driving load of the bus driver;

(2) the heavy load mode: corresponding to step S2042, that is, when the second on-load threshold voltage is less than the output voltage and less than or equal to the second short-circuit threshold voltage, the current flowing through the lower branch is determined by the third preset current injected into the lower branch, in this mode, the load is large, the output voltage at the output port of the bus driver is increased, and the nodes CAN-H and CAN-L cannot provide sufficient differential driving voltage, in this embodiment, the third preset current is injected into the lower branch, so that the current flowing through the lower branch is determined by the injected third preset current, which not only ensures that the driving stage of the bus driver has sufficient capacity of driving resistive and capacitive loads, but also limits the current of the lower branch of the driving stage within a controllable range;

(3) short circuit mode: at this time, corresponding to step S2043, that is, when the second short-circuit threshold voltage is less than the output voltage, the current flowing through the lower branch is determined by the fourth preset current injected into the lower branch, in this mode, the load is further increased, or the output port of the bus driver is abnormally shorted, so that the output voltage at the output port of the bus driver is higher.

From the above analysis, in this embodiment, when the lower branch circuit is overloaded or short-circuited, the current flowing through the lower branch circuit is reasonably limited by the reference currents with different magnitudes generated inside, which not only can control the temperature rise of the bus driver and improve the reliability of the bus driver, but also can realize the decoupling between the differential output voltage and the short-circuit current of the bus driver and make the two not mutually restricted by the control strategy of reducing the conduction number of the switch tubes under parallel connection in comparison with the prior art, so that the defect that the current value of the lower branch circuit is very low when the short-circuit recovery is in an electrified state does not exist, and the load carrying capacity of the bus driver is improved in a wide range of the positive and negative common mode output voltages.

Further, when step S201 is executed, whether the lower branch is conducted is determined by the level of the gate driving signal of the switching tube in the lower branch.

Because the switching tube of the lower branch needs to drive a signal to control the switching on and off of the switching tube, when the lower branch is judged to be conducted, the lower branch is judged to be conducted according to the level of the gate drive signal of the switching tube in the lower branch, so that the need of adding an additional detection step is avoided.

Third embodiment

Fig. 5 is a flowchart of a short-circuit protection method according to a third embodiment of the present invention, and referring to fig. 5, the short-circuit protection method of the present embodiment combines the method of the first embodiment and the method of the second embodiment.

It is easy to understand that the short-circuit protection method of this embodiment aims to improve the temperature rise problem and the load carrying capability problem of the upper branch and the lower branch at the same time, in this embodiment, step S101 and step S201 are performed synchronously, and since only one of the upper branch and the lower branch is conducted when the bus driver works normally, at the same time, the judgment result of only one of step S101 and step S201 is yes, and the step of judging yes will continue to execute other steps after the step. When the determination result in step S101 is "yes", three operation modes are included, which are the same as those in the first embodiment and thus are not described again; when the determination result in step S201 is "yes", three operation modes are included, which are the same as those in the second embodiment and are not described again.

In the embodiment, no matter the upper branch circuit has a heavy load or a short circuit, or the lower branch circuit has a heavy load or a short circuit, the current flowing in the corresponding branch circuit can be reasonably limited by the reference currents generated in the corresponding branch circuit, thereby not only controlling the temperature rise of the bus driver and improving the reliability of the bus driver, but also realizing the decoupling between the differential output voltage and the short-circuit current of the bus driver by reducing the conducting number of the upper switch tube or the lower switch tube in parallel compared with the control strategy in the prior art, so that the two are not restricted with each other, thereby avoiding the defect that the short circuit recovery requires the current value of the corresponding branch circuit to be very low in the live state, and improving the load carrying capacity of the bus driver in the wide range of the positive and negative common mode output voltages.

Fourth embodiment

Fig. 6 is a schematic block diagram of a short-circuit protection circuit according to a fourth embodiment of the present invention, please refer to fig. 6, where the short-circuit protection circuit of the present embodiment is applied to the bus driver in fig. 1 and fig. 2, and the bus driver includes an upper branch and a lower branch; the switch tube 106 in the upper branch is a PMOS tube MP1, and the first anti-backflow unit 105 is a diode DP; the gate driving signal of the PMOS tube MP1 is GateP; the switch tube 206 in the lower branch is an NMOS tube MN1, the second backflow prevention unit 206 is a diode DN, and a gate driving signal of the NMOS tube MN1 is GateN; when the bus driver works normally, only one of the upper branch circuit and the lower branch circuit is conducted, and the short-circuit protection circuit comprises a first short-circuit protection unit;

the first short-circuit protection unit includes:

when the output voltage is less than or equal to a first short-circuit threshold voltage, the current flowing in the upper branch is determined by a first preset current injected into the upper branch;

when the first load threshold voltage is less than the output voltage and less than or equal to the power supply rail voltage, the current flowing in the upper branch is determined by the driving load of the bus driver;

the first preset current is less than the second preset current.

It is easy to understand that the short-circuit protection circuit of this embodiment aims to improve the temperature rise problem and the load carrying capability problem of the upper branch, and when the determination result of the first determining unit is "yes", the first executing unit includes three operating modes, which are the same as those of the first embodiment, and the beneficial effects are also the same, so that details are not described.

Further, the first judging unit judges whether the upper branch is conducted or not according to the high and low of the gate driving signal of the switching tube in the upper branch, so that the need of adding an additional detecting unit is avoided.

Fifth embodiment

Fig. 7 is a schematic diagram of an application of a short-circuit protection circuit in a bus driver according to a fifth embodiment of the present invention, referring to fig. 7, the short-circuit protection circuit of the present embodiment is applied to the bus driver in fig. 1 and fig. 2, and the bus driver includes an upper branch and a lower branch; the switch tube 106 in the upper branch is a PMOS tube MP1, and the first anti-backflow unit 105 is a diode DP; the gate driving signal of the PMOS tube MP1 is GateP; the switch tube 206 in the lower branch is an NMOS tube MN1, the second backflow prevention unit 206 is a diode DN, and a gate driving signal of the NMOS tube MN1 is GateN; when the bus driver works normally, only one of the upper branch circuit and the lower branch circuit is conducted, and the short-circuit protection circuit comprises:

a positive phase input end of the first comparator 101 is used for connecting an output port OUT of the bus driver, and a negative phase input end of the first comparator 101 is used for inputting a first short-circuit threshold voltage Vthp; the setting end of the first comparator 101 is used for inputting a gate driving signal GateP of a switching tube in the upper branch circuit to judge whether the upper branch circuit is conducted; when the gate driving signal GateP of the switching tube in the upper branch is at a high level, the output terminal of the first comparator 101 is set to a high level; when the gate driving signal GateP of the switching tube in the upper branch is at a low level, the output end of the first comparator 101 outputs a first short-circuit comparison result;

a first delay unit 102, an input end of the first delay unit 102 is configured to receive an output end level of the first comparator 101, when the output end level of the first comparator 101 is a high level, the first delay unit 102 is configured to shape and transmit the high level, and an output end thereof outputs a corresponding high level; when the output terminal level of the first comparator 101 is a low level, the first delay unit 102 is configured to output the low level from the output terminal thereof after a first delay time;

a first voltage control current unit 103, a control end of the first voltage control current unit being connected to the output end of the first delay unit 102, when the control end of the first voltage control current unit 103 receives a high level, the output end of the first voltage control current unit 103 outputs a first constant current; when the control terminal of the first voltage-controlled current unit 103 receives a low level, the output terminal of the first voltage-controlled current unit 103 outputs a second constant current, and the first constant current is greater than the second constant current;

the first current proportion unit 104 comprises a PMOS tube MP2 and a PMS tube MP3, a source electrode of the PMOS tube MP2 and a source electrode of the PMS tube MP3 are connected together and then are connected with a power supply rail, a drain electrode of the PMOS tube MP2, a grid electrode of the PMOS tube MP2 and a grid electrode of the PMS tube MP3 are connected together and then are connected with an output end of the first voltage control current unit 103, and a drain electrode of the PMOS tube MP3 is connected with an anode of a back-flow prevention diode DP of an upper branch.

It should be noted that the PMOS transistor MP2 and the PMS transistor MP3 are low-voltage PMOS transistors, and the PMOS transistor MP2 and the PMS transistor MP3 are controlled in a ratio of 1: the width-to-length ratio of m (m is an appropriate natural number) constitutes a connection mode of the current mirror. Under the condition that the upper branch is conducted: when the PMOS transistor MP3 works in a linear region, the current flowing through the PMOS transistor MP3 is determined by the driving load; when the PMOS transistor MP3 operates in saturation, the current flowing through the PMOS transistor MP3 is determined by the current mirrored from the PMOS transistor MP2 by the PMOS transistor MP 3.

Fig. 8 is a schematic diagram of an application of the short-circuit protection circuit in a bus driver according to a fifth embodiment of the present invention, which provides specific circuits for all units in fig. 7, please refer to fig. 8:

the first delay unit 102 includes: a PMOS transistor MP4, an NMOS transistor MN4, a capacitor C1 and a Schmidt inverter SMT 1; the gate of the PMOS transistor MP4 and the gate of the NMOS transistor MN4 are connected together and then serve as the input terminal of the first delay unit 102, the source of the PMOS transistor MP4 is used for connecting a power rail, the drain of the PMOS transistor MP4, the drain of the NMOS transistor MN4, one end of the capacitor C1 and the input terminal of the schmidt inverter SMT1 are connected together, the source of the NMOS transistor MN4 and the other end of the capacitor C1 are connected together and then used for grounding, and the output terminal of the schmidt inverter SMT1 serves as the output terminal of the first delay unit 102.

Wherein, the first voltage-controlled current unit 103 includes: a switch tube S1, a first reference current IP1 and a second reference current IP 2; the control end of the switch tube S1 is used as the control end of the first voltage-controlled current unit 103, one end of the switch tube S1 and one end of the second reference current IP2 are connected together and then used as the output end of the first voltage-controlled current unit 103, the other end of the switch tube S1 is connected with one end of the first reference current IP1, the other end of the first reference current IP1 is used for inputting a first reference current signal, and the other end of the second reference current IP2 is used for inputting a second reference current signal.

It should be noted that the current magnitudes of the first reference current IP1 and the second reference current IP2 can be selected according to the requirement of the driving capability of the bus driver during normal operation and the magnitude of the current limiting value set in the short-circuit state, and the currents of the first reference current IP1 and the second reference current IP2 are both provided by the reference current sink.

In this embodiment, the gate voltage of the PMOS transistor MP2 and the gate voltage VGP of the PMOS transistor MP3 are determined by the output current of the first voltage-controlled current unit 103, the power rail voltage VCC is a fixed value, and the output voltage VOUT at the output port of the bus driver is a variable value.

The condition that the PMOS transistor MP2 and the PMOS transistor MP3 work in the saturation region is | Vds | > | Vgs | - | Vth |, where Vgs is the gate-source voltage of the MOS transistor, Vds is the drain-source voltage of the MOS transistor, Vth is the threshold voltage of the MOS transistor, and the three are negative values.

The PMOS transistor MP2 is used as an input transistor of the current mirror, and the gate and drain thereof are short-circuited, and at this time, | Vds | > | Vgs | - | Vth | is always satisfied, and the PMOS transistor MP2 always operates in a saturation region.

From the above analysis, the inventive concept of the present embodiment is the same as that of the first and fourth embodiments, since the operating state of the PMOS transistor MP3 in the present embodiment enters saturation from the linear region and needs to satisfy the condition that VOUT is smaller than the above threshold VGP-VDP- | VDSMP1+ | VthMP3|, which can be regarded as the first on-load threshold voltage in the first and fourth embodiments, the present embodiment utilizes the natural operating characteristics of the PMOS transistor MP3 to implement the function of comparing VOUT with the first on-load threshold voltage, obtain the first on-load comparison result, and execute the related action according to the first on-load comparison result.

The short-circuit protection circuit of this embodiment aims to improve the temperature rise problem and the load capacity problem of the upper branch, and the working principle of this embodiment will be analyzed with reference to the circuit of fig. 8. For convenience of explanation, the following analysis directly considers the threshold VGP-VDP- | VDSMP1| + | VthMP3| as VGP, and in practical circuit design, designing | VthMP3| -VDP- | VDSMP1| to be zero can also achieve the effect of VGP-VDP- | VDSMP1| + | VthMP3| -VGP. It is easy to understand that, when no short-circuit protection measure is taken, as the load gradually increases, that is, the current flowing through the upper branch gradually increases, the bus driver in this embodiment will sequentially operate in the light load mode, the heavy load mode, and the short-circuit mode, and the output voltage VOUT at the output port of the bus driver will gradually decrease.

Based on the design conditions of the threshold, the present embodiment includes the following three modes:

(1) and (3) a light load mode: the load is small, the output voltage VOUT of the output port of the bus driver is large, when VGP is greater than VOUT and less than VCC, the positive phase input end of the first comparator 101 is greater than the negative phase input end, the high level output by the first comparator 101 controls the switching tube S1 of the first voltage control current unit 103 to be closed through the first delay unit 102, so that the sum of the first reference current IP1 and the second reference current IP2 is selected to be provided to the input end of the first current proportion unit 104, but at this time, because VOUT is greater than VGP, the low-voltage PMOS transistor MP3 in the first current proportion unit 103 is in a linear region and does not have the function of mirroring current from the PMOS transistor MP2, at this time, the internal resistance of the PMOS transistor MP3 is low, the voltage drop of loss between the source and the drain is small, and the current flowing through the driving upper branch is completely determined by the load of the driving output;

(2) a heavy-load mode: as the driving output load increases, the output voltage at the output port of the bus driver decreases, when Vthp < VOUT ≦ VGP, the positive phase input terminal of the first comparator 101 is still larger than the negative phase input terminal, the first comparator 101 still outputs a high level, which controls the switching tube S1 of the first voltage control current unit 103 to close via the first delay unit 102, so that the sum of the first reference current IP1 and the second reference current IP2 is still selected to be provided to the input terminal of the first current proportional unit 104, but at this time, since VOUT ≦ VGP, the low voltage PMOS transistor MP3 in the first current proportional unit 103 starts to enter the saturation region, which can mirror the reference current on the PMOS transistor MP2, so that the first current proportional unit 103 can define the value of the current flowing through the driving upper leg as (IP1+ IP2) multiplied by the proportional value m between the low voltage PMOS transistors designed by the first current proportional unit 103, that is (IP1+ IP2) m, the bus driver has the advantages that the driving stage in the bus driver is ensured to have the capacity of driving resistive loads and capacitive loads, and the current of an upper branch circuit is limited within a controllable range;

(3) short circuit mode: with the further increase of the driving output load or the abnormal short of the port, which results in lower VOUT, when VOUT is smaller than or equal to Vthp, the first comparator 101 outputs a low level to the first delay unit 102, the PMOS transistor MP4 in the first delay unit 102 is turned on, the power rail charges the capacitor C1 through the PMOS transistor MP4 until the voltage drop across the capacitor C1 reaches the turning point of the schmitt inverter SMT1, that is, after a set delay time, the low level is output to control the switching transistor S1 in the first voltage-controlled current unit 103 to be turned off, only the second reference current IP2 is selected to be provided to the first current proportioning unit 104, at this time, VOUT is low, the low-voltage PMOS transistor MP3 in the first current proportioning unit 104 is in the saturation region, and the current mirror formed by the PMOS transistor MP2 keeps mirroring action, at this time, the first current proportioning unit 104 limits the current value flowing through the upper branch to be the second reference current IP2 multiplied by the proportional value m between the low-voltage PMOS transistors designed by the first current proportioning unit 104, i.e., IP2 m, causes the upper branch current of the bus driver to be limited to a lower level in a short circuit state, improving the reliability of the bus driver.

The inventive concept of this embodiment is the same as that of the first and fourth embodiments, and when the upper branch has a heavy load or a short circuit, the current flowing through the upper branch is reasonably limited by the reference currents (equivalent to the externally injected currents in the first and fourth embodiments) with different magnitudes generated by the first voltage control current unit 103, so that not only can the temperature rise of the bus driver be controlled and the reliability of the bus driver be improved, but also compared with the control strategy of reducing the conduction number of the parallel upper switch tubes in the prior art, the decoupling between the differential output voltage and the short-circuit current of the bus driver is realized, and the two are not restricted with each other, so that the defect that the current value of the upper branch is very low when the short circuit is recovered during charging does not exist, and the load capacity of the bus driver is improved in a wide range of the positive and negative common mode output voltages.

Sixth embodiment

Fig. 9 is a schematic diagram of an application of a short-circuit protection circuit in a bus driver according to a sixth embodiment of the present invention, please refer to fig. 9, in which the short-circuit protection circuit of the present embodiment is applied to the bus driver in fig. 1 and fig. 2, and the bus driver includes an upper branch and a lower branch; the switch tube 106 in the upper branch is a PMOS tube MP1, and the first anti-backflow unit 105 is a diode DP; the gate driving signal of the PMOS tube MP1 is GateP; the switch tube 206 in the lower branch is an NMOS tube MN1, the second backflow prevention unit 206 is a diode DN, and a gate driving signal of the NMOS tube MN1 is GateN; when the bus driver works normally, only one of the upper branch circuit and the lower branch circuit is conducted, and the short-circuit protection circuit is a second short-circuit protection unit;

the second short-circuit protection unit includes:

a second executing unit, configured to, when the determination result of the second determining unit is that the lower link is connected, further execute the following actions:

when the output voltage is more than or equal to 0 and less than or equal to a second loaded threshold voltage, the current flowing in the lower branch is determined by the driving load of the bus driver;

when the second short-circuit threshold voltage is smaller than the output voltage, the current flowing in the lower branch is determined by a fourth preset current injected into the lower branch;

the third preset current is larger than the fourth preset current.

It is easy to understand that the short-circuit protection circuit of this embodiment aims to improve the temperature rise problem and the load carrying capability problem of the lower branch, and when the determination result of the second determining unit is "yes", the second performing unit includes three operating modes, which are the same as the second embodiment, and the beneficial effects thereof are also the same, so that details are not described.

Furthermore, the second judging unit judges whether the lower branch is conducted according to the level of the gate driving signal of the switching tube in the lower branch, so that the need of adding an additional detecting unit is avoided.

Seventh embodiment

Fig. 10 is a schematic diagram of an application of a short-circuit protection circuit in a bus driver according to a seventh embodiment of the present invention, referring to fig. 7, the short-circuit protection circuit of the present embodiment is applied in the bus driver in fig. 1 and fig. 2, and the bus driver includes an upper branch and a lower branch; the switch tube 106 in the upper branch is a PMOS tube MP1, and the first anti-backflow unit 105 is a diode DP; the gate driving signal of the PMOS tube MP1 is GateP; the switch tube 206 in the lower branch is an NMOS tube MN1, the second backflow prevention unit 206 is a diode DN, and a gate driving signal of the NMOS tube MN1 is GateN; when the bus driver works normally, only one of the upper branch circuit and the lower branch circuit is conducted, and the short-circuit protection circuit comprises:

a second comparator 201, wherein a positive phase input end of the second comparator 201 is used for inputting a second short-circuit threshold voltage Vthn, and a negative phase input end of the second comparator 201 is used for inputting an output voltage of an output port of the bus driver; the setting end of the second comparator 201 is used for inputting a gate driving signal GateN of a switching tube in the lower branch circuit to judge whether the lower branch circuit is conducted; when the gate driving signal GateN of the switching tube in the lower branch is at a low level, the output terminal of the second comparator 201 is set to a high level; when the gate driving signal GateN of the switching tube in the upper branch is at a high level, the output end of the second comparator 201 outputs the second short-circuit comparison result;

a second delay unit 202, an input end of the second delay unit 202 is configured to receive the output end level of the second comparator 201, when the output end level of the second comparator 201 is a high level, the second delay unit 202 is configured to shape and transmit the high level, and an output end thereof outputs a corresponding high level; when the output end level of the second comparator 201 is a low level, the second delay unit 202 is configured to output the low level from the output end thereof after a second delay time;

a second voltage-controlled current unit 203, a control terminal of the second voltage-controlled current unit 203 being connected to the output terminal of the second delay unit 202, and when the control terminal of the second voltage-controlled current unit 203 receives a high level, the output terminal of the second voltage-controlled current unit 203 outputs a third constant current; when the control terminal of the second voltage-controlled current unit 203 receives a low level, the output terminal of the second voltage-controlled current unit 203 outputs a fourth constant current, and the third constant current is greater than the fourth constant current;

the second current proportion unit 204, the second current proportion unit 204 includes an NMOS transistor MN2 and an NMOS transistor MN3, the source of the NMOS transistor MN2 and the source of the NMS transistor MN3 are connected together and then used for grounding, the drain of the NMOS transistor MN2, the gate of the NMOS transistor MN2 and the gate of the NMS transistor MN3 are connected together and then connected to the output end of the second voltage control current unit 203, and the drain of the NMOS transistor MN3 is used for connecting the source of the NMOS transistor of the lower branch.

It should be noted that the NMOS transistor MN2 and the NMOS transistor are low voltage NMOS transistors, and the NMOS transistor MN2 and the NMOS transistor have a voltage ratio of 1: the width-to-length ratio of n (n is an appropriate natural number) constitutes a connection mode of the current mirror. Under the condition that the lower branch is conducted: when the NMOS transistor MN3 works in a linear region, the current flowing through the NMOS transistor MN3 is determined by the driving load; when the NMOS transistor MN3 operates in the saturation region, the current flowing through the NMOS transistor MN3 is determined by the current value mirrored from the NMOS transistor MN2 by the NMOS transistor MN 3.

Fig. 11 is a schematic diagram of an application of the short-circuit protection circuit in a bus driver according to a fifth embodiment of the present invention, which provides specific circuits for all units in fig. 10, please refer to fig. 11:

wherein the second delay unit 202 includes: a PMOS tube MP5, an NMOS tube MN5, a capacitor C2 and a Schmidt inverter SMT 2; the gate of the PMOS transistor MP5 and the gate of the NMOS transistor MN5 are connected together and then serve as the input terminal of the second delay unit, the source of the PMOS transistor MP5 is used for connecting a power supply rail, the drain of the PMOS transistor MP5, the drain of the NMOS transistor MN5, one end of the capacitor C2 and the input terminal of the schmitt inverter SMT2 are connected together, the source of the NMOS transistor MN5 and the other end of the capacitor C2 are connected together and then serve as the ground, and the output terminal of the schmitt inverter SMT2 serves as the output terminal of the second delay unit 202.

Wherein the second voltage control current unit includes: a switch tube S2, a third reference current IN1 and a fourth reference current IN 2; the control terminal of the switching tube S2 is used as the control terminal of the second voltage-controlled current unit 203, one terminal of the switching tube S2 and one terminal of the fourth reference current IN2 are connected together and then used as the output terminal of the second voltage-controlled current unit 203, the other terminal of the switching tube S2 is connected to one terminal of the third reference current IN1, the other terminal of the third reference current IN1 is used for inputting the third reference current signal, and the other terminal of the fourth reference current IN2 is used for inputting the fourth reference current signal.

It should be noted that the current levels of the third reference current IN1 and the fourth reference current IN2 can be selected according to the requirement of the driving capability of the bus driver during normal operation and the current level set by the current limit value IN the short-circuit state, and the currents of the third reference current IN1 and the fourth reference current IN2 are both provided downwards by the reference current sources.

In this embodiment, the gate voltage of the NMOS transistor MN2 and the gate voltage VGN of the NMOS transistor MN3 are determined by the output current of the second voltage control current unit 203, the power rail voltage VCC is a fixed value, and the output voltage VOUT at the output port of the bus driver is a variable value.

The conditions that the NMOS tube MN2 and the NMOS tube MN3 work in a saturation region are that Vds is larger than Vgs-Vth, wherein Vgs is the grid-source voltage of the MOS tube, Vds is the drain-source voltage of the MOS tube, Vth is the threshold voltage of the MOS tube, and all three are positive values.

The NMOS transistor MN2 is used as an input transistor of the current mirror, the grid electrode and the drain electrode of the NMOS transistor MN2 are in short circuit, Vds is Vgs, Vds is larger than Vgs-Vth all the time, and the NMOS transistor MN2 works in a saturation region all the time.

The NMOS MN2 is used as an output tube of the current mirror, and the NMOS MN3 also works in the saturation region is a necessary condition for mirroring current from the NMOS MN2, and at this time, VDMN3 > VGN-VthMN3, where VDMP3 is the drain voltage of the NMOS MN3, and VthMN3 is the threshold voltage of the NMOS MN3, and since VDMN3 is VOUT-VDN-VDSMN1, where VDN is the forward conduction voltage drop of the diode DN, VDSMN1 is the drain-source voltage drop of the NMOS MN1, and the above formula of VDMN3 > VGN-VthMN3 is substituted: VOUT >)

VGN + VDP + VDSMN1-VthMN3, that is, when VOUT > VGN + VDP + VDSMN1-VthMN3, the NMOS tube MN3 works in the saturation region, and VGN, VDP, VDSMN1 and VthMN3 are fixed values, so that the threshold value of the NMOS tube MN3 entering the saturation region from the linear region can be designed by designing the values of VGN, VDP, VDSMN1 and VthMN3, and the threshold value is VGN + VDP + VDSMN1-VthMN 3.

As can be seen from the above analysis, the inventive concept of the present embodiment is the same as that of the second and fifth embodiments, since the operating state of the NMOS transistor MN3 in the present embodiment goes from the linear region to saturation needs to satisfy the condition that VOUT is greater than the above threshold VGN + VDP + VDSMN1-VthMN3, which can be regarded as the second on-load threshold voltage in the second and fifth embodiments, so that the present embodiment utilizes the natural operating characteristics of the NMOS transistor MN3 to implement the function of comparing the output voltage VOUT with the second on-load threshold voltage, obtain the second on-load comparison result, and perform the related action according to the second on-load comparison result.

The short-circuit protection circuit of the present embodiment aims to improve the temperature rise problem and the load capacity problem of the lower branch, and the operation principle of the present embodiment will be analyzed with reference to the circuit of fig. 11. For convenience of explanation and understanding, the following analysis directly considers the threshold VGN + VDP + VDSMN1-VthMN3 as VGN, and in the actual circuit design, the effect of VGN + VDP + VDSMN1-VthMN3 being VGN + VDP + VDSMN1-VthMN3 ═ VGN can be achieved by designing VDP + VDSMN1-VthMN3 to be zero. It is easy to understand that, when no short-circuit protection measure is taken, as the load gradually increases, that is, the current flowing through the lower branch gradually increases, the bus driver in this embodiment will sequentially operate in the light load mode, the heavy load mode, and the short-circuit mode, and the output voltage VOUT at the output port of the bus driver will gradually increase.

The short-circuit protection circuit of this embodiment aims at improving the temperature rise problem and the load carrying capability problem of the lower branch, and is analyzed in conjunction with the circuit of fig. 11, and includes the following three modes:

(1) and (3) a light load mode: the load is smaller, the output voltage VOUT of the output port of the bus driver is smaller, when VOUT is greater than or equal to 0 and is less than or equal to VGN, the negative phase input end of the second comparator 201 is smaller than the positive phase input end, and the high level output by the second comparator 201 controls the switching tube S2 of the second voltage control current unit 203 to be closed through the second delay unit 202, so that the sum of the third reference current IP3 and the fourth reference current IN2 is selected to be provided to the input end of the second current proportion unit 203, but at this time, because VOUT is less than or equal to VGN, the low-voltage NMOS tube MN3 IN the second current proportion unit 203 is IN a linear region and does not have a function of mirroring current from the NMOS tube MN2, at this time, the internal resistance of the NMOS tube MN3 is lower, the voltage drop of loss between the source and drain is smaller, and the magnitude of current flowing through the lower branch is completely determined by the load driving the output;

(2) the heavy load mode: as the driving output load increases, the output voltage at the output port of the bus driver increases, when VGN < VOUT < Vthn, the negative phase input terminal of the second comparator 201 is still smaller than the positive phase input terminal, the second comparator 201 still outputs a high level, and the high level controls the switching tube S2 of the second voltage control current unit 203 to close via the second delay unit 202, so that the sum of the third reference current IP3 and the fourth reference current IN2 is still selected to be provided to the input terminal of the second current proportional unit 203, but at this time, since VOUT > VGN, the low-voltage NMOS tube MN3 IN the second current proportional unit enters the saturation region, which can mirror the reference current on the NMOS tube MN2, so that the second current proportional unit 203 can limit the current value flowing through the lower branch by multiplying (IN1+ IN2) by the proportional value n between the low-voltage PMOS designed by the second current proportional unit 203, that is (IN1+ 2), which ensures that the driving stage IN the bus driver has the capability of driving the resistive load and the capacitive load, meanwhile, the current of the lower branch of the driving stage is limited within a controllable range;

(3) short circuit mode: with the further increase of the driving output load or the abnormal short-circuit of the port, which results IN higher VOUT, where VOUT > Vthn, the second comparator 201 outputs a low level to the second delay unit 202, the PMOS transistor MP5 IN the second delay unit 202 is turned on, the power rail charges the capacitor C2 through the PMOS transistor MP5 until the voltage drop across the capacitor C2 reaches the flip point of the schmitt inverter SMT2, that is, after a set delay time, the low level is output to control the switch tube S2 IN the second voltage-controlled current unit 203 to be turned off, only the fourth reference current IN2 is selected to be provided to the second current proportion unit 204, where VOUT is high and remains greater than VGN, the low-voltage NMOS transistor MN3 IN the second current proportion unit 203 is IN the saturation region, and keeps the mirror effect with the current mirror formed by the NMOS transistor MN2, where the second current proportion unit 203 limits the current value flowing through the lower branch, which is the fourth reference current IN2 multiplied by the proportion value n between the low-voltage NMOS designed by the second current proportion unit, IN2 n, the current of the lower branch is limited to a lower level when the chip is IN a short circuit state, and the reliability of the bus driver is improved.

The inventive concept of this embodiment is the same as that of the second embodiment and the sixth embodiment, and when the lower branch has a heavy load or a short circuit, the current flowing in the lower branch is reasonably limited by the reference currents (equal to the externally injected currents in the second embodiment and the sixth embodiment) with different magnitudes generated by the second voltage control current unit 203, so that not only can the temperature rise of the bus driver be controlled and the reliability of the bus driver be improved, but also compared with the control strategy of reducing the conduction number of the parallel lower switch tubes in the prior art, the decoupling between the differential output voltage and the short-circuit current of the bus driver is realized, and the two are not restricted with each other, so that the defect that the current value of the lower branch is very low when the short circuit is recovered during electrification is avoided, and the load carrying capability of the bus driver is improved in a wide range of the positive and negative common mode output voltages.

Eighth embodiment

Fig. 12 is a schematic block diagram of a short-circuit protection circuit according to a fourth embodiment of the present invention, and referring to fig. 12, the short-circuit protection circuit of the present embodiment combines a circuit according to the fourth embodiment and a circuit according to a sixth embodiment.

It is easy to understand that the short-circuit protection circuit of this embodiment aims to improve the temperature rise problem and the load carrying capability problem of the upper branch at the same time, and when the determination result of the first determining unit is "yes", the first executing unit includes three working modes, which are the same as the first embodiment and the fourth embodiment, and the beneficial effects are also the same, so that details are not described; when the determination result of the second determining unit is "yes", the second executing unit includes three working modes, which are the same as the second embodiment and the sixth embodiment, and the beneficial effects are also the same, and are not described again.

In the embodiment, no matter the upper branch circuit has a heavy load or a short circuit, or the lower branch circuit has a heavy load or a short circuit, the current flowing in the corresponding branch circuit can be reasonably limited by the reference currents with different sizes generated by the corresponding voltage control current units, so that not only can the temperature rise of the bus driver be controlled, but also the reliability of the bus driver is improved.

Ninth embodiment

Fig. 13 is a schematic block diagram of a short-circuit protection circuit according to a ninth embodiment of the present invention, fig. 14 is a schematic diagram of an application of the short-circuit protection circuit according to the ninth embodiment of the present invention in a bus driver, and the schematic diagram provides specific circuits for all units in fig. 10, please refer to fig. 13 and fig. 14, in which the short-circuit protection circuit according to the present embodiment combines the circuit according to the fifth embodiment with the circuit according to the seventh embodiment.

It is easy to understand that the short-circuit protection circuit of this embodiment aims at improving the temperature rise problem and the load carrying capability problem of the upper branch at the same time, and this embodiment includes three working modes when the upper branch is turned on, and these three working modes are the same as the fifth embodiment, and the beneficial effects brought by them are also the same, so they are not described again; when the lower branch is turned on, three working modes are included, which are the same as those in the seventh embodiment, and the beneficial effects are also the same, which is not described again.

IN the embodiment, by adding a corresponding voltage control current unit and a current proportion unit to an upper branch and a lower branch of a driving stage main power IN a bus driver respectively, wherein the voltage control current unit can output reference currents with different magnitudes, the current proportion unit is designed as a current mirror, and a low-voltage PMOS transistor MP3 and a low-voltage NMOS transistor MN3 IN the current mirror are connected IN series IN the upper branch and the lower branch of the driving stage main power IN the bus driver, so that the driving stage can be designed to make the on-internal resistances of the low-voltage PMOS transistor MP3 and the low-voltage NMOS transistor MN3 low to enhance the load capacity of the driving stage, raise the differential voltage output by the bus nodes (a, B), and also can respectively through reasonable distribution of currents IN the voltage control current units (i.e. magnitude configuration of a first reference current IP1 and a second reference current IP2, and magnitude configuration of a third reference current IN1 and a fourth reference current IN2), and the current proportion unit is provided with a proper mirror proportion (namely, the m and n values are selected), the current of the driving stage of the bus driver before entering the short-circuit protection and after entering the short-circuit protection is reasonably limited, the short-circuit temperature rise of the bus driver is further controlled, and the reliability is improved.

In the embodiment, no matter the upper branch circuit has a heavy load or a short circuit, or the lower branch circuit has a heavy load or a short circuit, the current flowing through the corresponding branch circuit can be reasonably limited by the reference currents with different sizes generated by the corresponding voltage control current units, so that not only can the temperature rise of the bus driver be controlled, and the reliability of the bus driver is improved, but also compared with the prior art, the decoupling between the differential output voltage and the short-circuit current of the bus driver is realized by reducing the conducting number of the upper switch tube or the lower switch tube which are connected in parallel, the two are not restricted mutually, so that the defect that the short circuit recovery requires the current value of the corresponding branch circuit to be very low during electrification does not exist, and the output disconnection of the bus driver improves the load capacity in a wide range of positive and negative common mode output voltages.

Tenth embodiment

In this embodiment, a bus driver includes the short-circuit protection circuit described in any one of the fourth embodiment to the ninth embodiment, and please refer to the attached drawings corresponding to the embodiments for the connection relationship between the short-circuit protection circuit and the bus driver.

In this embodiment, the switching tube 106 in the upper branch is a high-voltage P power MOS tube, and the switching tube 206 in the lower branch is a high-voltage N power MOS tube; the first anti-backflow unit 105 and the second anti-backflow unit 205 may each be one of a conventional diode, a schottky diode, or a MOS transistor connected in a diode connection manner.

In this embodiment, when the short-circuit protection circuit includes the low-voltage PMOS transistor MP3 and the low-voltage NMOS transistor MN3 in the relevant drawings, since the low-voltage PMOS transistor MP3 and the low-voltage NMOS transistor MN3 are also connected in series to the main power branch of the bus driver driving stage, the maximum current flowing through the low-voltage PMOS transistor MP3 and the low-voltage NMOS transistor MN3 is generally in the order of 100mA, and in a normal load state, in order to pursue low voltage drop loss, the linear area resistances of the PMOS transistor MP3 and the NMOS transistor MN3 cannot be too large, that is, the sizes of the two transistors cannot be too small. Meanwhile, in a short-circuit state, in order to ensure the matching accuracy of the PMOS tube MP3 and the PMOS tube MP2, and the NMOS tube MN3 and the NMOS tube MN2 in a saturation region, when the size of the PMOS tube MP3 is m times of that of the PMOS tube MP2, the size of the NMOS tube MN3 is n times of that of the NMOS tube MN2, the sizes of the PMOS tube MP2 and the NMOS tube MN2 cannot be too small, otherwise, the current matching accuracy is deteriorated due to device parameter boundary effect caused by the too small size, so the multiples m and n cannot be too large, and are recommended to be about 100 times (200 uA:200 mA).

As shown in fig. 15, which is a schematic diagram of waveforms of control voltages and output ports for driving the upper branch switching tube and the lower branch switching tube in the bus driver of this embodiment, when the upper branch switching tube and the lower branch switching tube are in a normal operating state and each pulse is output, an initial value of a level VOUT of the driving port OUT always satisfies VOUT > Vthn or VOUT < Vthp, and both the first comparator and the second comparator determine a short circuit, considering that a transmission rate is a key indicator of the driving circuit, therefore, the fifth embodiment, the seventh embodiment, and the ninth embodiment design corresponding delay units for avoiding a false short circuit state, and the corresponding voltage-controlled current units immediately select a small reference current to be provided to the current proportioning unit, and then the current proportioning unit multiplies the small reference current by the current proportioning unit to limit a current value flowing through the driving branch, i.e. IP2 mm or IN2 mm, which will slow down the first half of the rise and fall times tr and tf of the power tube, i.e. tp and tn IN the figure.

It should be noted that the delay time of the delay units should be designed to ensure that the switching parameter indicators tr and tf at the highest required transmission rate are not affected, i.e. the transmission delay tdp > tr of the first delay unit and the transmission delay tdn > tf of the second delay unit are designed.

The bus driver of this embodiment is added with the short-circuit protection circuit according to any one of the fourth to ninth embodiments, so that no matter the upper branch is overloaded or short-circuited, or the lower branch is overloaded or short-circuited, the current flowing through the corresponding branch can be reasonably limited, thereby not only controlling the temperature rise of the bus driver and improving the reliability of the bus driver, but also realizing the decoupling between the differential output voltage and the short-circuit current of the bus driver by reducing the conducting number of the upper switch tube or the lower switch tube connected in parallel compared with the control strategy in the prior art, so that the two are not mutually restricted, thereby avoiding the defect that the current value of the corresponding branch is very low when the short-circuit recovery is in an electrified state, and improving the load capacity when the output of the bus driver is disconnected in a wide range of positive and negative common mode output voltages.

Those of skill would further appreciate that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure.

Claims

1. A short-circuit protection method is applied to a bus driver, the bus driver comprises an upper branch circuit and a lower branch circuit, a switch tube in the upper branch circuit is a PMOS tube, a switch tube in the lower branch circuit is an NMOS tube, and only one of the upper branch circuit and the lower branch circuit is conducted when the bus driver works normally, the short-circuit protection method is characterized by comprising the following steps:

judging whether the upper branch is conducted or not;

the first preset current is less than the second preset current.

2. The short-circuit protection method according to claim 1, wherein: and judging whether the upper branch is conducted or not according to the high and low of the grid driving signal of the switching tube in the upper branch.

3. A short-circuit protection method is applied to a bus driver, the bus driver comprises an upper branch circuit and a lower branch circuit, a switch tube in the upper branch circuit is a PMOS tube, a switch tube in the lower branch circuit is an NMOS tube, and only one of the upper branch circuit and the lower branch circuit is conducted when the bus driver works normally, the short-circuit protection method is characterized by comprising the following steps:

judging whether the lower branch is conducted or not;

the third preset current is larger than the fourth preset current.

4. The short-circuit protection method according to claim 3, wherein: and judging whether the lower branch is conducted or not according to the high and low of the grid driving signal of the switching tube in the lower branch.

5. A short-circuit protection method is applied to a bus driver, the bus driver comprises an upper branch circuit and a lower branch circuit, a switch tube in the upper branch circuit is a PMOS tube, a switch tube in the lower branch circuit is an NMOS tube, and only one of the upper branch circuit and the lower branch circuit is conducted when the bus driver works normally, the short-circuit protection method is characterized by comprising the following steps:

judging whether the upper branch is conducted or not;

when the first loaded threshold voltage is less than the output voltage and less than or equal to the power supply rail voltage, the current flowing in the upper branch is determined by the driving load of the bus driver;

judging whether the lower branch is conducted or not;

when the output voltage is not less than 0 and not more than the second on-load threshold voltage, the current flowing in the lower branch is determined by the driving load of the bus driver;

6. The short-circuit protection method according to claim 5, wherein: judging whether the upper branch is conducted or not according to the high and low of the grid driving signal of the switching tube in the upper branch; and judging whether the lower branch is conducted or not according to the high and low of the grid driving signal of the switching tube in the lower branch.

7. A short-circuit protection circuit is applied to a bus driver, the bus driver comprises an upper branch circuit and a lower branch circuit, a switch tube in the upper branch circuit is a PMOS tube, a switch tube in the lower branch circuit is an NMOS tube, and when the bus driver works normally, only one of the upper branch circuit and the lower branch circuit is conducted, and the short-circuit protection circuit is characterized in that: the short-circuit protection circuit comprises a first short-circuit protection unit;

the first short-circuit protection unit includes:

the first preset current is less than the second preset current.

8. The short-circuit protection circuit of claim 7, wherein: the first judging unit judges whether the upper branch is conducted or not according to the high and low of the grid driving signal of the switching tube in the upper branch.

9. A short-circuit protection circuit is applied to a bus driver, the bus driver comprises an upper branch circuit and a lower branch circuit, a switch tube in the upper branch circuit is a PMOS tube, a switch tube in the lower branch circuit is an NMOS tube, and only one of the upper branch circuit and the lower branch circuit is conducted when the bus driver works normally, the short-circuit protection circuit is characterized by comprising:

10. The short protection circuit of claim 9, wherein the first delay unit comprises: a PMOS transistor MP4, an NMOS transistor MN4, a capacitor C1 and a Schmidt inverter SMT 1; the gate of the PMOS transistor MP4 and the gate of the NMOS transistor MN4 are connected together and then serve as the input terminal of the first delay unit, the source of the PMOS transistor MP4 is connected to the power rail, the drain of the PMOS transistor MP4, the drain of the NMOS transistor MN4, one end of the capacitor C1 and the input terminal of the schmitt inverter SMT1 are connected together, the source of the NMOS transistor MN4 and the other end of the capacitor C1 are connected together and then serve as the ground, and the output terminal of the schmitt inverter SMT1 serves as the output terminal of the first delay unit.

11. The short-circuit protection circuit of claim 9, wherein the first voltage-controlled current unit comprises: a switch tube S1, a first reference current IP1 and a second reference current IP 2; the control end of the switch tube S1 is used as the control end of the first voltage-controlled current unit, one end of the switch tube S1 and one end of the second reference current IP2 are connected together and then used as the output end of the first voltage-controlled current unit, the other end of the switch tube S1 is connected to one end of the first reference current IP1, the other end of the first reference current IP1 is used for inputting a first reference current signal, and the other end of the second reference current IP2 is used for inputting a second reference current signal.

12. A short-circuit protection circuit is applied to a bus driver, the bus driver comprises an upper branch circuit and a lower branch circuit, a switch tube in the upper branch circuit is a PMOS tube, a switch tube in the lower branch circuit is an NMOS tube, and when the bus driver works normally, only one of the upper branch circuit and the lower branch circuit is conducted, and the short-circuit protection circuit is characterized in that: the short-circuit protection circuit comprises a second short-circuit protection unit;

the second short-circuit protection unit includes:

the third preset current is larger than the fourth preset current.

13. The short-circuit protection circuit of claim 12, wherein: the second judging unit judges whether the lower branch is conducted or not according to the height of a grid driving signal of a switching tube in the lower branch.

14. A short-circuit protection circuit is applied to a bus driver, the bus driver comprises an upper branch circuit and a lower branch circuit, a switch tube in the upper branch circuit is a PMOS tube, a switch tube in the lower branch circuit is an NMOS tube, and only one of the upper branch circuit and the lower branch circuit is conducted when the bus driver works normally, the short-circuit protection circuit is characterized by comprising:

a positive phase input end of the second comparator is used for inputting the second short-circuit threshold voltage, and a negative phase input end of the second comparator is used for inputting the output voltage of the output port of the bus driver; the setting end of the second comparator is used for inputting a gate drive signal of a switching tube in the lower branch circuit to judge whether the lower branch circuit is conducted; when the grid driving signal of the switching tube in the lower branch circuit is at a low level, the output end of the second comparator is set to be at a high level; when a grid electrode driving signal of a switching tube in the upper branch circuit is in a high level, the output end of the second comparator outputs a second short circuit comparison result;

the input end of the second delay unit is used for receiving the output end level of the second comparator, when the output end level of the second comparator is high level, the second delay unit is used for shaping and transmitting the high level, and the output end of the second delay unit outputs the corresponding high level; when the level of the output end of the second comparator is low level, the second delay unit is used for outputting the low level from the output end of the second delay unit after second delay time;

15. The short protection circuit of claim 14, wherein the second delay unit comprises: a PMOS transistor MP5, an NMOS transistor MN5, a capacitor C2 and a Schmidt inverter SMT 2; the gate of the PMOS transistor MP5 and the gate of the NMOS transistor MN5 are connected together and then serve as the input terminal of the second delay unit, the source of the PMOS transistor MP5 is connected to the power rail, the drain of the PMOS transistor MP5, the drain of the NMOS transistor MN5, one end of the capacitor C2 and the input terminal of the schmitt inverter SMT2 are connected together, the source of the NMOS transistor MN5 and the other end of the capacitor C2 are connected together and then serve as the ground, and the output terminal of the schmitt inverter SMT2 serves as the output terminal of the second delay unit.

16. The short-circuit protection circuit of claim 14, wherein the second voltage-controlled current unit comprises: a switch tube S2, a third reference current IN1 and a fourth reference current IN 2; the control end of the switch tube S2 is used as the control end of the second voltage-controlled current unit, one end of the switch tube S2 and one end of the fourth reference current IN2 are connected together and then used as the output end of the second voltage-controlled current unit, the other end of the switch tube S2 is connected with one end of the third reference current IN1, the other end of the third reference current IN1 is used for inputting a third reference current signal, and the other end of the fourth reference current IN2 is used for inputting a fourth reference current signal.

17. A short-circuit protection circuit is applied to a bus driver, the bus driver comprises an upper branch circuit and a lower branch circuit, a switch tube in the upper branch circuit is a PMOS tube, a switch tube in the lower branch circuit is an NMOS tube, and when the bus driver works normally, only one of the upper branch circuit and the lower branch circuit is conducted, and the short-circuit protection circuit is characterized in that: the short-circuit protection circuit comprises a first short-circuit protection unit and a second short-circuit protection unit;

the first short-circuit protection unit includes:

the first preset current is less than the second preset current;

the second short-circuit protection unit includes:

when the second short-circuit threshold voltage is smaller than the output voltage, the current flowing in the lower branch circuit is determined by a fourth preset current injected into the lower branch circuit;

the third preset current is larger than the fourth preset current.

18. The short-circuit protection circuit of claim 17, wherein: the first judging unit judges whether the upper branch is conducted or not according to the height of a grid driving signal of a switching tube in the upper branch; the second judging unit judges whether the lower branch is conducted or not according to the height of a grid driving signal of a switching tube in the lower branch.

19. A short-circuit protection circuit is applied to a bus driver, the bus driver comprises an upper branch circuit and a lower branch circuit, a switch tube in the upper branch circuit is a PMOS tube, a switch tube in the lower branch circuit is an NMOS tube, and only one of the upper branch circuit and the lower branch circuit is conducted when the bus driver works normally, the short-circuit protection circuit is characterized by comprising:

the first current proportion unit comprises a PMOS (P-channel metal oxide semiconductor) tube MP2 and a PMS tube MP3, a source electrode of the PMOS tube MP2 and a source electrode of the PMS tube MP3 are connected together and then are used for being connected with a power supply rail, a drain electrode of the PMOS tube MP2, a grid electrode of the PMOS tube MP2 and a grid electrode of the PMS tube MP3 are connected together and then are connected with an output end of the first voltage control current unit, and a drain electrode of the PMOS tube MP3 is used for being connected with an anode of a backflow prevention diode of the upper branch;

20. The short protection circuit of claim 19, wherein the first delay unit comprises: a PMOS transistor MP4, an NMOS transistor MN4, a capacitor C1 and a Schmidt inverter SMT 1; the gate of the PMOS transistor MP4 and the gate of the NMOS transistor MN4 are connected together and then serve as the input terminal of the first delay unit, the source of the PMOS transistor MP4 is connected to the power rail, the drain of the PMOS transistor MP4, the drain of the NMOS transistor MN4, one end of the capacitor C1 and the input terminal of the schmitt inverter SMT1 are connected together, the source of the NMOS transistor MN4 and the other end of the capacitor C1 are connected together and then serve as the ground, and the output terminal of the schmitt inverter SMT1 serves as the output terminal of the first delay unit.

21. The short protection circuit of claim 19, wherein the first voltage controlled current cell comprises: a switch tube S1, a first reference current IP1 and a second reference current IP 2; the control end of the switch tube S1 is used as the control end of the first voltage control current unit, one end of the switch tube S1 and one end of the second reference current IP2 are connected together and then used as the output end of the first voltage control current unit, the other end of the switch tube S1 is connected with one end of the first reference current IP1, the other end of the first reference current IP1 is used for inputting a first reference current signal, and the other end of the second reference current IP2 is used for inputting a second reference current signal.

22. The short protection circuit of claim 19, wherein the second delay unit comprises: a PMOS transistor MP5, an NMOS transistor MN5, a capacitor C2 and a Schmidt inverter SMT 2; the gate of the PMOS transistor MP5 and the gate of the NMOS transistor MN5 are connected together and then serve as the input terminal of the second delay unit, the source of the PMOS transistor MP5 is connected to the power rail, the drain of the PMOS transistor MP5, the drain of the NMOS transistor MN5, one end of the capacitor C2 and the input terminal of the schmitt inverter SMT2 are connected together, the source of the NMOS transistor MN5 and the other end of the capacitor C2 are connected together and then serve as the ground, and the output terminal of the schmitt inverter SMT2 serves as the output terminal of the second delay unit.

23. The short protection circuit of claim 22, wherein the second voltage controlled current cell comprises: a switch tube S2, a third reference current IN1 and a fourth reference current IN 2; the control end of the switch tube S2 is used as the control end of the second voltage-controlled current unit, one end of the switch tube S2 and one end of the fourth reference current IN2 are connected together and then used as the output end of the second voltage-controlled current unit, the other end of the switch tube S2 is connected to one end of the third reference current IN1, the other end of the first reference current IP1 is used for inputting a first reference current signal, and the other end of the second reference current IP2 is used for inputting a second reference current signal.

24. A bus driver, comprising: the short-circuit protection circuit of any one of claims 7 to 23.