CN114995565A - A short circuit protection method, circuit and bus driver - Google Patents

Abstract

The invention discloses a short-circuit protection method, a circuit and a bus driver, wherein the short-circuit protection method comprises the following steps: judging whether the upper branch is conducted or not; when the judgment result is that the upper branch is conducted, the following steps are further executed: comparing the output voltage of the output port of the bus driver with a first short-circuit threshold voltage to obtain a first short-circuit comparison result; comparing the output voltage with a first on-load threshold voltage to obtain a first on-load comparison result; and controlling the current flowing in the upper branch circuit according to the first short circuit comparison result and the first load comparison result, wherein when the upper branch circuit is in a heavy load or a short circuit, the current flowing in the upper branch circuit is determined by different injected currents respectively. The invention can decouple the mutual restriction relationship between the internal resistance of the switching tube and the short-circuit current in the driving circuit and improve the amplitude of the differential driving voltage output by the circuit node on the bus.

Description

A short circuit protection method, circuit and bus driver

technical field

The present invention relates to the technical field of bus drivers, in particular to a short-circuit protection method, circuit and bus driver of the bus driver.

Background technique

Interface devices used for standard data exchange, such as interface chips such as RS485, RS232, and CAN, must not only be designed in accordance with the electrical characteristics standards of the corresponding communication protocol, but their bus ports must also be able to resist various risks from the bus, especially It is its bus driver. It is not only necessary to consider the situation when the bus driver is not powered on, but also to consider whether the output port of the bus driver may have been in the state of conduction or high resistance when it is powered on. Whether the bus driver can exit from the current state, Whether the signal path between the power rail-bus driver-bus can be opened or closed to ensure that the path of the current flow caused by the risk is controlled, ensuring that the bus driver itself is not damaged. In addition, the bus driver must also be resistant to overvoltage events that may occur in certain environments.

Fig. 1 is the conventional circuit schematic diagram of the prior art bus driver, in which only the driver stage part related to the present invention is drawn, including the upper branch, the lower branch, the power supply port VCC, the ground port GND and the output port OUT, the upper branch One end of the circuit is used as a power supply port to connect the power rail, the other end of the upper branch and one end of the lower branch are connected together as an output port for outputting the output voltage of the bus driver, and the other end of the lower branch is used as a ground port for grounding; each The branch circuit includes a switch unit and an anti-backflow unit. The diodes DP and DN in Fig. 1 are the anti-backflow units of the upper branch and the lower branch, respectively. They can be conventional diodes, or they can be different from other semiconductor devices in order to lower the voltage drop in the forward conduction condition. The diode is formed by the connection method; the PMOS tube MP1 and the NMOS tube N1 are the switch units of the upper branch and the lower branch respectively. In the actual chip design, the switch tubes in each branch can be designed as multiple switches of the same type The tubes are connected in parallel, for example, the MOS tube MP1 is designed as two PMOS tubes in parallel, and the MOS tube MN1 is designed as two NMOS tubes in parallel.

FIG. 2 is a schematic diagram of the application of the bus driver shown in FIG. 1 in the bus, which includes two buses and at least one circuit node. The circuit node is connected to one of the buses at point A, and the other bus is connected to the point B. The circuit node (A, B) is configured with two bus drivers shown in Figure 1. The output port of the first bus driver is connected to point A, and the output port of the second bus driver is connected to point B. At the same time, ① channel and ② channel There is only one operation, so that the nodes (A, B) will output a differential drive voltage, so when the bus driver in Figure 1 is in operation, only one branch will operate.

The protection strategy of the conventional bus driver when the output is overloaded or the output port is short-circuited is generally designed as follows: when the output voltage of the output port is high, that is, the upper branch P switch is turned on, and the lower branch N switch is turned off. Overload or short circuit causes the output voltage of the output port to be too low, lower than the short-circuit threshold of the upper branch, and the control signal turns off most of the P switches connected in parallel, thereby limiting the current drawn by the output port from the power rail; otherwise, When the output voltage of the output port is low level, when the output voltage of the output port is too high due to overload or short circuit, which is higher than the short circuit threshold of the lower branch, the control signal will turn off most of the N switches connected in parallel, thereby limiting the The current sinking into the ground from the output port acts as a short-circuit protection for the bus driver. But this method has the following disadvantages:

(1) In order to ensure the amplitude of the differential driving voltage output by the nodes (A, B), the internal resistance of the switch tube is generally designed to be as small as possible during chip design. However, before the output port voltage reaches the corresponding short-circuit threshold point, the corresponding switch tube will enter the saturation region. The smaller the internal resistance, the greater the saturation current. The saturation current flows from the power rail to the output port through the upper branch, or from the output port through the upper branch. The lower branch flows to the ground, which makes the temperature rise of the bus driver significantly, and the reliability is greatly reduced;

(2) When the bus driver is in a short-circuit state, due to the small number of switches on the driver stage and the large internal resistance, it will be difficult to achieve the short-circuit recovery point. For example, the internal resistance of the switch in the design short-circuit state is 3 times that of the normal state. To limit the current, when returning from the short-circuit state to the normal state, the current flowing through the switch tube needs to be reduced to 1/3 of the normal state, so that the output voltage of the output port can be restored to the threshold point, and most of the switches are turned on again. However, this shortcoming directly causes the node (A, B) to fail to provide sufficient differential drive voltage when the common mode level output by the bus driver is lower and more negative.

For the application schematic diagram of FIG. 2, the output voltage of the output port of the bus driver includes: the output voltage VA of the output port of the first bus driver, and the output voltage VB of the output port of the second bus driver; the common mode level output by the bus driver refers to : Half of the sum of the output voltage of the output port of the first bus driver and the output voltage of the output port of the second bus driver, namely (VA+VB)/2; the differential driving voltage output by the node (A, B) refers to: the first The difference between the output voltage of one bus driver output port and the output voltage of the second bus driver output port is (VA-VB).

The above shortcomings limit the internal resistance of the switch tube to not be too small, which actually limits the load-carrying capability of the bus driver.

SUMMARY OF THE INVENTION

In view of this, the technical problem to be solved by the present invention is to provide a driving short-circuit protection method and at least to a certain extent solve one of the technical problems existing in the prior art.

As a first aspect of the present invention, the provided short-circuit protection method is as follows:

A short-circuit protection method is applied to a bus driver, wherein the bus driver includes an upper branch and a lower branch, the switch tube in the upper branch is a PMOS tube, and the switch tube in the lower branch is an NMOS tube, When the bus driver works normally, only one of the upper branch and the lower branch is turned on, and the short-circuit protection method includes the following steps:

judging whether the upper branch is turned on;

When the judgment result is that the upper branch is turned on, the following steps are further performed:

comparing the output voltage of the output port of the bus driver with the first short-circuit threshold voltage to obtain a first short-circuit comparison result;

comparing the output voltage with the first on-load threshold voltage to obtain a first on-load comparison result;

The magnitude of the current flowing in the upper branch is controlled according to the first short-circuit comparison result and the first on-load comparison result, and the control logic is as follows:

When the output voltage≤the first short-circuit threshold voltage, the current flowing in the upper branch is determined by the first preset current injected into the upper branch;

When the first short-circuit threshold voltage<the output voltage≤the first on-load threshold voltage, the current flowing in the upper branch is determined by the second preset current injected into the upper branch;

When the first load threshold voltage is less than the output voltage≤power rail voltage, the current flowing in the upper branch is determined by the driving load of the bus driver;

The first preset current < the second preset current.

Further, whether the upper branch is turned on is determined by the level of the gate driving signal of the switch transistor in the upper branch.

A short-circuit protection method is applied to a bus driver, wherein the bus driver includes an upper branch and a lower branch, the switch tube in the upper branch is a PMOS tube, and the switch tube in the lower branch is an NMOS tube, When the bus driver works normally, only one of the upper branch and the lower branch is turned on, and the short-circuit protection method includes the following steps:

judging whether the lower branch is turned on;

When the judgment result is that the lower branch is turned on, the following steps are further performed:

comparing the output voltage of the output port of the bus driver with the second short-circuit threshold voltage to obtain a second short-circuit comparison result;

comparing the output voltage with the second on-load threshold voltage to obtain a second on-load comparison result;

The magnitude of the current flowing in the lower branch is controlled according to the second short-circuit comparison result and the second on-load comparison result, and the control logic is as follows:

When 0≤the output voltage≤the second load threshold voltage, the current flowing in the lower branch is determined by the driving load of the bus driver;

When the second on-load threshold voltage<the output voltage≤the second short-circuit threshold voltage, the current flowing in the lower branch is determined by a third preset current injected into the lower branch;

When the second short-circuit threshold voltage < the output voltage, the current flowing in the lower branch is determined by a fourth preset current injected into the lower branch;

The third preset current>the fourth preset current.

Further, whether the lower branch is turned on is determined according to the level of the gate driving signal of the switch transistor in the lower branch.

A short-circuit protection method is applied to a bus driver, wherein the bus driver includes an upper branch and a lower branch, the switch tube in the upper branch is a PMOS tube, and the switch tube in the lower branch is an NMOS tube, When the bus driver works normally, only one of the upper branch and the lower branch is turned on, and the short-circuit protection method includes the following steps:

judging whether the upper branch is turned on;

When the judgment result is that the upper branch is turned on, the following steps are further performed:

comparing the output voltage of the output port of the bus driver with the first short-circuit threshold voltage to obtain a first short-circuit comparison result;

comparing the output voltage with the first on-load threshold voltage to obtain a first on-load comparison result;

The magnitude of the current flowing in the upper branch is controlled according to the first short-circuit comparison result and the first on-load comparison result, and the control logic is as follows:

When the output voltage≤the first short-circuit threshold voltage, the current flowing in the upper branch is determined by the first preset current injected into the upper branch;

When the first short-circuit threshold voltage<the output voltage≤the first on-load threshold voltage, the current flowing in the upper branch is determined by the second preset current injected into the upper branch;

When the first load threshold voltage is less than the output voltage≤power rail voltage, the current flowing in the upper branch is determined by the driving load of the bus driver;

judging whether the lower branch is turned on;

When the judgment result is that the lower branch is turned on, the following steps are further performed:

comparing the output voltage of the output port of the bus driver with the second short-circuit threshold voltage to obtain a second short-circuit comparison result;

comparing the output voltage with the second on-load threshold voltage to obtain a second on-load comparison result;

The magnitude of the current flowing in the lower branch is controlled according to the second short-circuit comparison result and the second on-load comparison result, and the control logic is as follows:

When 0≤the output voltage≤the second load threshold voltage, the current flowing in the lower branch is determined by the driving load of the bus driver;

When the second on-load threshold voltage<the output voltage≤the second short-circuit threshold voltage, the current flowing in the lower branch is determined by a third preset current injected into the lower branch;

When the second short-circuit threshold voltage < the output voltage, the current flowing in the lower branch is determined by a third preset current injected into the lower branch;

The first preset current<the second preset current; the third preset current>the fourth preset current.

Further, whether the upper branch is turned on is judged by the level of the gate drive signal of the switch in the upper branch; the lower branch is judged by the level of the gate drive signal of the switch in the lower branch whether the road is connected.

As the second aspect of the present invention, the provided short circuit protection circuit is implemented as follows:

A short circuit protection circuit is applied to a bus driver, wherein the bus driver includes an upper branch and a lower branch, the switch tube in the upper branch is a PMOS tube, and the switch tube in the lower branch is an NMOS tube, When the bus driver works normally, only one of the upper branch and the lower branch is turned on, and the short-circuit protection circuit includes a first short-circuit protection unit;

The first short-circuit protection unit includes:

a first judging unit for judging whether the upper branch is turned on;

The first execution unit is configured to further perform the following actions when the judgment result of the first judgment unit is that the upper branch is turned on:

comparing the output voltage of the output port of the bus driver with the first short-circuit threshold voltage to obtain a first short-circuit comparison result;

comparing the output voltage with the first on-load threshold voltage to obtain a first on-load comparison result;

The magnitude of the current flowing in the upper branch is controlled according to the first short-circuit comparison result and the first on-load comparison result, and the control logic is as follows:

When the output voltage≤the first short-circuit threshold voltage, the current flowing in the upper branch is determined by the first preset current injected into the upper branch;

When the first short-circuit threshold voltage<the output voltage≤the first on-load threshold voltage, the current flowing in the upper branch is determined by the second preset current injected into the upper branch;

When the first load threshold voltage is less than the output voltage≤power rail voltage, the current flowing in the upper branch is determined by the driving load of the bus driver;

The first preset current < the second preset current.

Further, the first judging unit judges whether the upper branch is turned on according to the level of the gate driving signal of the switch transistor in the upper branch.

A short circuit protection circuit is applied to a bus driver, wherein the bus driver includes an upper branch and a lower branch, the switch tube in the upper branch is a PMOS tube, and the switch tube in the lower branch is an NMOS tube, When the bus driver works normally, only one of the upper branch and the lower branch is turned on, and the short-circuit protection circuit includes:

a first comparator, the positive-phase input terminal of the first comparator is used to input the output voltage of the output port of the bus driver, and the negative-phase input terminal is used to input the first short-circuit threshold voltage; the setting of the first comparator The terminal is used to input the gate drive signal of the switch tube in the upper branch, so as to realize the judgment of whether the upper branch is turned on; when the gate drive signal of the switch tube in the upper branch is high level, The output end of the first comparator is set to a high level; when the gate drive signal of the switch in the upper branch is a low level, the output end of the first comparator outputs the first short circuit comparison result;

a first delay unit, the input end of the first delay unit is used for receiving the level of the output end of the first comparator, when the level of the output end of the first comparator is a high level, the first The delay unit is used for shaping and transmitting the high level, and its output terminal outputs the corresponding high level; when the level of the output terminal of the first comparator is a low level, the first delay unit is used for After the first delay time, the output terminal outputs the low level;

a first voltage-controlled current unit, the control terminal of the first voltage-controlled current unit is connected to the output terminal of the first delay unit, when the control terminal of the first voltage-controlled current unit receives a high level, the first voltage-controlled current unit The output terminal of a voltage-controlled current unit outputs a first constant current; when the control terminal of the first voltage-controlled current unit receives a low level, the output terminal of the first voltage-controlled current unit outputs a second constant current, so the first constant current > the second constant current;

A first current proportional unit, the first current proportional unit includes a PMOS transistor MP2 and a PMS transistor MP3, the source of the PMOS transistor MP2 and the source of the PMS transistor MP3 are connected together for connecting the power rail, so The drain of the PMOS transistor MP2, the gate of the PMOS transistor MP2 and the gate of the PMS transistor MP3 are connected together and then connected to the output end of the first voltage-controlled current unit, and the drain of the PMOS transistor MP3 Used to connect the anode of the anti-backflow diode of the upper branch.

As a specific implementation of the first delay unit, it includes: a PMOS transistor MP4, an NMOS transistor MN4, a capacitor C1 and a Schmitt inverter SMT1; the gate of the PMOS transistor MP4 and the NMOS transistor MN4 The gates are connected together as the input end of the first delay unit, the source of the PMOS transistor MP4 is used to connect the power rail, the drain of the PMOS transistor MP4, the drain of the NMOS transistor MN4 electrode, one end of the capacitor C1 and the input end of the Schmitt inverter SMT1 are connected together, the source of the NMOS transistor MN4 and the other end of the capacitor C1 are connected together for grounding, the The output terminal of the mitt inverter SMT1 serves as the output terminal of the first delay unit.

As a specific implementation of the first voltage control current unit, it includes: a switch tube S1, a first reference current IP1 and a second reference current IP2; the control end of the switch tube S1 serves as the first voltage control The control end of the current unit, one end of the switch tube S1 and one end of the second reference current IP2 are connected together as the output end of the first voltage-controlled current unit, and the other end of the switch tube S1 is connected to the One end of the first reference current IP1, the other end of the first reference current IP1 is used for inputting the first reference current signal, and the other end of the second reference current IP2 is used for inputting the second reference current signal.

A short circuit protection circuit is applied to a bus driver, wherein the bus driver includes an upper branch and a lower branch, the switch tube in the upper branch is a PMOS tube, and the switch tube in the lower branch is an NMOS tube, When the bus driver works normally, only one of the upper branch and the lower branch is turned on, and the short-circuit protection circuit includes a second short-circuit protection unit;

The second short-circuit protection unit includes:

a second judging unit, configured to judge whether the lower branch is turned on;

The second execution unit is configured to further perform the following actions when the judgment result of the second judgment unit is that the lower branch is turned on:

comparing the output voltage of the output port of the bus driver with the second short-circuit threshold voltage to obtain a second short-circuit comparison result;

comparing the output voltage with the second on-load threshold voltage to obtain a second on-load comparison result;

The magnitude of the current flowing in the lower branch is controlled according to the second short-circuit comparison result and the second on-load comparison result, and the control logic is as follows:

When 0≤the output voltage≤the second load threshold voltage, the current flowing in the lower branch is determined by the driving load of the bus driver;

When the second on-load threshold voltage<the output voltage≤the second short-circuit threshold voltage, the current flowing in the lower branch is determined by a third preset current injected into the lower branch;

When the second short-circuit threshold voltage < the output voltage, the current flowing in the lower branch is determined by a fourth preset current injected into the lower branch;

The third preset current>the fourth preset current.

Further, the second judging unit judges whether the lower branch is turned on according to the level of the gate driving signal of the switch transistor in the lower branch.

A short circuit protection circuit is applied to a bus driver, wherein the bus driver includes an upper branch and a lower branch, the switch tube in the upper branch is a PMOS tube, and the switch tube in the lower branch is an NMOS tube, When the bus driver works normally, only one of the upper branch and the lower branch is turned on, and the short-circuit protection circuit includes:

a second comparator, the positive-phase input terminal of the second comparator is used for inputting the second short-circuit threshold voltage, and the negative-phase input terminal is used for inputting the output voltage of the output port of the bus driver; the setting of the second comparator The terminal is used to input the gate drive signal of the switch tube in the lower branch, so as to realize the judgment of whether the lower branch is turned on; when the gate drive signal of the switch tube in the lower branch is low level, The output end of the second comparator is set to a high level; when the gate drive signal of the switch in the upper branch is a high level, the output end of the second comparator outputs the second short circuit comparison result;

The second delay unit, the input end of the second delay unit is used to receive the level of the output end of the second comparator, when the level of the output end of the second comparator is a high level, the second delay unit The delay unit is used to shape and transmit the high level, and output the corresponding high level from its output terminal; when the level of the output terminal of the second comparator is a low level, the second delay unit is used for After the second delay time, the output terminal outputs the low level;

The second voltage-controlled current unit, the control terminal of the second voltage-controlled current unit is connected to the output terminal of the second delay unit, when the control terminal of the second voltage-controlled current unit receives a high level, the first The output terminal of the two voltage-controlled current units outputs a third constant current; when the control terminal of the second voltage-controlled current unit receives a low level, the output terminal of the second voltage-controlled current unit outputs a fourth constant current, so the third constant current > the fourth constant current;

A second current proportional unit, the second current proportional unit includes an NMOS transistor MN2 and an NMOS transistor MN3, the source of the NMOS transistor MN2 and the source of the NMS transistor MN3 are connected together for grounding, and the NMOS transistor The drain of the transistor MN2, the gate of the NMOS transistor MN2 and the gate of the NMS transistor MN3 are connected together and then connected to the output terminal of the second voltage-controlled current unit, and the drain of the NMOS transistor MN3 is used for The source electrode of the NMOS transistor of the lower branch is connected.

As a specific implementation of the second delay unit, it includes: a PMOS transistor MP5, an NMOS transistor MN5, a capacitor C2 and a Schmitt inverter SMT2; the gate of the PMOS transistor MP5 and the NMOS transistor MN5 The gates of the PMOS transistors are connected together as the input terminal of the second delay unit, the source of the PMOS transistor MP5 is used to connect the power rail, the drain of the PMOS transistor MP5, the drain of the NMOS transistor MN5 pole, one end of the capacitor C2 and the input end of the Schmitt inverter SMT2 are connected together, the source of the NMOS transistor MN5 and the other end of the capacitor C2 are connected together for grounding, and the The output terminal of the mitt inverter SMT2 serves as the output terminal of the second delay unit.

As a specific implementation of the second voltage control current unit, it includes: a switch tube S2, a third reference current IN1 and a fourth reference current IN2; the control end of the switch tube S2 serves as the second voltage control The control end of the current unit, one end of the switch tube S2 and one end of the fourth reference current IN2 are connected together as the output end of the second voltage-controlled current unit, and the other end of the switch tube S2 is connected to the One end of the third reference current IN1, the other end of the third reference current IN1 is used for inputting a third reference current signal, and the other end of the fourth reference current IN2 is used for inputting a fourth reference current signal.

A short circuit protection circuit is applied to a bus driver, wherein the bus driver includes an upper branch and a lower branch, the switch tube in the upper branch is a PMOS tube, and the switch tube in the lower branch is an NMOS tube, When the bus driver works normally, only one of the upper branch and the lower branch is turned on, and the short-circuit protection circuit includes a first short-circuit protection unit and a second short-circuit protection unit;

The first short-circuit protection unit includes:

a first judging unit for judging whether the upper branch is turned on;

The first execution unit is configured to further perform the following actions when the judgment result of the first judgment unit is that the upper branch is turned on:

comparing the output voltage of the output port of the bus driver with the first short-circuit threshold voltage to obtain a first short-circuit comparison result;

comparing the output voltage with the first on-load threshold voltage to obtain a first on-load comparison result;

The magnitude of the current flowing in the upper branch is controlled according to the first short-circuit comparison result and the first on-load comparison result, and the control logic is as follows:

When the output voltage≤the first short-circuit threshold voltage, the current flowing in the upper branch is determined by the first preset current injected into the upper branch;

When the first short-circuit threshold voltage<the output voltage≤the first on-load threshold voltage, the current flowing in the upper branch is determined by the second preset current injected into the upper branch;

When the first load threshold voltage is less than the output voltage≤power rail voltage, the current flowing in the upper branch is determined by the driving load of the bus driver;

the first preset current < the second preset current;

The second short-circuit protection unit includes:

a second judging unit, configured to judge whether the lower branch is turned on;

The second execution unit is configured to further perform the following actions when the judgment result of the second judgment unit is that the lower branch is turned on:

comparing the output voltage of the output port of the bus driver with the second short-circuit threshold voltage to obtain a second short-circuit comparison result;

comparing the output voltage with the second on-load threshold voltage to obtain a second on-load comparison result;

The magnitude of the current flowing in the lower branch is controlled according to the second short-circuit comparison result and the second on-load comparison result, and the control logic is as follows:

When 0≤the output voltage≤the second load threshold voltage, the current flowing in the lower branch is determined by the driving load of the bus driver;

When the second on-load threshold voltage<the output voltage≤the second short-circuit threshold voltage, the current flowing in the lower branch is determined by a third preset current injected into the lower branch;

When the second short-circuit threshold voltage < the output voltage, the current flowing in the lower branch is determined by a fourth preset current injected into the lower branch;

The third preset current>the fourth preset current.

Further, the first judging unit judges whether the upper branch is turned on according to the level of the gate drive signal of the switch tube in the upper branch; the second judging unit is determined by the switch tube in the lower branch. The level of the gate driving signal is used to determine whether the lower branch is turned on.

A short circuit protection circuit is applied to a bus driver, wherein the bus driver includes an upper branch and a lower branch, the switch tube in the upper branch is a PMOS tube, and the switch tube in the lower branch is an NMOS tube, When the bus driver works normally, only one of the upper branch and the lower branch is turned on, and the short-circuit protection circuit includes:

a first comparator, the positive-phase input terminal of the first comparator is used to input the output voltage of the output port of the bus driver, and the negative-phase input terminal is used to input the first short-circuit threshold voltage; the setting of the first comparator The terminal is used to input the gate drive signal of the switch tube in the upper branch, so as to realize the judgment of whether the upper branch is turned on; when the gate drive signal of the switch tube in the upper branch is high level, The output end of the first comparator is set to a high level; when the gate drive signal of the switch in the upper branch is a low level, the output end of the first comparator outputs the first short circuit comparison result;

a first delay unit, the input end of the first delay unit is used for receiving the level of the output end of the first comparator, when the level of the output end of the first comparator is a high level, the first The delay unit is used for shaping and transmitting the high level, and its output terminal outputs the corresponding high level; when the level of the output terminal of the first comparator is a low level, the first delay unit is used for After the first delay time, the output terminal outputs the low level;

a first voltage-controlled current unit, the control terminal of the first voltage-controlled current unit is connected to the output terminal of the first delay unit, when the control terminal of the first voltage-controlled current unit receives a high level, the first voltage-controlled current unit The output terminal of a voltage-controlled current unit outputs a first constant current; when the control terminal of the first voltage-controlled current unit receives a low level, the output terminal of the first voltage-controlled current unit outputs a second constant current, so the first constant current > the second constant current;

A first current proportional unit, the first current proportional unit includes a PMOS transistor MP2 and a PMS transistor MP3, the source of the PMOS transistor MP2 and the source of the PMS transistor MP3 are connected together for connecting the power rail, so The drain of the PMOS transistor MP2, the gate of the PMOS transistor MP2 and the gate of the PMS transistor MP3 are connected together and then connected to the output end of the first voltage-controlled current unit, and the drain of the PMOS transistor MP3 an anode for connecting the anti-backflow diode of the upper branch;

a second comparator, the positive-phase input terminal of the second comparator is used for inputting the second short-circuit threshold voltage, the negative-phase input terminal is used for inputting the output voltage; the set terminal of the second comparator is used for inputting the second short-circuit threshold voltage The gate drive signal of the switch tube in the lower branch is input to realize the judgment of whether the lower branch is turned on; when the gate drive signal of the switch tube in the lower branch is at a low level, the first The output terminal of the second comparator is set to a high level; when the gate driving signal of the switch in the upper branch is a high level, the output terminal of the second comparator outputs the second short-circuit comparison result ;

The second delay unit, the input end of the second delay unit is used to receive the level of the output end of the second comparator, when the level of the output end of the second comparator is a high level, the second delay unit The delay unit is used to shape and transmit the high level, and output the corresponding high level from its output terminal; when the level of the output terminal of the second comparator is a low level, the second delay unit is used for After the second delay time, the output terminal outputs the low level;

The second voltage-controlled current unit, the control terminal of the second voltage-controlled current unit is connected to the output terminal of the second delay unit, when the control terminal of the second voltage-controlled current unit receives a high level, the first The output terminal of the two voltage-controlled current units outputs a third constant current; when the control terminal of the second voltage-controlled current unit receives a low level, the output terminal of the second voltage-controlled current unit outputs a fourth constant current, so the third constant current > the fourth constant current;

A second current proportional unit, the second current proportional unit includes an NMOS transistor MN2 and an NMOS transistor MN3, the source of the NMOS transistor MN2 and the source of the NMS transistor MN3 are connected together for grounding, and the NMOS transistor The drain of the transistor MN2, the gate of the NMOS transistor MN2 and the gate of the NMS transistor MN3 are connected together and then connected to the output terminal of the second voltage-controlled current unit, and the drain of the NMOS transistor MN3 is used for The source electrode of the NMOS transistor of the lower branch is connected.

As a specific implementation of the first delay unit, it includes: a PMOS transistor MP4, an NMOS transistor MN4, a capacitor C1 and a Schmitt inverter SMT1; the gate of the PMOS transistor MP4 and the NMOS transistor MN4 The gates are connected together as the input end of the first delay unit, the source of the PMOS transistor MP4 is used to connect the power rail, the drain of the PMOS transistor MP4, the drain of the NMOS transistor MN4 electrode, one end of the capacitor C1 and the input end of the Schmitt inverter SMT1 are connected together, the source of the NMOS transistor MN4 and the other end of the capacitor C1 are connected together for grounding, the The output terminal of the mitt inverter SMT1 serves as the output terminal of the first delay unit.

As a specific implementation of the first voltage control current unit, it includes: a switch tube S1, a first reference current IP1 and a second reference current IP2; the control end of the switch tube S1 serves as the first voltage control The control end of the current unit, one end of the switch tube S1 and one end of the second reference current IP2 are connected together as the output end of the first voltage-controlled current unit, and the other end of the switch tube S1 is connected to the One end of the first reference current IP1, the other end of the first reference current IP1 is used for inputting the first reference current signal, and the other end of the second reference current IP2 is used for inputting the second reference current signal.

As a specific implementation of the second delay unit, it includes: a PMOS transistor MP5, an NMOS transistor MN5, a capacitor C2 and a Schmitt inverter SMT2; the gate of the PMOS transistor MP5 and the NMOS transistor MN5 The gates of the PMOS transistors are connected together as the input terminal of the second delay unit, the source of the PMOS transistor MP5 is used to connect the power rail, the drain of the PMOS transistor MP5, the drain of the NMOS transistor MN5 pole, one end of the capacitor C2 and the input end of the Schmitt inverter SMT2 are connected together, the source of the NMOS transistor MN5 and the other end of the capacitor C2 are connected together for grounding, and the The output terminal of the mitt inverter SMT2 serves as the output terminal of the second delay unit.

As a specific implementation of the second voltage control current unit, it includes: a switch tube S2, a third reference current IN1 and a fourth reference current IN2; the control end of the switch tube S2 serves as the second voltage control The control end of the current unit, one end of the switch tube S2 and one end of the fourth reference current IN2 are connected together as the output end of the second voltage-controlled current unit, and the other end of the switch tube S2 is connected to the One end of the third reference current IN1, the other end of the first reference current IP1 is used for inputting the first reference current signal, and the other end of the second reference current IP2 is used for inputting the second reference current signal.

As the third aspect of the present invention, the provided bus driver is as follows:

A bus driver includes the short-circuit protection circuit described in any one of the above embodiments.

Term meaning:

Current sink: Current is input from one end of the device, flows out from the other end of the device and flows to the power supply ground, similar to absorbing current, often called current sink;

Current source: The current enters one end of the device from the power rail and flows out from the other end of the device. This current can be used as the input source signal of other circuits, so it is often called a current source;

The embodiments of the present invention include at least the following beneficial effects: when the bus driver is overloaded or short-circuited, the current flowing in the upper branch or the lower branch will be reasonably limited by internally generated reference currents of different sizes, and not only can control the bus driver Compared with the control strategy of reducing the number of connected upper switches or lower switches in parallel in the prior art, the solution between the differential output voltage of the bus driver and the short-circuit current is realized. Coupling, so that the two no longer restrict each other, so that there is no short-circuit recovery when electrified, the current value of the corresponding branch is very low, and the load capacity of the bus driver is improved within a wide range of positive and negative common mode output voltages.

Other features and advantages of the present invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention may be realized and attained by the structure particularly pointed out in the description, claims and drawings.

Description of drawings

Fig. 1 is the conventional circuit schematic diagram of the prior art bus driver;

Fig. 2 is the application principle diagram of the bus driver shown in Fig. 1 in the bus;

3 is a flowchart of a short-circuit protection method provided by the first embodiment of the present invention;

4 is a flowchart of a short-circuit protection method provided by a second embodiment of the present invention;

5 is a flowchart of a short-circuit protection method provided by a third embodiment of the present invention;

6 is a schematic block diagram of a short-circuit protection circuit provided by a fourth embodiment of the present invention;

7 is a schematic diagram of the application of the short-circuit protection circuit provided in the fifth embodiment of the present invention in a bus driver;

8 is a schematic diagram of the application of the short-circuit protection circuit provided in the fifth embodiment of the present invention in a bus driver, and the diagram provides a specific circuit for all the units in FIG. 7;

9 is a schematic block diagram of a short-circuit protection circuit provided by a sixth embodiment of the present invention;

10 is a schematic diagram of the application of the short-circuit protection circuit provided in the seventh embodiment of the present invention in a bus driver;

FIG. 11 is a schematic diagram of the application of the short-circuit protection circuit provided in the seventh embodiment of the present invention in a bus driver, and the diagram provides a specific circuit for all the units in FIG. 10;

12 is a schematic block diagram of a short-circuit protection circuit provided by the eighth embodiment of the present invention;

13 is a schematic diagram of the application of the short-circuit protection circuit provided in the ninth embodiment of the present invention in a bus driver;

14 is a schematic diagram of the application of the short-circuit protection circuit provided in the ninth embodiment of the present invention in a bus driver, and the diagram provides a specific circuit for all the units in FIG. 10;

FIG. 15 is a schematic diagram of the waveform of the short-circuit protection delay time design of the present invention.

Detailed ways

It should be noted that the embodiments in the present application and the features of the embodiments may be combined with each other in the case of no conflict. The present application will be described in detail below with reference to the accompanying drawings and in conjunction with the embodiments.

In order to make those skilled in the art better understand the solutions of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only The embodiments are part of the present application, but not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work shall fall within the scope of protection of the present application.

It should be noted that the terms "first", "second", etc. in the description and claims of the present application and the above drawings are used to distinguish similar objects, and are not necessarily used to describe a specific sequence or sequence. It is to be understood that the data so used are interchangeable under appropriate circumstances for the embodiments of the application described herein. Furthermore, the terms "comprising" and "having" and any variations thereof, are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those expressly listed Rather, those steps or units may include other steps or units not expressly listed or inherent to these processes, methods, products or devices.

It should be understood that, in the description, the claims and the accompanying drawings, when a step is described as being connected to another step, the step can be directly connected to the other step, or connected to the other step through the third step. Step; when an element/unit is described as being "connected" to another element/unit, the element/unit may be "directly connected" to the other element/unit, or "connected" to the other element/unit through a third element/unit element/unit.

Furthermore, the drawings of the present disclosure are merely schematic representations of the present disclosure and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and thus repeated descriptions thereof will be omitted. Some of the block diagrams shown in the figures are functional entities that do not necessarily necessarily correspond to physically or logically separate entities. These functional entities may be implemented in software, or in one or more hardware modules or integrated circuits, or in different networks and/or processor devices and/or microcontroller devices.

first embodiment

FIG. 3 is a flowchart of the short-circuit protection method provided by the first embodiment of the present invention. Please refer to FIG. 3. The short-circuit protection method of this embodiment is applied to the bus driver in FIG. 1 and FIG. 2. The bus driver includes an upper branch and a In the lower branch, the switch tube in the upper branch is a PMOS tube, and the switch tube in the lower branch is an NMOS tube. When the bus driver is working normally, only one of the upper branch and the lower branch is turned on. Short circuit protection method It includes the following steps:

S101: determine whether the upper branch is turned on;

When the judgment result is that the upper branch is turned on, the following steps are further performed:

S1021: Compare the output voltage of the output port of the bus driver with the first short-circuit threshold voltage to obtain a first short-circuit comparison result;

S1022: Compare the output voltage with a first on-load threshold voltage to obtain a first on-load comparison result;

S103: Control the magnitude of the current flowing in the upper branch according to the first short-circuit comparison result and the first on-load comparison result, and the control logic is as follows:

S1041: when the output voltage≤the first short-circuit threshold voltage, the current flowing in the upper branch is determined by the first preset current injected into the upper branch;

S1042: when the first short-circuit threshold voltage<the output voltage≤the first on-load threshold voltage, the current flowing in the upper branch is determined by the second preset current injected into the upper branch;

S1043: When the first load threshold voltage < the output voltage≤ power rail voltage, the current flowing in the upper branch is determined by the driving load of the bus driver;

The first preset current < the second preset current.

Wherein, steps S1021 and S1022 are performed synchronously, and steps S1041, S1042 and S1043 are one of the specific situations of step S103, that is, when step 103 is specifically executed, only one of steps S1041, S1042 and S1043 is executed.

The purpose of the short-circuit protection method of this embodiment is to improve the temperature rise problem and the load capacity problem of the upper branch, and is divided into the following three modes:

(1) Light load mode: this corresponds to step S1043, that is, when the first load threshold voltage is <the output voltage≤power rail voltage, the current flowing in the upper branch is determined by the driving load of the bus driver, this mode Under the load, the load is small, the output voltage of the bus driver output port is large, and nodes A and B can provide sufficient differential driving voltage, so the current flowing in the upper branch can be determined by the driving load of the bus driver;

(2) Heavy-load mode: this corresponds to step S1042, that is, the first short-circuit threshold voltage < the output voltage ≤ the first on-load threshold voltage, and the current flowing in the upper branch is injected into the upper branch by the second The preset current is determined. In this mode, the load is large, the output voltage of the bus driver output port is reduced, and nodes A and B can no longer provide enough differential driving voltage. In this embodiment, the second preset is injected into the upper branch. current, so that the current flowing in the upper branch is determined by the injected second preset current, which not only ensures that the bus driver driver stage has sufficient ability to drive resistive loads and capacitive loads, but also drives the current of the upper branch of the stage. limited to a controllable range;

(3) Short-circuit mode: this corresponds to step S1041, that is, the output voltage ≤ the first short-circuit threshold voltage, and the current flowing in the upper branch is determined by the first preset current injected into the upper branch. In this mode , the load is further increased, or the output port of the bus driver is abnormally short-circuited, resulting in a lower output voltage of the output port of the bus driver. In this embodiment, the first preset current is injected into the upper branch, so that the current flowing in the upper branch It is determined by the injected first preset current, and the first preset current is smaller than the second preset current, so that the current flowing through the upper branch of the bus driver in the short-circuit state is limited to a lower level, and the reliability of the bus driver is improved. .

It can be seen from the above analysis that in this embodiment, when the upper branch is overloaded or short-circuited, the current flowing in the upper branch is reasonably limited by the internally generated reference currents of different sizes, which can not only control the temperature rise of the bus driver, but also control the temperature rise of the bus driver. The reliability of the bus driver is improved, and the decoupling between the differential output voltage and the short-circuit current of the bus driver is achieved compared with the control strategy of reducing the number of switches connected in parallel in the prior art, so that the two no longer interact with each other. Therefore, there is no disadvantage that the current value of the upper branch is required to be very low for short-circuit recovery when electrified, and the load-carrying capability of the bus driver is improved within a wide range of positive and negative common-mode output voltages.

Further, when step S101 is performed, whether the upper branch is turned on is determined by the level of the gate driving signal of the switch transistor in the upper branch.

Since the switch tube of the upper branch needs a driving signal to control its turn-on and turn-off, in this embodiment, when judging whether the upper branch is turned on, the upper branch is judged by the level of the gate drive signal of the switch in the upper branch. whether it is turned on or not, thus avoiding the need to add additional detection steps.

Second Embodiment

FIG. 4 is a flowchart of a short-circuit protection method provided by a second embodiment of the present invention. Please refer to FIG. 4. The short-circuit protection method of this embodiment is applied to the bus driver in FIG. 1 and FIG. 2. The bus driver includes an upper branch and a In the lower branch, the switch tube in the upper branch is a PMOS tube, and the switch tube in the lower branch is an NMOS tube. When the bus driver is working normally, only one of the upper branch and the lower branch is turned on. Short circuit protection method It includes the following steps:

S201: determine whether the lower branch is turned on;

When the judgment result is that the lower branch is turned on, the following steps are further performed:

S2021: Compare the output voltage of the output port of the bus driver with the second short-circuit threshold voltage to obtain a second short-circuit comparison result;

S2022: Compare the output voltage with the second on-load threshold voltage to obtain a second on-load comparison result;

S203: Control the magnitude of the current flowing in the lower branch according to the second short-circuit comparison result and the second on-load comparison result, and the control logic is as follows:

S2041: when 0≤the output voltage≤the second load threshold voltage, the current flowing in the lower branch is determined by the driving load of the bus driver;

S2042: When the second on-load threshold voltage<the output voltage≤the second short-circuit threshold voltage, the current flowing in the lower branch is determined by the third preset current injected into the lower branch;

S2043: when the second short-circuit threshold voltage < the output voltage, the current flowing in the lower branch is determined by the fourth preset current injected into the lower branch;

The third preset current>the fourth preset current.

Wherein, steps S2021 and S2022 are performed synchronously, and steps S2041, S2042 and S2043 are one of the specific situations of step S203, that is, when step 203 is specifically executed, only one of steps S2041, S2042 and S2043 is executed.

The purpose of the short-circuit protection method of the present embodiment is to improve the temperature rise problem and the load capacity problem of the lower branch, and is divided into the following three modes:

(1) Light load mode: this corresponds to step S2041, that is, when 0≤the output voltage≤the second load threshold voltage, the current flowing in the lower branch is determined by the driving load of the bus driver. In this mode, the load Small, the output voltage of the bus driver output port is small, the nodes CAN-H and CAN-L can provide enough differential driving voltage, so the current flowing in the lower branch can be determined by the driving load of the bus driver;

(2) Overload mode: this corresponds to step S2042, that is, when the second on-load threshold voltage < the output voltage ≤ the second short-circuit threshold voltage, the current flowing in the lower branch is injected into the lower branch by the third The preset current determines that in this mode, the load is large, the output voltage of the bus driver output port increases, and the nodes CAN-H and CAN-L can no longer provide enough differential driving voltage. The third preset current makes the current flowing in the lower branch determined by the injected third preset current, which not only ensures that the bus driver driver stage has sufficient ability to drive resistive loads and capacitive loads, but also lowers the driver stage. The current of the branch is limited within a controllable range;

(3) Short-circuit mode: At this time, corresponding to step S2043, that is, when the second short-circuit threshold voltage < the output voltage, the current flowing in the lower branch is determined by the fourth preset current injected into the lower branch. In this mode , the load is further increased, or the output port of the bus driver is abnormally short-circuited, resulting in a higher output voltage of the output port of the bus driver. In this embodiment, a fourth preset current is injected into the lower branch, so that the current flowing in the lower branch is The injected fourth preset current is determined, and the third preset current is greater than the fourth preset current, so that the current flowing through the branch of the bus driver in the short-circuit state is limited to a lower level, thereby improving the reliability of the bus driver.

It can be seen from the above analysis that in this embodiment, when the lower branch is overloaded or short-circuited, the current flowing in the lower branch is reasonably limited by the internally generated reference currents of different sizes, which can not only control the temperature rise of the bus driver, but also improve the The reliability of the bus driver is also compared with the control strategy of reducing the number of switches connected in parallel in the prior art, which realizes the decoupling between the differential output voltage of the bus driver and the short-circuit current, so that the two no longer restrict each other. , so that there is no short-circuit recovery requirement in the case of electrification that the current value of the lower branch is very low, and the load-carrying capability of the bus driver is improved within a wide range of positive and negative common-mode output voltages.

Further, when step S201 is performed, whether the lower branch is turned on is determined by the level of the gate driving signal of the switch transistor in the lower branch.

Since the switch tube of the lower branch needs a driving signal to control its turn-on and turn-off, in this embodiment, when judging whether the lower branch is turned on, the level of the gate drive signal of the switch tube in the lower branch is used to judge whether the lower branch is turned on or not. pass through, thus avoiding the need to add additional detection steps.

Third Embodiment

FIG. 5 is a flowchart of a short-circuit protection method provided by a third embodiment of the present invention. Please refer to FIG. 5 . The short-circuit protection method of this embodiment combines the method of the first embodiment and the method of the second embodiment.

It is easy to understand that the purpose of the short-circuit protection method in this embodiment is to simultaneously improve the temperature rise problem and the load capacity problem of the upper branch and the lower branch. In this embodiment, step S101 and step S201 are performed synchronously. At the same time, only one of the upper branch and the lower branch is turned on, so at the same moment, only one of the judgment results of step S101 and step S201 is "yes", and the step of judging "yes" will continue to be executed other steps after this step. When the judgment result judged in step S101 is "Yes", it includes three working modes, which are the same as the first embodiment, so they will not be repeated; when the judgment result judged in step S201 is "Yes", It includes three working modes, which are the same as those in the second embodiment, and will not be described again.

In this embodiment, whether the upper branch is overloaded or short-circuited, or the lower branch is overloaded or short-circuited, the current flowing in the corresponding branch will be reasonably limited by the internally generated reference currents of different sizes, so that not only can The temperature rise of the bus driver is controlled, the reliability of the bus driver is improved, and the difference between the differential output voltage of the bus driver and the short-circuit current is realized compared with the control strategy of reducing the number of connected upper switches or lower switches in parallel in the prior art. The decoupling between the two makes the two no longer restrict each other, so that there is no short-circuit recovery requirement when the current value of the corresponding branch is very low, and the load capacity of the bus driver is improved within a wide range of positive and negative common mode output voltages. .

Fourth Embodiment

FIG. 6 is a schematic block diagram of a short-circuit protection circuit provided by a fourth embodiment of the present invention. Please refer to FIG. 6. The short-circuit protection circuit of this embodiment is applied to the bus driver in FIG. 1 and FIG. 2. The bus driver includes an upper branch and a The lower branch; the switch tube 106 in the upper branch is a PMOS transistor MP1, and the first anti-backflow unit 105 is a diode DP; the gate drive signal of the PMOS tube MP1 is GateP; the switch tube 206 in the lower branch is an NMOS transistor MN1 , the second anti-backflow unit 206 is a diode DN, and the gate drive signal of the NMOS transistor MN1 is GateN; when the bus driver works normally, only one of the upper branch and the lower branch is turned on, and the short-circuit protection circuit includes the first short-circuit protection unit;

The first short-circuit protection unit includes:

a first judging unit for judging whether the upper branch is turned on;

The first execution unit is configured to further perform the following actions when the judgment result of the first judgment unit is that the upper branch is turned on:

comparing the output voltage of the output port of the bus driver with the first short-circuit threshold voltage to obtain a first short-circuit comparison result;

comparing the output voltage with the first on-load threshold voltage to obtain a first on-load comparison result;

The magnitude of the current flowing in the upper branch is controlled according to the first short-circuit comparison result and the first on-load comparison result, and the control logic is as follows:

When the output voltage≤the first short-circuit threshold voltage, the current flowing in the upper branch is determined by the first preset current injected into the upper branch;

When the first short-circuit threshold voltage<the output voltage≤the first on-load threshold voltage, the current flowing in the upper branch is determined by the second preset current injected into the upper branch;

When the first load threshold voltage is less than the output voltage≤power rail voltage, the current flowing in the upper branch is determined by the driving load of the bus driver;

The first preset current < the second preset current.

It is easy to understand that the purpose of the short-circuit protection circuit in this embodiment is to improve the temperature rise problem and the load capacity problem of the upper branch. When the judgment result of the first judgment unit is "Yes", the first execution unit includes three kinds of work. These three working modes are the same as those of the first embodiment, and the beneficial effects brought by them are also the same, so they will not be described in detail.

Further, the first judging unit judges whether the upper branch is turned on according to the level of the gate driving signal of the switch tube in the upper branch, thereby avoiding the need to add an additional detection unit.

Fifth Embodiment

FIG. 7 is a schematic diagram of the application of the short-circuit protection circuit provided in the fifth embodiment of the present invention in a bus driver. Please refer to FIG. 7. The short-circuit protection circuit of this embodiment is applied to the bus driver in FIG. 1 and FIG. 2. The bus driver It includes an upper branch and a lower branch; the switch tube 106 in the upper branch is a PMOS tube MP1, and the first anti-backflow unit 105 is a diode DP; the gate drive signal of the PMOS tube MP1 is GateP; the switch tube in the lower branch 206 is an NMOS transistor MN1, the second anti-backflow unit 206 is a diode DN, and the gate drive signal of the NMOS transistor MN1 is GateN; when the bus driver is working normally, only one of the upper branch and the lower branch is turned on, short circuit protection The circuit includes:

The first comparator 101, the positive-phase input terminal of the first comparator 101 is used to connect to the output port OUT of the bus driver, and the negative-phase input terminal is used to input the first short-circuit threshold voltage Vthp; the set terminal of the first comparator 101 is used to The gate drive signal GateP of the switch tube in the upper branch is input to determine whether the upper branch is turned on; when the gate drive signal GateP of the switch tube in the upper branch is at a high level, the output end of the first comparator 101 is Set to a high level; when the gate drive signal GateP of the switch in the upper branch is a low level, the output end of the first comparator 101 outputs the first short-circuit comparison result;

The first delay unit 102, the input end of the first delay unit 102 is used to receive the level of the output end of the first comparator 101, when the level of the output end of the first comparator 101 is high, the first delay unit 102 uses In order to shape and transmit the high level, its output terminal outputs the corresponding high level; when the output terminal level of the first comparator 101 is low level, the first delay unit 102 is used to pass the first delay time. The low level is output by its output terminal after time;

The first voltage-controlled current unit 103, the control terminal of the first voltage-controlled current unit is connected to the output terminal of the first delay unit 102, when the control terminal of the first voltage-controlled current unit 103 receives a high level, the first voltage-controlled current unit The output terminal of 103 outputs a first constant current; when the control terminal of the first voltage-controlled current unit 103 receives a low level, the output terminal of the first voltage-controlled current unit 103 outputs a second constant current, the first constant current > the second constant current;

The first current proportional unit 104, the first current proportional unit 104 includes a PMOS transistor MP2 and a PMS transistor MP3, the source of the PMOS transistor MP2 and the source of the PMS transistor MP3 are connected together to connect the power rail, and the drain of the PMOS transistor MP2 The gate of the PMOS transistor MP2 and the gate of the PMOS transistor MP3 are connected together and then connected to the output end of the first voltage-controlled current unit 103. The drain of the PMOS transistor MP3 is used to connect the anode of the anti-backflow diode DP of the upper branch. .

It should be noted that the PMOS transistor MP2 and the PMS transistor MP3 are low-voltage PMOS transistors, and the PMOS transistor MP2 and the PMS transistor MP3 form the connection mode of the current mirror with a ratio of width to length of 1:m (m is a suitable natural number). When the upper branch is turned on: when the PMOS tube MP3 is working in the linear region, the current flowing through the PMOS tube MP3 is determined by the driving load; when the PMOS tube MP3 is working in the saturation region, the current flowing through the PMOS tube MP3 is determined by the PMOS tube. The current value of the tube MP3 is determined by mirroring the PMOS tube MP2.

FIG. 8 is a schematic diagram of the application of the short-circuit protection circuit provided in the fifth embodiment of the present invention in a bus driver. This diagram provides a specific circuit for all the units in FIG. 7, please refer to FIG. 8:

The first delay unit 102 includes: a PMOS transistor MP4, an NMOS transistor MN4, a capacitor C1 and a Schmitt inverter SMT1; the gate of the PMOS transistor MP4 and the gate of the NMOS transistor MN4 are connected together as a first delay unit The input terminal of 102, the source of the PMOS transistor MP4 is used to connect the power rail, the drain of the PMOS transistor MP4, the drain of the NMOS transistor MN4, one end of the capacitor C1 and the input terminal of the Schmitt inverter SMT1 are connected together, NMOS The source of the tube MN4 and the other end of the capacitor C1 are connected together for grounding, and the output end of the Schmitt inverter SMT1 is used as the output end of the first delay unit 102 .

The first voltage-controlled current unit 103 includes: a switch S1, a first reference current IP1 and a second reference current IP2; the control end of the switch S1 serves as the control end of the first voltage-controlled current unit 103, and one end of the switch S1 It is connected with one end of the second reference current IP2 as the output end of the first voltage-controlled current unit 103, the other end of the switch S1 is connected to one end of the first reference current IP1, and the other end of the first reference current IP1 is used for input The other end of the first reference current signal and the second reference current IP2 is used to input the second reference current signal.

It should be noted that the current sizes of the first reference current IP1 and the second reference current IP2 can be selected according to the requirements of the bus driver’s driving capability during normal operation and the current limit value set in the short-circuit state, and the first reference current IP1 and the second reference current IP2 are provided upward by the reference current sink.

In this embodiment, the gate voltage of the PMOS transistor MP2 and the gate voltage VGP of the PMOS transistor MP3 are determined by the output current of the first voltage control current unit 103, the power rail voltage VCC is a fixed value, and the output of the bus driver output port The voltage VOUT is a changing value.

The condition for PMOS transistor MP2 and PMOS transistor MP3 to work in the saturation region is |Vds|>|Vgs|-|Vth|, where Vgs is the gate-source voltage of the MOS transistor, Vds is the drain-source voltage of the MOS transistor, and Vth is the MOS transistor The threshold voltage of the tube, all three are negative.

Among them, the PMOS tube MP2 is used as the input tube of the current mirror, and its gate and drain are short-circuited. At this time, |Vds|=|Vgs|, so it will always satisfy |Vds|>|Vgs|-|Vth|, and the PMOS tube MP2 always works at saturation region.

The PMOS tube MP2 is used as the output tube of the current mirror, and the PMOS tube MP3 also works in the saturation region, which is a necessary condition for mirroring the current from the PMOS tube MP2. At this time, (VCC-VDMP3)>(VCC-VGP-|Vth MP3|) , after simplifying the formula, there is VGP>VDMP3-|VthMP3|, where VDMP3 is the drain voltage of the PMOS transistor MP3, and VthMP3 is its threshold voltage. Since VDMP3=VDP+|VDSMP1|+VOUT, where VDP is the forward direction of the diode DP Pass voltage drop, VDSMP1 is the drain-source voltage drop of PMOS transistor MP1, substitute into the above formula VGP>VDMP3-|VthMP3|: VOUT<VGP-VDP-|VDSMP1+|VthMP3|, that is, when VOUT<VGP-VDP- When |VDSMP1+|VthMP3|, the PMOS tube MP3 works in the saturation region, and VGP, VDP, |VDSMP1| and |VthMP3| are all fixed values. Therefore, by designing the values of VGP, VDP, |VDSMP1| and |Vth|, the PMOS can be designed The threshold value of the working state of the tube MP3 entering the saturation region from the linear region is VGP-VDP-|VDSMP1+|VthMP3|.

It can be seen from the above analysis that the inventive concept of this embodiment is the same as that of the first and fourth embodiments. Since the working state of the PMOS transistor MP3 in this embodiment enters saturation from the linear region, it needs to satisfy that VOUT is less than the above-mentioned threshold VGP-VDP -|VDSMP1+|VthMP3|, the threshold can be regarded as the first load threshold voltage in the first embodiment and the fourth embodiment, so this embodiment utilizes the natural working characteristics of the PMOS transistor MP3 to realize the output voltage VOUT The function of comparing with the first on-load threshold voltage, obtaining the first on-load comparison result, and executing the relevant action according to the first on-load comparison result.

The purpose of the short-circuit protection circuit of this embodiment is to improve the temperature rise problem and the load capacity problem of the upper branch. The working principle of this embodiment will be analyzed below with reference to the circuit of FIG. 8 . In order to facilitate understanding, the following analysis regards the threshold VGP-VDP-|VDSMP1|+|VthMP3| as VGP directly. In actual circuit design, VGP can also be realized by designing |VthMP3|-VDP-|VDSMP1| to zero -VDP-|VDSMP1|+|VthMP3|=Effect of VGP. It is easy to understand that, when the output voltage VOUT of the bus driver does not take any short-circuit protection measures, as the load gradually increases, that is, the current flowing in the upper branch increases gradually, the bus driver in this embodiment will work in turn in the light mode. In load mode, heavy load mode and short-circuit mode, the output voltage VOUT of the output port of the bus driver will gradually decrease. In order to achieve the purpose of the invention of this embodiment, when the PMOS transistor MP3 of this embodiment works in the saturation region, the load current should be smaller than the bus driver. The current flowing in the upper branch when a short circuit occurs, so the corresponding threshold VGP should be smaller than the first short circuit protection threshold Vthp in design, that is, Vthp<VGP.

Based on the design conditions of the above thresholds, the present embodiment includes the following three modes:

(1) Light load mode: the load is small, and the output voltage VOUT of the output port of the bus driver is relatively large. When VGP<VOUT≤VCC, the positive-phase input terminal of the first comparator 101 is larger than the negative-phase input terminal, and the first comparator 101 The output high level is controlled by the first delay unit 102 to close the switch S1 of the first voltage-controlled current unit 103, so that the sum of the first reference current IP1 and the second reference current IP2 is selected to be provided to the first current proportional unit 104. The input terminal, but at this time because VOUT>VGP, the low-voltage PMOS transistor MP3 in the first current proportional unit 103 is in the linear region, and does not have the function of mirroring the current from the PMOS transistor MP2. At this time, the internal resistance of the PMOS transistor MP3 is low, and its The voltage drop lost between the source and drain is small, and the current flowing through the upper branch of the driver is completely determined by the load of the driver output;

(2) Heavy load mode: as the drive output load increases, the output voltage of the bus driver output port decreases. When Vthp<VOUT≤VGP, the positive phase input terminal of the first comparator 101 is still larger than the negative phase input terminal, and the first comparator 101 is still larger than the negative phase input terminal. The comparator 101 still outputs a high level, which is controlled by the first delay unit 102 to control the switch S1 of the first voltage-controlled current unit 103 to close, so that the sum of the first reference current IP1 and the second reference current IP2 is still selected It is provided to the input end of the first current proportional unit 104, but at this time because VOUT≤VGP, the low-voltage PMOS transistor MP3 in the first current proportional unit 103 begins to enter the saturation region, which can mirror the reference current on the PMOS transistor MP2, so the first The current proportional unit 103 can limit the current value flowing through the driving upper branch, which is (IP1+IP2) multiplied by the proportional value m between the low-voltage PMOSs designed by the first current proportional unit 103, that is, (IP1+IP2)*m, Ensure that the driver stage in the bus driver has the ability to drive resistive and capacitive loads, while limiting the current in the upper branch to a controllable range;

(3) Short-circuit mode: as the drive output load further increases, or the port is abnormally short-circuited, resulting in lower VOUT, when VOUT≤Vthp, the first comparator 101 will output a low level to the first delay unit 102, the first The PMOS transistor MP4 in the delay unit 102 is turned on, and the power rail charges the capacitor C1 through the PMOS transistor MP4 until the voltage drop on the capacitor C1 reaches the flip point of the Schmitt inverter SMT1, that is, after a set delay time, Then output a low level to control the switch S1 in the first voltage control current unit 103 to turn off, and only select the second reference current IP2 to provide it to the first current proportional unit 104. At this time, VOUT is very low, and the first current proportional unit 104 The low-voltage PMOS transistor MP3 in the middle is in the saturation region, and the current mirror formed by the PMOS transistor MP2 maintains a mirror effect. At this time, the first current proportional unit 104 limits the current value flowing through the upper branch to the second reference current IP2 multiplied by the first current. The proportional value m between the low-voltage PMOSs designed by the proportional unit 104, ie IP2*m, makes the current of the upper branch of the bus driver be limited to a lower level in a short-circuit state, thereby improving the reliability of the bus driver.

The inventive concept of this embodiment is the same as that of the first and fourth embodiments. When the upper branch is overloaded or short-circuited, the current flowing in the upper branch is generated by the first voltage-controlled current unit 103 of different magnitudes. Reasonably limited by the reference current (equivalent to the externally injected current in the first embodiment and the fourth embodiment), it can not only control the temperature rise of the bus driver, improve the reliability of the bus driver, but also reduce the parallel connection compared with the prior art. In terms of the control strategy of the number of conduction of the upper switch tube, the decoupling between the differential output voltage of the bus driver and the short-circuit current is realized, so that the two no longer restrict each other, so that there is no current value of the upper branch required for short-circuit recovery when electrified Very low disadvantage, improving the load capacity of the bus driver over a wide range of positive and negative common-mode output voltages.

Sixth Embodiment

FIG. 9 is a schematic diagram of the application of the short-circuit protection circuit provided in the sixth embodiment of the present invention in a bus driver. Please refer to FIG. 9. The short-circuit protection circuit of this embodiment is applied to the bus driver in FIG. 1 and FIG. 2. The bus driver It includes an upper branch and a lower branch; the switch tube 106 in the upper branch is a PMOS tube MP1, and the first anti-backflow unit 105 is a diode DP; the gate drive signal of the PMOS tube MP1 is GateP; the switch tube in the lower branch 206 is an NMOS transistor MN1, the second anti-backflow unit 206 is a diode DN, and the gate drive signal of the NMOS transistor MN1 is GateN; when the bus driver is working normally, only one of the upper branch and the lower branch is turned on, short circuit protection The second short circuit protection unit of the circuit;

The second short-circuit protection unit includes:

a second judging unit, configured to judge whether the lower branch is turned on;

The second execution unit is configured to further perform the following actions when the judgment result of the second judgment unit is that the lower branch is turned on:

comparing the output voltage of the output port of the bus driver with the second short-circuit threshold voltage to obtain a second short-circuit comparison result;

comparing the output voltage with the second on-load threshold voltage to obtain a second on-load comparison result;

The magnitude of the current flowing in the lower branch is controlled according to the second short-circuit comparison result and the second on-load comparison result, and the control logic is as follows:

When 0≤the output voltage≤the second load threshold voltage, the current flowing in the lower branch is determined by the driving load of the bus driver;

When the second on-load threshold voltage<the output voltage≤the second short-circuit threshold voltage, the current flowing in the lower branch is determined by the third preset current injected into the lower branch;

When the second short-circuit threshold voltage < the output voltage, the current flowing in the lower branch is determined by the fourth preset current injected into the lower branch;

The third preset current>the fourth preset current.

It is easy to understand that the purpose of the short-circuit protection circuit in this embodiment is to improve the temperature rise problem and the load capacity problem of the lower branch. When the judgment result of the second judgment unit is "Yes", the second execution unit includes three kinds of work. These three working modes are the same as those of the second embodiment, and the beneficial effects brought by them are also the same, so they will not be repeated.

Further, the second judging unit judges whether the lower branch is turned on according to the level of the gate driving signal of the switch tube in the lower branch, thereby avoiding the need to add an additional detection unit.

Seventh Embodiment

10 is a schematic diagram of the application of the short-circuit protection circuit provided in the seventh embodiment of the present invention in a bus driver. Please refer to FIG. 7 . The short-circuit protection circuit of this embodiment is applied to the bus driver in FIG. 1 and FIG. 2 . It includes an upper branch and a lower branch; the switch tube 106 in the upper branch is a PMOS tube MP1, and the first anti-backflow unit 105 is a diode DP; the gate drive signal of the PMOS tube MP1 is GateP; the switch tube in the lower branch 206 is an NMOS transistor MN1, the second anti-backflow unit 206 is a diode DN, and the gate drive signal of the NMOS transistor MN1 is GateN; when the bus driver is working normally, only one of the upper branch and the lower branch is turned on, short circuit protection The circuit includes:

The second comparator 201, the positive-phase input terminal of the second comparator 201 is used to input the second short-circuit threshold voltage Vthn, the negative-phase input terminal is used to input the output voltage of the output port of the bus driver; the set terminal of the second comparator 201 is used for The gate drive signal GateN of the switch tube in the lower branch is input to determine whether the lower branch is turned on; when the gate drive signal GateN of the switch tube in the lower branch is at a low level, the output end of the second comparator 201 is Set to a high level; when the gate drive signal GateN of the switch tube in the upper branch is a high level, the output end of the second comparator 201 outputs the second short-circuit comparison result;

In the second delay unit 202, the input terminal of the second delay unit 202 is used to receive the level of the output terminal of the second comparator 201. When the level of the output terminal of the second comparator 201 is high, the second delay unit 202 uses In order to shape and transmit the high level, its output terminal outputs the corresponding high level; when the output terminal level of the second comparator 201 is low level, the second delay unit 202 is used to pass the second delay time. The low level is output by its output terminal after time;

The second voltage-controlled current unit 203, the control terminal of the second voltage-controlled current unit 203 is connected to the output terminal of the second delay unit 202, when the control terminal of the second voltage-controlled current unit 203 receives a high level, the second voltage-controlled current unit 203 The output terminal of the unit 203 outputs a third constant current; when the control terminal of the second voltage-controlled current unit 203 receives a low level, the output terminal of the second voltage-controlled current unit 203 outputs a fourth constant current, the third constant current > the third constant current Four constant currents;

The second current proportional unit 204, the second current proportional unit 204 includes an NMOS transistor MN2 and an NMOS transistor MN3, the source of the NMOS transistor MN2 and the source of the NMS transistor MN3 are connected together for grounding, and the drain of the NMOS transistor MN2, The gate of the NMOS transistor MN2 and the gate of the NMS transistor MN3 are connected together and then connected to the output terminal of the second voltage-controlled current unit 203. The drain of the NMOS transistor MN3 is used to connect to the source of the NMOS transistor of the lower branch.

It should be noted that the NMOS transistor MN2 and the NMOS transistor are low-voltage NMOS transistors, and the NMOS transistor MN2 and the NMOS transistor form the connection mode of the current mirror with a ratio of width to length of 1:n (n is a suitable natural number). When the lower branch is turned on: when the NMOS transistor MN3 is operating in the linear region, the current flowing through the NMOS transistor MN3 is determined by the driving load; when the NMOS transistor MN3 is operating in the saturation region, the current flowing through the NMOS transistor MN3 is determined by the NMOS transistor. The transistor MN3 is determined by the current value mirrored from the NMOS transistor MN2.

FIG. 11 is a schematic diagram of the application of the short-circuit protection circuit provided in the fifth embodiment of the present invention in a bus driver. This diagram provides a specific circuit for all the units in FIG. 10, please refer to FIG. 11:

The second delay unit 202 includes: a PMOS transistor MP5, an NMOS transistor MN5, a capacitor C2 and a Schmitt inverter SMT2; the gate of the PMOS transistor MP5 and the gate of the NMOS transistor MN5 are connected together as a second delay unit The input end of the PMOS tube MP5 is used to connect the power rail, the drain of the PMOS tube MP5, the drain of the NMOS tube MN5, one end of the capacitor C2 and the input end of the Schmitt inverter SMT2 are connected together, the NMOS tube The source of the MN5 and the other end of the capacitor C2 are connected together for grounding, and the output end of the Schmitt inverter SMT2 is used as the output end of the second delay unit 202 .

The second voltage-controlled current unit includes: a switch tube S2, a third reference current IN1 and a fourth reference current IN2; the control end of the switch tube S2 serves as the control end of the second voltage-controlled current unit 203, and one end of the switch tube S2 and One end of the fourth reference current IN2 is connected together as the output end of the second voltage-controlled current unit 203, the other end of the switch S2 is connected to one end of the third reference current IN1, and the other end of the third reference current IN1 is used to input the first Three reference current signals, the other end of the fourth reference current IN2 is used to input the fourth reference current signal.

It should be noted that the current sizes of the third reference current IN1 and the fourth reference current IN2 can be selected according to the requirements of the bus driver’s driving capability during normal operation and the current limit value set in the short-circuit state, and the third reference current IN1 and the fourth reference current IN2 are provided downward by the reference current source.

In this embodiment, the gate voltage of the NMOS transistor MN2 and the gate voltage VGN of the NMOS transistor MN3 are determined by the output current of the second voltage control current unit 203, the power rail voltage VCC is a fixed value, and the output of the bus driver output port The voltage VOUT is a changing value.

The condition for NMOS transistor MN2 and NMOS transistor MN3 to work in the saturation region is Vds>Vgs-Vth, where Vgs is the gate-source voltage of the MOS transistor, Vds is the drain-source voltage of the MOS transistor, and Vth is the threshold voltage of the MOS transistor. Both are positive values.

The NMOS transistor MN2 is used as the input transistor of the current mirror, and its gate and drain are short-circuited. At this time, Vds=Vgs, so Vds>Vgs-Vth is always satisfied, and the NMOS transistor MN2 always works in the saturation region.

Among them, the NMOS transistor MN2 is used as the output tube of the current mirror, and the NMOS transistor MN3 also works in the saturation region, which is a necessary condition for mirroring the current from the NMOS transistor MN2. At this time, VDMN3>VGN-VthMN3, where VDMP3 is the drain voltage of the NMOS transistor MN3. , VthMN3 is the threshold voltage of the NMOS transistor MN3, since VDMN3=VOUT-VDN-VDSMN1, where VDN is the forward voltage drop of the diode DN, and VDSMN1 is the drain-source voltage drop of the NMOS transistor MN1. Substitute into the above formula VDMN3>VGN -VthMN3 has: VOUT>

VGN+VDP+VDSMN1-VthMN3, that is, when VOUT>VGN+VDP+VDSMN1-VthMN3, NMOS transistor MN3 works in the saturation region, VGN, VDP, VDSMN1 and VthMN3 are all fixed values, so by designing VGN, VDP, VDSMN1 and The value of VthMN3 can design the threshold value of the working state of the NMOS transistor MN3 from the linear region to the saturation region, and the threshold value is VGN+VDP+VDSMN1-VthMN3.

It can be seen from the above analysis that the inventive concept of this embodiment is the same as that of the second and fifth embodiments. Since the working state of the NMOS transistor MN3 in this embodiment enters saturation from the linear region, it needs to satisfy that VOUT is greater than the above-mentioned threshold VGN+VDP The condition of +VDSMN1-VthMN3, the threshold can be regarded as the second load threshold voltage in the second embodiment and the fifth embodiment, so this embodiment uses the natural working characteristics of the NMOS transistor MN3 to realize the output voltage VOUT and the first A function of comparing two on-load threshold voltages, obtaining a second on-load comparison result, and performing related actions according to the second on-load comparison result.

The purpose of the short-circuit protection circuit in this embodiment is to improve the temperature rise problem and the load capacity problem of the lower branch. The working principle of this embodiment will be analyzed below with reference to the circuit in FIG. 11 . In order to facilitate understanding, the following analysis regards the threshold VGN+VDP+VDSMN1-VthMN3 as VGN directly. In the actual circuit design, VDP+VDSMN1-VthMN3 can be designed to be zero to achieve VGN+VDP+VDSMN1-VthMN3=VGN Effect. It is easy to understand that, when the output voltage VOUT of the bus driver does not take any short-circuit protection measures, as the load gradually increases, that is, the current flowing in the lower branch gradually increases, the bus driver in this embodiment will work in turn in the light mode. In load mode, heavy load mode and short-circuit mode, the output voltage VOUT of the output port of the bus driver will gradually increase. In order to achieve the purpose of the invention of this embodiment, when the NMOS transistor MN3 of this embodiment works in the saturation region, the load current should be greater than that of the bus driver. The current flowing in the branch circuit when a short circuit occurs, so the corresponding threshold value VGP should be greater than the second short circuit protection threshold value Vthn during design, that is, Vthn>VGN.

The purpose of the short-circuit protection circuit in this embodiment is to improve the temperature rise problem and the load capacity problem of the lower branch. The circuit in Fig. 11 is analyzed, including the following three modes:

(1) Light load mode: the load is small, the output voltage VOUT of the output port of the bus driver is small, when 0≤VOUT≤VGN, the negative phase input terminal of the second comparator 201 is smaller than the positive phase input terminal, and the second comparator 201 outputs The high level of the second delay unit 202 controls the switch S2 of the second voltage-controlled current unit 203 to close, so that the sum of the third reference current IP3 and the fourth reference current IN2 is selected to be provided to the input of the second current proportional unit 203 However, at this time, since VOUT≤VGN, the low-voltage NMOS transistor MN3 in the second current proportional unit 203 is in the linear region and does not have the function of mirroring the current from the NMOS transistor MN2. At this time, the internal resistance of the NMOS transistor MN3 is low, and its source The voltage drop lost between the drains is small, and the current flowing through the lower branch is completely determined by the load of the drive output;

(2) Heavy-duty mode: as the drive output load increases, the output voltage of the bus driver output port increases. When VGN<VOUT<Vthn, the negative-phase input terminal of the second comparator 201 is still smaller than the positive-phase input terminal, and the second comparator The controller 201 still outputs a high level, which is controlled by the second delay unit 202 to close the switch S2 of the second voltage-controlled current unit 203, so that the sum of the third reference current IP3 and the fourth reference current IN2 is still selected to provide To the input terminal of the second current proportional unit 203, but at this time because VOUT>VGN, the low-voltage NMOS transistor MN3 in the second current proportional unit enters the saturation region and can mirror the reference current on the NMOS transistor MN2, so the second current proportional unit 203 can limit the current value flowing through the lower branch, which is (IN1+IN2) multiplied by the ratio value n between the low-voltage PMOSs designed by the second current proportional unit 203, that is, (IN1+IN2)*n, to ensure that the bus driver is in the The driver stage has the ability to drive resistive loads and capacitive loads, while limiting the current of the lower branch of the driver stage within a controllable range;

(3) Short-circuit mode: as the drive output load further increases, or the port is abnormally short-circuited, VOUT is higher, at this time VOUT>Vthn, the second comparator 201 will output a low level to the second delay unit 202, the second In the delay unit 202, the PMOS transistor MP5 is turned on, and the power rail charges the capacitor C2 through the PMOS transistor MP5 until the voltage drop on the capacitor C2 reaches the inversion point of the Schmitt inverter SMT2, that is, after a set delay time, and then The output low level controls the switch S2 in the second voltage control current unit 203 to turn off, and only the fourth reference current IN2 is selected to be supplied to the second current proportional unit 204. At this time, VOUT is very high, VOUT remains greater than VGN, and the second The low-voltage NMOS transistor MN3 in the current proportional unit 203 is in the saturation region, and the current mirror formed by the NMOS transistor MN2 maintains a mirror effect. At this time, the second current proportional unit 203 limits the current value flowing through the lower branch, which is the fourth reference current IN2 multiplied by The ratio value n between the low-voltage NMOSs designed by the second current ratio unit, ie IN2*n, causes the current of the branch of the chip to be limited to a lower level in a short-circuit state, thereby improving the reliability of the bus driver.

The inventive concept of this embodiment is the same as that of the second and sixth embodiments, and is also a reference of different magnitudes generated by the second voltage-controlled current unit 203 for the current flowing in the lower branch when the lower branch is overloaded or short-circuited The reasonable limit of the current (equivalent to the externally injected current in the second embodiment and the sixth embodiment) can not only control the temperature rise of the bus driver, improve the reliability of the bus driver, but also reduce the number of parallel down switches compared with the prior art. In terms of the control strategy of the number of tube conduction, the decoupling between the differential output voltage of the bus driver and the short-circuit current is realized, so that the two no longer restrict each other, so that there is no need for short-circuit recovery when electrified. The current value of the lower branch is very low. The disadvantage is that the load capacity of the bus driver is improved over a wide range of positive and negative common-mode output voltages.

Eighth Embodiment

FIG. 12 is a schematic block diagram of the short circuit protection circuit provided by the fourth embodiment of the present invention. Referring to FIG. 12 , the short circuit protection circuit of this embodiment combines the circuit of the fourth embodiment and the circuit of the sixth embodiment.

It is easy to understand that the purpose of the short-circuit protection circuit in this embodiment is to improve the temperature rise problem and the load capacity problem of the upper branch at the same time. When the judgment result of the first judgment unit is "Yes", the first execution unit includes three kinds of Working mode, these three working modes are the same as the first embodiment and the fourth embodiment, and the beneficial effects are also the same, so they will not be repeated; when the judgment result of the second judgment unit is "Yes", the second execution The unit includes three working modes, and these three working modes are the same as those of the second embodiment and the sixth embodiment, and the beneficial effects brought by them are also the same, which will not be repeated.

In this embodiment, whether the upper branch is overloaded or short-circuited, or the lower branch is overloaded or short-circuited, the current flowing in the corresponding branch will be reasonable by the reference currents of different sizes generated by the corresponding voltage-controlled current unit. Therefore, it can not only control the temperature rise of the bus driver and improve the reliability of the bus driver, but also realize the differential output of the bus driver compared with the control strategy of reducing the number of connected upper switches or lower switches in parallel in the prior art. The decoupling between the voltage and the short-circuit current makes the two no longer restrict each other, so there is no disadvantage that the short-circuit recovery requires a very low current value of the corresponding branch when the power is on, and the bus is improved in the wide positive and negative common mode output voltage range. The load capacity of the drive.

Ninth Embodiment

13 is a schematic block diagram of the short-circuit protection circuit provided by the ninth embodiment of the present invention, and FIG. 14 is a schematic diagram of the application of the short-circuit protection circuit provided by the ninth embodiment of the present invention in a bus driver. All units provide specific circuits, please refer to FIG. 13 and FIG. 14 , the short-circuit protection circuit of this embodiment combines the circuit of the fifth embodiment and the circuit of the seventh embodiment.

It is easy to understand that the purpose of the short-circuit protection circuit in this embodiment is to improve the temperature rise problem and the load capacity problem of the upper branch at the same time. This embodiment includes three working modes when the upper branch is turned on. These three working modes It is the same as the fifth embodiment, and the beneficial effects are also the same, so it will not be repeated; when the lower branch is turned on, it includes three working modes, and these three working modes are the same as the seventh embodiment, and the beneficial effects brought by It is also the same, and I will not repeat it.

In this embodiment, a corresponding voltage-controlled current unit and a current proportional unit are respectively added to the upper branch and the lower branch of the main power of the driver stage in the bus driver, wherein the voltage-controlled current unit can output reference currents of different sizes, and the current proportional unit Designed as a current mirror, the low-voltage PMOS transistor MP3 and the low-voltage NMOS transistor MN3 in the current mirror are connected in series in the upper and lower branches of the main power of the driver stage in the bus driver, so that the driver stage can be designed with both low-voltage PMOS transistors. The on-resistance of MP3 and the low-voltage NMOS transistor MN3 is made low to enhance the load capacity of the driver stage and improve the differential voltage output by the bus nodes (A, B). The size configuration of the first reference current IP1 and the second reference current IP2, as well as the size configuration of the third reference current IN1 and the fourth reference current IN2), and set an appropriate mirror ratio for the current proportional unit (that is, the value of m and n Selected), the current of the driver stage of the bus driver before entering the short-circuit protection and after entering the short-circuit protection is reasonably limited, so as to control the short-circuit temperature rise of the bus driver and improve the reliability.

In this embodiment, whether the upper branch is overloaded or short-circuited, or the lower branch is overloaded or short-circuited, the current flowing in the corresponding branch will be reasonable by the reference currents of different sizes generated by the corresponding voltage-controlled current unit. Therefore, it can not only control the temperature rise of the bus driver and improve the reliability of the bus driver, but also realize the differential output of the bus driver compared with the control strategy of reducing the number of connected upper switches or lower switches in parallel in the prior art. The decoupling between the voltage and the short-circuit current makes the two no longer restrict each other, so there is no short-circuit recovery when the current is charged, and the current value of the corresponding branch is very low, so that the output of the bus driver is disconnected in the wide positive and negative common mode. The load capacity is improved within the output voltage range.

Tenth Embodiment

This embodiment provides a bus driver, which includes the short-circuit protection circuit according to any one of the fourth embodiment to the ninth embodiment. For the connection relationship between the short-circuit protection circuit and the bus driver, please refer to the drawings corresponding to each embodiment.

In this embodiment, the switch tube 106 in the upper branch is a high-voltage P power MOS tube, and the switch tube 206 in the lower branch is a high-voltage N power MOS tube; the first anti-backflow unit 105 and the second anti-backflow unit 205 can be respectively Choose a conventional diode, or a Schottky diode, or one of the MOS tubes connected in a diode connection.

When the short-circuit protection circuit adopted in this embodiment includes the low-voltage PMOS transistor MP3 and the low-voltage NMOS transistor MN3 in the related drawings, since the low-voltage PMOS transistor MP3 and the low-voltage NMOS transistor MN3 are also connected in series on the main power branch of the bus driver driver stage, The maximum current flowing is generally at the level of 100mA. Under normal load conditions, in order to pursue low voltage drop loss, the linear resistance of both the PMOS transistor MP3 and the NMOS transistor MN3 should not be too large, that is, the size should not be too small. At the same time, in the short-circuit state, in order to ensure the matching accuracy of the PMOS transistor MP3 and the PMOS transistor MP2, the NMOS transistor MN3 and the NMOS transistor MN2 in the saturation region, when the size of the PMOS transistor MP3 is m times the size of the PMOS transistor MP2, the NMOS transistor MN3 The size is n times that of the NMOS transistor MN2, and the size of the PMOS transistor MP2 and NMOS transistor MN2 should not be too small, otherwise the current matching accuracy will be deteriorated due to the boundary effect of the device parameters caused by the too small size, so the multiples m and n should not be too large. , it is recommended to be up and down 100 times (such as 200uA: 200mA).

FIG. 15 is a schematic diagram of the control voltage and output port waveforms for driving the upper branch switch tube and driving the lower branch switch tube in the bus driver of the present embodiment, when the upper branch switch tube and the lower branch switch tube are in normal working state , when each pulse is output, the initial value of the level VOUT of the drive port OUT always satisfies VOUT>Vthn or VOUT<Vthp, the first comparator or the second comparator will determine a short circuit, considering that the transmission rate is the driving circuit. A key indicator, so the fifth embodiment, the seventh embodiment and the ninth embodiment design the corresponding delay unit to avoid entering the short-circuit state by mistake, and the corresponding voltage-controlled current unit will immediately select a small reference current to provide the current to the current. Proportional unit, the current proportional unit will limit the current value flowing through the driving branch to the small reference current multiplied by the proportional value of the current proportional unit, namely IP2*m or IN2*n, which will slow down the rise and fall time of the power tube The first half of tr and tf, i.e. tp and tn in the figure.

It should be noted that the design of the delay time of the delay unit should ensure that the switching parameter indicators tr and tf under the required maximum transmission rate are not affected, that is, the transmission delay tdp>tr of the first delay unit is designed, and the transmission delay tdn of the second delay unit is designed. >tf.

Since the short-circuit protection circuit described in any one of the fourth to ninth embodiments is added to the bus driver of this embodiment, whether the upper branch is overloaded or short-circuited, or the lower branch is overloaded or short-circuited, the corresponding The current flowing in the branch will be reasonably limited, so that it can not only control the temperature rise of the bus driver, improve the reliability of the bus driver, but also reduce the number of on-off switches of the upper or lower switches in parallel compared with the prior art. In terms of strategy, the decoupling between the differential output voltage of the bus driver and the short-circuit current is realized, so that the two no longer restrict each other, so that there is no short-circuit recovery when electrified. The output disconnect improves load carrying capability over a wide positive and negative common mode output voltage range.

Those skilled in the art will also appreciate that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the embodiments herein may be implemented as electronic hardware, computer software, or combinations thereof. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether this functionality is implemented as hardware or software depends on the specific application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, however, such implementation decisions should not be interpreted as a departure from the scope of the present disclosure.

Claims (24)

1. A short-circuit protection method is applied to a bus driver, the bus driver comprises an upper branch circuit and a lower branch circuit, a switch tube in the upper branch circuit is a PMOS tube, a switch tube in the lower branch circuit is an NMOS tube, and only one of the upper branch circuit and the lower branch circuit is conducted when the bus driver works normally, the short-circuit protection method is characterized by comprising the following steps:

judging whether the upper branch is conducted or not;

when the judgment result is that the upper branch is conducted, the following steps are further executed:

comparing the output voltage of the output port of the bus driver with a first short-circuit threshold voltage to obtain a first short-circuit comparison result;

comparing the output voltage with a first on-load threshold voltage to obtain a first on-load comparison result;

controlling the current flowing in the upper branch according to the first short circuit comparison result and the first load comparison result, wherein the control logic is as follows:

when the output voltage is less than or equal to the first short-circuit threshold voltage, the current flowing in the upper branch is determined by a first preset current injected into the upper branch;

when the first short-circuit threshold voltage is less than the output voltage and less than or equal to the first loaded threshold voltage, the current flowing in the upper branch is determined by a second preset current injected into the upper branch;

when the first on-load threshold voltage is less than the output voltage and less than or equal to the power supply rail voltage, the current flowing in the upper branch is determined by the driving load of the bus driver;

the first preset current is less than the second preset current.

2. The short-circuit protection method according to claim 1, wherein: and judging whether the upper branch is conducted or not according to the high and low of the grid driving signal of the switching tube in the upper branch.

3. A short-circuit protection method is applied to a bus driver, the bus driver comprises an upper branch circuit and a lower branch circuit, a switch tube in the upper branch circuit is a PMOS tube, a switch tube in the lower branch circuit is an NMOS tube, and only one of the upper branch circuit and the lower branch circuit is conducted when the bus driver works normally, the short-circuit protection method is characterized by comprising the following steps:

judging whether the lower branch is conducted or not;

when the judgment result is that the lower branch is conducted, the following steps are further executed:

comparing the output voltage of the output port of the bus driver with a second short-circuit threshold voltage to obtain a second short-circuit comparison result;

comparing the output voltage with a second on-load threshold voltage to obtain a second on-load comparison result;

controlling the current flowing in the lower branch according to the second short circuit comparison result and the second on-load comparison result, wherein the control logic is as follows:

when the output voltage is not less than 0 and not more than the second loading threshold voltage, the current flowing in the lower branch is determined by the driving load of the bus driver;

when the second on-load threshold voltage is smaller than the output voltage and smaller than or equal to the second short-circuit threshold voltage, the current flowing in the lower branch is determined by a third preset current injected into the lower branch;

when the second short-circuit threshold voltage is less than the output voltage, the current flowing in the lower branch is determined by a fourth preset current injected into the lower branch;

the third preset current is larger than the fourth preset current.

4. The short-circuit protection method according to claim 3, wherein: and judging whether the lower branch is conducted or not according to the high and low of the grid driving signal of the switching tube in the lower branch.

5. A short-circuit protection method is applied to a bus driver, the bus driver comprises an upper branch circuit and a lower branch circuit, a switch tube in the upper branch circuit is a PMOS tube, a switch tube in the lower branch circuit is an NMOS tube, and only one of the upper branch circuit and the lower branch circuit is conducted when the bus driver works normally, the short-circuit protection method is characterized by comprising the following steps:

judging whether the upper branch is conducted or not;

when the judgment result is that the upper branch is conducted, the following steps are further executed:

comparing the output voltage of the output port of the bus driver with a first short-circuit threshold voltage to obtain a first short-circuit comparison result;

comparing the output voltage with a first on-load threshold voltage to obtain a first on-load comparison result;

controlling the current flowing in the upper branch according to the first short circuit comparison result and the first load comparison result, wherein the control logic is as follows:

when the output voltage is less than or equal to the first short-circuit threshold voltage, the current flowing in the upper branch is determined by a first preset current injected into the upper branch;

when the first short-circuit threshold voltage is smaller than the output voltage and smaller than or equal to the first loaded threshold voltage, the current flowing in the upper branch is determined by a second preset current injected into the upper branch;

when the first loaded threshold voltage is less than the output voltage and less than or equal to the power supply rail voltage, the current flowing in the upper branch is determined by the driving load of the bus driver;

judging whether the lower branch is conducted or not;

when the judgment result is that the lower branch is conducted, the following steps are further executed:

comparing the output voltage of the output port of the bus driver with a second short-circuit threshold voltage to obtain a second short-circuit comparison result;

comparing the output voltage with a second on-load threshold voltage to obtain a second on-load comparison result;

controlling the current flowing in the lower branch according to the second short circuit comparison result and the second on-load comparison result, wherein the control logic is as follows:

when the output voltage is not less than 0 and not more than the second on-load threshold voltage, the current flowing in the lower branch is determined by the driving load of the bus driver;

when the second on-load threshold voltage is smaller than the output voltage and smaller than or equal to the second short-circuit threshold voltage, the current flowing in the lower branch is determined by a third preset current injected into the lower branch;

when the second short-circuit threshold voltage is less than the output voltage, the current flowing in the lower branch is determined by a third preset current injected into the lower branch;

the first preset current is less than the second preset current; the third preset current is larger than the fourth preset current.

6. The short-circuit protection method according to claim 5, wherein: judging whether the upper branch is conducted or not according to the high and low of the grid driving signal of the switching tube in the upper branch; and judging whether the lower branch is conducted or not according to the high and low of the grid driving signal of the switching tube in the lower branch.

7. A short-circuit protection circuit is applied to a bus driver, the bus driver comprises an upper branch circuit and a lower branch circuit, a switch tube in the upper branch circuit is a PMOS tube, a switch tube in the lower branch circuit is an NMOS tube, and when the bus driver works normally, only one of the upper branch circuit and the lower branch circuit is conducted, and the short-circuit protection circuit is characterized in that: the short-circuit protection circuit comprises a first short-circuit protection unit;

the first short-circuit protection unit includes:

the first judgment unit is used for judging whether the upper branch is conducted or not;

a first executing unit, configured to, when the determination result of the first determining unit is that the upper branch is turned on, further execute the following actions:

comparing the output voltage of the output port of the bus driver with a first short-circuit threshold voltage to obtain a first short-circuit comparison result;

comparing the output voltage with a first on-load threshold voltage to obtain a first on-load comparison result;

controlling the current flowing in the upper branch according to the first short circuit comparison result and the first load comparison result, wherein the control logic is as follows:

when the output voltage is less than or equal to the first short-circuit threshold voltage, the current flowing in the upper branch is determined by a first preset current injected into the upper branch;

when the first short-circuit threshold voltage is smaller than the output voltage and smaller than or equal to the first loaded threshold voltage, the current flowing in the upper branch is determined by a second preset current injected into the upper branch;

when the first on-load threshold voltage is less than the output voltage and less than or equal to the power supply rail voltage, the current flowing in the upper branch is determined by the driving load of the bus driver;

the first preset current is less than the second preset current.

8. The short-circuit protection circuit of claim 7, wherein: the first judging unit judges whether the upper branch is conducted or not according to the high and low of the grid driving signal of the switching tube in the upper branch.

9. A short-circuit protection circuit is applied to a bus driver, the bus driver comprises an upper branch circuit and a lower branch circuit, a switch tube in the upper branch circuit is a PMOS tube, a switch tube in the lower branch circuit is an NMOS tube, and only one of the upper branch circuit and the lower branch circuit is conducted when the bus driver works normally, the short-circuit protection circuit is characterized by comprising:

the positive phase input end of the first comparator is used for inputting the output voltage of the output port of the bus driver, and the negative phase input end of the first comparator is used for inputting the first short-circuit threshold voltage; the setting end of the first comparator is used for inputting a grid driving signal of a switching tube in the upper branch circuit to judge whether the upper branch circuit is conducted; when a grid electrode driving signal of a switching tube in the upper branch circuit is at a high level, the output end of the first comparator is set to be at the high level; when a grid electrode driving signal of a switching tube in the upper branch circuit is in a low level, the output end of the first comparator outputs the first short circuit comparison result;

the input end of the first delay unit is used for receiving the output end level of the first comparator, when the output end level of the first comparator is a high level, the first delay unit is used for shaping and transmitting the high level, and the output end of the first delay unit outputs a corresponding high level; when the output end level of the first comparator is low level, the first delay unit is used for outputting the low level from the output end after first delay time;

the control end of the first voltage control current unit is connected with the output end of the first delay unit, and when the control end of the first voltage control current unit receives a high level, the output end of the first voltage control current unit outputs a first constant current; when the control end of the first voltage control current unit receives a low level, the output end of the first voltage control current unit outputs a second constant current, and the first constant current is larger than the second constant current;

the first current proportion unit comprises a PMOS tube MP2 and a PMS tube MP3, a source electrode of the PMOS tube MP2 and a source electrode of the PMS tube MP3 are connected together and then are used for being connected with a power supply rail, a drain electrode of the PMOS tube MP2, a grid electrode of the PMOS tube MP2 and a grid electrode of the PMS tube MP3 are connected together and then are connected with an output end of the first voltage control current unit, and a drain electrode of the PMOS tube MP3 is used for being connected with an anode of a backflow prevention diode of the upper branch.

10. The short protection circuit of claim 9, wherein the first delay unit comprises: a PMOS transistor MP4, an NMOS transistor MN4, a capacitor C1 and a Schmidt inverter SMT 1; the gate of the PMOS transistor MP4 and the gate of the NMOS transistor MN4 are connected together and then serve as the input terminal of the first delay unit, the source of the PMOS transistor MP4 is connected to the power rail, the drain of the PMOS transistor MP4, the drain of the NMOS transistor MN4, one end of the capacitor C1 and the input terminal of the schmitt inverter SMT1 are connected together, the source of the NMOS transistor MN4 and the other end of the capacitor C1 are connected together and then serve as the ground, and the output terminal of the schmitt inverter SMT1 serves as the output terminal of the first delay unit.

11. The short-circuit protection circuit of claim 9, wherein the first voltage-controlled current unit comprises: a switch tube S1, a first reference current IP1 and a second reference current IP 2; the control end of the switch tube S1 is used as the control end of the first voltage-controlled current unit, one end of the switch tube S1 and one end of the second reference current IP2 are connected together and then used as the output end of the first voltage-controlled current unit, the other end of the switch tube S1 is connected to one end of the first reference current IP1, the other end of the first reference current IP1 is used for inputting a first reference current signal, and the other end of the second reference current IP2 is used for inputting a second reference current signal.

12. A short-circuit protection circuit is applied to a bus driver, the bus driver comprises an upper branch circuit and a lower branch circuit, a switch tube in the upper branch circuit is a PMOS tube, a switch tube in the lower branch circuit is an NMOS tube, and when the bus driver works normally, only one of the upper branch circuit and the lower branch circuit is conducted, and the short-circuit protection circuit is characterized in that: the short-circuit protection circuit comprises a second short-circuit protection unit;

the second short-circuit protection unit includes:

the second judging unit is used for judging whether the lower branch is conducted or not;

a second executing unit, configured to, when the determination result of the second determining unit is that the lower branch is connected, further execute the following actions:

comparing the output voltage of the output port of the bus driver with a second short-circuit threshold voltage to obtain a second short-circuit comparison result;

comparing the output voltage with a second on-load threshold voltage to obtain a second on-load comparison result;

controlling the current flowing in the lower branch according to the second short circuit comparison result and the second on-load comparison result, wherein the control logic is as follows:

when the output voltage is not less than 0 and not more than the second loading threshold voltage, the current flowing in the lower branch is determined by the driving load of the bus driver;

when the second on-load threshold voltage is smaller than the output voltage and smaller than or equal to the second short-circuit threshold voltage, the current flowing in the lower branch is determined by a third preset current injected into the lower branch;

when the second short-circuit threshold voltage is less than the output voltage, the current flowing in the lower branch is determined by a fourth preset current injected into the lower branch;

the third preset current is larger than the fourth preset current.

13. The short-circuit protection circuit of claim 12, wherein: the second judging unit judges whether the lower branch is conducted or not according to the height of a grid driving signal of a switching tube in the lower branch.

14. A short-circuit protection circuit is applied to a bus driver, the bus driver comprises an upper branch circuit and a lower branch circuit, a switch tube in the upper branch circuit is a PMOS tube, a switch tube in the lower branch circuit is an NMOS tube, and only one of the upper branch circuit and the lower branch circuit is conducted when the bus driver works normally, the short-circuit protection circuit is characterized by comprising:

a positive phase input end of the second comparator is used for inputting the second short-circuit threshold voltage, and a negative phase input end of the second comparator is used for inputting the output voltage of the output port of the bus driver; the setting end of the second comparator is used for inputting a gate drive signal of a switching tube in the lower branch circuit to judge whether the lower branch circuit is conducted; when the grid driving signal of the switching tube in the lower branch circuit is at a low level, the output end of the second comparator is set to be at a high level; when a grid electrode driving signal of a switching tube in the upper branch circuit is in a high level, the output end of the second comparator outputs a second short circuit comparison result;

the input end of the second delay unit is used for receiving the output end level of the second comparator, when the output end level of the second comparator is high level, the second delay unit is used for shaping and transmitting the high level, and the output end of the second delay unit outputs the corresponding high level; when the level of the output end of the second comparator is low level, the second delay unit is used for outputting the low level from the output end of the second delay unit after second delay time;

a second voltage control current unit, a control end of the second voltage control current unit being connected to an output end of the second delay unit, and when the control end of the second voltage control current unit receives a high level, the output end of the second voltage control current unit outputs a third constant current; when the control end of the second voltage control current unit receives a low level, the output end of the second voltage control current unit outputs a fourth constant current, and the third constant current is larger than the fourth constant current;

the second current proportion unit comprises an NMOS tube MN2 and an NMOS tube MN3, the source electrode of the NMOS tube MN2 and the source electrode of the NMS tube MN3 are connected together and then are grounded, the drain electrode of the NMOS tube MN2, the grid electrode of the NMOS tube MN2 and the grid electrode of the NMS tube MN3 are connected together and then are connected with the output end of the second voltage control current unit, and the drain electrode of the NMOS tube MN3 is connected with the source electrode of the NMOS tube of the lower branch.

15. The short protection circuit of claim 14, wherein the second delay unit comprises: a PMOS transistor MP5, an NMOS transistor MN5, a capacitor C2 and a Schmidt inverter SMT 2; the gate of the PMOS transistor MP5 and the gate of the NMOS transistor MN5 are connected together and then serve as the input terminal of the second delay unit, the source of the PMOS transistor MP5 is connected to the power rail, the drain of the PMOS transistor MP5, the drain of the NMOS transistor MN5, one end of the capacitor C2 and the input terminal of the schmitt inverter SMT2 are connected together, the source of the NMOS transistor MN5 and the other end of the capacitor C2 are connected together and then serve as the ground, and the output terminal of the schmitt inverter SMT2 serves as the output terminal of the second delay unit.

16. The short-circuit protection circuit of claim 14, wherein the second voltage-controlled current unit comprises: a switch tube S2, a third reference current IN1 and a fourth reference current IN 2; the control end of the switch tube S2 is used as the control end of the second voltage-controlled current unit, one end of the switch tube S2 and one end of the fourth reference current IN2 are connected together and then used as the output end of the second voltage-controlled current unit, the other end of the switch tube S2 is connected with one end of the third reference current IN1, the other end of the third reference current IN1 is used for inputting a third reference current signal, and the other end of the fourth reference current IN2 is used for inputting a fourth reference current signal.

17. A short-circuit protection circuit is applied to a bus driver, the bus driver comprises an upper branch circuit and a lower branch circuit, a switch tube in the upper branch circuit is a PMOS tube, a switch tube in the lower branch circuit is an NMOS tube, and when the bus driver works normally, only one of the upper branch circuit and the lower branch circuit is conducted, and the short-circuit protection circuit is characterized in that: the short-circuit protection circuit comprises a first short-circuit protection unit and a second short-circuit protection unit;

the first short-circuit protection unit includes:

the first judgment unit is used for judging whether the upper branch is conducted or not;

a first executing unit, configured to, when the determination result of the first determining unit is that the upper branch is turned on, further execute the following actions:

comparing the output voltage of the output port of the bus driver with a first short-circuit threshold voltage to obtain a first short-circuit comparison result;

comparing the output voltage with a first on-load threshold voltage to obtain a first on-load comparison result;

controlling the current flowing in the upper branch according to the first short circuit comparison result and the first load comparison result, wherein the control logic is as follows:

when the output voltage is less than or equal to the first short-circuit threshold voltage, the current flowing in the upper branch is determined by a first preset current injected into the upper branch;

when the first short-circuit threshold voltage is less than the output voltage and less than or equal to the first loaded threshold voltage, the current flowing in the upper branch is determined by a second preset current injected into the upper branch;

when the first loaded threshold voltage is less than the output voltage and less than or equal to the power supply rail voltage, the current flowing in the upper branch is determined by the driving load of the bus driver;

the first preset current is less than the second preset current;

the second short-circuit protection unit includes:

the second judging unit is used for judging whether the lower branch is conducted or not;

a second executing unit, configured to, when the determination result of the second determining unit is that the lower branch is connected, further execute the following actions:

comparing the output voltage of the output port of the bus driver with a second short-circuit threshold voltage to obtain a second short-circuit comparison result;

comparing the output voltage with a second on-load threshold voltage to obtain a second on-load comparison result;

controlling the current flowing in the lower branch according to the second short circuit comparison result and the second on-load comparison result, wherein the control logic is as follows:

when the output voltage is not less than 0 and not more than the second loading threshold voltage, the current flowing in the lower branch is determined by the driving load of the bus driver;

when the second on-load threshold voltage is less than the output voltage and less than or equal to the second short-circuit threshold voltage, the current flowing in the lower branch is determined by a third preset current injected into the lower branch;

when the second short-circuit threshold voltage is smaller than the output voltage, the current flowing in the lower branch circuit is determined by a fourth preset current injected into the lower branch circuit;

the third preset current is larger than the fourth preset current.

18. The short-circuit protection circuit of claim 17, wherein: the first judging unit judges whether the upper branch is conducted or not according to the height of a grid driving signal of a switching tube in the upper branch; the second judging unit judges whether the lower branch is conducted or not according to the height of a grid driving signal of a switching tube in the lower branch.

19. A short-circuit protection circuit is applied to a bus driver, the bus driver comprises an upper branch circuit and a lower branch circuit, a switch tube in the upper branch circuit is a PMOS tube, a switch tube in the lower branch circuit is an NMOS tube, and only one of the upper branch circuit and the lower branch circuit is conducted when the bus driver works normally, the short-circuit protection circuit is characterized by comprising:

the positive phase input end of the first comparator is used for inputting the output voltage of the output port of the bus driver, and the negative phase input end of the first comparator is used for inputting the first short-circuit threshold voltage; the setting end of the first comparator is used for inputting a grid driving signal of a switching tube in the upper branch circuit to judge whether the upper branch circuit is conducted; when a grid electrode driving signal of a switching tube in the upper branch circuit is at a high level, the output end of the first comparator is set to be at the high level; when a grid electrode driving signal of a switching tube in the upper branch circuit is in a low level, the output end of the first comparator outputs the first short circuit comparison result;

the input end of the first delay unit is used for receiving the output end level of the first comparator, when the output end level of the first comparator is a high level, the first delay unit is used for shaping and transmitting the high level, and the output end of the first delay unit outputs a corresponding high level; when the output end level of the first comparator is low level, the first delay unit is used for outputting the low level from the output end after first delay time;

the control end of the first voltage control current unit is connected with the output end of the first delay unit, and when the control end of the first voltage control current unit receives a high level, the output end of the first voltage control current unit outputs a first constant current; when the control end of the first voltage control current unit receives a low level, the output end of the first voltage control current unit outputs a second constant current, and the first constant current is larger than the second constant current;

the first current proportion unit comprises a PMOS (P-channel metal oxide semiconductor) tube MP2 and a PMS tube MP3, a source electrode of the PMOS tube MP2 and a source electrode of the PMS tube MP3 are connected together and then are used for being connected with a power supply rail, a drain electrode of the PMOS tube MP2, a grid electrode of the PMOS tube MP2 and a grid electrode of the PMS tube MP3 are connected together and then are connected with an output end of the first voltage control current unit, and a drain electrode of the PMOS tube MP3 is used for being connected with an anode of a backflow prevention diode of the upper branch;

a positive phase input end of the second comparator is used for inputting the second short-circuit threshold voltage, and a negative phase input end of the second comparator is used for inputting the output voltage; the setting end of the second comparator is used for inputting a gate drive signal of a switching tube in the lower branch circuit to judge whether the lower branch circuit is conducted; when the grid driving signal of the switching tube in the lower branch circuit is at a low level, the output end of the second comparator is set to be at a high level; when the grid electrode driving signal of the switching tube in the upper branch circuit is in a high level, the output end of the second comparator outputs the second short circuit comparison result;

the input end of the second delay unit is used for receiving the output end level of the second comparator, when the output end level of the second comparator is high level, the second delay unit is used for shaping and transmitting the high level, and the output end of the second delay unit outputs the corresponding high level; when the level of the output end of the second comparator is low level, the second delay unit is used for outputting the low level from the output end of the second delay unit after the second delay time;

a second voltage control current unit, a control end of the second voltage control current unit being connected to an output end of the second delay unit, and when the control end of the second voltage control current unit receives a high level, the output end of the second voltage control current unit outputs a third constant current; when the control end of the second voltage control current unit receives a low level, the output end of the second voltage control current unit outputs a fourth constant current, and the third constant current is larger than the fourth constant current;

the second current proportion unit comprises an NMOS tube MN2 and an NMOS tube MN3, the source electrode of the NMOS tube MN2 and the source electrode of the NMS tube MN3 are connected together and then are grounded, the drain electrode of the NMOS tube MN2, the grid electrode of the NMOS tube MN2 and the grid electrode of the NMS tube MN3 are connected together and then are connected with the output end of the second voltage control current unit, and the drain electrode of the NMOS tube MN3 is connected with the source electrode of the NMOS tube of the lower branch.

20. The short protection circuit of claim 19, wherein the first delay unit comprises: a PMOS transistor MP4, an NMOS transistor MN4, a capacitor C1 and a Schmidt inverter SMT 1; the gate of the PMOS transistor MP4 and the gate of the NMOS transistor MN4 are connected together and then serve as the input terminal of the first delay unit, the source of the PMOS transistor MP4 is connected to the power rail, the drain of the PMOS transistor MP4, the drain of the NMOS transistor MN4, one end of the capacitor C1 and the input terminal of the schmitt inverter SMT1 are connected together, the source of the NMOS transistor MN4 and the other end of the capacitor C1 are connected together and then serve as the ground, and the output terminal of the schmitt inverter SMT1 serves as the output terminal of the first delay unit.

21. The short protection circuit of claim 19, wherein the first voltage controlled current cell comprises: a switch tube S1, a first reference current IP1 and a second reference current IP 2; the control end of the switch tube S1 is used as the control end of the first voltage control current unit, one end of the switch tube S1 and one end of the second reference current IP2 are connected together and then used as the output end of the first voltage control current unit, the other end of the switch tube S1 is connected with one end of the first reference current IP1, the other end of the first reference current IP1 is used for inputting a first reference current signal, and the other end of the second reference current IP2 is used for inputting a second reference current signal.

22. The short protection circuit of claim 19, wherein the second delay unit comprises: a PMOS transistor MP5, an NMOS transistor MN5, a capacitor C2 and a Schmidt inverter SMT 2; the gate of the PMOS transistor MP5 and the gate of the NMOS transistor MN5 are connected together and then serve as the input terminal of the second delay unit, the source of the PMOS transistor MP5 is connected to the power rail, the drain of the PMOS transistor MP5, the drain of the NMOS transistor MN5, one end of the capacitor C2 and the input terminal of the schmitt inverter SMT2 are connected together, the source of the NMOS transistor MN5 and the other end of the capacitor C2 are connected together and then serve as the ground, and the output terminal of the schmitt inverter SMT2 serves as the output terminal of the second delay unit.

23. The short protection circuit of claim 22, wherein the second voltage controlled current cell comprises: a switch tube S2, a third reference current IN1 and a fourth reference current IN 2; the control end of the switch tube S2 is used as the control end of the second voltage-controlled current unit, one end of the switch tube S2 and one end of the fourth reference current IN2 are connected together and then used as the output end of the second voltage-controlled current unit, the other end of the switch tube S2 is connected to one end of the third reference current IN1, the other end of the first reference current IP1 is used for inputting a first reference current signal, and the other end of the second reference current IP2 is used for inputting a second reference current signal.

24. A bus driver, comprising: the short-circuit protection circuit of any one of claims 7 to 23.

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