CN114994391A - RS232 signal detection circuit - Google Patents
RS232 signal detection circuit Download PDFInfo
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- CN114994391A CN114994391A CN202210721377.0A CN202210721377A CN114994391A CN 114994391 A CN114994391 A CN 114994391A CN 202210721377 A CN202210721377 A CN 202210721377A CN 114994391 A CN114994391 A CN 114994391A
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Abstract
The invention discloses an RS232 signal detection circuit, which comprises: the circuit comprises a clamping unit, a first signal conversion unit, a second signal conversion unit and a delay unit. The clamping unit is used for clamping the RS232 signal. The first signal conversion unit is used for converting a high-level signal of the RS232 signal and outputting a first identification signal. The second signal conversion unit is used for converting the low-level signal of the RS232 signal and outputting a second identification signal. When the RS232 signal is in a level range between a high level and a low level, the first signal conversion unit outputs a third identification signal, and determines whether the RS232 signal is input based on the first identification signal, the second identification signal, and the third identification signal. According to the RS232 signal detection circuit, the RS232 signal is detected through few components, and compared with the traditional scheme, the cost of a chip is obviously reduced. Meanwhile, the power consumption of the whole circuit is almost zero in a DC state, and the application coverage of low power consumption is greatly improved.
Description
Technical Field
The present invention relates to the field of integrated circuits, and more particularly, to an RS232 signal detection circuit.
Background
RS232 communication is widely applied to the fields of computers and industrial control. According to the EIA-RS-232C standard, in RS232 communication, a signal level is recognized as a logical "0" when it is +3V to +15V, as a logical "1" when it is-3V to-15V, and as an invalid signal, a signal between-3V to +3V is recognized.
In some low power applications, it is necessary to detect RS232 bus signals in real time, and when the system considers that there is no signal transmission, the circuit or some modules of the system are turned off to save power consumption. It is generally considered that no signal is transmitted when the RS232 signal level is between-0.3V to +0.3V and is maintained for about 30 μ s.
As shown in fig. 1, the prior art generally implements detection of an RS232 signal by two comparators. In the scheme, a high-voltage RS232 signal is converted into a low-voltage signal, then the low-voltage signal is compared with a-0.3V reference level and a +0.3V reference level respectively, and a result is output after delay of about 30us through logic judgment. Obviously, the existing RS232 signal detection technology needs more circuit components and devices, and is higher in cost, and the level conversion circuit and the comparator both need to consume a certain DC power consumption, which is not beneficial to low power consumption application.
The information disclosed in this background section is only for enhancement of understanding of the general background of the invention and should not be taken as an acknowledgement or any form of suggestion that this information forms the prior art already known to a person skilled in the art.
Disclosure of Invention
The invention aims to provide an RS232 signal detection circuit which can reduce the cost, complete the detection of RS232 signals under extremely low power consumption and meet the application requirement of low power consumption.
To achieve the above object, an embodiment of the present invention provides an RS232 signal detection circuit, including: the circuit comprises a clamping unit, a first signal conversion unit, a second signal conversion unit and a delay unit.
The clamping unit is connected with a ground voltage and a power supply voltage and is used for clamping the RS232 signal.
The first signal conversion unit is connected with the clamping unit and used for converting a high-level signal of the RS232 signal and outputting a first identification signal.
The second signal conversion unit is connected with the clamping unit and used for converting the low-level signal of the RS232 signal and outputting a second identification signal.
When the RS232 signal is in a level range between a high level and a low level, the first signal conversion unit outputs a third identification signal.
The delay unit is connected with the first signal conversion unit and the second signal conversion unit, and is used for outputting a third identification signal in a delayed manner by matching with the first signal conversion unit and judging whether an RS232 signal is input or not based on the first identification signal, the second identification signal and the third identification signal.
In one or more embodiments of the present invention, the detection circuit further includes an output unit, and the output unit is connected to the first signal conversion unit, the second signal conversion unit, and the delay unit, and is configured to receive the first identification signal, the second identification signal, and the third identification signal to output corresponding level detection signals.
In one or more embodiments of the present invention, the first signal conversion unit includes a logic unit and a switching unit, the logic unit is connected to the clamping unit, and is configured to invert and shape the RS232 signal several times and output a control signal, the switching unit is connected to the logic unit, a power supply voltage and a ground voltage, the switching unit is turned on or off under control of the control signal, and an output terminal of the first signal conversion unit is connected to the ground voltage or the power supply voltage when the switching unit is in an on state.
In one or more embodiments of the present invention, the switch unit includes a second resistor and a third MOS transistor, a first end of the second resistor is connected to a power supply voltage, a second end of the second resistor is connected to a drain of the third MOS transistor and the second signal conversion unit, a source of the third MOS transistor is connected to a ground voltage, a gate of the third MOS transistor is connected to the logic unit, and when the control signal output by the logic unit is a high-level signal, a drain of the third MOS transistor is conducted to the ground voltage and outputs the first identification signal.
In one or more embodiments of the present invention, the logic unit includes a first inverter and a second inverter, an input terminal of the first inverter is connected to the clamping unit to receive the RS232 signal, an output terminal of the first inverter is connected to an input terminal of the second inverter, and an output terminal of the second inverter outputs the control signal.
In one or more embodiments of the present invention, the clamping unit includes a first resistor, a first diode, and a second diode, a first terminal of the first resistor is an input terminal of the RS232 signal, a second terminal of the first resistor is connected to a cathode of the first diode, an anode of the first diode is connected to a ground voltage, a second terminal of the first resistor is connected to an anode of the second diode, a cathode of the second diode is connected to a power voltage, a second terminal of the first resistor is connected to the first signal converting unit, the second signal converting unit is connected to a second terminal of the first resistor and a cathode of the first diode, the first signal converting unit receives a high level signal of the RS232 signal and outputs the first identification signal when the second terminal of the first resistor outputs the high level signal of the RS232 signal, and the second signal converting unit receives a low level signal of the RS232 signal when the second terminal of the first resistor outputs the low level signal of the RS232 signal, the second signal conversion unit receives a low-level signal of the RS232 signal and outputs a second identification signal.
In one or more embodiments of the present invention, the second signal conversion unit includes a first MOS transistor and a second MOS transistor, gates of the first MOS transistor and the second MOS transistor are connected, a gate and a drain of the first MOS transistor are connected to form a first connection point, sources of the first MOS transistor and the second MOS transistor are connected to form a second connection point, the first connection point and the second connection point are connected in the clamping unit, the second connection point is configured to receive a low-level signal of the RS232 signal, and a drain of the second MOS transistor is used as an output end of the second identification signal.
In one or more embodiments of the present invention, the delay unit includes a second resistor and a capacitor, a first end of the second resistor is connected to the power supply voltage and a first end of the capacitor, and a second end of the second resistor is connected to the second end of the capacitor, the first signal conversion unit, and the second signal conversion unit.
In one or more embodiments of the present invention, the clamping unit further includes a fourth MOS transistor, a source of the fourth MOS transistor is connected to an anode of the second diode, a gate of the fourth MOS transistor is connected to a ground voltage, and a drain of the fourth MOS transistor is connected to the first signal conversion unit.
In one or more embodiments of the present invention, the output unit includes a third inverter, an input terminal of the third inverter is connected to the first signal converting unit, the second signal converting unit, and the delay unit, and an output terminal of the third inverter outputs the level detection signal.
Compared with the prior art, according to the RS232 signal detection circuit provided by the embodiment of the invention, the RS232 signal is detected through few components, the signal validity of the RS232 in different level ranges is detected through the first level conversion unit and the second level conversion unit, and compared with the traditional scheme, the number of the components used by the first level conversion unit and the second level conversion unit is very small, so that the chip cost is obviously reduced. Meanwhile, the power consumption of the whole circuit is almost zero in a DC state (the input RS232 signal is 0), and the application coverage of low power consumption is greatly improved.
Drawings
Fig. 1 is a circuit schematic diagram of a prior art RS232 signal detection circuit.
Fig. 2 is a schematic circuit diagram of an RS232 signal detection circuit according to a first embodiment of the present invention.
Detailed Description
Specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings, but it should be understood that the scope of the present invention is not limited to the specific embodiments.
Throughout the specification and claims, unless explicitly stated otherwise, the word "comprise", or variations such as "comprises" or "comprising", will be understood to imply the inclusion of a stated element or component but not the exclusion of any other element or component.
It should be understood that in the following description, "circuitry" may comprise singly or in combination hardware circuitry, programmable circuitry, state machine circuitry, and/or elements capable of storing instructions executed by programmable circuitry. When an element or circuit is referred to as being "connected to" another element or element/circuit is referred to as being "connected between" two nodes, it may be directly coupled or connected to the other element or intervening elements may be present, and the connection between the elements may be physical, logical, or a combination thereof. In contrast, when an element is referred to as being "directly coupled" or "directly connected" to another element, it is intended that the two be absent intermediate elements.
The invention is further illustrated with reference to the following figures and examples.
As shown in fig. 2, an RS232 signal detection circuit includes: the circuit comprises a clamping unit 10, a first signal conversion unit 20, a second signal conversion unit 30, a delay unit 40 and an output unit 50. The first signal conversion unit 20 and the second signal conversion unit 30 are both connected to the clamping unit 10, and the output unit 50 is connected to the first signal conversion unit 20, the second signal conversion unit 30, and the delay unit 40.
The clamping unit 10 is connected to a ground voltage GND and a power supply voltage VCC, and the clamping unit 10 is used for clamping an input range of an RS232 signal.
Specifically, the clamping unit 10 includes a first resistor R1, a first diode D1, and a second diode D2. A first terminal of the first resistor R1 is an input terminal of the RS232 signal, a second terminal of the first resistor R1 is connected to a cathode of the first diode D1, and an anode of the first diode D1 is connected to the ground voltage GND. A second terminal of the first resistor R1 is connected to an anode of a second diode D2, and a cathode of the second diode D2 is connected to the supply voltage VCC. In other embodiments, the first diode D1 and the second diode D2 may be replaced by other semiconductor devices such as MOS transistors, triodes, and the like.
The RS232 signal is clamped between-VBE 1 and (VCC + VBE2) by the clamping unit 10, where VBE1 is the turn-on voltage of the first diode D1, VBE2 is the turn-on voltage of the second diode D2, and VCC is the power supply voltage VCC.
A second terminal of the first resistor R1 is connected to an input terminal of the first signal converting unit 20, and the second signal converting unit 30 is connected to a second terminal of the first resistor R1 and a cathode of the first diode D1.
When the second end of the first resistor R1 outputs the high level signal of the RS232 signal, the first signal conversion unit 20 receives the high level of the RS232 signal and outputs the first identification signal; when the second terminal of the first resistor R1 outputs the low level signal of the RS232 signal, the second signal converting unit 30 receives the low level signal of the RS232 signal and outputs the second identification signal.
As shown in fig. 2, the first signal conversion unit 20 includes a logic unit and a switch unit. The logic unit is connected with the clamping unit 10, the logic unit is used for performing phase inversion processing and shaping on an RS232 signal to output a control signal, the switch unit is connected with the logic unit, a power supply voltage VCC and a ground voltage GND, the switch unit is turned on or off under the control of the control signal, and when the switch tube is in a conducting state, the output end of the first signal conversion unit 20 is connected to the ground voltage GND or the power supply voltage VCC.
The logic cell in this embodiment includes a first inverter INV1 and a second inverter INV2, and the number of the first inverter INV1 and the second inverter INV2 is not particularly limited. An input end of the first inverter INV1 is connected to the clamping unit 10, an input end of the second inverter INV2 is connected to an output end of the first inverter INV1, and an output end of the second inverter INV2 outputs a control signal. The first inverter INV1 and the second inverter INV2 are schmitt inverters or ordinary inverters, and in other embodiments, a comparator may be used instead.
The switch unit comprises a second resistor R2 and a third MOS transistor N3. A first end of the second resistor R2 is connected to the power supply voltage VCC, a second end of the second resistor R2 is connected to the drain of the third MOS transistor N3 and the second signal conversion unit 30, a source of the third MOS transistor N3 is connected to the ground voltage GND, and a gate of the third MOS transistor N3 is connected to the output end of the second inverter INV 2.
In this embodiment, the third MOS transistor N3 is an N-channel fet, so when the control signal output by the output terminal of the second inverter INV2 is a high level signal, the third MOS transistor N3 is turned on to the ground voltage GND and outputs the first identification signal, and if the first identification signal is generated, it indicates that the RS232 signal is transmitted. In other embodiments, the third MOS transistor N3 is a P-channel fet, at this time, only one of the first inverter INV1 and the second inverter INV2 is selected, or the number of inverters is increased, so that the control signal output by the logic unit is a low level signal, and by changing the connection mode of the switch unit, when the control signal output by the logic unit is a low level signal, the third MOS transistor N3 is turned on to the power supply voltage VCC.
The clamping unit 10 further includes a fourth MOS transistor P1. The source of the fourth MOS transistor P1 is connected to the anode of the second diode D2, the gate of the fourth MOS transistor P1 is connected to the ground voltage GND, and the drain of the fourth MOS transistor P1 is connected to the input terminal of the logic unit.
In this embodiment, the fourth MOS transistor P1 is a P-channel field effect transistor, and the fourth MOS transistor P1 is configured to further raise a low level signal of the RS232 signal, and the RS232 signal is further clamped between (-VBE1+ VTHP) - (VCC + VBE2) by the fourth MOS transistor P1, where VTHP is an on voltage of the fourth MOS transistor P1, and raising the low level signal of the RS232 signal makes the low level signal of the RS232 signal higher than 0V, so as to raise an input voltage of the first inverter INV1, reduce VGS of a PMOS transistor in the first inverter INV1, increase stability of a PMOS transistor in the first inverter INV1, and improve a service life.
In other embodiments, the fourth MOS transistor P1 may be omitted, and an N-channel fet, a transistor, or a diode may be used instead.
As shown in fig. 2, the second signal conversion unit 30 is connected to the clamping circuit 10, and not only clamps the RS232 signal with the clamping circuit 10, but also outputs the second identification signal when the input RS232 signal is a low-level signal.
The second signal conversion unit 30 includes a first MOS transistor N1 and a second MOS transistor N2. The grid electrodes of the first MOS tube N1 and the second MOS tube N2 are connected, the grid electrode and the drain electrode of the first MOS tube N1 are connected to form a first connection point, the source electrodes of the first MOS tube N1 and the second MOS tube N2 are connected to form a second connection point, the first MOS tube N1 and the second MOS tube N2 form a current mirror, and the first connection point and the second connection point are connected in the clamping unit 10. Specifically, the first connection point is connected to the cathode of the first diode D1, and the second connection point is connected to the second terminal of the first resistor R1 and the anode of the second diode D2. The second connection point is used for receiving a low-level signal of the RS232 signal, and the drain of the second MOS transistor N2 is used as an output end of the second identification signal. If the second identification signal is generated, it indicates that an RS232 signal is transmitted.
In this embodiment, the first MOS transistor N1 and the second MOS transistor N2 are N-channel fets, so when the input RS232 signal is a low level signal, the voltage of the first connection point is greater than the voltage of the second connection point, and the first MOS transistor N1 and the second MOS transistor N2 are turned on. In other embodiments, the first MOS transistor N1 and the second MOS transistor N2 may be P-channel fets or triodes instead of P-channel fets by changing the connection structure.
In the embodiment, the clamp circuit 10 is connected to the first MOS transistor N1, so as to further clamp the RS232 signal, and the RS232 signal is finally clamped between (-VBE1-VGSN1+ VTHP) - (VCC + VBE2), where VGSN1 is a voltage between the gate and the source of the first MOS transistor N1. The requirement of the input voltage range of the first inverter INV1 is met by clamping the level signal of the RS232 signal between (-VBE1-VGSN1+ VTHP) - (VCC + VBE 2).
The delay unit 40 is connected to the first signal conversion unit 20, the second signal conversion unit 30 and the power voltage VCC, when the input RS232 signal is in a level range (-0.3 to +0.3V) between a high level and a low level, the first signal conversion unit 20 outputs a third identification signal, and the delay unit 40 is configured to output the third identification signal in a delayed manner in cooperation with the first signal conversion unit 20.
As shown in fig. 2, the delay unit 40 includes a second resistor R2 and a capacitor C1. A first terminal of the second resistor R2 is connected to the power supply voltage VCC and a first terminal of the capacitor C1, and a second terminal of the second resistor R2 is connected to a second terminal of the capacitor C1, the first signal converting unit 20, and the second signal converting unit 30. The second resistor R2 and the capacitor C1 are arranged to generate a delay time of about 30 mus, so that the third identification signal is delayed by about 30 mus and then output to meet the time requirement of signal detection.
The second resistor R2 in the delay unit 40 and the second resistor R2 in the switch unit are the same resistor, i.e. the second resistor R2 has the function of limiting current in the switch unit, and also affects the time constant of the delay unit 40 in the delay unit 40. In other embodiments, the second resistor R2 may be retained, and the capacitor C1 may be eliminated, while other configurations of the delay cell 40 may be used.
The output unit 50 is configured to receive the first identification signal, the second identification signal and the third identification signal to output corresponding level detection signals.
As shown in fig. 2, the output unit 50 includes a third inverter INV 3. An input end of the third inverter INV3 is connected to the first signal converting unit 20, the second signal converting unit 30 and the delay unit 40 to receive the first identification signal, the second identification signal and the third identification signal, and an output end of the third inverter INV3 outputs the level detection signal INVALID.
The working principle of the embodiment is as follows:
when a high-level signal of the RS232 signal is input, the first MOS transistor N1 and the second MOS transistor N2 are turned off, the second inverter INV2 outputs a high-level signal, the third MOS transistor N3 is turned on, at this time, the first identification signal input by the third inverter INV3 is a low-level signal, and at this time, the output level detection signal INVALID is a high-level signal, so that the RS232 signal is considered to be transmitted.
When a low level signal of the RS232 signal is input, the second inverter INV2 outputs a low level signal, the third MOS transistor N3 is turned off, the first MOS transistor N1 and the second MOS transistor N2 are turned on, the second identification signal input by the third inverter INV3 is a low level signal, and the level detection signal INVALID output by the third inverter INV3 is a high level signal, so that it is still determined that the RS232 signal is transmitted.
When the level signal of the input RS232 signal is between-0.3V to +0.3V, the first MOS transistor N1, the second MOS transistor N2, and the third MOS transistor N3 are all turned off, the input end of the third inverter INV3 is pulled up to a high level through the second resistor R2, and the third identification signal at the input end of the third inverter INV3 is a high level signal, so that the level detection signal INVALID output by the third inverter INV3 is a low level signal, and it is determined that no RS232 signal is transmitted at this time.
Due to the capacitor C1, the level at the input end of the third inverter INV3 needs to experience a delay of about 30 μ s during the transition from low to high, where R is the resistance of the second resistor R2 and C is the capacitance of the capacitor C1.
In conclusion, the invention completes the detection of the RS232 signal through few components, and compared with the traditional scheme, the cost of the chip is obviously reduced. Meanwhile, the power consumption of the whole circuit is almost zero in a DC state (the input RS232 signal is 0), and the application coverage of low power consumption is greatly improved.
The foregoing descriptions of specific exemplary embodiments of the present invention have been presented for purposes of illustration and description. It is not intended to limit the invention to the precise form disclosed, and obviously many modifications and variations are possible in light of the above teaching. The exemplary embodiments were chosen and described in order to explain certain principles of the invention and its practical application to enable one skilled in the art to make and use various exemplary embodiments of the invention and various alternatives and modifications as are suited to the particular use contemplated. It is intended that the scope of the invention be defined by the claims and their equivalents.
Claims (10)
1. An RS232 signal detection circuit, comprising:
the clamping unit is connected with the ground voltage and the power supply voltage and is used for clamping the RS232 signal;
the first signal conversion unit is connected with the clamping unit and used for converting a high-level signal of the RS232 signal and outputting a first identification signal;
the second signal conversion unit is connected with the clamping unit and used for converting the low-level signal of the RS232 signal and outputting a second identification signal;
when the RS232 signal is in a level range between a high level and a low level, the first signal conversion unit outputs a third identification signal; and
and the delay unit is connected with the first signal conversion unit and the second signal conversion unit and is used for outputting a third identification signal in a delayed manner by matching with the first signal conversion unit and judging whether an RS232 signal is input or not based on the first identification signal, the second identification signal and the third identification signal.
2. The RS232 signal detection circuit of claim 1 further comprising an output unit, connected to the first signal conversion unit, the second signal conversion unit and the delay unit, for receiving the first identification signal, the second identification signal and the third identification signal to output corresponding level detection signals.
3. The RS232 signal detection circuit of claim 1, wherein the first signal conversion unit includes a logic unit and a switching unit, the logic unit is connected to the clamping unit for inverting and shaping the RS232 signal several times and outputting the control signal, the switching unit is connected to the logic unit, the power supply voltage and the ground voltage, the switching unit is turned on or off under control of the control signal, and the output terminal of the first signal conversion unit is connected to the ground voltage or the power supply voltage in a turned-on state of the switching unit.
4. The RS232 signal detection circuit of claim 3, wherein the switch unit includes a second resistor and a third MOS transistor, a first terminal of the second resistor is connected to a power voltage, a second terminal of the second resistor is connected to a drain of the third MOS transistor and the second signal conversion unit, a source of the third MOS transistor is connected to a ground voltage, a gate of the third MOS transistor is connected to the logic unit, and when the control signal output by the logic unit is a high-level signal, the drain of the third MOS transistor is conducted to the ground voltage and outputs the first identification signal.
5. The RS232 signal detection circuit of claim 3 wherein the logic cell includes a first inverter and a second inverter, an input of the first inverter is coupled to the clamping unit to receive the RS232 signal, an output of the first inverter is coupled to an input of the second inverter, and an output of the second inverter outputs the control signal.
6. The RS232 signal detecting circuit according to claim 1, wherein the clamping unit includes a first resistor, a first diode, and a second diode, a first terminal of the first resistor is an input terminal of the RS232 signal, a second terminal of the first resistor is connected to a cathode of the first diode, an anode of the first diode is connected to a ground voltage, a second terminal of the first resistor is connected to an anode of the second diode, a cathode of the second diode is connected to a power supply voltage, a second terminal of the first resistor is connected to the first signal converting unit, the second signal converting unit is connected to a second terminal of the first resistor and a cathode of the first diode, the first signal converting unit receives a high level signal of the RS232 signal and outputs the first identification signal when the second terminal of the first resistor outputs the high level signal of the RS232 signal, when the second end of the first resistor outputs a low-level signal of the RS232 signal, the second signal conversion unit receives the low-level signal of the RS232 signal and outputs a second identification signal.
7. The RS232 signal detection circuit of claim 1, wherein the second signal conversion unit includes a first MOS transistor and a second MOS transistor, gates of the first MOS transistor and the second MOS transistor are connected, a gate and a drain of the first MOS transistor are connected to form a first connection point, sources of the first MOS transistor and the second MOS transistor are connected to form a second connection point, the first connection point and the second connection point are connected to the clamping unit, the second connection point is configured to receive a low level signal of the RS232 signal, and a drain of the second MOS transistor is used as an output terminal of the second identification signal.
8. The RS232 signal detection circuit of claim 1, wherein the delay unit includes a second resistor and a capacitor, a first end of the second resistor is connected to the power voltage and a first end of the capacitor, and a second end of the second resistor is connected to the second end of the capacitor, the first signal conversion unit and the second signal conversion unit.
9. The RS232 signal detection circuit of claim 6 wherein the clamping unit further includes a fourth MOS transistor, a source of the fourth MOS transistor is connected to an anode of the second diode, a gate of the fourth MOS transistor is connected to a ground voltage, and a drain of the fourth MOS transistor is connected to the first signal conversion unit.
10. The RS232 signal detection circuit according to claim 2, wherein the output unit includes a third inverter, an input terminal of the third inverter is connected to the first signal conversion unit, the second signal conversion unit and the delay unit, and an output terminal of the third inverter outputs the level detection signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210721377.0A CN114994391A (en) | 2022-06-16 | 2022-06-16 | RS232 signal detection circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210721377.0A CN114994391A (en) | 2022-06-16 | 2022-06-16 | RS232 signal detection circuit |
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| CN114994391A true CN114994391A (en) | 2022-09-02 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117119075A (en) * | 2023-10-25 | 2023-11-24 | 浙江地芯引力科技有限公司 | Protocol identification circuit, chip, protocol identification method and electronic equipment |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117119075A (en) * | 2023-10-25 | 2023-11-24 | 浙江地芯引力科技有限公司 | Protocol identification circuit, chip, protocol identification method and electronic equipment |
| CN117119075B (en) * | 2023-10-25 | 2024-02-09 | 浙江地芯引力科技有限公司 | Protocol identification circuit, chip, protocol identification method and electronic equipment |
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