CN114979030A - Method and system for realizing large-scale time-sensitive network asynchronous gating - Google Patents

Method and system for realizing large-scale time-sensitive network asynchronous gating Download PDF

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Publication number
CN114979030A
CN114979030A CN202210513686.9A CN202210513686A CN114979030A CN 114979030 A CN114979030 A CN 114979030A CN 202210513686 A CN202210513686 A CN 202210513686A CN 114979030 A CN114979030 A CN 114979030A
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gating
time window
time
window
group
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刘端
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Kungao New Core Microelectronics Jiangsu Co ltd
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Kungao New Core Microelectronics Jiangsu Co ltd
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Priority to PCT/CN2023/086397 priority patent/WO2023216777A1/en
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/10—Packet switching elements characterised by the switching fabric construction
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/30—Peripheral units, e.g. input or output ports
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D30/00—Reducing energy consumption in communication networks
    • Y02D30/50—Reducing energy consumption in communication networks in wire-line communication networks, e.g. low power modes or reduced link rate

Abstract

The invention provides a method and a system for realizing large-scale time-sensitive network asynchronous gating. The method comprises the following steps: two dual-port RAMs are arranged in a message processing pipeline, and two time windows corresponding to each gate control, namely a preparation time window and a working time window, are respectively stored in two different dual-port RAMs; dividing N continuous gating time windows into a group of access gating, and accessing gating time window information according to the group, wherein N is 2 n N is a natural number greater than 0; performing pipeline processing on the group of access gates and performing parallel computing processing on each gate of the group of access gates by a gate update module; wherein, the execution pipeline of the gating update module meets the following conditions: read and write operations to the same dual port RAM cannot be performed in parallel in the same clock cycle. The invention improves the scale quantity of the asynchronous gating of the time sensitive network in a low-cost mode, and simultaneously can keep the high precision of the gating.

Description

Method and system for realizing large-scale time-sensitive network asynchronous gating
Technical Field
The invention relates to the field of implementation of an Ethernet time sensitive network TSN integrated circuit, in particular to a method and a system for implementing large-scale time sensitive network asynchronous gating.
Background
The IEEE 802.1 TSN task group defines a time sensitive network, and a deterministic network with ultra-low time delay and jitter and high reliability is constructed through a set of protocol specifications. On the basis of 802.1AS time synchronization, protocol specifications such AS 802.1Qci and 802.1Qbv realize a time deterministic function and a function of periodic data aperiodic data simultaneous transmission by simulating Time Division Multiplexing (TDM).
The asynchronous gating based on streams implemented by 802.1Qci and the synchronous gating based on ports implemented by 802.1Qbv together complete the time-sensitive scheduling algorithm TAS. In a practical application scenario, for a TSN bridge, the number of streams to be managed is much larger than the number of access terminal devices, for example, in a TSN network having 0.5K (512) Talker terminal devices and 0.5K (512) Listener terminal devices, the number of streams may exceed 9K, and thus the corresponding stream gating needs to reach a certain number scale.
In implementing asynchronous gating, two windows are typically implemented through a ping-pong operation, and then the gating windows are updated through a timer or periodic refresh.
In the above prior art, the method for implementing gating update by using a timer is suitable for the situation with less gating number. The number and scale of the method for updating the gating by periodic refreshing are also limited by hardware performance, if each system clock updates one gating (one RAM access), in a system with a system clock frequency of 250MHz, to realize the gating with the gating precision of 5us, the refreshing period also needs to be 5us, and within 5us of one refreshing period, only 1250 gating can be updated at maximum, that is, the upper limit of the gating number is 1250 or less. While in practice more gating is required in some scenarios.
Disclosure of Invention
In order to solve the technical problem, the invention discloses a method and a system for realizing large-scale time-sensitive network asynchronous gating.
The embodiment of the invention provides a method for realizing large-scale time-sensitive network asynchronous gating, which comprises the following steps: two dual-port RAMs are arranged in a message processing pipeline, and two time windows corresponding to each gate control, namely a preparation time window and a working time window, are respectively stored in two different dual-port RAMs; dividing N successive gated time windows into a set of access doorsControlling and accessing the gated time window information in groups, wherein N is 2 n N is a natural number greater than 0; performing pipeline processing on the group of access gates and performing parallel computing processing on each gate of the group of access gates by a gate update module; wherein, the execution pipeline of the gating update module meets the following conditions: the read and write operations for the same dual port RAM cannot be performed in parallel in the same clock cycle.
In a further technical scheme, a gating updating module periodically updates gating in parallel in a pipeline mode, firstly two window groups Group1 and Group2 corresponding to one Group of access gating in two dual-port RAMs are read simultaneously according to groups, then each gating time window information in one Group of access gating is checked and calculated in parallel according to N paths, and finally the gating window groups Group1 and Group2 are written back to the dual-port RAMs simultaneously.
In a further technical solution, when updating the gating, if a start time currts of a refresh period of the gating, an end time tswin (end) of a working time window of the current refresh gating, and a gating refresh period T satisfy a condition currts +2 × T > ═ tswin (end), the preparation window is updated, otherwise, the gating information is not updated in the refreshing of the gating.
In a further technical scheme, a message processing pipeline receives a message with a timestamp, reads a gate control time window A and a gate control time window B corresponding to the message, and determines the belonging time window by comparing window boundaries, thereby executing a gate control operation set corresponding to the time window.
The embodiment of the invention also provides a system for realizing the large-scale time-sensitive network asynchronous gating, which comprises the following steps: the system comprises a message processing pipeline, a data processing unit and a data processing unit, wherein two dual-port RAMs are arranged in the message processing pipeline, so that two time windows corresponding to each gate control, namely a preparation time window and a working time window, are respectively stored in two different dual-port RAMs; a gate grouping module for dividing N continuous gate time windows into a group of access gates to access the gate time window information according to the group, wherein N is 2 n N is a natural number greater than 0; a gate update module that performs pipeline processing for a set of access gates and performs parallel computation processing for each of the set of access gates; wherein the execution pipeline of the gated update module satisfies the followingA piece: the read and write operations for the same dual port RAM cannot be performed in parallel in the same clock cycle.
In a further technical scheme, a gating updating module periodically updates gating in parallel in a pipeline mode, firstly two window groups Group1 and Group2 corresponding to one Group of access gating in two dual-port RAMs are read simultaneously according to groups, then each gating time window information in one Group of access gating is checked and calculated in parallel according to N paths, and finally the gating window groups Group1 and Group2 are written back to the dual-port RAM simultaneously.
In a further technical solution, when updating the gating, if a start time currts of a refresh period of the gating, an end time tswin (end) of a working time window of the current refresh gating, and a gating refresh period T satisfy a condition currts +2 × T > ═ tswin (end), the preparation window is updated, otherwise, the gating information is not updated in the refreshing of the gating.
In a further technical scheme, a message processing pipeline receives a message with a timestamp, reads a gate control time window A and a gate control time window B corresponding to the message, and determines the belonging time window by comparing window boundaries, thereby executing a gate control operation set corresponding to the time window.
Drawings
FIG. 1 is a block diagram of a system for implementing large scale time sensitive network asynchronous gating of the present invention;
FIG. 2 is an exemplary diagram of a memory model of the present invention for gating a time window at a time;
FIG. 3 is an exemplary diagram of a gated update module pipeline model of the present invention.
Detailed Description
The technical solution of the present invention will be further described with reference to the following specific examples, but the present invention is not limited to these examples.
The design points of the invention are as follows:
(1) each gate corresponds to two windows and is stored in two RAMs respectively, and the message processing pipeline module uses the two gate windows in a reading mode. And the door control updating module reads and writes the door control window to finish the updating operation of the door control.
(2) Dual port RAM is used to store gating window and behavior information.
(3) The gating windows are grouped and access gating is carried out according to groups, namely, one-time dual-port RAM reading or writing operation contains N (N can be 2, 4, 8, 16 and the like) pieces of gating window information, and the storage model of the gating window at a certain time can be referred to as shown in FIG. 2.
(4) The gated update module performs pipeline processing on the gated packets and satisfies the constraint: only one access to the same RAM is contained in the same system clock cycle.
(5) The gating update module performs parallel computation processing on each gating of a group of gating.
In an embodiment of the present invention, a method for implementing large-scale time-sensitive network asynchronous gating includes: two dual-port RAMs are arranged in a message processing pipeline, and two time windows corresponding to each gate control, namely a preparation time window and a working time window, are respectively stored in two different dual-port RAMs; dividing N continuous gating time windows into a group of access gating, and accessing gating time window information according to the group, wherein N is 2 n N is a natural number greater than 0; performing pipeline processing on the group of access gates and performing parallel computing processing on each gate of the group of access gates by a gate update module; wherein, the execution pipeline of the gating update module meets the following conditions: the read and write operations for the same dual port RAM cannot be performed in parallel in the same clock cycle.
In a further technical scheme, a gating updating module periodically updates gating in parallel in a pipeline mode, firstly two window groups Group1 and Group2 corresponding to one Group of access gating in two dual-port RAMs are read simultaneously according to groups, then each gating time window information in one Group of access gating is checked and calculated in parallel according to N paths, and finally the gating window groups Group1 and Group2 are written back to the dual-port RAMs simultaneously.
In a further technical solution, when updating the gating, if a start time currts of a refresh period of the gating, an end time tswin (end) of a working time window of the current refresh gating, and a gating refresh period T satisfy a condition currts +2 × T > ═ tswin (end), the preparation window is updated, otherwise, the gating information is not updated in the refreshing of the gating.
In a further technical scheme, a message processing pipeline receives a message with a timestamp, reads a gate control time window A and a gate control time window B corresponding to the message, and determines the belonging time window by comparing window boundaries, thereby executing a gate control operation set corresponding to the time window.
In another embodiment of the present invention, a system for implementing large-scale time-sensitive network asynchronous gating comprises: the system comprises a message processing pipeline, a data processing unit and a data processing unit, wherein two dual-port RAMs are arranged in the message processing pipeline, so that two time windows corresponding to each gate control, namely a preparation time window and a working time window, are respectively stored in two different dual-port RAMs; a gate grouping module for dividing N continuous gate time windows into a group of access gates to access the gate time window information according to the group, wherein N is 2 n N is a natural number greater than 0; the gate control updating module executes pipeline processing on the group of access gate controls and performs parallel computing processing on each gate control of the group of access gate controls; wherein, the execution pipeline of the gating update module meets the following conditions: read and write operations to the same dual port RAM cannot be performed in parallel in the same clock cycle.
In a further technical scheme, a gating updating module periodically updates gating in parallel in a pipeline mode, firstly two window groups Group1 and Group2 corresponding to one Group of access gating in two dual-port RAMs are read simultaneously according to groups, then each gating time window information in one Group of access gating is checked and calculated in parallel according to N paths, and finally the gating window groups Group1 and Group2 are written back to the dual-port RAMs simultaneously.
In a further technical solution, when updating the gating, if a start time currts of a refresh period of the gating, an end time tswin (end) of a working time window of the current refresh gating, and a gating refresh period T satisfy a condition currts +2 × T > ═ tswin (end), the preparation window is updated, otherwise, the gating information is not updated in the refreshing of the gating.
In a further technical scheme, a message processing pipeline receives a message with a timestamp, reads a gate control time window A and a gate control time window B corresponding to the message, and determines the belonging time window by comparing window boundaries, thereby executing a gate control operation set corresponding to the time window.
DETAILED DESCRIPTION OF EMBODIMENT (S) OF INVENTION
Referring to fig. 1, the system of the present invention includes a message processing pipeline and a gate control update module, two dual-port RAMs are built in the message processing pipeline for storing gate control information, each gate control corresponds to two time windows a and B, which are a current working time window and a reserved time window of the gate control respectively, the two time windows are stored in different dual-port RAMs respectively, a plurality of consecutive gate control windows are an access group, that is, the message processing pipeline and the gate control update module can read or write N pieces of gate control time window information at a time, and N can be 2, 4, 8, 16, etc. for facilitating memory allocation and address calculation. N continuous gating windows are an access group, N can be 2, 4, 8, 16 and the like, and the message processing pipeline and the gating updating module access gating window information according to groups. As shown in the storage model example of the gated windows of fig. 2 at a time, the working window a of gate 0 is stored in group 0 in the dual port RAM1, the preparation window B of gate 0 is stored in group 0 in the dual port RAM2, the working window a of gate 1 is stored in group 0 in the dual port RAM1, the preparation window B of gate 1 is stored in group 0 in the dual port RAM2, and so on.
The message processing pipeline receives the message with the timestamp, reads a gate control time window A and a gate control time window B corresponding to the message, and determines the time window through comparing the window boundary, thereby executing the gate control operation set corresponding to the time window.
The gating update module periodically updates gating in parallel in a pipeline manner, and if the precision of gating is T (for example, 5us), the gating update module needs to refresh all gating groups once by groups in the period T, and first reads two window groups Group1 and Group2 corresponding to one Group of gating in the dual-port RAM1 and the RAM2 simultaneously by groups, as in the RD operation in fig. 2. The gated time window information within a group is then updated by N-way parallel check, calculation, as in the operations in Op2 through Op7 in the example of FIG. 2. And when the gating is updated, if the starting time CurTs of the gating refreshing period of the current round, the ending time TsWin (end) of the working time window for refreshing the gating currently and the gating refreshing period T meet the condition CurTs + 2T > -TsWin (end), updating the preparation window, otherwise, the gating information is not updated in the current round of refreshing. Finally, gated window groups Group1 and Group2 are written back to the dual port RAM simultaneously, as in the WR operation of fig. 2.
The execution pipeline of the gated update module satisfies the condition: the read and write operations for the same dual port RAM cannot be performed in parallel in the same clock cycle. The RD operation and WR operation should be separated into different clock cycles as in the example of fig. 2.
In an embodiment, assuming that the window information is stored in 4 bytes, and one memory read/write operation is 32 bytes, the 32 bytes include 8 gating window information (N is 8), and in the RD (read) stage of the pipeline, the 32 bytes of the dual port 1 and the 32 bytes of the dual port RAM2 are read simultaneously, which correspond to eight gating windows a and B, respectively, of gates M, M +1 and M +2 … M +7(M is 0, 8, and 16 …), and the final WR (write back) is the same.
The embodiment of FIG. 3 shows an 8-stage pipeline (RD, Op2, Op3 … Op7, WR) that is to say that 8 operations, RD, Op2, Op3 … Op7, WR, are required to complete a set of gated updates, which are completed in 8 clock cycles in turn. The whole logic reads a group of gating information (RD) at one time, then completes the calculation processing of the gating time window in a mode of parallel execution of N paths (Op 2-Op 7), and finally writes back once (WR). Of course, it is understood that a 9-stage pipeline is also possible, with 7 steps in between Op 2-Op 8. The complexity of the gating computation may affect the need for multiple steps. That is, calculating the time window requires multiple steps, each of which can be completed in one clock cycle.
The invention has the beneficial technical effects
The invention can greatly improve the scale quantity of the asynchronous gating of the time sensitive network under the condition of not increasing the clock frequency of the system. According to the technical scheme, if 16 gates (N is 16) are read and written each time, the gated updating pipeline completes one group of gated refreshing operation every 2 system clock cycles, and then the gated refreshing of 8K scale is completed, and 1K (8K/16 x 2) system clock cycles are needed. If the system clock frequency is 250MHz, 8K-scale high-precision gated refresh can be achieved within 5us (containing 1250 system clock cycles).
The invention improves the scale quantity of the asynchronous gating of the time sensitive network in a low-cost mode, and simultaneously can keep the high precision of the gating.
The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various changes and modifications can be made without departing from the inventive concept of the present invention, and these changes and modifications are all within the scope of the present invention.

Claims (8)

1. A method for realizing large-scale time-sensitive network asynchronous gating is characterized by comprising the following steps:
two dual-port RAMs are arranged in a message processing pipeline, and two time windows corresponding to each gate control, namely a preparation time window and a working time window, are respectively stored in two different dual-port RAMs;
dividing N continuous gating time windows into a group of access gating, and accessing gating time window information according to the group, wherein N is 2 n N is a natural number greater than 0;
performing pipeline processing on the group of access gates and performing parallel computing processing on each gate of the group of access gates by a gate update module; wherein the content of the first and second substances,
the execution pipeline of the gated update module meets the following conditions: read and write operations to the same dual port RAM cannot be performed in parallel in the same clock cycle.
2. The method of claim 1, wherein the gating update module periodically updates the gating in parallel in a pipeline manner, first reading two window groups Group1 and Group2 corresponding to one Group of access gates in two dual-port RAMs simultaneously in groups, then checking and calculating and updating each gating time window information in one Group of access gates in parallel in N ways, and finally writing the gating window groups Group1 and Group2 back to the dual-port RAMs simultaneously.
3. The method according to claim 2, wherein when updating the gate control, if the starting time CurTs of the refresh period of the current gate control, the ending time tswin (end) of the working time window of the current refresh gate control and the gate control refresh period T satisfy the condition CurTs + 2T > -tswin (end), the preparation window is updated, otherwise the gate control information is not updated in the current refresh.
4. The method of claim 2, wherein the message processing pipeline receives the message with the timestamp, reads the corresponding gated time window a and the corresponding gated time window B of the message, and determines the corresponding gated time window by comparing the window boundaries, thereby executing the set of gated operations corresponding to the time window.
5. A system for implementing large-scale time-sensitive network asynchronous gating is characterized by comprising:
the system comprises a message processing pipeline, a data processing unit and a data processing unit, wherein two dual-port RAMs are arranged in the message processing pipeline, so that two time windows corresponding to each gate control, namely a preparation time window and a working time window, are respectively stored in two different dual-port RAMs;
a gate grouping module for dividing N continuous gate time windows into a group of access gates to access the gate time window information according to the group, wherein N is 2 n N is a natural number greater than 0;
a gate update module that performs pipeline processing for a set of access gates and performs parallel computation processing for each of the set of access gates; wherein the content of the first and second substances,
the execution pipeline of the gated update module satisfies the following conditions: the read and write operations for the same dual port RAM cannot be performed in parallel in the same clock cycle.
6. The system of claim 5, wherein the gating update module periodically updates the gating in parallel in a pipeline manner, first reads two window groups Group1 and Group2 corresponding to one Group of access gates in two dual-port RAMs simultaneously in groups, then checks and calculates and updates each gating time window information in one Group of access gates in parallel in N ways, and finally writes the gating window groups Group1 and Group2 back to the dual-port RAMs simultaneously.
7. The system according to claim 6, wherein when updating the gate control, if the starting time CurTs of the refresh period of the current gate control, the ending time TsWin (end) of the working time window of the current refresh gate control, and the gate control refresh period T satisfy the condition CurTs + 2T > -TsWin (end), the preparation window is updated, otherwise, the gate control information is not updated in the current refresh.
8. The system of claim 2, wherein the message processing pipeline receives the message with the timestamp, reads the corresponding gated time window a and the corresponding gated time window B of the message, and determines the corresponding gated time window by comparing the window boundaries, thereby performing the set of gating operations corresponding to the time window.
CN202210513686.9A 2022-05-12 2022-05-12 Method and system for realizing large-scale time-sensitive network asynchronous gating Pending CN114979030A (en)

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WO2019145028A1 (en) * 2018-01-24 2019-08-01 Renesas Electronics Corporation Time-sensitive networking
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CN114979030A (en) * 2022-05-12 2022-08-30 昆高新芯微电子(江苏)有限公司 Method and system for realizing large-scale time-sensitive network asynchronous gating

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