WO2010034327A1

WO2010034327A1 - Apparatus and method for emulating a full-rate finite state machine

Info

Publication number: WO2010034327A1
Application number: PCT/EP2008/008089
Authority: WO
Inventors: Jochen Rivoir
Original assignee: Verigy (Singapore) Pte. Ltd.
Priority date: 2008-09-24
Filing date: 2008-09-24
Publication date: 2010-04-01
Also published as: TW201033834A; TWI430124B

Abstract

A method for processing a full-rate input signal (u_n,...,u_n+R) having a first clock rate (f₁) and for providing a full-rate output signal (Y_n,..., Y_n+R) in dependence on the full-rate input signal (u_n,..., u_n+R), the method comprising deserializing the full-rate input signal (u_n,..., u_n+R-1) to obtain a sub-rate input signal (U_n) comprising a plurality of subsequent values of the full-rate input signal, such that the sub-rate input signal has a second clock rate (f₂) being a fraction of the first clock rate (f₁), updating a sub-rate internal state of a sub-rate finite state machine in dependence on a previous sub-rate internal state (z_n) and the sub-rate input signal (U_n) at the second clock rate (f₂), providing a sub-rate output signal (Y_n) in dependence on the previous or updated sub-rate internal state (z_n; z_n+R), the sub-rate output signal comprising a plurality of output values (Y_n,..., Y_n+R-1), and serializing the sub-rate output signal (Y_n) comprising the plurality of output values (Y_n,..., Y_n+R-1) to obtain a serialized output signal having the first clock rate (f₁) and having values equal to the full-rate output signal.

Description

Apparatus and method for emulating a full-rate finite state machine

The present invention relates to sequential control in digital circuits, and in particular to finite state machine (FSM) circuits.

Digital processing devices generally utilize FSM circuits where sequential control is required. A typical synchronous FSM circuit comprises several flip-flops which function to hold a previous internal state, and several decoding logic gates which function to determine a current or new internal state. An output signal from such an FSM circuit may, for example, be dependent on both the previous and/or present internal state at the time the flip-flops are clocked. Also, the output signal may for example be dependent on an input signal. In general, an internal state stores information about the past, i.e. it reflects input changes from a start to the present moment. A state transition indicates an internal state change and is described by a condition that would need to be fulfilled to enable the state transition. Hard-wired FSM circuits are limited in the range of functions that can be performed because control functions of the hard-wired FSM are fixed, i.e., each time the FSM circuit being in a particular state receives a certain input signal, then the output signal will be the same.

In order to enable a FSM to perform a greater range of functions, it is known to implement an FSM as a set of instructions (or using a set of instructions) for a microprocessor. Fig. 1 illustrates a conventional programmable FSM circuit 10 comprising a programmable logic array 11 (PLA) as a basic logical element. In a clock interval n, a first full-rate input signal U_n to the PLA 11 is provided via an external input line 12 and a second full-rate input Z_n for the PLA 11 is provided via a internal state register output line 13. The first full-rate input signal U_n may be of the form U_n= (ui [n] , u₂ [n] , ..., u_P [n] ) , wherein u_p[n] (p=l,...,P; P > 1) represents input signal values from an input signal value alphabet B. In case the values u_p[n] are binary values, i.e. u_p[n]e{0;l}, i.e. B = 2, the full-rate input signal vector U_n may then comprise B^p = 2^P values. The second full-rate input, i.e. a previous full-rate internal state, Z_n may be of the form Z_n= (Zi [n] , Z₂ [n] ,..., z_N[n] ) , wherein Z₁Jn] (i=l,...,N; N > 1) represents full-rate internal state values from an full- rate internal state value alphabet B. The internal state is sometimes also designated with x. A first full-rate output signal y_n= (yi [n] , y₂ [n] , ..., u_Q [n] ; Q > 1) from the PLA 11 is provided via an output line 14 and a second full-rate output Z_n+1= (zi [n+1] , Z₂ [n+1] ,..., z_N[n+l] ) from the PLA 11 is provided via a state register input line 15. The internal state register 18 has a signal output line 16 which divides in two routes. A first route 17 is coupled to another part of the system of which the full-rate FSM 10 is a subsection and the second route is the previous internal state which is the output line 13. In other words, the internal state register receives the second full-rate output signal Z_n+I describing a current state, stores the information describing the current state and provides the information describing the current state as a feedback to the PLA 11.

In operation, the full-rate input signal U_n on the external input line 12 is fed into the PLA 11 at a first clock-rate fi and the updated full-rate internal state

Z_n+i= (zi [n+1] , Z₂ [n+1] , ..., z_N[n+l] ) is input to the internal state register 18 via the internal state register input line 15 also at the first clock-rate fi. This updated internal state z_n+i is temporarily stored in the internal state register 18. When a new clock cycle commences, the PLA 11 receives two input signals, u_n and Z_n, i.e. a further full-rate input signal, via the external input line 12 and via the internal state register output line 13. The PLA 11 receives the internal state signal representing the previous state of the full-rate finite state machine 10 from the internal state register output line 13. The PLA 11 acts on these inputs according to a full-rate internal state update function according to z_n+i = f{z_n, ^un) if ε B^N+P x B^N) and a full-rate output function according to y_n = g(z_n, ¹Un) {9 £ B^N+P x B^Q) and outputs the full-rate output signal y_n to the output line 14 and an updated full-rate internal state Z_n+I to the register input line 15.

In case the first clock rate fi for clocking the full-rate input signal U_n and the full-rate output signal y_n is in the range of several GHz (Giga-Hertz) , it is required to provide a full-rate finite state machine circuit 10 which is also able to perform the internal state transitions at the first clock rate fi. Since today's finite state machine circuits are based on PLAs or RAMs (Random Access Memory) as basic logical elements, updating internal states with a clock frequency of several GHz is rather infeasible.

Hence, it would be desirable to emulate a full-rate FSM circuit by a sub-rate FSM architecture where logical elements of the sub-rate FSM, such as PLAs or RAMs, can run at a lower clock rate f₂ than the full-rate input and output signals U_n, Yn, but wherein the same output sequences (γ_n,y_n+ir -,Yn+R-i) are generated, compared to a full-rate FSM architecture, given the same input sequences (U_n, u_n+i, ..., U_n+Ri₁) . Further a method is needed to find internal state transition equations of a sub-rate FSM when the internal state transition equations -f(z_n/ U_n) (f e B^N+P x B^N) , g(z_n, U_n) (g e B^N+P x B^Q) of a full-rate FSM are given . This object is achieved by a method for obtaining a description of a full-rate finite state machine according to claim 1, a method for processing a full-rate input signal according to claim 7, an apparatus for obtaining a description of a full-rate finite state machine according to claim 20, an apparatus for processing a full-rate input signal according to claim 21 and a test-system according to claim 31.

According to a further aspect, the present invention provides a computer program for performing the inventive methods .

The present invention is based on the finding that the behavior of a full-rate finite state machine running at a first clock-rate fi can be emulated by sub-rate finite state machine running at a second clock-rate f₂ being smaller than the first clock-rate fi by merging a plurality of full-rate internal state transitions, e.g. Z_n+1 = f(z_n, U_n) , Z_n+2 = Jf(Z_n+I, u_n+i) , into a single sub-rate internal state transition, e.g. Z_n+2 = F(Z_n, U_n), U_n = (u_n, U_n+1). In particular, R (R > 1) subsequent full-rate internal state transitions at the first clock rate fi dependent on R subsequent full-rate input signals U_n, U_n+1, ..., u_n+R_i are merged into a single sub-rate internal state transition z_n+R = F(Z_n, U_n) at the second clock rate f₂ being a fraction of the first clock rate t_lr wherein the single sub-rate internal state transition Z_n —> z_n+R is dependent on a single sub-rate input signal U_n having the second clock- rate f₂ and . comprising R subsequent full-rate input signals U_n, U_n+1, ..., u_n+R-₁.

According to embodiments of the present invention a description F of a sub-rate internal state transition between a previous sub-rate internal state Z_n and an updated sub-rate internal state z_n+R of the sub-rate finite state machine can be obtained by subsequently inputting values of the full-rate input signal U_n, U_n+1, ..., U_n+^₁ comprised by the sub-rate input signal U_n to the full-rate finite state machine assuming the previous sub-rate internal state Z_n as an initial full-rate internal state of the full-rate finite state machine. The full-rate internal state z_n+R obtained after inputting the R-th full-rate input signal U_Π+R-_I to the full-rate finite state machine corresponds to the updated sub-rate internal state of the sub-rate finite state machine.

According to embodiments, a sub-rate output signal Y_n having the second clock rate f₂ comprises R values of the full-rate output signal y_n,Yn+ir -, Yn+R-i/ which would have been obtained with the full-rate finite state machine which is to be emulated by the sub-rate finite state machine. The sub-rate output signal Y_n can be obtained by inputting the sub-rate input signal U_n and the previous sub-rate internal state Z_n to a sub-rate output function G that outputs the sub-rate output signal Y_n comprising a plurality of output values y_n,y_n+i, ...,y_n+_R-i being equal to values of the full-rate output signal obtained by subsequently inputting values U_n, U_n+I, ...,u_n+R_i of the full-rate input signal comprised by the sub-rate input signal U_n to the full-rate finite state machine assuming the previous sub-rate internal state Z_n as initial full-rate internal state of the full-rate finite state machine.

Further, embodiments of the present invention provide a method for processing a full-rate input signal U_n having a first clock rate fi and for providing a full-rate output signal y_n in dependence on the full-rate input signal, comprising de-serializing the full-rate input signal U_n to obtain a sub-rate input signal U_n comprising a plurality of subsequent values of the full-rate input signal ^_n, u_n+i, ...,U_n+R-_!, such that the sub-rate input signal U_n has a second clock rate f₂ being a fraction of the first clock rate fi, updating a sub-rate internal state of a sub-rate finite state machine circuit in dependence on a previous sub-rate internal state Z_n and the sub-rate input signal U_n at the second clock rate f₂, providing a sub-rate output signal Y_n in dependence on the previous or updated sub-rate internal state z_n, z_n+R, the sub-rate output signal Y_n comprising a plurality of output values, and serializing the sub-rate output signal comprising the plurality of output values y_n,yn+i,-,y_n+R-i to obtain a serialized output signal having the first clock rate fi and having values equal to the full-rate output signal.

Yet further, embodiments of the present invention provide an apparatus comprising an input for a full-rate input signal U_n having a first clock rate fi, a de-serializer for converting the full-rate input signal U_n to a sub-rate input signal U_n having a second clock rate f₂ being a fraction of the first clock rate fi, a sub-rate finite state machine circuit configured to update a sub-rate internal state in dependence on a previous sub-rate internal state z_n and the sub-rate input signal U_n, and to provide a sub-rate output signal Y_n in dependence on the previous or updated sub-rate internal state Z_n, Z_n+R, and a serializer configured to serialize the sub-rate output signal Y_n to obtain a full-rate output signal y_n having the first clock rate fi. Thereby the sub-rate finite state machine is configured to update the sub-rate internal state at the second clock rate f₂.

According to further embodiments, an inventive apparatus may be comprised in a test system, the test system further comprising a device under test (DUT), configured to provide a DUT-signal in accordance with a communication protocol, wherein the apparatus comprised by the test system is configured to receive the DUT-signal or a signal derived therefrom as the full-rate input signal U_n, wherein the sub-rate finite state machine is configured to process the DUT-signal according to the communication protocol to follow a sequence of states of the communication protocol in dependence on the DUT-signal U_n, and wherein the sub- rate finite state machine is configured, such that a single transition between two subsequent sub-rate internal states z_nr z_n+R of the sub-rate finite state machine reflects a plurality of R subsequent transitions between subsequent communication protocol states Z_n → z_n+i -» ... -> Z_Π+R.

Yet further embodiments of the present invention provide a method and an apparatus for obtaining a description of a sub-rate finite state machine describing sub-rate internal state transitions between subsequent sub-rate internal states by deriving, from a description f of a full-rate finite state machine, a description F of the sub-rate finite state machine. The method comprises merging a plurality of subsequent full-rate internal state transitions Z_n —> Z_n+1 -» ... —> z_n+R into a single sub-rate internal state transition Z_n —> z_n+R.

Hence, embodiments of the present invention allow processing high speed input signals having a high clock rate fi with a finite state machine circuit operating at a lower clock frequency f₂, and providing output signals at the first clock frequency. The output signals thereby seem to be provided by a full-rate finite state machine circuit running at the first clock frequency fi. Hence it is possible to process high speed input signals with finite state machines circuits that are operated at a slower clock rate than the high speed input signals. In this way power consumption can be reduced, for example. Also, an implementation of high-speed re-configurable state machines can be facilitated in some embodiments.

Preferred embodiments of the present invention are described in detail with respect to the following drawings, in which:

Fig. 1 shows a block diagram of a conventional full-rate finite state machine circuit; Fig. 2 shows a block diagram of an apparatus for emulating the full-rate finite state machine of Fig. 1, according to an embodiment of the present invention;

Fig. 3 schematically depicts two clock signals having different clock-rates;

Fig. 4 shows a flow chart of a method for emulating a full- rate finite state machine, according to an embodiment of the present invention;

Fig. 5a shows an example of a state transition diagram of full-rate finite state machine;

Fig. 5b shows an input/state table according to the state transition diagram of Fig. 5a;

Fig. 5c shows an input/state table of a sub-rate finite state machine emulating a full-rate finite state machine having the state transition diagram of Fig. 5a;

Fig. 5d shows an input/output table according to the state transition diagram of Fig. 5a; and

Fig. 5e shows an input/output table of a sub-rate finite state machine for emulating the full-rate finite state machine according to Fig. 5a.

With respect to the following description, it is to be noted that in the different embodiments the same or similarly acting functional elements have the same reference numerals, and hence the descriptions of these functional elements in the various embodiments illustrated in the following are mutually interchangeable.

Fig. 2 illustrates an apparatus 20 for emulating a full- rate FSM according to an embodiment of the present invention. An exemplary full-rate FSM has been described above with regard to Fig. 1.

The apparatus 20 comprises a first input 22 for a full-rate input signal U_n, wherein subsequent values of the full-rate input signal are being clocked to the input terminal 22 with a first clock rate fi. Further, the apparatus 20 comprises a de-serializer 27 for converting the full-rate input signal U_n to a sub-rate input signal U_n wherein the sub-rate input signal O_n is clocked into a sub-rate finite state machine circuit 21 with a second clock rate t₂ being a fraction of the first clock rate fi. According to an embodiment of the present invention, the de-serializer 27 may be a circuit for a serial-to-parallel conversion of the full-rate input signal U_n. Hence, the de-serialized sub- rate input signal U_n may comprise R subsequent values U_n, u_n+i, ...,U_n+R-_! of the full-rate input signal, which are being clocked to the sub-rate FSM circuit 21 with the second clock rate f₂. The sub-rate FSM circuit 21, which may comprise a memory, in particular- a RAM, or a programmable logic device or a programmable logic array (PLA), is configured to update a sub-rate internal state in dependence on a previous sub-rate internal state Z_n fed to the sub-rate FSM circuit 21 by means of a second input 23 and in dependence on the sub-rate input signal U_n = [U_n, U_n+I,..., u_n+R_i]. Optionally, the sub-rate FSM circuit 21 may be configured to provide a sub-rate output signal Y_n in dependence on the previous or updated sub-rate internal state Z_n, Z_n+R. Thereby the sub-rate output signal Y_n comprises R signal values y_n/Y_n+i, -,γ_n+R-i that are fed into a serializer 28 in order serialize the sub-rate output signal Y_n to obtain full-rate output signals Y_n,y_n+i, ..., y_n+R-i having the first clock rate fi. . According to embodiments, the serializer circuit 28 may comprise a circuit for a parallel-to-serial conversion of the sub-rate output signal Y_n comprising R output signal values y_n/y_n+if -,Yn+R-i • The sub-rate FSM circuit 21 acts on the inputs in the form of the sub-rate input signal U_n = [U_n, u_n+i, ..., u_n+R-i] and the previous sub-rate internal state Z_n and outputs the sub- rate output signal Y_n = [ynrYn+i_*-./ YΠ+R-I] and an updated sub- rate internal state Z_n+R, both with the second clock rate f₂. The updated sub-rate internal state z_n+R is fed into a sub-rate internal state register 29, which may have a single output line 26 which may be divided into two routes. A first route is coupled to another part of the system of which the sub-rate FSM is a sub-section, and a second route is the state register output line 23.

According to embodiments, the de-serializer 27 is configured to serial-to-parallel-convert the full-rate input signal U_n, such that the sub-rate input signal U_n comprises, within a time interval T₂ (being inverse to the second clock rate f₂, i.e. T₂ = l/±z), a plurality of subsequent values U_n, u_n+i, ..., u_n+R_i of the full-rate input signal corresponding to a plurality of subsequent time intervals Ti, which intervals may be inverse to the first clock rate f_lr i.e. Ti = 1/fi.

Fig. 3 exemplarily shows a graphical representation of two different clock signals 32 and 34, wherein the first clock signal 32 has a first clock rate fi and wherein the second clock signal 34 has a second clock rate f₂. In the example given in Fig. 3, the first clock rate fi is twice the second rate f₂, i.e. f_!=2*f₂. The clock rates may be defined by the duration of the respective clock signal pulses. For the first clock signal 32 a clock signal has a period duration of Ti. For the second clock signal 34, a clock signal has a period duration of T₂. The relationship Ti/T₂ is inverse to the relationship fi/f₂. Since in this case the relationship Ti/T₂ is 1/2, the relationship of fi/f₂ is R=2. In general, the relationship fi/f₂ may be R (R > 1).

The de-serializer 27 may therefore be configured to serial- to-parallel convert R subsequent values U_n, u_n+i, ...,U_n+R-_! of the full-rate input signal, wherein R denotes the ratio of the full-rate frequency fi to the sub-rate frequency f₂.

In the following, let us assume that the apparatus 20 is designed for emulating the behavior, i.e. the state transitions, of the full-rate FSM 10. It is assumed that the full-rate FSM 10 runs at full-rate frequency fi with P input bits in vector U_n at rate fi, N state bits in vector Z_n at rate fi and Q output bits in vector y_n at rate fi.

U_n = (uχ[n], u₂[n],..., up[n]) € B^p (1)

Z_n= (Z₁Cn], z₂[n],..., z_N[n]) e B^N (2)

y_n = (yi[n], y₂[n],..., y_Q[n]) e B^Q (3)

Z_n+1 = f(«_n, U_n), £ e B^N+P x B^N (4)

y_n = g(z_n,u_n), g e B^N+P x B^Q (5)

That is, a memory comprised by the full-rate FSM circuit 11 may look up an updated full-rate internal state Z_n+1 and a full-rate output signal y_n as a function of the full-rate input U_n and the current full-rate internal state Z_n. N + P possible address inputs hence lead to N + Q possible data outputs .

Referring again to Fig. 2 the behavior of a sub-rate machine will be described. The full-rate de-serializer 27 combines R sequential full-rate input signals U_n, U_n+1, ...,U_n+R-_!^ to the sub-rate input signal U_n. U_n is hence updated at rate fi/R in this example. A memory comprised by the sub- rate FSM circuit 21 may run at the second frequency f₂ = fi/R. The sub-rate output signal Y_n, which contains R subsequent output values y_n,y_n+1, ...,y_n+R-i? is also updated at the second clock rate f₂. The relationships between updated sub-rate internal states z_n+R, sub-rate output signals Y_n and sub-rate input signals U_n and previous sub-rate internal states Z_n can be summarized as follows:

U_n = (U_n, U_n+1,...,U_n+R-_!) € B^PxR (6)

Yn = (Yn, Yn₊I, -,Yn₊R-I) ≡ B^QxR (7) z_n+R = F(Z_n, U_n) , F e B^N+P*R x B^N (8) Y_n = G(Z_n, U_n) , G e B^N+p*R x B^Q*R (9)

In general this means, that the sub-rate FSM circuit 21 may look up the updated sub-rate internal state z_n+R in a time interval T₂ corresponding to R time intervals Ti as a function of the current sub-rate internal state Z_n and the last R values u_n,u_n+i, ...,u_n+R-i of the full-rate input signal. In other words, for the sub-rate FSM we have N + P x R possible memory address inputs and N + Q * R possible data outputs .

The question is now how to choose the sub-rate internal state update function F(Z_n, U_n), F e B^N+P*R x B^N, and the sub- rate output function G(Z_n, U_n), G e B^N+P*R x B^Q*R, for given full-rate internal state update functions £(z_n,u_n), f e. B^N+P x B^N, full-rate output functions g(z_n,U_n), g e B^N+P x B^Q, and the full-rate to sub-rate clock rate ratio R.

Iteratively applying the full-rate internal state update function f(z_n,u_n), f e B^N+P x B^N, to the current sub-rate internal state Z_n and the R values u_n,u_n+i, ...,U_n+R-_! of the sub-rate input signal U_n yields the updated sub-rate internal state z_n+R corresponding to a full-rate internal state after R clock periods Ti. That is, the desired sub- rate internal state update function F(Z_n, U_n), F 6 B^N+P*R X B^N, may be determined in the following way:

Z_n+1 = £(z_n,u_π) (10) Z_n+2 = f ( z_n+i , u_n+i ) = f ( f ( Z_n , U_n) , u_{n+ 1} ) ( H )

z_n+« =fC_l;(f(f(z_π, U_n), U_n+1 ),...), u_π+/M ) ( 12 !

R tones

Z_n+R = F(Z_n , U_n , U_n+1 ,..., U_n+Λ_, )) 1 3 '

z_n+R = F( Z_n , U_n ) ( 14 )

Hence, according to embodiments of the present invention, the sub-rate FSM circuit 21 is configured to update the sub-rate internal state by inputting the sub-rate input signal U_n and the previous sub-rate internal state z_n to the sub-rate internal state update function F(z_n,U_n) , F e g^N+p*R _χ g^N _^ that outputs the updated sub-rate internal state z_n+R, wherein the sub-rate internal state update function JP(SS_n, U_n), Jf e B^N+P*R x B^N, is configured such that the updated sub-rate internal state z_n+R is equal to a full-rate internal state obtained by subsequently inputting R values U_n, u_n+i, ..., U_n+R-_! of the full-rate input signal comprised by the sub-rate input signal U_n to a full-rate FSM circuit assuming the previous sub-rate internal state Z_n as initial full-rate internal state of the full-rate FSM circuit.

That is, in case an updated full-rate internal state z_n+i depends on the previous full-rate internal state Z_n and the full-rate input signal U_n according to Z_n+1 = £(z_n,u_n), with f denoting the full-rate internal state update function, the sub-rate internal state update function F(Z_n, U_n), F 6 _β ^N+p*R _χ g^N^ between the updated sub-rate internal state z_n+R and the previous sub-rate internal state Z_n and the sub- rate input signal U_n comprising the plurality of full-rate input signals u_n, u_n+i, ..., u_n+R_i I S based on z_n+R =fC_1;(f(f(z_n,uJ₅u_π+I),...),u_π+Λ.1) .

R times

Regarding the sub-rate output signal Y_n, each of the full- rate output signals y_n,y_n+i, -,Yn+R-i comprised by the sub-rate output signal Y_n this determined by the full-rate output equation y_n+k = g"(z_n+k, u_n+k) . The full-rate internal state z_n+k after k clock periods with the first clock rate fi can be determined according to

z_n+* =£0-^(2,,,u_n),u_π+1),...),u_n+jt_,) (is: k tones

To obtain the sub-rate output signal Y_n all R subsequent values y_n,yn+i,

of the full-rate output signal may be combined according to

γ_n = G(Z_n,U_n,U_n+1 ,...,u,,_+/M) = G(Z_n,U_n) (17) u.

Hence, according to embodiments of the present invention, the sub-rate FSM circuit 21 is configured to provide the sub-rate output signal Y_n by inputting the sub-rate input signal U_n and the previous sub-rate internal state Z_n to the sub-rate output function G that outputs the sub-rate output signal Y_n comprising a plurality of output values, wherein the sub-rate output function G is configured such that the sub-rate output signal Y_n comprises values yn,y_n+i,-,yn+R-i of a full-rate output signal which could be obtained by subsequently inputting values U_n, u_n+i, ...,U_n+R-_!, of the full-rate input signal comprised by the sub-rate input signal U_n, to a full-rate finite state machine assuming the previous sub-rate internal state Z_n as initial full-rate internal state of the full-rate finite state machine.

In case the sub-rate output signal Y_n comprises at least two full-rate output signal values y_n, y_n+i_> the first full- rate output signal value y_n solely depends on a first full- rate input signal value U_n comprised by the sub-rate input signal U_n and the previous sub-rate internal state Z_n according to y_n = g(z_n,u_n). The second full-rate output signal value y_n+i solely depends on a second full-rate input signal value u_n+i, the first full-rate input value U_n and the previous sub-rate internal state Z_n according to y_n+i = g(f(z_n,u_n), U_n+1), etc.

In case of a memory-based sub-rate FSM circuit 21 the memory content may be predetermined by evaluating the sub- rate internal state update function F and the sub-rate output function G for each of the 2^N+PxR combinations that correspond to all possible combinations of the sub-rate internal states (N bits) and the sub-rate input signal U_n (P x R input bits) .

Alternatively, the sub-rate FSM machine 21 may be implemented using a programmable logic device, for example using a field programmable gate array. The internal state update function may in this case be implemented using a logic circuit for mapping an internal state to a subsequent internal state or successor internal state. For example, a table or logic table (or any other logic description) may be established which describes a mapping between an internal state and a successor internal state. A logic circuit structure for implementation in a field programmable gate array (which may be adapted to a hardware available in the field programmable gate array) may be derived from the table or logic table (or form any other logic description) using any logic circuit design approach. A logic design optimization may also be used, for example to reduce a complexity of the logic circuit.

According to an embodiment of the present invention the apparatus 20 is configured to determine the sub-rate internal state update function F and to determine the sub- rate output function G automatically based on the known full-rate internal state up-date function f, the known full-rate output function g and the ratio R = fi/f2- Hence the apparatus 20 may be configurable in order to emulate a plurality of different full-rate FSM circuits, given respective f, g and R. That is, according to embodiments, the apparatus 20 comprises an apparatus for obtaining a description of a full-rate FSM describing a transition between subsequent full-rate internal states according to z_n+i = f(z_n, U_n), f e B^N+P x B^N, by deriving, from the description f of the full-rate finite state machine, a description F of the sub-rate finite state machine comprising merging a plurality of full-rate internal state transitions into a single sub-rate internal state transition. Thereby, R subsequent full-rate internal states ( or state transitions) updated at the first clock rate fi, dependent on R subsequent full-rate input signals U_n, u_n+i, ...,u_n+R_i, are merged into a single sub-rate internal state transition at the second clock rate at f₂ being a fraction of the first clock rate fi, dependent on one single sub-rate input signal (or signal vector) U_n comprising the R subsequent full-rate input signals (or signal vectors) u_n,u_n+i, ...,u_n+R-i . Obtaining the description F of the sub-rate finite state machine based on the description f of the full-rate finite state machine can be performed, for example, by a computer or a micro-controller comprised by the apparatus 20.

To summarize, the apparatus depicted in Fig. 2 can be used to perform a method for processing a full-rate input signal U_n having a first clock rate fi and for providing a full- rate output signal y_n in dependence on the full-rate input signal, wherein the method is exemplarily shown in Fig. 4.

The inventive method comprises a first step 41 of de- serializing the full-rate input signal (or input signal vector) U_n to obtain the sub-rate input signal (or input signal vector) U_n comprising (for example in a parallel representation) a plurality of subsequent values U_n, u_n+i, ...,u_n+R_i of the full-rate input signal, such that the sub-rate input signal (or input signal) U_n has the second clock rate f₂ being a fraction of the first clock rate fi . In a second step 42 a sub-rate internal state of the sub- rate FSM circuit 21 is updated in dependence on a previous sub-rate internal state Z_n and the sub-rate input signal U_n at the second clock rate f₂. In a third step 43 the sub- rate output signal Y_n is provided in dependence on the previous or updated sub-rate internal state Z_n z_n+R, wherein the sub-rate output signal Y_n comprises a plurality of output values y_n,y_n+i, ...,y_n+R-i- In a further step 44 the sub- rate output signal Y_n is serialized to obtain the serialized output signal having the first clock rate f_1#

As described before, the method referred to in Fig. 4 can be used to emulate a full-rate FSM circuit by means of a sub-rate FSM circuit. Updating the internal sub-rate internal state comprises a plurality of subsequent full- rate internal state updates or transitions in one single sub-rate internal state update step or transition. This can be achieved, for example, by updating the sub-rate internal state by looking up the updated sub-rate internal state z_n+R at a memory position depending on the sub-rate input signal U_n and the previous sub-rate internal state Z_n.

Of course, the same may hold true for the sub-rate output signal Y_n. Providing the sub-rate output signal Y_n comprises a plurality of subsequent full-rate output signal provisions in one single output signal provision step. This can be achieved by looking up the sub-rate output signal Y_n at a memory position depending on the sub-rate input signal U_n and/or the previous or updated sub-rate internal state

The emulation of a full-rate FSM shall be explained in more detail referring to a simple example given in the Figs. 5a to 5e.

Fig. 5a shows a state transition diagram 50 of a simple and exemplary full-rate FSM having four full-rate internal states 51 ("0"), 52 ("1"), 53 ("2") and 54 ("3"). The arrows from and to the individual full-rate internal states denote state transitions depending on a full-rate input value τi_n=(ui[n]) e {0,1}. For example, if the full-rate FSM is in initial state 51 ("0") and a "0" is input to the full-rate FSM the updated full-rate internal state will be again state 51 ("0"). However, if a "1" is received as input signal, there will be a state transition from internal state 51 ("0") to internal state 52 ("1") . Assuming current internal state 52 ("1") and a current full-rate input "1", a state transition to internal state 53 ("2") will happen. In case of a "0" as full-rate input signal, internal state 52 ("1") will transition to internal state 54 ("3") , etc.

The related state update/transition table is shown in Fig. 5b.

In the left column a respective current full-rate internal state Z_n is shown. The middle column represents the current full-rate input signal U_n. The right column shows the updated full-rate internal state z_n+i depending on the current full-rate internal state and the full-rate input signal according to z_n+i = -£(z_n,u_n). Hence, the table shown in Fig. 5b describes the full-rate internal state update function f(Z_n, Ti_n). The updated full-rate internal state Z_n+1 can be determined by performing a table look-up in a memory depending on the current full-rate internal state z_n and the current full-rate input U_n. In this example, this would require a look-up table with eight (B^N+P = 2²⁺¹) entries, corresponding to four (B^N = 2²) internal states and two (B^p = 2¹) possible input values.

The full-rate FSM having state transitions according to Fig. 5a can be emulated by a sub-rate FSM according to embodiments of the present invention. This shall be explained in the following.

If two subsequent values U_n, u_n+i of the full-rate input signal are combined to the sub-rate input signal U_n the state transitions of the full-rate FSM can be emulated as shown by the sub-rate state transition table in Fig. 5c. The sub-rate state transition table of Fig. 5c corresponds to a state transition diagram (not shown) , where each state serves as a source and a destination for four (2²) data transition arrows, not only two as shown in Fig. 5a. Starting from the current sub-rate internal Z_n state, the updated sub-rate internal state Z_n+2 can be determined by subsequently applying the full-rate update function £ according to eq. (13). For example, being in current internal sub-rate state 52 ("1") the first value U_n of the sub-rate input signal U_n defines a first "invisible" state transition according to f(z_n,u_n) . If the first value U_n is "1", then there would be an "invisible" state transition from internal state 52 ("1") to internal state S3 ("2") . Applying the second input value U_n+1 to this new invisible state £(z_n,u_n) yields the updated sub-rate internal state Z_n+2 according to f(f(Z_n, U_n) ,U_n+1) . If the second value u_n+i of the sub-rate input signal U_n is "1", there would be a state transition from the invisible state 53 ("2") to the updated sub-rate state 54 ("3") , as can be verified with Fig. 5a. Consequently, applying the inventive concept, one can fill the sub-rate state update table as shown in Fig. 5c, which describes the sub-rate internal state update function F = f{f(z_n, u_n) , U_n+1) . The sub-rate internal state updates can be again realized by a table lookup depending on the current sub-rate internal state z_n and the combined sub-rate input signal U_n. As there are still four sub-rate internal state possibilities but, however, four possibilities for a combined sub-rate input signal U_n, this results in a look-up table size of 16 values for Z_n+2.

Fig. 5d shows an exemplary output table according to an exemplary full-rate output function Cj(Z_n, U_n).

Fig. 5e reflects how the sub-rate output signal Y_n comprising the two values y_n, y_n+i of the full-rate output signal can be obtained based on the sub-rate internal state z_n and the sub-rate input signal U_n. The first value y_n of the sub-rate output signal only depends on the sub-rate Z_n and first value U_n of the sub-rate input signal. The second value y_n+i depends on the sub-rate internal state Z_n, the first value U_n of the sub-rate input signal and the second value U_n+1 of the sub-rate input signal according to y_n+i = g( z_n+i, U_n+I) = g-(z_n,u_n,u_n+i) . This relationship can be pre- computed for each combination of sub-rate internal states Z_n and sub-rate input signal U_n, which yields a look up table comprising 16 entries for Y_n = [y_n, y_n+i] . The correct sub-rate output signal entry can be chosen by using memory address indices comprising the sub-rate internal state Z_n and the sub-rate input signal U_n.

Embodiments of the present invention can be used for building test systems for testing a test object or a device under test (DUT) according to a predefined communication protocol, wherein a communication protocol comprises a set of standard rules for data representation, signaling, authentication and error detection required to send information over a communications channel. Thereby the communication protocol may comprise a certain number of valid communication protocol states.

Hence, embodiments of the present invention provide a test system comprising a DUT, configured to provide a DUT-signal in accordance with the communication protocol, and an apparatus for emulating a full-rate FSM according to an embodiment of the present invention, wherein the apparatus is configured to receive the DUT-signal or a signal derived there from as the full-rate input signal u_n, wherein the sub-rate FSM circuit of the apparatus is configured to process the DUT-signal according to the communication protocol to follow a sequence of states of the communication protocol in dependence on the DUT signal, and wherein the sub-rate FSM circuit is configured, such that a single transition between two subsequent sub-rate internal states of the sub-rate FSM circuit reflects a plurality of subsequent transitions between subsequent communication protocol states.

In some embodiments, the sub-rate FSM circuit may define transitions between a plurality of valid communication protocol states and at least one transition into an invalid communication protocol state in response to a communication protocol violation. In this case the test system may be configured to provide an error detection signal, in case the DUT-signal leads to a sub-rate internal state which indicates a violation of the communication protocol. The sub-rate FSM circuit defines transitions between a plurality of communication protocol states. According to embodiments of the present invention, the sub-rate FSM circuit is configured to extract useful data from the DUT- signal communicated in accordance with the communication protocol and to provide a serialized output signal corresponding to the useful data comprised by the DUT signal. Thereby the useful data does not comprise any signaling information of the communication protocol, but preferably unknown information data.

Within the test system, the sub-rate FSM circuit can be used to simulate a communication between the DUT and other components of a network, wherein the network components communicate by means of the communication protocol . Embodiments of the present invention allow to use FSM circuits comprising slow, cheap and power-saving FSM circuit components, such as, for example, low cost memory devices. These slower FSM circuit components may be clocked with a slower clock rate than full-rate input signals to and full-rate output signals from the sub-rate FSM circuit.

Depending on the circumstances, the inventive method for emulating a full-rate FSM may be implemented in hardware or in software. The implementation may be done on a digital storage medium, particularly a disc or a CD with electronically readable control signals, which may cooperate with a programmable computer system such that the method is executed. In general, the invention does also consist in a computer program product with a program code stored on a machine readable carrier for performing the inventive method when the computer program product runs on a computer and/or micro-controller. In other words, the invention may be thus realized as a computer program with a program code for performing the method when the computer program runs on a computer.

While this invention has been described in terms of several preferred embodiments, there are alternations, permutations and equivalents which fall within the scope of this invention. It should also be noted that there are many alternative ways of implementing the methods and compositions of the present invention. It is therefore intended that the following appended claims be interpreted as including all such alterations, permutations and equivalents as forwarded in the true spirit in the scope of the present invention.

Claims

1. A method for obtaining a description of a sub-rate finite state machine (10) , for performing a functionality of a full-rate finite state machine using the sub-rate state machine, the method comprising:

obtaining a description of the full-rate state machine, the description describing full-rate internal state transitions between subsequent full-rate internal states; and

deriving, from the description of the full-rate finite state machine, a description of the sub-rate finite state machine (20) ,

wherein deriving the description of the sub-rate finite state machine comprises merging a plurality of full-rate internal state transitions into a single sub-rate internal state transition.

2. The method according to claim 1, wherein deriving the description of the sub-rate finite state machine comprises merging R > 2 subsequent full-rate internal state transitions dependent on R subsequent full-rate input signals into a single sub-rate internal state transition dependent on one single sub-rate input signal comprising the R subsequent full-rate input signals .

3. The method according to claim 1 or 2, wherein deriving a description of a sub-rate internal state transition between a previous sub-rate internal state and an updated sub-rate internal state comprises applying a full-rate state transition function to the previous sub-rate internal state multiple times, to obtain the updated sub-rate internal state,

wherein the full-rate state transition function describes a transition between subsequent full-rate states .

4. The method according to claim 3, wherein applying the full-rate state transition function to the previous sub-rate internal state multiple times comprises taking into consideration temporally subsequent signal values of one or more input signals.

5. The method according to claim 3 or 4, wherein a plurality of different state transitions from a given previous sub-rate internal state to corresponding updated sub-rate internal states is evaluated, wherein the state transitions of the plurality of different state transitions are associated with different sequences of temporally subsequent input signal values .

6. The method according to one of claims 1 to 5, wherein deriving the description of the sub-rate finite state machine comprises deriving a description of a sub-rate internal state transition between a previous sub-rate internal state Z_n and an updated sub-rate internal state z_n+R of the sub-rate finite state machine using the relationship

with f(',') denoting a description of transitions between subsequent full-rate internal states in dependence on a previous full-rate internal state z_n and one or more full-rate input signals and with U_n,...,u_n+R-i denoting R > 2 subsequent full-rate input signals comprised by one single sub-rate input signal.

The method according to one of the preceding claims, wherein deriving the description of the sub-rate finite state machine comprises applying a full-rate output function to an information describing the updated sub-rate internal state, to obtain a component of a sub-rate output function.

The method according to one of the preceding claims, wherein deriving the description of the sub-rate finite state machine comprises deriving a description of a sub-rate output signal based on a previous sub- rate internal state (Z_n) and a sub-rate input signal (U_n) comprising R subsequent full-rate input signal values or R subsequent sets of input signal values u_n ... u_n+R-i according to

Y. £(/(*« iθ,)»o.₊i)

with g(',') denoting a description of a relationship between a full-rate output signal, a full-rate internal state and a full-rate input signal.

A method for processing a full-rate input signal (u_n,...,u_n+R) having a first clock rate (f_x) and for providing a full-rate output signal (y_n,..., YΠ+_R) in dependence on the full-rate input signal (u_n, ..., u_n+R) , the method comprising:

de-serializing the full-rate input signal (u_n, ...,u_n+_R_i) to obtain a sub-rate input signal (U_n) comprising a plurality of subsequent values of the full-rate input signal, such that the sub-rate input signal has a second clock rate (f₂) being a fraction of the first clock rate (fi) ;

updating a sub-rate internal state of a sub-rate finite state machine in dependence on a previous sub- rate internal state (z_n) and the sub-rate input signal (U_n) at the second clock rate (f₂) ;

providing a sub-rate output signal (Y_n) in dependence on the previous or updated sub-rate internal state (z_n; Z_Π+_R) I the sub-rate output signal comprising a plurality of output values (y_n,..., Yn+R-i) ; and

serializing the sub-rate output signal (Y_n) comprising the plurality of output values (y_n,..., Yn+R-i) to obtain a serialized output signal having the first clock rate (fi) and having values equal to the full-rate output signal.

10. The method according to claim 9, wherein deserializing the full-rate input signal (U_n, ..., u_n+R) comprises a serial-to-parallel conversion, such that the sub-rate input signal (U_n) comprises, within a time interval (IZf₂) inverse to the second clock rate (f₂), a plurality of subsequent values of the full- rate input signal (U_n, ..., u_n+R) corresponding to a plurality of subsequent time intervals (1/fi) inverse to the first clock rate (fi) .

11. The method according to claim 9 or 10, wherein updating the sub-rate internal state comprises inputting the sub-rate input signal (U_n) and the previous sub-rate internal state (Z_n) to a sub-rate internal state update function (F) that outputs the updated sub-rate internal state (Z_Π+R) , wherein the sub-rate internal state update function is configured such that the updated sub-rate internal state is equal to a full-rate internal state of a full-rate finite state machine, which would be obtained by subsequently inputting values of the full-rate input signal (u_n, ...,U_n+R-_I ) comprised by the sub-rate input signal (U_n) to the full-rate finite state machine assuming the previous sub-rate internal state (Z_n) as an initial full-rate internal state of the full-rate finite state machine.

12. The method according to claim 11, wherein an updated full-rate internal state (z_n+i) depends on the previous full-rate internal state (Z_n) and the full-rate input signal (u_n) according to

^Z _n+. =/(«„.«„)

with f^~(",") denoting a full-rate internal state update function, and wherein the sub-rate internal state update function (F) describing a relationship between the updated sub-rate internal state z_n+R and the previous sub-rate internal state z_n in dependence on the sub-rate input signal comprising the plurality of full-rate input signals U_n, ...,U_n+R-_! is based on a relationship of the form

z_n+« = /(-(/(/(»„«„),"_n+i ),-),^IWi) ,

R times

whererin n is a time index , and wherein R is an integer greater than one describing how many full-rate state transitions are merged in a sub-rate state transition.

13. The method according to one of claims 9 to 12, wherein providing the sub-rate output signal (Y_n) comprises inputting the sub-rate input signal (U_n) and the previous sub-rate internal state (z_n) or the updated sub-rate internal state to a sub-rate output function (G) that outputs the sub-rate output signal comprising a plurality of output values (y_n,..., y_n+R-i) r wherein the sub-rate output function is chosen such that the output values of the sub-rate output signal are equal to values of the full-rate output signal which would be obtained by subsequently inputting values (U_n, ...,U_n+R-_I) of the full-rate input signal comprised by the sub-rate input signal (U_n) to the full-rate finite state machine assuming the previous sub-rate internal state as initial full-rate internal state of the full- rate finite state machine.

14. The method according to claim 13, wherein the sub-rate output signal (Y_n) comprises at least two full-rate output signal values (y_n,y_n+i), wherein a first full- rate output signal value (y_n) solely depends on the first full-rate input signal value (u_n) comprised by the sub-rate input signal (Y_n) and the previous sub- rate internal state (z_n), and wherein a second full- rate output signal value (y_n+i) depends on a second full-rate input signal value (U_n+1), the first full- rate input signal value (u_n) and the previous sub-rate internal state (z_n) .

15. The method according to claim 13 or 14, wherein one of the full-rate output signal values (y_n) depends on the previous full-rate internal state (z_n) and the full- rate input signal according to

y_π = ^g(z_n>^uJ

with g{' ,') denoting a full-rate output function, and wherein the sub-rate output function (G) relating the sub-rate output signal (Y_n) and the previous sub-rate internal state (Z_n) in dependence on the sub-rate input signal (U_n) comprising the plurality of full- rate input signal values (U_n, ..., u_n+R_i) is based on a relationship of the form

Y.

with f(',') denoting a full-rate internal state update function .

16. The method according to one of claims 9 to 15, wherein updating the internal sub-rate internal state (z_n) comprises a plurality of subsequent full-rate internal state updates in one single sub-rate internal state update step.

17 The method according to one of claims 9 to 16, wherein updating the sub-rate internal state comprises looking up the updated sub-rate internal state (z_n+R) at a memory position depending on the sub-rate input signal (U_n) and the previous sub-rate internal state (z_n) .

The method according to one of claims 9 to 17, wherein providing the sub-rate output signal (Y_n) comprises providing a plurality of subsequent full-rate output signal values in one single output signal provision step.

19. The method according to one of claims 9 to 18, wherein providing the sub-rate output signal (Y_n) comprises looking up the sub-rate output signal at a memory position depending on the sub-rate input signal (U_n) and the previous or updated sub-rate internal state

.

20. The method according to one of claims 9 to 19, wherein serializing the sub-rate output signal (Y_n) comprises a parallel-to-serial conversion, such that the serialized output signal comprises, within a time interval (l/f2) inverse to the second clock rate Cf₂), a plurality of subsequent values of the full-rate output signal (y_n, ...,y_n+R-i) corresponding to a plurality of subsequent time intervals (1/fi) inverse to the first clock rate (fi) .

21. A computer program having a program code for performing a method according to one of the preceding claims, when the program code runs on a computer and/or micro-controller.

22. An apparatus, comprising:

an input (22) for a full-rate input signal (u_n,...,u_n+R-i) having a first clock rate (fi);

a deserializer (27) for converting the full-rate input signal (U_n, ...,U_n+R-_!) to a sub-rate input signal (U_n) having a second clock rate (f₂) being a fraction of the first clock rate (fi) ;

a sub-rate finite state machine (21) configured to update a sub-rate internal state in dependence on a previous sub-rate internal state (z_n) and the sub-rate input signal (U_n) , and to provide a sub-rate output signal (Y_n) in dependence on the previous or updated sub-rate internal state (z_n; z_n+R) ; and

a serializer (28) configured to serialize the sub-rate output signal (Y_n) to obtain a full-rate output signal having the first clock rate (fi) ,

wherein the sub-rate finite state machine is configured to update the sub-rate internal state at the second clock rate (f₂) .

23. The apparatus according to claim 22, wherein the deserializer (27) is configured to serial-to-parallel convert the full-rate input signal (u_n, ...,u_n+R) , such that the sub-rate input signal (U_n) comprises, within a time interval (T₂) inverse to the second clock rate (f₂) , a plurality of subsequent values of the full- rate input signal (u_n, ...,u_n+R) corresponding to a plurality of subsequent time intervals (Ti) inverse to the first clock rate (fi) .

24. The apparatus according to claim 22 or 23, wherein the sub-rate finite state machine (21) is configured to updated the sub-rate internal state by inputting the sub-rate input signal (U_n) and the previous sub-rate internal state (z_n) to a sub-rate internal state update function (F) that outputs the updated sub-rate internal state (z_n+R) , wherein the sub-rate internal state update function (F) is configured such that the updated sub-rate internal state is equal to a full- rate internal state obtained by subsequently inputting values of the full-rate input signal (u_n, ..., u_n+R_i) comprised by the sub-rate input signal (U_n) to a full- rate finite state machine assuming the previous sub- rate internal state (z_n) as initial full-rate internal state of the full-rate finite state machine.

25. The apparatus according to one of claims 22 to 24, wherein the sub-rate finite state machine (21) is configured to provide the sub-rate output signal (Y_n) by inputting the sub-rate input signal (U_n) and the previous sub-rate internal state (Z_n) to a sub-rate output function (G) that outputs the sub-rate output signal comprising a plurality of output values (y_n,_..., Yn₊R-i) , wherein the sub-rate output function (G) is configured such that sub-rate output signal (Y_n) comprises values of a full-rate output signal which would be obtained by subsequently inputting values (u_n, ..., u_n+R_i ) of the full-rate input signal comprised by the sub-rate input signal (U_n) to a full-rate finite state machine assuming the previous sub-rate internal state as initial full-rate internal state of the full-rate finite state machine.

26. The apparatus according to one of claims 22 to 25, wherein the sub-rate finite state machine (21) is configured to determine a sub-rate internal state update function (F) for updating the sub-rate internal state based the sub-rate input signal (U_n) and the previous sub-rate internal state (z_n) and to determine a sub-rate output function (G) for outputting the sub- rate output signal based on the sub-rate input signal (U_n) and the previous sub-rate internal state (z_n) , wherein determining the sub-rate internal state update function (F) and the sub-rate output function (G) is performed automatically based on a full-rate internal state update function (£) and a full-rate output function {g) .

27. The apparatus according to one of claims 22 to 26, wherein the sub-rate finite state machine (21) is configured to provide the sub-rate output signal (Y_n) with at least two full-rate output signal values (yn_^Yn+i) r wherein a first full-rate output signal value (y_n) solely depends on a first full-rate input signal value (u_n) comprised by the sub-rate input signal (Y_n) and the previous sub-rate internal state

(Z_n) , and wherein a second full-rate output signal value (y_n+i) solely depends on a second full-rate input signal value (u_n+i) , the first full-rate input signal value (u_n) and the previous sub-rate internal state

(Z_n) •

28. The apparatus according to one of claims 22 to 27, wherein the sub-rate finite state machine (21) is configured to update the sub-rate internal state by looking up the updated sub-rate internal state (z_n+R) at a memory position depending on the sub-rate input signal (U_n) and the previous sub-rate internal state

(Zn) •

29. The apparatus according to one of claims 22 to 28, wherein the sub-rate finite state machine (21) is configured to provide the sub-rate output signal (Y_n) comprising a plurality of subsequent full-rate output signal values in one single output signal provision step, such that the plurality of subsequent full-rate output signal values is provided simultaneously.

30. The apparatus according to one of claims 22 to 29, wherein the sub-rate finite state machine (21) is configured to provide the sub-rate output signal (Y_n) by looking up the sub-rate output signal at a memory- position depending on the sub-rate input signal (U_n) and the previous or updated sub-rate internal state (Z_n; 2_n+R) .

31. The apparatus according to one of claims 22 to 30, wherein the serializer (28) is configured to serialize the sub-rate output signal (Y_n) via a parallel-to- serial conversion, such that the serialized output signal comprises, within a time interval (T₂) inverse to the second clock rate (f₂), a plurality of subsequent values of the full-rate output signal (Ynr -/Yn+_R-i) corresponding to a plurality of subsequent time intervals (Ti) inverse to the first clock rate (U₁).

32. A test system comprising:

a device under test, configured to provide a DUT- signal (u_n) in accordance with a communication protocol; and an apparatus according to one of claims 22 to 31, wherein the apparatus is configured to receive the DUT-signal or a signal derived therefrom as the full- rate input signal (u_n) ,

wherein the sub-rate finite state machine (21) is configured to process the DUT-signal (u_n) according to the communication protocol to follow a sequence of states of the communication protocol in dependence on the DUT-signal, and

wherein the sub-rate finite state machine (21) is configured, such that a single transition between two subsequent sub-rate internal states of the sub-rate finite state machine reflects a plurality of subsequent transitions between subsequent communication protocol states.

33. The test system according to claim 32, wherein the sub-rate finite state machine (21) defines transitions between a plurality of valid communication protocol states and at least one transition into an invalid communication protocol state in response to a communication protocol violation and wherein the test system is configured to provide an error detection signal, in case the DUT-signal leads to an internal state which indicates a violation of the communication protocol .

34. The test system according to claim 32 or 33, wherein the sub-rate finite state machine defines transitions between a plurality of communication protocol states and wherein the sub-rate finite state machine is configured extract from the DUT-signal useful data communicated in accordance with the communication protocol and to provide a serialized output signal corresponding to the useful data comprised by the DUT- signal .