CN114975417A - 三维扇出型内存封装pop结构及其封装方法 - Google Patents

三维扇出型内存封装pop结构及其封装方法 Download PDF

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CN114975417A
CN114975417A CN202210475755.1A CN202210475755A CN114975417A CN 114975417 A CN114975417 A CN 114975417A CN 202210475755 A CN202210475755 A CN 202210475755A CN 114975417 A CN114975417 A CN 114975417A
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packaging
layer
metal
peripheral circuit
out type
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CN202210475755.1A
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陈彦亨
林正忠
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SJ Semiconductor Jiangyin Corp
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Shenghejing Micro Semiconductor Jiangyin Co Ltd
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Priority to CN202210475755.1A priority Critical patent/CN114975417A/zh
Publication of CN114975417A publication Critical patent/CN114975417A/zh
Priority to US18/139,748 priority patent/US20230352451A1/en
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Abstract

本发明提供一种三维扇出型内存封装POP结构及其封装方法，该结构包括：三维扇出型内存封装单元，包括：两片以上呈阶梯型构造层叠的内存芯片，第一金属连接柱，与内存芯片的焊垫电连接，第一封装层，第一重新布线层，第一金属凸块，形成于第一重新布线层上；及二维扇出型外围电路芯片SiP封装单元，包括：第二重新布线层，外围电路芯片，第三重新布线层，接合于外围电路芯片上，第二金属连接柱，第二封装层，包覆外围电路芯片及金属连接柱，第二金属凸块，形成于第二重新布线层上；第一金属凸块与第三重新布线层键合。该结构可以进行高密度高集成线宽线距；制程时间短，效率高；可使封装结构的厚度大幅降低，实现中道至后道取代基板的封装工艺形式。

Description

三维扇出型内存封装POP结构及其封装方法
技术领域
本发明属于半导体封装技术领域，特别是涉及一种三维扇出型内存封装POP结构及其封装方法。
背景技术
传统基板制作，电路板/线路板(Printed Circuit Board简称PCB)，用于电子元器件的支撑体，是电子元器件电气连接的载体。批量应用的多为1-12层，芯片I/O越多基板层数就越多，价格也就越高。制程也有一定极限，目前线宽/线距只能到20μm，正常普遍都是50μm以上，当前道芯片制造功能集成越高，未来基板技术将无法满足前道需求，所以逐渐发展出各种不同形式的先进封装方式，例如2.5D&Fan out wafer level先进封装技术，但这类技术相对于基板制造来说造价高且制作时间长。
发明内容
鉴于以上所述现有技术的缺点，本发明的目的在于提供一种三维扇出型内存封装POP结构及其封装方法，用于解决现有技术中采用基板制作进行半导体封装制造成本高、体积大等的问题。
为实现上述目的及其他相关目的，本发明提供一种三维扇出型内存封装POP结构，所述POP结构包括：三维扇出型内存封装单元及与其键合的二维扇出型外围电路芯片SiP封装单元；
所述三维扇出型内存封装单元包括：两片以上呈阶梯型构造层叠的内存芯片，所述内存芯片上具有焊垫，且所述焊垫设置于所述阶梯型构造的阶梯台面上；第一金属连接柱，形成于所述焊垫上并与所述焊垫电连接；第一封装层，包覆所述内存芯片及所述第一金属连接柱，且所述第一封装层的顶面显露所述第一金属连接柱；第一重新布线层，形成于所述第一封装层上，且与所述第一金属连接柱电连接；第一金属凸块，形成于所述第一重新布线层上；
所述二维扇出型外围电路芯片SiP封装单元包括：第二重新布线层；至少一个呈二维排布且电连接于所述第二重新布线层上的外围电路芯片；第三重新布线层，接合于所述外围电路芯片上；第二金属连接柱，设置于所述外围电路芯片的外侧，分别与所述第二重新布线层及所述第三重新布线层电连接；第二封装层，包覆所述外围电路芯片及所述第二金属连接柱；第二金属凸块，形成于所述第二重新布线层上；
所述第一金属凸块与所述第三重新布线层键合，实现所述三维扇出型内存封装单元与所述二维扇出型外围电路芯片SiP封装单元的键合。
可选地，所述第一金属连接柱的材料包括金、银、铝、铜中的至少一种；所述第二金属连接柱的材料包括金、银、铝、铜中的至少一种。
可选地，所述焊垫的材料包括金属铝；所述第一封装层的材料包括聚酰亚胺、硅胶及环氧树脂中的一种；所述第二封装层的材料包括聚酰亚胺、硅胶及环氧树脂中的一种。
可选地，所述第一重新布线层、所述第二重新布线层及所述第三重新布线层包括介质层及金属布线层，所述介质层的材料包括由环氧树脂、硅胶、PI、PBO、BCB、氧化硅、磷硅玻璃及含氟玻璃组成的群组中的一种或两种以上组合；所述金属布线层的材料包括由铜、铝、镍、金、银及钛组成的群组中的一种或两种以上组合。
可选地，所述第一金属凸块及所述第二金属凸块包括金锡焊球、银锡焊球、铜锡焊球中的一种，或者，所述第一金属凸块及所述第二金属凸块包括金属柱，以及形成于所述金属柱上的焊球。
本发明还提供一种三维扇出型内存封装POP结构的封装方法，所述封装方法包括：
提供三维扇出型内存封装单元及二维扇出型外围电路芯片SiP封装单元；其中，所述三维扇出型内存封装单元包括：两片以上呈阶梯型构造层叠的内存芯片，所述内存芯片上具有焊垫，且所述焊垫设置于所述阶梯型构造的阶梯台面上；第一金属连接柱，形成于所述焊垫上并与所述焊垫电连接；第一封装层，包覆所述内存芯片及所述第一金属连接柱，且所述第一封装层的顶面显露所述第一金属连接柱；第一重新布线层，形成于所述第一封装层上，且与所述第一金属连接柱电连接；第一金属凸块，形成于所述第一重新布线层上；所述二维扇出型外围电路芯片SiP封装单元包括：第二重新布线层；至少一个呈二维排布且电连接于所述第二重新布线层上的外围电路芯片；第三重新布线层，接合于所述外围电路芯片上；第二金属连接柱，设置于所述外围电路芯片的外侧，分别与所述第二重新布线层及所述第三重新布线层电连接；第二封装层，包覆所述外围电路芯片及所述第二金属连接柱；第二金属凸块，形成于所述第二重新布线层上；
将所述第一金属凸块与所述第三重新布线层进行键合，实现所述三维扇出型内存封装单元与所述二维扇出型外围电路芯片SiP封装单元的键合。
可选地，形成所述三维扇出型内存封装单元的方法包括：
提供两片以上具有所述焊垫的所述内存芯片，并将所述内存芯片呈阶梯形构造层叠；
于所述焊垫上形成所述第一金属连接柱；
采用所述第一封装层封装所述内存芯片及所述第一金属连接柱，并使所述第一封装层的顶面显露所述第一金属连接柱；
于所述第一封装层上形成所述第一重新布线层，所述第一金属连接柱与所述第一重新布线层电连接；
于所述第一重新布线层上形成所述第一金属凸块。
进一步地，采用表面贴装工艺将所述内存芯片层叠。
可选地，形成所述二维扇出型外围电路芯片SiP封装单元的方法包括：
形成所述第二重新布线层；
于所述第二重新布线层上电连接至少一个呈二维排布的所述外围电路芯片；
于所述第二重新布线层上电连接所述第二金属连接柱，所述第二金属连接柱形成于所述外围电路芯片的外侧；
采用所述第二封装层封装所述外围电路芯片及所述第二金属连接柱；
于所述外围电路芯片及所述第二金属连接柱上形成所述第三重新布线层；其中，所述第三重新布线层接合于所述外围电路芯片上，所述第二金属连接柱与所述第三重新布线层电连接；
于所述第二重新布线层上形成所述第二金属凸块。
可选地，形成所述第一封装层及所述第二封装层后还包括对其表面进行研磨或抛光的步骤。
如上所述，本发明的三维扇出型内存封装POP结构及其封装方法，采用扇出型方式并通过重新布线层实现三维扇出型内存封装单元及二维扇出型外围电路芯片SiP封装单元的堆叠型封装(Package On Package封装，简称POP封装)，得到内存封装POP结构，另外通过第一金属连接柱实现内存芯片电路的引出，整个封装结构不需要通过TSV孔实现电路引出，有效降低封装成本；且省去了传统的电子元器件封装所需的电路基板，可以进行高密度高集成线宽线距，达到1.5μm/1.5μm；制程时间短，效率高；还可使封装结构的厚度大幅降低；最后可以实现中道至后道取代基板的一条龙封装工艺形式。
附图说明
图1显示为本发明的三维扇出型内存封装POP结构中层叠内存芯片的结构示意图。
图2显示为本发明的三维扇出型内存封装POP结构中三维扇出型内存封装单元的结构示意图。
图3显示为本发明的三维扇出型内存封装POP结构中二维扇出型外围电路芯片SiP封装单元的结构示意图。
图4显示为本发明的三维扇出型内存封装POP结构。
元件标号说明
10 三维扇出型内存封装单元
101 内存芯片
102 焊垫
103 第一金属连接柱
104 第一封装层
105 第一重新布线层
106 介质层
107 金属布线层
108 第一金属凸块
109 第一接合层
20 二维扇出型外围电路芯片SiP封装单元
201 第二重新布线层
202 外围电路芯片
203 第三重新布线层
204 第二封装层
205 第二金属凸块
206 第二金属连接柱
207 底部填充层
208 第二接合层
具体实施方式
以下通过特定的具体实例说明本发明的实施方式，本领域技术人员可由本说明书所揭露的内容轻易地了解本发明的其他优点与功效。本发明还可以通过另外不同的具体实施方式加以实施或应用，本说明书中的各项细节也可以基于不同观点与应用，在没有背离本发明的精神下进行各种修饰或改变。
请参阅图1至图4。需要说明的是，本实施例中所提供的图示仅以示意方式说明本发明的基本构想，遂图示中仅显示与本发明中有关的组件而非按照实际实施时的组件数目、形状及尺寸绘制，其实际实施时各组件的型态、数量及比例可根据实际需要进行改变，且其组件布局型态也可能更为复杂。
实施例一
如图2至图4所示，本实施例提供一种三维扇出型内存封装POP结构，所述POP结构包括：三维扇出型内存封装单元10及与其键合的二维扇出型外围电路芯片SiP封装单元20；
如图2所示，所述三维扇出型内存封装单元10包括：两片以上呈阶梯型构造层叠的内存芯片101，所述内存芯片101上具有焊垫102，且所述焊垫102设置于所述阶梯型构造的阶梯台面上；第一金属连接柱103，形成于所述焊垫102上并与所述焊垫102电连接；第一封装层104，包覆所述内存芯片101及所述第一金属连接柱103，且所述第一封装层104的顶面显露所述第一金属连接柱103；第一重新布线层105，形成于所述第一封装层104上，且与所述第一金属连接柱103电连接；第一金属凸块108，形成于所述第一重新布线层105上；
如图3所示，所述二维扇出型外围电路芯片SiP封装单元20包括：第二重新布线层201；至少一个呈二维排布且电连接于所述第二重新布线层201上的外围电路芯片202；第三重新布线层203，接合于所述外围电路芯片202上；第二金属连接柱206，设置于所述外围电路芯片202的外侧，分别与所述第二重新布线层201及所述第三重新布线层203电连接；第二封装层204，包覆所述外围电路芯片202及所述第二金属连接柱206；第二金属凸块205，形成于所述第二重新布线层201上；
如图4所示，所述第一金属凸块108与所述第三重新布线层203键合，实现所述三维扇出型内存封装单元10与所述二维扇出型外围电路芯片SiP封装单元20的键合。
本实施例提供的三维扇出型内存封装POP结构，采用扇出型方式并通过重新布线层实现三维扇出型内存封装单元及二维扇出型外围电路芯片SiP封装单元的堆叠型封装(Package On Package封装，简称POP封装)，得到内存封装POP结构，另外通过第一金属连接柱实现内存芯片电路的引出，整个封装结构不需要通过TSV孔实现电路引出，有效降低封装成本；且省去了传统的电子元器件封装所需的电路基板，可以进行高密度高集成线宽线距，达到1.5μm/1.5μm；制程时间短，效率高；还可使封装结构的厚度大幅降低；最后可以实现中道至后道取代基板的一条龙封装工艺形式。
所述内存芯片101可以是现有的任意适于三维层叠的存储芯片，例如：DRAM、SRAM、闪存、EEPROM、PRAM、MRAM和RPAM等等，在此不做过分限制。另外，阶梯形构造的存储芯片层叠结构中，每层内存芯片101的功能可以相同也可以不同，每层内存芯片101的大小可以相同也可以不同，每层内存芯片101的阶梯台面的大小可以相同也可以不同，以上参数可根据封装结构的具体要求进行设定，在此不作限制。所述外围电路芯片202主要用以驱动和控制所述内存芯片101，其中可能会包括外围电路晶体管及外围逻辑电路，外围逻辑电路包括但不限于，静态随机存取存储器(SRAM)、锁相环(PLL)、中央处理器(CPU)、现场可编程门阵列(FPGA)等，具体根据不同的芯片及功能进行设置，在此不作限制。
如图4所示，所述第一金属连接柱103作为所述焊垫102与所述第一重新布线层105之间的电连接通道，以实现所述内存芯片101信号的引出，所述第二金属连接柱206作为所述第二重新布线层201与所述第三重新布线层203之间的电连接通道，以实现所述外围电路芯片202信号的引出，所述第一金属连接柱103及所述第二金属连接柱206的材料选择为导电性能较佳，且不易扩散的材料，例如，所述第一金属连接柱103的材料可以选择金、银、铝、铜中的至少一种，所述第二金属连接柱206的材料可以选择金、银、铝、铜中的至少一种。但也不限于此，其他较佳的导电材料也可。
如图1及图2所示，所述内存芯片101上的所述焊垫102的材料包括金属铝，为铝焊垫。制备所述焊垫102时，为了提高焊垫的电学性能及与内存芯片101的粘接性能等，还可在所述焊垫102下形成粘接层，在所述焊垫102上形成抗反射层。
如图4所示，作为示例，所述第一封装层104的材料包括聚酰亚胺、硅胶及环氧树脂中的一种；同理，所述第二封装层204的材料包括聚酰亚胺、硅胶及环氧树脂中的一种。所述第一封装层104及所述第二封装层204的顶面均为经过研磨或抛光的平整表面，以提高后续形成的重新布线层的质量以及封装体的封装质量。
如图1至图4所示，所述第一重新布线层105、所述第二重新布线层201及所述第三重新布线层203包括介质层106及金属布线层107，所述介质层106的材料包括由环氧树脂、硅胶、PI、PBO、BCB、氧化硅、磷硅玻璃及含氟玻璃组成的群组中的一种或两种以上组合；所述金属布线层107的材料包括由铜、铝、镍、金、银及钛组成的群组中的一种或两种以上组合。这里需要说明的是，所述第一重新布线层105、所述第二重新布线层201及所述第三重新布线层203包括介质层106及金属布线层107，但不同位置的重新布线层的材料、层数及分布形貌，具体根据实际需要进行设置，在此不作限制。
如图1至图4所示，所述第一金属凸块108及所述第二金属凸块205包括金锡焊球、银锡焊球、铜锡焊球中的一种，或者，所述第一金属凸块108及所述第二金属凸块205包括金属柱，以及形成于所述金属柱上的焊球，较佳地，所述金属柱为铜柱或镍柱。在本实施例中，所述第一金属凸块108及所述第二金属凸块205为金锡焊球，其制作步骤包括：首先形成金锡层，然后采用高温回流工艺使所述金锡层回流成球状，降温后形成金锡焊球；或者采用植球工艺形成金锡焊球。
实施例二
本实施例提供一种三维扇出型内存封装POP结构的封装方法，上述实施例一的三维扇出型内存封装POP结构可以采用该封装方法制备，但不限于本实施例的封装方法。
具体地，如图1至图4示意出了本实施例中三维扇出型内存封装POP结构的封装方法各步骤所呈现的结构示意图。
如图1至图3所示，首先进行步骤S1，提供三维扇出型内存封装单元10及二维扇出型外围电路芯片SiP封装单元20；其中，如图2所示，所述三维扇出型内存封装单元10包括：两片以上呈阶梯型构造层叠的内存芯片101，所述内存芯片101上具有焊垫102，且所述焊垫102设置于所述阶梯型构造的阶梯台面上；第一金属连接柱103，形成于所述焊垫102上并与所述焊垫102电连接；第一封装层104，包覆所述内存芯片101及所述第一金属连接柱103，且所述第一封装层104的顶面显露所述第一金属连接柱103；第一重新布线层105，形成于所述第一封装层104上，且与所述第一金属连接柱103电连接；第一金属凸块108，形成于所述第一重新布线层105上；如图3所示，所述二维扇出型外围电路芯片SiP封装单元20包括：第二重新布线层201；至少一个呈二维排布且电连接于所述第二重新布线层201上的外围电路芯片202；第三重新布线层203，接合于所述外围电路芯片202上；第二金属连接柱206，设置于所述外围电路芯片202的外侧，分别与所述第二重新布线层201及所述第三重新布线层203电连接；第二封装层204，包覆所述外围电路芯片202及所述第二金属连接柱206；第二金属凸块205，形成于所述第二重新布线层201上。
如图1及图2所示，作为一具体示例，形成所述三维扇出型内存封装单元10的方法包括：
如图1所示，S11、提供两片以上具有所述焊垫102的所述内存芯片101，并将所述内存芯片101呈阶梯形构造层叠。具体地，可先提供一支撑基底，并于支撑基底上形成分离层，然后将内存芯片101层叠接合在分离层上。较佳地，可采用表面贴装工艺将内存芯片101层叠接合于分离层上，相邻两内存芯片101之间以及内存芯片101与分离层之间通过第一接合层109实现粘合。
如图1所示，S12、于所述焊垫102上形成所述第一金属连接柱103。可以采用电镀或化学镀的方法形成所述第一金属连接柱103。
如图1所示，S13、采用所述第一封装层104封装所述内存芯片101及所述第一金属连接柱103，并使所述第一封装层104的顶面显露所述第一金属连接柱103。可以采用压缩成型、传递模塑成型、液,封成型、真空层压或旋涂等方法形成所述第一封装层104，较佳地，形成所述第一封装层104后，可采用研磨或者抛光的方法作用于所述第一封装层104的上表面，以提供表面平整的所述第一封装层104，提高产品质量。
如图2所示，S14、于所述第一封装层104上形成所述第一重新布线层105，所述第一金属连接柱103与所述第一重新布线层105电连接。作为示例，形成所述第一重新布线层105包括以下步骤：首先采用化学气相沉积工艺或物理气相沉积工艺形成介质层，并对所述介质层进行刻蚀形成图形化的介质层106；然后采用化学气相沉积工艺、物理气相沉积工艺、溅射工艺、电镀工艺或化学镀工艺于所述图形化的介质层106表面形成金属布线层，并对所述金属布线层进行刻蚀形成图形化的金属布线层107。这里需要说明的是，所述介质层106及所述金属布线层107的材料、层数及分布形貌，可根据不同存储芯片的具体情况进行设置，在此不作限制。
如图2所示，S15、于所述第一重新布线层105上形成所述第一金属凸块108。作为示例，所述第一金属凸块108包括金锡焊球、银锡焊球、铜锡焊球中的一种，或者，所述第一金属凸块108包括金属柱，以及形成于所述金属柱上的焊球，较佳地，所述金属柱为铜柱或镍柱。在本实施例中，所述第一金属凸块108为金锡焊球，其制作步骤包括：首先于所述第一重新布线层105表面形成金锡层，然后采用高温回流工艺使所述金锡层回流成球状，降温后形成金锡焊球；或者采用植球工艺形成金锡焊球。这里需要说明的是，形成所述第一金属凸块108后，去除分离层及支撑基底，得到所述三维扇出型内存封装单元10。
如图3所示，作为一具体示例，形成所述二维扇出型外围电路芯片SiP封装单元20的方法包括：形成所述第二重新布线层201；于所述第二重新布线层201上电连接至少一个呈二维排布的所述外围电路芯片202；于所述第二重新布线层201上电连接第二金属连接柱206，所述第二金属连接柱206形成于所述外围电路芯片202的外侧；采用所述第二封装层204封装所述外围电路芯片202及所述第二金属连接柱206，形成所述第二封装层204后，可采用研磨或者抛光的方法作用于所述第二封装层204的上表面，以提供表面平整的所述第二封装层204，提高产品质量；于所述外围电路芯片202及所述第二金属连接柱206上形成所述第三重新布线层203；其中，所述第三重新布线层203接合于所述外围电路芯片202上，所述第二金属连接柱206电连接于所述第三重新布线层203上；于所述第二重新布线层201上形成所述第二金属凸块205。所述外围电路芯片202与所述第二重新布线层201之间可设置底部填充层207，以提高两者之间的结合强度并保护第二重新布线层201。所述外围电路芯片202可通过第二接合层208与所述第三重新布线层203接合连接。
作为示例，所述第二重新布线层201及所述第三重新布线层203的制备方法可参照上述第一重新布线层105的制备方法，在此不再赘述。
如图4所示，然后进行步骤S2，将所述第一金属凸块108与所述第三重新布线层203进行键合，实现所述三维扇出型内存封装单元10与所述二维扇出型外围电路芯片SiP封装单元20的键合，得到本申请的三维扇出型内存封装POP结构。
综上所述，本发明的三维扇出型内存封装POP结构及其封装方法，采用扇出型方式并通过重新布线层实现三维扇出型内存封装单元及二维扇出型外围电路芯片SiP封装单元的堆叠型封装(Package On Package封装，简称POP封装)，得到内存封装POP结构，另外通过第一金属连接柱实现内存芯片电路的引出，整个封装结构不需要通过TSV孔实现电路引出，有效降低封装成本；且省去了传统的电子元器件封装所需的电路基板，可以进行高密度高集成线宽线距，达到1.5μm/1.5μm；制程时间短，效率高；还可使封装结构的厚度大幅降低；最后可以实现中道至后道取代基板的一条龙封装工艺形式。所以，本发明有效克服了现有技术中的种种缺点而具高度产业利用价值。
上述实施例仅例示性说明本发明的原理及其功效，而非用于限制本发明。任何熟悉此技术的人士皆可在不违背本发明的精神及范畴下，对上述实施例进行修饰或改变。因此，举凡所属技术领域中具有通常知识者在未脱离本发明所揭示的精神与技术思想下所完成的一切等效修饰或改变，仍应由本发明的权利要求所涵盖。

Claims (10)

1.一种三维扇出型内存封装POP结构，其特征在于，所述POP结构包括：三维扇出型内存封装单元及与其键合的二维扇出型外围电路芯片SiP封装单元；
所述三维扇出型内存封装单元包括：两片以上呈阶梯型构造层叠的内存芯片，所述内存芯片上具有焊垫，且所述焊垫设置于所述阶梯型构造的阶梯台面上；第一金属连接柱，形成于所述焊垫上并与所述焊垫电连接；第一封装层，包覆所述内存芯片及所述第一金属连接柱，且所述第一封装层的顶面显露所述第一金属连接柱；第一重新布线层，形成于所述第一封装层上，且与所述第一金属连接柱电连接；第一金属凸块，形成于所述第一重新布线层上；
所述二维扇出型外围电路芯片SiP封装单元包括：第二重新布线层；至少一个呈二维排布且电连接于所述第二重新布线层上的外围电路芯片；第三重新布线层，接合于所述外围电路芯片上；第二金属连接柱，设置于所述外围电路芯片的外侧，分别与所述第二重新布线层及所述第三重新布线层电连接；第二封装层，包覆所述外围电路芯片及所述第二金属连接柱；第二金属凸块，形成于所述第二重新布线层上；
所述第一金属凸块与所述第三重新布线层键合，实现所述三维扇出型内存封装单元与所述二维扇出型外围电路芯片SiP封装单元的键合。
2.根据权利要求1所述的三维扇出型内存封装POP结构，其特征在于：所述第一金属连接柱的材料包括金、银、铝、铜中的至少一种；所述第二金属连接柱的材料包括金、银、铝、铜中的至少一种。
3.根据权利要求1所述的三维扇出型内存封装POP结构，其特征在于：所述焊垫的材料包括金属铝；所述第一封装层的材料包括聚酰亚胺、硅胶及环氧树脂中的一种；所述第二封装层的材料包括聚酰亚胺、硅胶及环氧树脂中的一种。
4.根据权利要求1所述的三维扇出型内存封装POP结构，其特征在于：所述第一重新布线层、所述第二重新布线层及所述第三重新布线层包括介质层及金属布线层，所述介质层的材料包括由环氧树脂、硅胶、PI、PBO、BCB、氧化硅、磷硅玻璃及含氟玻璃组成的群组中的一种或两种以上组合；所述金属布线层的材料包括由铜、铝、镍、金、银及钛组成的群组中的一种或两种以上组合。
5.根据权利要求1所述的三维扇出型内存封装POP结构，其特征在于：所述第一金属凸块及所述第二金属凸块包括金锡焊球、银锡焊球、铜锡焊球中的一种，或者，所述第一金属凸块及所述第二金属凸块包括金属柱，以及形成于所述金属柱上的焊球。
6.一种三维扇出型内存封装POP结构的封装方法，其特征在于，所述封装方法包括：
提供三维扇出型内存封装单元及二维扇出型外围电路芯片SiP封装单元；其中，所述三维扇出型内存封装单元包括：两片以上呈阶梯型构造层叠的内存芯片，所述内存芯片上具有焊垫，且所述焊垫设置于所述阶梯型构造的阶梯台面上；第一金属连接柱，形成于所述焊垫上并与所述焊垫电连接；第一封装层，包覆所述内存芯片及所述第一金属连接柱，且所述第一封装层的顶面显露所述第一金属连接柱；第一重新布线层，形成于所述第一封装层上，且与所述第一金属连接柱电连接；第一金属凸块，形成于所述第一重新布线层上；所述二维扇出型外围电路芯片SiP封装单元包括：第二重新布线层；至少一个呈二维排布且电连接于所述第二重新布线层上的外围电路芯片；第三重新布线层，接合于所述外围电路芯片上；第二金属连接柱，设置于所述外围电路芯片的外侧，分别与所述第二重新布线层及所述第三重新布线层电连接；第二封装层，包覆所述外围电路芯片及所述第二金属连接柱；第二金属凸块，形成于所述第二重新布线层上；
将所述第一金属凸块与所述第三重新布线层进行键合，实现所述三维扇出型内存封装单元与所述二维扇出型外围电路芯片SiP封装单元的键合。
7.根据权利要求6所述的三维扇出型内存封装POP结构的封装方法，其特征在于，形成所述三维扇出型内存封装单元的方法包括：
提供两片以上具有所述焊垫的所述内存芯片，并将所述内存芯片呈阶梯形构造层叠；
于所述焊垫上形成所述第一金属连接柱；
采用所述第一封装层封装所述内存芯片及所述第一金属连接柱，并使所述第一封装层的顶面显露所述第一金属连接柱；
于所述第一封装层上形成所述第一重新布线层，所述第一金属连接柱与所述第一重新布线层电连接；
于所述第一重新布线层上形成所述第一金属凸块。
8.根据权利要求7所述的三维扇出型内存封装POP结构的封装方法，其特征在于：采用表面贴装工艺将所述内存芯片层叠。
9.根据权利要求6所述的三维扇出型内存封装POP结构的封装方法，其特征在于，形成所述二维扇出型外围电路芯片SiP封装单元的方法包括：
形成所述第二重新布线层；
于所述第二重新布线层上电连接至少一个呈二维排布的所述外围电路芯片；
于所述第二重新布线层上电连接所述第二金属连接柱，所述第二金属连接柱形成于所述外围电路芯片的外侧；
采用所述第二封装层封装所述外围电路芯片及所述第二金属连接柱；
于所述外围电路芯片及所述第二金属连接柱上形成所述第三重新布线层；其中，所述第三重新布线层接合于所述外围电路芯片上，所述第二金属连接柱与所述第三重新布线层电连接；
于所述第二重新布线层上形成所述第二金属凸块。
10.根据权利要求6所述的三维扇出型内存封装POP结构的封装方法，其特征在于：形成所述第一封装层及所述第二封装层后还包括对其表面进行研磨或抛光的步骤。
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CN110718522A (zh) * 2018-07-12 2020-01-21 三星电子株式会社 半导体封装件
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Patent Citations (3)

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CN109427759A (zh) * 2017-08-29 2019-03-05 华为技术有限公司 一种芯片封装结构及其制作方法、电子设备
CN110718522A (zh) * 2018-07-12 2020-01-21 三星电子株式会社 半导体封装件
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