CN114975129A - Integrated circuit packaging structure, isolation improving method, multiplexer and communication equipment - Google Patents

Integrated circuit packaging structure, isolation improving method, multiplexer and communication equipment Download PDF

Info

Publication number
CN114975129A
CN114975129A CN202110217525.0A CN202110217525A CN114975129A CN 114975129 A CN114975129 A CN 114975129A CN 202110217525 A CN202110217525 A CN 202110217525A CN 114975129 A CN114975129 A CN 114975129A
Authority
CN
China
Prior art keywords
layer
substrate
integrated circuit
dielectric layer
dielectric
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202110217525.0A
Other languages
Chinese (zh)
Inventor
徐利军
庞慰
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
ROFS Microsystem Tianjin Co Ltd
Original Assignee
ROFS Microsystem Tianjin Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by ROFS Microsystem Tianjin Co Ltd filed Critical ROFS Microsystem Tianjin Co Ltd
Priority to CN202110217525.0A priority Critical patent/CN114975129A/en
Publication of CN114975129A publication Critical patent/CN114975129A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D30/00—Reducing energy consumption in communication networks
    • Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Geometry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

The invention discloses an integrated circuit packaging structure, an isolation degree improving method, a multiplexer and communication equipment. The integrated circuit packaging structure comprises a substrate and a plastic packaging layer positioned above a substrate dielectric layer, wherein at least 1 layer of external signal wires are arranged on the upper surface of the substrate dielectric layer in the plastic packaging layer, and the method comprises the following steps: and covering a second dielectric layer on the surface of the out-of-layer signal wire, wherein the second dielectric layer has a specified thickness and a dielectric constant smaller than that of the plastic packaging layer so as to reduce surface waves excited by the out-of-layer signal wire. According to the technical scheme of the invention, the coupling between the signal lines is inhibited and the heat dissipation path is improved through the layout and packaging technology, so that the isolation and the power capacity of the duplexer are improved.

Description

Integrated circuit packaging structure, isolation improving method, multiplexer and communication equipment
Technical Field
The present invention relates to the field of filter technologies, and in particular, to an integrated circuit package structure, a method for improving isolation, a multiplexer, and a communication device.
Background
In wireless communication systems, particularly 5G communication, a small cell system is an important component, and is required to adopt higher transmission frequency and power; the filters and multiplexers in the small base station system will be developed toward miniaturization, high power capacity, high isolation, and low cost in the future.
At present, a cavity filter and a cavity multiplexer are mainly used in a base station system, the filter and the multiplexer of the cavity structure have small insertion loss, good out-of-band rejection and high isolation, but the significant defects of the filter and the multiplexer are large in size and high in processing cost, and the filter and the multiplexer are difficult to be widely applied to future 5G communication, and the bulk acoustic wave filter and the multiplexer have the characteristics of good insertion loss, high out-of-band rejection and low cost, but the significant defects of poor power capacity and only about 1.5W of power capacity at present, and are difficult to adapt to the requirements of the future 5G communication. Meanwhile, the small base station system requires that the coverage area is as large as possible, so the transmitting power is large, if the isolation degree of the receiving and transmitting system is small, the transmitting signal can be coupled to the receiving system, and the sensitivity of the receiving system is seriously influenced, so the small base station system has higher requirements on the isolation degree of the receiving and transmitting system, generally more than 70dB, and the common bulk acoustic wave duplexer is difficult to meet the requirements.
Fig. 1 is a schematic diagram of a circuit of a multiplexer according to the present invention. The principle of the multiplexer can be seen in patent CN 111181523B. The inventor finds in the process of implementing the present invention that the transmission line L1 and the transmission line L2 shown in fig. 1 inevitably overlap partially to generate coupling, which seriously affects the improvement of the isolation of the duplexer.
When the multiplexer is implemented as an integrated circuit, the multiplexer includes a substrate, a trace in the substrate, and a chip of elements such as the multiplexer and a bridge on the substrate, and is encapsulated with a plastic encapsulating material. Fig. 2 is a schematic diagram of a packaging method of a multiplexer in the prior art. As shown in fig. 2, 10 is a metal ground layer of the substrate, 11 is a dielectric layer of the substrate, 15 and 16 are signal lines, which are all disposed on the surface layer of the substrate, and their characteristic impedances are 50 ohms, 13 and 14 are duplexer chips and/or bridge chips, 12 is plastic package black glue, and the plastic package black glue 12 seals various chips on the substrate, so as to protect the chips. The sealant is generally epoxy resin, which has a relatively large dielectric constant, generally about 4.2, and when signal lines are arranged on the surface layer of the substrate and covered with the sealant, the signal lines excite surface waves, as shown at 17 and 18 in fig. 2, which spread on the surface layer of the substrate and enhance the coupling between the signal lines, resulting in poor isolation.
In order to solve the above problem, another packaging method is adopted in the prior art, as shown in fig. 3, fig. 3 is a schematic diagram of another packaging method of the multiplexer in the prior art, where 20 is a metal ground layer of a substrate, 21 is a dielectric layer of the substrate, 25 and 26 are signal lines, which are all disposed on the top layer of the substrate, and have characteristic impedances of 50 ohms, 23 and 24 are duplexer chips and/or bridge chips, 22 is a cover plate, and an air layer 27 is disposed between the cover plate 22 and the substrate, the lower surface of the cover plate 22 can contact with the upper surfaces of the chips 23 and 24, but the cover plate 22 and the upper surfaces of the signal lines 25 and 26 cannot contact, and the material of the cover plate 22 is epoxy resin, which is fixed on the substrate and can play a role of protecting the chips. The advantage of this package is that it can overcome the disadvantages of the package shown in fig. 2, because the signal line surface layer is not coated with a medium, it will not excite surface waves, and can suppress the coupling between the signal lines, thereby improving the isolation, but because there is an air layer 27 between the substrate and the cover plate 22, the thermal resistance between the substrate and the cover plate is increased, which is not good for heat dissipation, thereby causing the power capacity to deteriorate.
Disclosure of Invention
In view of this, the present invention provides an integrated circuit package structure, an isolation enhancing method, a multiplexer and a communication device, which suppress coupling between signal lines and improve a heat dissipation path by using a layout and a package technology, so as to improve isolation and power capacity of the duplexer and adapt to the development of a 5G small base station in the future.
The invention provides the following technical scheme:
a method for improving the isolation of an integrated circuit packaging structure, the integrated circuit packaging structure comprises a substrate and a plastic packaging layer positioned above a substrate dielectric layer, at least 1 external signal wire is arranged on the upper surface of the substrate dielectric layer in the plastic packaging layer, and the method comprises the following steps: and covering a second dielectric layer on the surface of the out-of-layer signal wire, wherein the second dielectric layer has a specified thickness and a dielectric constant smaller than that of the plastic packaging layer so as to reduce surface waves excited by the out-of-layer signal wire.
Optionally, the substrate has multiple metal layers, at least 1 metal layer inside the substrate is provided with an in-layer signal line, and at least 1 metal layer is arranged between the in-layer signal line and the out-layer signal line, and the at least 1 metal layer is grounded.
Optionally, the thickness of the second dielectric layer is between 25 microns and 40 microns, and the relative dielectric constant is between 1 and 2.5.
Optionally, the thermal conductivity of the second dielectric layer is greater than a specified value.
Optionally, for 2 crossed signal lines, the included angle between the two lines is 85 degrees to 95 degrees.
The integrated circuit packaging structure comprises a substrate and a plastic packaging layer positioned above a substrate dielectric layer, wherein at least 1 layer of external signal wires is arranged on the upper surface of the substrate dielectric layer in the plastic packaging layer, a second dielectric layer covers the surface of each external signal wire, and the second dielectric layer has a specified thickness and a dielectric constant smaller than that of the plastic packaging layer.
Optionally, the substrate has multiple metal layers, at least 1 metal layer inside the substrate is provided with an in-layer signal line, and at least 1 metal layer is arranged between the in-layer signal line and the out-layer signal line, and the at least 1 metal layer is grounded.
Optionally, the thickness of the second dielectric layer is between 25 microns and 40 microns, and the relative dielectric constant is between 1 and 2.5.
Optionally, the thermal conductivity of the second dielectric layer is greater than a specified value.
The invention relates to a multiplexer, wherein the packaging structure of the multiplexer is an integrated circuit packaging structure provided by the invention, and a plastic packaging layer of the integrated circuit packaging structure comprises a duplexer chip and/or a bridge chip.
A communication device comprises an integrated circuit, and the integrated circuit adopts the integrated circuit packaging structure.
According to the technical scheme of the invention, in the integrated circuit packaging structure, for the condition of adopting a packaging material with a larger dielectric constant, a dielectric layer with a smaller dielectric constant is covered on the signal line on the surface layer of the substrate so as to reduce the surface wave excited by the signal line and improve the isolation. Because the dielectric layer is additionally embedded, the heat dissipation can be improved by selecting the thermal conductivity. If a multilayer substrate is adopted, part of the signal lines can be arranged in the substrate and isolated from the signal lines on the surface layer of the substrate by a grounded metal layer, which is beneficial to further improving the isolation. The packaging structure can be applied to packaging of integrated circuit devices such as duplexers, multiplexers and the like, and can also be applied to other integrated circuit devices.
Drawings
For purposes of illustration and not limitation, the present invention will now be described in accordance with its preferred embodiments, particularly with reference to the accompanying drawings, in which:
FIG. 1 is a schematic diagram of a multiplexer circuit according to the present invention;
FIG. 2 is a diagram illustrating a prior art multiplexer package;
FIG. 3 is a diagram illustrating another packaging method of a multiplexer in the prior art;
FIG. 4 is a schematic diagram of an integrated circuit package according to an embodiment of the present invention;
FIG. 5 is a diagram illustrating the variation trend of the isolation of the duplexer along with the dielectric layer h;
FIG. 6 is a schematic diagram of another integrated circuit packaging approach according to an embodiment of the present invention.
Detailed Description
In the embodiment of the invention, for the packaging structure of the integrated circuit which adopts the plastic packaging material with larger dielectric constant such as epoxy resin, another dielectric layer is covered on the signal line on the upper surface of the substrate in the packaging structure, and the relative dielectric constant of the dielectric layer is smaller than the dielectric constant of the plastic packaging material, so that the surface wave excited by the signal line is reduced. The following description is made with reference to the accompanying drawings.
Fig. 4 is a schematic diagram of an integrated circuit package according to an embodiment of the invention. As shown in fig. 4, 30 is a metal ground layer of the substrate, 31 is a dielectric layer of the substrate, and 35 and 36 are signal lines, which are all disposed on the top layer of the substrate, i.e., on the upper surface of the dielectric layer of the substrate, and have a characteristic impedance of 50 ohms. The signal lines 35 and 36 are covered with a thin dielectric layer, such as 37 and 38, having a relative dielectric constant of between 1 and 2.5. The dielectric layers 37 and 38 have the same thickness, and the vertical distance between the upper surface of the dielectric layers and the upper surface of the signal line is h, wherein the value range of h is 25um < h <40 um. 33 and 34 are for example diplexer chips, bridge chips or other chips. And 32, plastic black glue for sealing various chips and dielectric layers 37 and 38 on the substrate, which can protect the chips. Because the signal lines 35 and 36 are covered by a thin dielectric layer with small dielectric constant, the signal lines 35 and 36 are not easy to excite surface waves, so that the coupling between the signal lines 35 and 36 can be well inhibited, and the isolation is improved. In addition, the dielectric layers 37 and 38 may be made of a material with a high thermal conductivity, which may improve heat dissipation and thus power capacity.
Taking the packaging structure of the duplexer as an example, the packaging manner shown in fig. 4 is adopted, the variation of the isolation of the duplexer along with the dielectric layer h is shown in fig. 5, and fig. 5 is a schematic diagram of the variation trend of the isolation of the duplexer along with the dielectric layer h. As can be seen from fig. 5, when h is 30um, the isolation is best, and can reach 75dB, and when h is 20um, the isolation is poor, and is only 65dB, so h may be in a range of 25um < h <40 um.
According to the packaging method of fig. 4, one or more signal lines on the upper surface of the substrate dielectric layer are covered with the dielectric layer to reduce surface waves. In addition, because the substrate can be a multilayer structure, a part of the signal line can be arranged on the upper surface of the substrate dielectric layer, and the other part of the signal line can be arranged in the substrate. As shown in fig. 6, fig. 6 is a schematic diagram of another integrated circuit package according to an embodiment of the invention.
The substrate in fig. 6 is a multilayer substrate, 40 is a metal ground layer of the substrate, 41 is a dielectric layer of the substrate, 45 and 46 are signal lines, and their characteristic impedances are all 50 ohms, wherein the signal line 46 is disposed on the top layer of the substrate, and a thin dielectric layer, e.g. 49 in the figure, covers the surface layer of the signal line 46, and has a relative dielectric constant between 1 and 2.5, and its upper surface is higher than the upper surface of the signal line by h, and the range of h is 25um < h <40 um. The difference from the structure shown in fig. 4 is mainly that the signal line 45 is disposed in the third metal layer, the second metal layer 48 is disposed between the signal lines 45 and 46, and the second metal layer is communicated with the metal ground layer 40 through the metal via 47 to be grounded. 43 and 44 are diplexer and/or bridge chips and 42 is a plastic black glue. Because the signal line 46 is covered with a thin dielectric layer with small dielectric constant, surface waves are not easy to excite, and meanwhile, the signal line 45 is isolated from the signal line 46 through the metal layer 48, so that the coupling between the signal lines 45 and 46 can be well inhibited, and the isolation degree is improved.
If the integrated circuit adopting the packaging mode of fig. 4 and fig. 6 includes 2 crossed signal lines, the 2 signal lines are perpendicular to each other as much as possible, namely, the included angle between the two signal lines is between 85 degrees and 95 degrees, so as to reduce the coupling. If the top layer of the substrate is not provided with the signal lines, the top layer covers the metal layer, and most of the signal lines are arranged on a second layer from the top layer.
According to the technical scheme of the embodiment of the invention, in the integrated circuit packaging structure, for the condition of adopting a packaging material with a larger dielectric constant, a dielectric layer with a smaller dielectric constant is covered on the signal line on the surface layer of the substrate so as to reduce the surface wave excited by the signal line and improve the isolation. Because the dielectric layer is additionally embedded, the heat dissipation can be improved by selecting the thermal conductivity. If a multilayer substrate is adopted, part of the signal lines can be arranged in the substrate and isolated from the signal lines on the surface layer of the substrate by a grounded metal layer, which is beneficial to further improving the isolation. The packaging structure can be applied to packaging of integrated circuit devices such as duplexers, multiplexers and the like, and can also be applied to other integrated circuit devices.
The above-described embodiments should not be construed as limiting the scope of the invention. Those skilled in the art will appreciate that various modifications, combinations, sub-combinations, and substitutions can occur, depending on design requirements and other factors. Any modification, equivalent replacement, and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims (11)

1. A method for improving the isolation of an integrated circuit packaging structure, the integrated circuit packaging structure comprises a substrate and a plastic packaging layer positioned above a substrate dielectric layer, and at least 1 external signal wire is arranged on the upper surface of the substrate dielectric layer in the plastic packaging layer, and the method is characterized by comprising the following steps:
and covering a second dielectric layer on the surface of the out-of-layer signal wire, wherein the second dielectric layer has a specified thickness and a dielectric constant smaller than that of the plastic packaging layer so as to reduce surface waves excited by the out-of-layer signal wire.
2. The method of claim 1, wherein the substrate has a plurality of metal layers, at least 1 metal layer inside the substrate has an intra-layer signal line disposed therein, and at least 1 metal layer is disposed between the intra-layer signal line and the extra-layer signal line, and the at least 1 metal layer is grounded.
3. The method of claim 1 or 2, wherein the second dielectric layer has a thickness of between 25 and 40 microns and a relative dielectric constant of between 1 and 2.5.
4. The method of claim 1 or 2, wherein the thermal conductivity of the second dielectric layer is greater than a specified value.
5. The method of claim 1 or 2, wherein the angle between the two is between 85 and 95 degrees for 2 crossed signal lines.
6. An integrated circuit packaging structure comprises a substrate and a plastic packaging layer arranged above a substrate dielectric layer, wherein at least 1 external signal wire is arranged on the upper surface of the substrate dielectric layer in the plastic packaging layer,
the surface of the out-of-layer signal wire is covered by a second dielectric layer which has a specified thickness and a dielectric constant smaller than that of the molding layer.
7. The package structure of claim 6, wherein the substrate has a plurality of metal layers, at least 1 metal layer inside the substrate has an inner signal line disposed therein, and at least 1 metal layer between the inner signal line and the outer signal line, and the at least 1 metal layer is grounded.
8. The integrated circuit package structure of claim 6 or 7, wherein the second dielectric layer has a thickness of between 25 microns and 40 microns and a relative dielectric constant of between 1 and 2.5.
9. The integrated circuit package structure of claim 6 or 7, wherein the second dielectric layer has a thermal conductivity greater than a specified value.
10. A multiplexer, wherein the package structure of the duplexer is the package structure of the integrated circuit according to any one of claims 1 to 8, and the package layer of the integrated circuit package structure includes a duplexer chip and/or a bridge chip.
11. A communication device comprising an integrated circuit employing the integrated circuit package structure of any one of claims 1 to 8.
CN202110217525.0A 2021-02-26 2021-02-26 Integrated circuit packaging structure, isolation improving method, multiplexer and communication equipment Pending CN114975129A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202110217525.0A CN114975129A (en) 2021-02-26 2021-02-26 Integrated circuit packaging structure, isolation improving method, multiplexer and communication equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202110217525.0A CN114975129A (en) 2021-02-26 2021-02-26 Integrated circuit packaging structure, isolation improving method, multiplexer and communication equipment

Publications (1)

Publication Number Publication Date
CN114975129A true CN114975129A (en) 2022-08-30

Family

ID=82973128

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202110217525.0A Pending CN114975129A (en) 2021-02-26 2021-02-26 Integrated circuit packaging structure, isolation improving method, multiplexer and communication equipment

Country Status (1)

Country Link
CN (1) CN114975129A (en)

Similar Documents

Publication Publication Date Title
JP2003273571A (en) High-frequency module for shielding inter-element radio wave interference
US20080180206A1 (en) Coil Transducer with Reduced Arcing and Improved High Voltage Breakdown Performance Characteristics
CN216120295U (en) Acoustic surface filter radio frequency module packaging structure and electronic equipment
CN212991092U (en) Packaging module, module carrier plate and electronic equipment
JP4603527B2 (en) Modular component with capsule
US7362038B1 (en) Surface acoustic wave (SAW) device package and method for packaging a SAW device
CN104078458A (en) Stack-based semiconductor structure and manufacturing method thereof
US6754471B1 (en) Surface acoustic wave filter packaging
CN114512790A (en) Antenna packaging structure and manufacturing method thereof
CN114512789A (en) Antenna packaging structure and manufacturing method thereof
CN109904128B (en) Three-dimensional integrated T/R assembly packaging structure and packaging method based on silicon-based carrier plate
CN114975129A (en) Integrated circuit packaging structure, isolation improving method, multiplexer and communication equipment
KR100698570B1 (en) Package device with electromagnetic interference shield
CN100378967C (en) Ceramic package and fabrication method thereof
CN116072620A (en) Chip module packaging structure, packaging method and circuit board
JP2002033444A (en) Semiconductor device
CN106373926B (en) Package structure, shielding member and method for fabricating the same
CN209497436U (en) A kind of stack encapsulation structure of filter
JP6253306B2 (en) Electronic devices
CN218632005U (en) Chip module packaging structure and circuit board
JP2004235877A (en) High frequency module
JP2005086615A (en) High frequency module equipped with surface acoustic wave filter
JP2003298004A (en) High-frequency module of inter-device interference radio wave shielding type, and electronic device
KR100431182B1 (en) Surface acoustic wave device package and method
CN214675097U (en) Filter system-in-package module

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination