CN116072620A - Chip module packaging structure, packaging method and circuit board - Google Patents

Chip module packaging structure, packaging method and circuit board Download PDF

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Publication number
CN116072620A
CN116072620A CN202211477309.0A CN202211477309A CN116072620A CN 116072620 A CN116072620 A CN 116072620A CN 202211477309 A CN202211477309 A CN 202211477309A CN 116072620 A CN116072620 A CN 116072620A
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China
Prior art keywords
chip
cavity
layer
filter
bump
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Pending
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CN202211477309.0A
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Chinese (zh)
Inventor
钱刚
石岩
陆立胜
陈转玲
邹秋红
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Carsem Semiconductor Suzhou Co Ltd
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Carsem Semiconductor Suzhou Co Ltd
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Priority to CN202211477309.0A priority Critical patent/CN116072620A/en
Publication of CN116072620A publication Critical patent/CN116072620A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135—Double encapsulation or coating and encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/315—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the encapsulation having a cavity
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

The application provides a chip module packaging structure, a packaging method and a circuit board, comprising the following steps: a substrate having opposite first and second surfaces; the filter chip comprises a first chip body and a first bump, wherein a first cavity is formed between the first chip body and the first surface, and the first bump is electrically connected with the first surface; the non-filter chip comprises a second chip body and a second bump, wherein a second cavity is formed between the second chip body and the second surface, and the second bump is electrically connected with the second surface and is positioned in the second cavity; an isolation layer covering the filter chip on the first surface to close the first cavity; the first plastic layer encapsulates the filter chip and the isolation layer on the first surface and is isolated from the outer side of the first cavity by the isolation layer; and the second plastic layer encapsulates the non-filter chip on the second surface and fills the second cavity so as to avoid the situation that the salient points of the non-filter chip are locally cracked or are in poor contact with the substrate and improve the reliability of the chip module.

Description

Chip module packaging structure, packaging method and circuit board
Technical Field
The present disclosure relates to the field of chip packaging technologies, and in particular, to a chip module packaging structure, a packaging method, and a circuit board.
Background
The working principle of the surface acoustic wave Filter (Saw Filter) is that sound waves are transmitted on the surface of a chip, so that the packaging of the surface acoustic wave Filter must ensure that the surface of an interdigital transducer cannot contact other substances, namely that the surface of the chip is of a cavity structure, otherwise, signal transmission is influenced. The radio frequency module product based on the surface acoustic wave filter also comprises an antenna switch, a low-noise amplifier, a capacitor, an inductor and other conventional elements which can work without a cavity, namely a non-filter chip.
In the prior art, cavities are formed at the bottoms of all chips (including filter chips and non-filter chips) in the radio frequency module, and part of non-filter components have too small bump duty ratio, so that after being subjected to reliability tests such as cold and hot impact, local cracks can appear on bumps and the bumps are melted, so that the reliability failure risk exists.
Disclosure of Invention
The purpose of the application is to provide a chip module packaging structure, a packaging method and a circuit board, so as to avoid local cracks of bumps of a chip and improve the reliability of the chip module.
An embodiment of a first aspect of the present application provides a chip module package structure, including: a substrate having opposite first and second surfaces; the filter chip comprises a first chip body and a first bump, wherein a first cavity is formed between the first chip body and the first surface, and the first bump is electrically connected with the first surface; a non-filter chip including a second chip body forming a second cavity with the second surface, and a second bump electrically connected with the second surface and located in the second cavity; an isolation layer covering the filter chip on the first surface to close the first cavity; a first molding layer encapsulating the filter chip and the isolation layer on the first surface and isolated from the outside of the first cavity by the isolation layer; and a second plastic layer encapsulating the non-filter chip on the second surface and filling the second cavity.
In some examples, at least two of the filter chips are disposed on the first surface, and the isolation layer extends continuously between the at least two of the filter chips.
In some examples, the height of the first cavity is not less than the height of the first bump.
In some examples, the filter chip includes a plurality of spaced first bumps, the first surface is provided with a plurality of first metal pads corresponding to the first bumps, and the first bumps are electrically connected to the corresponding first metal pads; any two adjacent first metal pads are separated by a first insulating layer arranged on the first surface, and the first insulating layer isolates the first surface from the isolating layer covering the first surface.
In some examples, the package structure further includes a solder ball disposed on the second surface, a portion of the solder ball being exposed outside the second molding layer, and another portion of the solder ball being encapsulated on the second surface by the second molding layer.
In some examples, the non-filter chip includes a plurality of spaced second bumps, the second surface having a plurality of second metal pads thereon corresponding to the solder balls and the plurality of second bumps, respectively, the solder balls and the plurality of second bumps being electrically connected to the corresponding second metal pads, respectively; any two adjacent second metal pads are separated by a second insulating layer arranged on the second surface, and the second insulating layer isolates the second surface from the second plastic sealing layer.
An embodiment of a second aspect of the present application provides a method for packaging a chip module, including: providing a substrate having opposing first and second surfaces; providing a filter chip to the first surface, wherein the filter chip comprises a first chip body and first bumps, and a first cavity is formed between the first chip body and the first surface; electrically connecting the first bump with the first surface; forming an isolation layer covering the filter chip on the first surface; forming a first plastic layer which encapsulates the filter chip and the isolation layer on the first surface, wherein the first plastic layer is isolated outside the first cavity by the isolation layer; providing a non-filter chip to the second surface, wherein the non-filter chip comprises a second chip body and a second bump, a second cavity is formed between the second chip body and the second surface, and the second bump is positioned in the second cavity; electrically connecting the second bump with the second surface; and forming a second plastic sealing layer for sealing the non-filter chip on the second surface, wherein the second plastic sealing layer fills the second cavity.
In some examples, the method further comprises: forming solder balls on the second surface; the forming a second molding layer encapsulating the non-filter chip to the second surface includes: forming a second plastic layer which encapsulates the non-filter chip and the solder balls on the second surface; the method further comprises the steps of: and removing part of the second plastic sealing layer on the tin ball so that part of the tin ball is exposed out of the second plastic sealing layer.
In some examples, the method further comprises: removing part of the second plastic sealing layer around the tin ball, so that a gap is formed between the outer peripheral wall of the tin ball and the second plastic sealing layer; printing solder paste on the surface of the solder ball; and (5) performing reflow soldering to finish packaging.
An embodiment of a third aspect of the present application provides a circuit board, including the chip module package structure according to the embodiment of the first aspect.
According to the embodiment of the application, the filter chip and the non-filter chip are respectively arranged on the two different surfaces of the substrate, so that the filter chip and the non-filter chip can be packaged in different forms, on one hand, the cavity between the first chip body and the substrate is reserved, the filtering function is realized, on the other hand, the cavity between the second chip body and the substrate is filled with the plastic packaging material, the convex point of the non-filter chip is wrapped by the plastic packaging material, or the plastic packaging material provides protection for the convex point of the non-filter chip, the situation that poor contact with the substrate is caused by flow after the convex point of the non-filter chip is melted in the reliability testing process is avoided, local cracks are avoided, and the reliability of the chip module is improved. In addition, the above structure configuration enables the chip module packaging structure to have smaller packaging size.
Drawings
In order to more clearly illustrate the embodiments of the present description or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described below, it being obvious that the drawings in the following description are only some of the embodiments described in the present description, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art. In the drawings:
FIG. 1 is a cross-sectional view of a substrate in an embodiment of the present application;
FIG. 2 is a cross-sectional view of a filter chip disposed on a substrate in an embodiment of the present application;
FIG. 3 is a cross-sectional view of an isolation layer encapsulated filter chip in an embodiment of the present application;
FIG. 4 is a cross-sectional view of a first molding layer encapsulating an isolation layer and a filter chip in an embodiment of the present application;
FIG. 5 is a cross-sectional view of a solder ball disposed on a substrate in an embodiment of the present application;
FIG. 6 is a cross-sectional view of a non-filter chip disposed on a substrate in an embodiment of the present application;
FIG. 7 is a cross-sectional view of a second molding layer encapsulating solder balls and a non-filter chip in an embodiment of the present application;
fig. 8 is a cross-sectional view of an embodiment of the present application with a portion of the second molding layer removed;
FIG. 9 is a cross-sectional view of a solder paste printed on the surface of a solder ball according to an embodiment of the present application;
FIG. 10 is a cross-sectional view of a chip module package structure in an embodiment of the present application;
fig. 11 is a flow chart of a method for packaging a chip module according to an embodiment of the application.
Detailed Description
In order to make the technical solutions in the present specification better understood by those skilled in the art, the technical solutions in the embodiments of the present specification will be clearly and completely described below with reference to the drawings in the embodiments of the present specification, and it is obvious that the described embodiments are only some embodiments of the present specification, not all embodiments. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are intended to be within the scope of the present disclosure.
In the embodiments of the present application, the terms "first," "second," and the like are used to distinguish between different elements from each other by reference, but do not denote a spatial arrangement or a temporal order of the elements, and the elements should not be limited by the terms. The term "and/or" includes any and all combinations of one or more of the associated listed terms. The terms "comprises," "comprising," "including," "having," and the like, are intended to reference the presence of stated features, elements, components, or groups of components, but do not preclude the presence or addition of one or more other features, elements, components, or groups of components. The term "plurality" means two or more, unless otherwise indicated.
Example of the first aspect
An embodiment of a first aspect of the present application provides a chip module package structure, which includes a substrate, a filter chip, a non-filter chip, an isolation layer, a first molding layer, and a second molding layer. The substrate has opposite first and second surfaces. The filter chip comprises a first chip body and a first bump, wherein a first cavity is formed between the first chip body and the first surface, and the first bump is electrically connected with the first surface. The non-filter chip comprises a second chip body forming a second cavity with the second surface and a second bump electrically connected with the second surface and positioned in the second cavity. The isolation layer covers the filter chip on the first surface to close the first cavity. The first plastic layer encapsulates the filter chip and the isolation layer on the first surface and is isolated outside the first cavity by the isolation layer. A second molding layer encapsulates the non-filter chip on the second surface and fills the second cavity.
According to the embodiment of the application, the filter chip and the non-filter chip are respectively arranged on two different surfaces (namely the first surface and the second surface) of the substrate, so that the filter chip and the non-filter chip are packaged in different forms, on one hand, the cavity between the first chip body and the substrate is reserved, the filtering function is realized, on the other hand, the cavity between the second chip body and the substrate is filled with the plastic package material, the convex point of the non-filter chip is wrapped by the plastic package material, or the plastic package material provides protection for the convex point of the non-filter chip, the situation that poor contact with the substrate is caused by flow after the convex point of the non-filter chip is melted in the reliability testing process is avoided, local cracks are avoided, and the reliability of the chip module is improved. In addition, the above structure configuration enables the chip module packaging structure to have smaller packaging size.
The following describes the implementation of the examples of the present application with reference to the drawings.
Fig. 10 is a schematic diagram of an example of a chip module package structure according to an embodiment of the present application.
As shown in fig. 10, the substrate 1 has opposite first and second surfaces 101 and 102. The filter chip is disposed on the first surface 101. Although fig. 10 shows two filter chips, i.e., the filter chip 2 and the filter chip 3, it should be understood that the number of filter chips in the embodiment of the present application may be one or more than two, which is not limited in this application.
As shown in fig. 10, the filter chip 2 includes a first chip body 21 and a first bump 22 disposed on the first chip body 21, a first cavity 23 is formed between the first chip body 21 and the first surface 101, the first bump 22 is located in the first cavity 23, and the first bump 22 is electrically connected to the first surface 101. Similarly, the filter chip 3 includes a first chip body 31 and a first bump 32 disposed on the first chip body 31, a first cavity 33 is formed between the first chip body 31 and the first surface 101, the first bump 32 is located in the first cavity 33, and the first bump 32 is electrically connected to the first surface 101. In the example of fig. 10, the entire first bump 22 is located within the first cavity 23 and the entire first bump 32 is located within the first cavity 33.
Although fig. 10 shows that the filter chip 2 includes two first bumps 22 and the filter chip 3 includes three first bumps 32, it should be understood that the number of bumps per filter chip may be fewer or greater in the embodiment of the present application, which is not limited in this application.
As shown in fig. 10, the isolation layer 4 covers the filter chips 2, 3 on the first surface 101 to close the first cavities 23, 33, in other words, the first cavities 23, 33 are closed cavities. The isolation layer 4 may be a dry film, for example, a solder mask, and the isolation layer 4 may be made of an isolation material such as green paint, epoxy resin glue, ultraviolet glue, PCB, and silicone.
As shown in fig. 10, the first plastic layer 51 encapsulates the filter chips 2, 3 and the isolation layer 4 on the first surface 101, and is isolated from the outside of the first cavities 23, 33 by the isolation layer 4 without entering the inside of the first cavities 23, 33. In the example of fig. 10, the isolation layer 5 completely isolates the substrate 1 from the first plastic layer 51, in other words, the substrate 1 is not in contact with the first plastic layer 51.
As shown in fig. 10, the non-filter chip 7 includes a second chip body 71 and a second bump 72 disposed on the second chip body 71, a second cavity 73 is formed between the second chip body 71 and the second surface 102, the second bump 72 is located in the second cavity 73, and the second bump 72 is connected to the second surface 102.
Although fig. 10 shows one non-filter chip 7 and the non-filter chip 7 includes four second bumps 72, it should be understood that the number of non-filter chips 7 may be more than one in the embodiment of the present application, and the number of bumps of each non-filter chip 7 may be fewer or more, which is not limited in this application. The non-filter chip 7 may be an antenna switch, a low noise amplifier, a capacitor, an inductor, etc. that can operate without a cavity.
As shown in fig. 10, the second molding layer 52 encapsulates the non-filter chip 71 on the second surface 102 and fills the second cavity 73, and the second bump 72 is encapsulated by the second molding layer 52, so that the situation that the second bump 72 of the non-filter functional chip 7 flows to cause poor contact with the substrate after being melted in the reliability test process is avoided, local cracks of the second bump 72 are avoided, and the reliability of the chip module is improved.
Alternatively, the thickness of the spacer layer 4 is not more than 20 μm. The thickness of the spacer layer 4 may be equal to 20 μm or less than 20 μm, for example 18 μm, 15 μm, 10 μm or 5 μm. The thickness of the isolating layer 4 is thus smaller compared to the prior art. The thinner isolation layer 4 is such that the isolation layer 4 does not impact the first bumps 22, 32 during plastic packaging to affect performance.
In some embodiments, at least two filter chips are provided on the first surface 101, the isolation layer 4 extending continuously between the at least two filter chips, e.g. the isolation layer 4 may extend continuously between all filter chips or between parts of the filter chips. In the example of fig. 10, the isolation layer 4 extends continuously between the filter chip 2 and the filter chip 3, in other words, the isolation layer 4 continuously covers the filter chip 2 and the filter chip 3, simplifying the packaging process. In addition, the isolation layer 4 between the filter chip 2 and the filter chip 3 is in a continuous rather than disconnected state after packaging is completed, so that the integrity of the packaging structure is better, and the overall structural strength is better.
In some embodiments, as shown in fig. 10, the substrate 1 defines a height direction H in which the first surface 101 and the second surface 102 are opposite to each other. In the height direction H, the height of the first cavities 23, 33 is not smaller than the height of the first bumps 22, 32, for example, the height of the first cavities 23, 33 is equal to the height of the first bumps 22, 32. Alternatively, the height of the first cavities 23, 33 is 50 μm to 60 μm, for example 55 μm.
In some embodiments, as shown in fig. 10, a plurality of first metal pads 12 corresponding to the first bumps 22 and 32 are disposed on the first surface 101 of the substrate 1, and each of the first bumps 22 and 32 is electrically connected to the corresponding first metal pad 12, for example, the first bumps 22 and 32 may be electrically connected to the first metal pad 12 by flip-chip bonding.
In this embodiment, further, any two adjacent first metal pads 12 are separated by a first insulating layer 11 disposed on the first surface 101, so that the first metal pads 12 are insulated from each other, the first insulating layer 11 separates the first surface 101 from the insulating layer 4 covering the first surface 101, in other words, the first insulating layer 11 is laid on the first surface 101, and the insulating layer 4 is laid on the first insulating layer 11.
Alternatively, as shown in fig. 10, the surface of the first insulating layer 11 facing the isolation layer 4 is substantially flush with the surface of the first metal pad 12 facing the first bump 22, 32 in the height direction H, and accordingly, the isolation layer 4 extends from the surfaces 211, 311 of the first chip bodies 21, 31 facing away from the substrate 1 toward the first surface 101 to be substantially flush with the surfaces 221, 321 of the first bump 22, 32 facing the substrate 1 in the height direction H.
In some embodiments, as shown in fig. 10, the chip module package structure further includes at least one solder ball 6, the solder ball 6 is disposed on the second surface 102, a portion of the solder ball 6 is exposed outside the second molding layer 52, and another portion of the solder ball 6 is encapsulated by the second molding layer 52. Fig. 10 shows two solder balls 6, and it should be understood that the number of solder balls 6 in the embodiment of the present application may be fewer or greater, which is not limited in this application. After the filter chips 2, 3 and the non-filter chip 7 are packaged, the solder balls 6 are exposed electrical connection pads of the package structure. Solder balls 6 may be formed on the second surface 102 using a BGA ball mounting process.
In some embodiments, as shown in fig. 10, the second surface 102 is provided with a plurality of second metal pads 14 corresponding to the solder balls 6 and the second bumps 72, respectively, and the solder balls 6 and the second bumps 72 are electrically connected to the corresponding second metal pads 14, respectively. The second bump 72 may be electrically connected to the second metal pad 14, for example, by flip-chip bonding.
In this embodiment, further, any two adjacent second metal pads 14 are separated by a second insulating layer 13 disposed on the second surface 102, so that the second metal pads 14 are insulated from each other, and the second insulating layer 13 isolates the second surface 102 from the second plastic layer 52.
Embodiments of the second aspect
As shown in fig. 11, an embodiment of the second aspect of the present application provides a method for packaging a chip module. It should be noted that the order of steps listed in the embodiments of the present application is only one manner of performing the steps, and does not represent a unique order of execution. In the actual packaging process, the method shown in the embodiment or the drawing may be performed sequentially, sequentially or in parallel.
A preferred embodiment of the present application is shown in fig. 1-10.
Referring to fig. 1, the packaging method may begin by providing a substrate 1. The substrate 1 has opposite first and second surfaces 101, 102 (see fig. 2). In the example of fig. 1, a plurality of first metal pads 12 and a first insulating layer 11 isolating each first metal pad 12 are provided on a first surface 101, and a plurality of second metal pads 14 and a second insulating layer 13 isolating each second metal pad 14 are provided on a second surface 102.
Referring to fig. 2, the filter chips 2, 3 are provided to the first surface 101. The filter chip 2, 3 includes a first chip body 21, 31 and a first bump 22, 32, a first cavity 23, 33 is formed between the first chip body 21, 31 and the first surface 101, and the first bump 22, 32 is located in the first cavity 23, 33.
Referring again to fig. 2, the first bumps 22, 32 are electrically connected to the first surface 101. Illustratively, each first bump 22, 32 may be electrically connected to each first metal pad 12 on the first surface 101 by flip-chip bonding.
Referring to fig. 3, an isolation layer 4 covering the filter chips 2, 3 is formed on the first surface 101. The separator 4 may be a dry film, for example, an epoxy resin film.
Alternatively, the isolating layer 4 extends continuously between the at least two filter chips 2, 3, in other words the isolating layer 4 forms a continuous coverage of the at least two filter chips 2, 3.
Alternatively, the isolation layer 4 may be a dry film, and the isolation layer 4 may be a solder mask, for example, the isolation layer 4 is made of an isolation material such as green paint, epoxy glue, ultraviolet glue, PCB, and silicone.
Referring to fig. 4, a first plastic layer 51 is formed to encapsulate the filter chips 2, 3 and the isolation layer 4 on the first surface 101, the first plastic layer 51 being isolated from the outside of the first cavities 23, 33 by the isolation layer 4, thereby preventing the first plastic layer 51 from filling the first cavities 23, 33, ensuring that the filter chips 2, 3 can realize filtering.
Referring to fig. 5, optionally, solder balls 6 are formed on the second surface 102, the solder balls 6 being electrically connected to the second metal pads 14. Solder balls 6 may be formed on the second surface 102 using, for example, a BGA ball mounting process.
Referring to fig. 6, a non-filter chip 7 is provided to the second surface 102, the non-filter chip 7 includes a second chip body 71 and a second bump 72, a second cavity 73 is formed between the second chip body 71 and the second surface 102, and the second bump 72 is located in the second cavity 73.
Referring again to fig. 6, the second bump 72 is electrically connected to the second surface 102. Illustratively, each second bump 72 may be electrically connected to each second metal pad 14 on the second surface 102 by flip-chip bonding.
Referring to fig. 7, a second molding layer 52 is formed to encapsulate the non-filter chip 7 and the solder balls 6 on the second surface 102, and the second molding layer 52 fills the second cavity 73 (see fig. 8), so as to encapsulate and protect the second bump 72, thereby avoiding the situation that the second bump 72 of the non-filter chip 7 flows after being melted to cause poor contact with the substrate in the reliability test process, avoiding local cracks of the second bump 72, and improving the reliability of the chip module.
Referring to fig. 8, a portion of the second molding layer 52 on the solder balls 6 is optionally removed so that a portion of the solder balls 6 is exposed outside the second molding layer 52. When removing part of the second plastic layer 52, it is necessary to ensure that the non-filter functional chip 7 is still completely encapsulated by the second plastic layer 52. A substrate back grinding process may be used to remove portions of the second molding layer 52 on the solder balls 6, for example.
Referring to fig. 9, optionally, a portion of the second molding layer 52 around the solder balls 6 is removed, so that a space 8 is formed between the outer peripheral wall of the solder balls 6 and the second molding layer 52. Portions of the second plastic layer 52 around the solder balls 6 may be cut away, for example, using a laser cutter, to form the voids 8.
Referring again to fig. 9, optionally, a solder paste 9 is printed on the surface of the solder balls 6.
Referring to fig. 10, reflow soldering is performed to complete the package. After reflow soldering, the solder paste 9 and the solder balls 6 are melted again to form new solder ball bumps, which are more convenient for the solderability of subsequent products.
Embodiments of the third aspect
An embodiment of a third aspect of the present application provides a circuit board, which includes the chip module package structure according to the embodiment of the first aspect. Since in the embodiment of the first aspect, the structure of the chip module package structure has been described in detail, the contents thereof are incorporated herein and the description thereof is omitted herein.
The foregoing is merely exemplary of the present disclosure and is not intended to limit the disclosure. Various modifications and alterations to this specification will become apparent to those skilled in the art. Any modifications, equivalent substitutions, improvements, or the like, which are within the spirit and principles of the present description, are intended to be included within the scope of the claims of the present description.

Claims (10)

1. The utility model provides a chip module packaging structure which characterized in that includes:
a substrate having opposite first and second surfaces;
the filter chip comprises a first chip body and a first bump, wherein a first cavity is formed between the first chip body and the first surface, and the first bump is electrically connected with the first surface;
a non-filter chip including a second chip body forming a second cavity with the second surface, and a second bump electrically connected with the second surface and located in the second cavity;
an isolation layer covering the filter chip on the first surface to close the first cavity;
a first molding layer encapsulating the filter chip and the isolation layer on the first surface and isolated from the outside of the first cavity by the isolation layer;
and a second plastic layer encapsulating the non-filter chip on the second surface and filling the second cavity.
2. The chip module package according to claim 1, wherein,
at least two filter chips are arranged on the first surface, and the isolating layer extends continuously between the at least two filter chips.
3. The chip module package according to claim 1, wherein,
the height of the first cavity is not smaller than the height of the first bump.
4. The chip module package according to claim 1, wherein,
the filter chip comprises a plurality of first bumps at intervals, a plurality of first metal pads corresponding to the first bumps are arranged on the first surface, and the first bumps are electrically connected with the corresponding first metal pads;
any two adjacent first metal pads are separated by a first insulating layer arranged on the first surface, and the first insulating layer isolates the first surface from the isolating layer covering the first surface.
5. The chip module package structure of claim 1, further comprising:
and the tin ball is arranged on the second surface, one part of the tin ball is exposed out of the second plastic sealing layer, and the other part of the tin ball is encapsulated on the second surface by the second plastic sealing layer.
6. The chip module package according to claim 5, wherein,
the non-filter chip comprises a plurality of second bumps at intervals, a plurality of second metal pads corresponding to the solder balls and the second bumps are arranged on the second surface, and the solder balls and the second bumps are electrically connected with the corresponding second metal pads;
any two adjacent second metal pads are separated by a second insulating layer arranged on the second surface, and the second insulating layer isolates the second surface from the second plastic sealing layer.
7. The chip module packaging method is characterized by comprising the following steps:
providing a substrate having opposing first and second surfaces;
providing a filter chip to the first surface, wherein the filter chip comprises a first chip body and first bumps, and a first cavity is formed between the first chip body and the first surface;
electrically connecting the first bump with the first surface;
forming an isolation layer covering the filter chip on the first surface;
forming a first plastic layer which encapsulates the filter chip and the isolation layer on the first surface, wherein the first plastic layer is isolated outside the first cavity by the isolation layer;
providing a non-filter chip to the second surface, wherein the non-filter chip comprises a second chip body and a second bump, a second cavity is formed between the second chip body and the second surface, and the second bump is positioned in the second cavity;
electrically connecting the second bump with the second surface;
and forming a second plastic sealing layer for sealing the non-filter chip on the second surface, wherein the second plastic sealing layer fills the second cavity.
8. The method of claim 7, wherein,
the method further comprises the steps of: forming solder balls on the second surface;
the forming a second molding layer encapsulating the non-filter chip to the second surface includes:
forming a second plastic layer which encapsulates the non-filter chip and the solder balls on the second surface;
the method further comprises the steps of: and removing part of the second plastic sealing layer on the tin ball so that part of the tin ball is exposed out of the second plastic sealing layer.
9. The method of chip module packaging according to claim 8, further comprising:
removing part of the second plastic sealing layer around the tin ball, so that a gap is formed between the outer peripheral wall of the tin ball and the second plastic sealing layer;
printing solder paste on the surface of the solder ball;
and (5) performing reflow soldering to finish packaging.
10. A circuit board comprising the chip module package structure of any one of claims 1 to 6.
CN202211477309.0A 2022-11-23 2022-11-23 Chip module packaging structure, packaging method and circuit board Pending CN116072620A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202211477309.0A CN116072620A (en) 2022-11-23 2022-11-23 Chip module packaging structure, packaging method and circuit board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202211477309.0A CN116072620A (en) 2022-11-23 2022-11-23 Chip module packaging structure, packaging method and circuit board

Publications (1)

Publication Number Publication Date
CN116072620A true CN116072620A (en) 2023-05-05

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Family Applications (1)

Application Number Title Priority Date Filing Date
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Country Link
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116864462A (en) * 2023-09-04 2023-10-10 唯捷创芯(天津)电子技术股份有限公司 Packaging structure and manufacturing method thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116864462A (en) * 2023-09-04 2023-10-10 唯捷创芯(天津)电子技术股份有限公司 Packaging structure and manufacturing method thereof

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