CN218769494U - Chip module packaging structure and circuit board - Google Patents
Chip module packaging structure and circuit board Download PDFInfo
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- CN218769494U CN218769494U CN202223121331.XU CN202223121331U CN218769494U CN 218769494 U CN218769494 U CN 218769494U CN 202223121331 U CN202223121331 U CN 202223121331U CN 218769494 U CN218769494 U CN 218769494U
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Abstract
The application provides a chip module packaging structure and circuit board, include: a substrate having opposing first and second surfaces; the filter chip comprises a first chip body and a first bump, wherein a first cavity is formed between the first chip body and the first surface, and the first bump is electrically connected with the first surface; the non-filter chip comprises a second chip body and a second bump, wherein a second cavity is formed between the second chip body and the second surface, and the second bump is electrically connected with the second surface and is positioned in the second cavity; the isolation layer covers the filter chip on the first surface to seal the first cavity; the first plastic packaging layer is used for packaging the filter chip and the isolation layer on the first surface and isolated outside the first cavity by the isolation layer; and the second plastic packaging layer encapsulates the non-filter chip on the second surface and fills the second cavity, so that the situation that the salient points of the non-filter chip have local cracks or are in poor contact with the substrate is avoided, and the reliability of the chip module is improved.
Description
Technical Field
The application relates to the technical field of chip packaging, in particular to a chip module packaging structure and a circuit board.
Background
The working principle of the surface acoustic wave Filter (Saw Filter) is that sound waves are transmitted on the surface of a chip, so that the surface of an interdigital transducer must be ensured not to contact other substances aiming at the packaging of the surface acoustic wave Filter, namely the surface of the chip is required to be ensured to be a cavity structure, otherwise, the signal transmission is influenced. The radio frequency module product based on the surface acoustic wave filter further comprises an antenna switch, a low-noise amplifier, a capacitor, an inductor and other conventional elements which can work without a cavity, namely a non-filter chip.
In the prior art, cavities are formed in the bottoms of all chips (including a filter chip and a non-filter chip) in a radio frequency module, and due to the fact that the duty ratio of the salient points of some non-filter components is too small, after reliability tests such as cold and hot impact are conducted, the salient points can have local cracks and are melted, and the reliability failure risk exists.
SUMMERY OF THE UTILITY MODEL
The application aims to provide a chip module packaging structure and a circuit board so as to avoid local cracks appearing on salient points of a chip and improve the reliability of a chip module.
An embodiment of a first aspect of the present application provides a chip module package structure, including: a substrate having opposing first and second surfaces; the filter chip comprises a first chip body and a first bump, wherein a first cavity is formed between the first chip body and the first surface, and the first bump is electrically connected with the first surface; the non-filter chip comprises a second chip body and a second bump, wherein a second cavity is formed between the second chip body and the second surface, and the second bump is electrically connected with the second surface and is positioned in the second cavity; the isolation layer covers the filter chip on the first surface to seal the first cavity; the first plastic packaging layer is used for packaging the filter chip and the isolation layer on the first surface and isolated from the outer side of the first cavity by the isolation layer; and the second plastic packaging layer is used for packaging the non-filter chip on the second surface and filling the second cavity.
In some examples, the first surface is provided with at least two of the filter chips, and the isolation layer extends continuously between the at least two filter chips.
In some examples, a height of the first cavity is not less than a height of the first bump.
In some examples, the first cavity has a height of 50 μm to 60 μm.
In some examples, the spacer layer has a thickness of no greater than 20 μm.
In some examples, the filter chip includes a plurality of spaced first bumps, a plurality of first metal pads respectively corresponding to the first bumps are disposed on the first surface, and the first bumps are electrically connected to the corresponding first metal pads respectively; any two adjacent first metal pads are separated by a first insulating layer arranged on the first surface, and the first insulating layer isolates the first surface from the isolating layer covering the first surface.
In some examples, the package structure further includes a solder ball disposed on the second surface, a portion of the solder ball is exposed outside the second molding layer, and another portion of the solder ball is encapsulated on the second surface by the second molding layer.
In some examples, the non-filter chip includes a plurality of spaced second bumps, the second surface is provided with a plurality of second metal pads corresponding to the solder balls and the plurality of second bumps, respectively, and the solder balls and the plurality of second bumps are electrically connected to the corresponding second metal pads, respectively; any two adjacent second metal pads are separated by a second insulating layer arranged on the second surface, and the second insulating layer isolates the second surface from the second plastic packaging layer.
In some examples, the entire first bump is located within the first cavity.
An embodiment of a second aspect of the present application provides a circuit board, which includes the chip module package structure described in the embodiment of the first aspect.
The embodiment of the application arranges the filter chip and the non-filter chip on two different surfaces of the substrate respectively, so as to be convenient for carrying out different forms of packaging on the filter chip and the non-filter chip respectively, on one hand, the cavity between the first chip body and the substrate is reserved, the filtering function is realized, on the other hand, the cavity between the second chip body and the substrate is filled by the plastic package material, the salient point of the non-filter chip is wrapped by the plastic package material, or the plastic package material provides protection for the salient point of the non-filter chip, the condition that the salient point of the non-filter chip flows after being melted in the reliability test process to cause bad contact with the substrate is avoided, the local crack of the salient point is avoided, and the reliability of the chip module is improved. In addition, the chip module packaging structure has a smaller packaging size due to the structural configuration.
Drawings
In order to more clearly illustrate the embodiments of the present specification or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, it is obvious that the drawings in the following description are only some embodiments described in the present specification, and for those skilled in the art, other drawings can be obtained according to the drawings without any creative effort. In the drawings:
FIG. 1 is a cross-sectional view of a substrate in an embodiment of the present application;
fig. 2 is a cross-sectional view illustrating a filter chip disposed on a substrate according to an embodiment of the disclosure;
fig. 3 is a cross-sectional view of an isolation layer encapsulating a filter chip in an embodiment of the present application;
fig. 4 is a cross-sectional view of a first molding layer encapsulating an isolation layer and a filter chip in an embodiment of the present application;
FIG. 5 is a cross-sectional view of a solder ball disposed on a substrate according to an embodiment of the present invention;
FIG. 6 is a cross-sectional view of a non-filter chip disposed on a substrate according to an embodiment of the present disclosure;
FIG. 7 is a cross-sectional view of a second molding compound encapsulating solder balls and a non-filter chip in an embodiment of the present application;
FIG. 8 is a cross-sectional view of an embodiment of the present application with a portion of the second molding layer removed;
FIG. 9 is a cross-sectional view of solder paste printed on the surface of a solder ball according to an embodiment of the present invention;
fig. 10 is a cross-sectional view of a chip module package structure in an embodiment of the present application.
Detailed Description
In order to make those skilled in the art better understand the technical solutions in the present specification, the technical solutions in the embodiments of the present specification will be clearly and completely described below with reference to the drawings in the embodiments of the present specification, and it is obvious that the described embodiments are only a part of the embodiments of the present specification, and not all of the embodiments. All other embodiments obtained by a person skilled in the art based on the embodiments in the present specification without any inventive step should fall within the scope of protection of the present specification.
In the embodiments of the present application, the terms "first", "second", and the like are used for distinguishing different elements by reference, but do not denote a spatial arrangement, a temporal order, or the like of the elements, and the elements should not be limited by the terms. The term "and/or" includes any and all combinations of one or more of the associated listed terms. The terms "comprising," "including," "having," and the like, refer to the presence of stated features, elements, components, and do not preclude the presence or addition of one or more other features, elements, components, and elements. The term "plurality" means two or more unless otherwise specified.
Embodiments of the first aspect
An embodiment of a first aspect of the present application provides a chip module package structure, which includes a substrate, a filter chip, a non-filter chip, an isolation layer, a first molding compound layer, and a second molding compound layer. The substrate has opposing first and second surfaces. The filter chip comprises a first chip body and a first bump, wherein a first cavity is formed between the first chip body and the first surface, and the first bump is electrically connected with the first surface. The non-filter chip comprises a second chip body and a second bump, wherein a second cavity is formed between the second chip body and the second surface, and the second bump is electrically connected with the second surface and is positioned in the second cavity. The isolation layer covers the filter chip on the first surface to seal the first cavity. The first plastic packaging layer encapsulates the filter chip and the isolation layer on the first surface, and the filter chip and the isolation layer are isolated from the outer side of the first cavity by the isolation layer. The second plastic packaging layer encapsulates the non-filter chip on the second surface and fills the second cavity.
The embodiment of the application respectively arranges the filter chip and the non-filter chip on two different surfaces (namely the first surface and the second surface) of the substrate, thereby being convenient for respectively packaging the filter chip and the non-filter chip in different forms, on one hand, the cavity between the first chip body and the substrate is reserved, and the filtering function is realized, on the other hand, the cavity between the second chip body and the substrate is filled with the plastic package material, the salient point of the non-filter chip is wrapped by the plastic package material, or the plastic package material provides protection for the salient point of the non-filter chip, the condition that the contact with the substrate is bad due to the fact that the salient point of the non-filter chip flows after being melted in the reliability test process is avoided, the local crack of the salient point is avoided, and the reliability of the chip module is improved. In addition, the chip module packaging structure has a smaller packaging size due to the structural configuration.
Embodiments of the present application will be described below with reference to the drawings.
Fig. 10 is a schematic diagram of an example of a chip module package structure according to an embodiment of the present application.
As shown in fig. 10, the substrate 1 has a first surface 101 and a second surface 102 opposed to each other. The filter chip is disposed on the first surface 101. Although fig. 10 shows two filter chips, i.e., filter chip 2 and filter chip 3, it should be understood that the number of filter chips in the embodiment of the present application may also be one or more than two, and the present application does not limit this.
As shown in fig. 10, the filter chip 2 includes a first chip body 21 and a first bump 22 disposed on the first chip body 21, a first cavity 23 is formed between the first chip body 21 and the first surface 101, the first bump 22 is located in the first cavity 23, and the first bump 22 is electrically connected to the first surface 101. Similarly, the filter chip 3 includes a first chip body 31 and a first bump 32 disposed on the first chip body 31, a first cavity 33 is formed between the first chip body 31 and the first surface 101, the first bump 32 is located in the first cavity 33, and the first bump 32 is electrically connected to the first surface 101. In the example of fig. 10, the entire first bump 22 is located within the first cavity 23 and the entire first bump 32 is located within the first cavity 33.
Although fig. 10 shows that the filter chip 2 includes two first bumps 22 and the filter chip 3 includes three first bumps 32, it should be understood that the number of bumps of each filter chip in the embodiment of the present application may be fewer or more, and the present application is not limited thereto.
As shown in fig. 10, the isolation layer 4 covers the filter chips 2 and 3 on the first surface 101 to close the first cavities 23 and 33, in other words, the first cavities 23 and 33 are closed cavities. The isolation layer 4 may be a dry film, for example, a solder mask, and the isolation layer 4 may be made of isolation materials such as green paint, epoxy resin glue, ultraviolet glue, PCB, and silica gel.
As shown in fig. 10, the first molding layer 51 encapsulates the filter chips 2 and 3 and the isolation layer 4 on the first surface 101, and is isolated from the outside of the first cavities 23 and 33 by the isolation layer 4 without entering the inside of the first cavities 23 and 33. In the example of fig. 10, the isolation layer 5 completely isolates the substrate 1 from the first molding layer 51, in other words, the substrate 1 does not contact the first molding layer 51.
As shown in fig. 10, the non-filter chip 7 includes a second chip body 71 and a second bump 72 disposed on the second chip body 71, a second cavity 73 is formed between the second chip body 71 and the second surface 102, the second bump 72 is located in the second cavity 73, and the second bump 72 is electrically connected to the second surface 102.
Although fig. 10 shows one non-filter chip 7 and the non-filter chip 7 includes four second bumps 72, it should be understood that the number of the non-filter chips 7 in the embodiment of the present application may be more than one, and the number of the bumps of each non-filter chip 7 may also be less or more, which is not limited in the present application. The non-filter chip 7 may be an antenna switch, a low noise amplifier, a capacitor, an inductor, or other electronic component that can operate without a cavity.
As shown in fig. 10, the second molding compound layer 52 encapsulates the non-filter chip 71 on the second surface 102 and fills the second cavity 73, and the second bump 72 is encapsulated by the second molding compound layer 52, so that the situation that the second bump 72 of the non-filter function chip 7 flows after being melted in the reliability test process to cause poor contact with the substrate is avoided, the second bump 72 is prevented from generating local cracks, and the reliability of the chip module is improved.
Optionally, the thickness of the isolation layer 4 is not more than 20 μm. The thickness of the spacer layer 4 may be equal to 20 μm or less than 20 μm, for example 18 μm, 15 μm, 10 μm or 5 μm. The thickness of the spacer layer 4 is therefore smaller compared to the prior art. The thinner isolation layer 4 prevents the isolation layer 4 from impacting the first bumps 22 and 32 during plastic molding to affect performance.
In some embodiments, at least two filter chips are provided on the first surface 101, and the isolation layer 4 extends continuously between at least two filter chips, for example, the isolation layer 4 may extend continuously between all filter chips or continuously between part of the filter chips. In the example of fig. 10, the isolation layer 4 extends continuously between the filter chip 2 and the filter chip 3, in other words, the isolation layer 4 continuously covers the filter chip 2 and the filter chip 3, simplifying the packaging process. In addition, because the isolation layer 4 between the filter chip 2 and the filter chip 3 is in a continuous state rather than a disconnected state after the packaging is finished, the integrity of the packaging structure is better, and the strength of the whole structure is better.
In some embodiments, as shown in fig. 10, the substrate 1 defines a height direction H in which the first surface 101 and the second surface 102 are opposite to each other. In the height direction H, the height of the first cavity 23, 33 is not less than the height of the first bump 22, 32, for example, the height of the first cavity 23, 33 is equal to the height of the first bump 22, 32. Optionally, the height of the first cavity 23, 33 is 50 μm to 60 μm, for example 55 μm.
In some embodiments, as shown in fig. 10, a plurality of first metal pads 12 corresponding to the first bumps 22 and 32 are disposed on the first surface 101 of the substrate 1, and each of the first bumps 22 and 32 is electrically connected to the corresponding first metal pad 12, for example, the first bumps 22 and 32 can be electrically connected to the first metal pads 12 by flip-chip bonding.
In the present embodiment, any two adjacent first metal pads 12 are further separated by a first insulating layer 11 disposed on the first surface 101, so that the first metal pads 12 are insulated from each other, the first insulating layer 11 isolates the first surface 101 from the isolating layer 4 covering the first surface 101, in other words, the first insulating layer 11 is disposed on the first surface 101, and the isolating layer 4 is disposed on the first insulating layer 11.
Alternatively, as shown in fig. 10, the surface of the first insulating layer 11 facing the isolation layer 4 and the surface of the first metal pad 12 facing the first bump 22, 32 are substantially flush in the height direction H, and accordingly, the isolation layer 4 extends from the surface 211, 311 of the first chip body 21, 31 facing away from the substrate 1 toward the first surface 101 to be substantially flush in the height direction H with the surface 221, 321 of the first bump 22, 32 facing the substrate 1.
In some embodiments, as shown in fig. 10, the chip module package structure further includes at least one solder ball 6, the solder ball 6 is disposed on the second surface 102, a portion of the solder ball 6 is exposed outside the second molding layer 52, and another portion of the solder ball 6 is encapsulated by the second molding layer 52. Fig. 10 shows two solder balls 6, and it should be understood that the number of solder balls 6 in the embodiment of the present application may be smaller or larger, and the present application is not limited thereto. After the filter chips 2 and 3 and the non-filter chip 7 are packaged, the solder balls 6 are exposed electrical connection pads of the package structure. The solder balls 6 may be formed on the second surface 102 by a BGA ball-mounting process.
In some embodiments, as shown in fig. 10, a plurality of second metal pads 14 corresponding to the solder balls 6 and the second bumps 72 are disposed on the second surface 102, and the solder balls 6 and the second bumps 72 are electrically connected to the corresponding second metal pads 14. The second bump 72 and the second metal pad 14 may be electrically connected by flip-chip bonding, for example.
In this embodiment, any two adjacent second metal pads 14 are separated by a second insulating layer 13 disposed on the second surface 102, so that the second metal pads 14 are insulated from each other, and the second insulating layer 13 separates the second surface 102 from the second molding layer 52.
The chip module package structure of the embodiment of the application can be obtained by the following packaging method. Fig. 1 to 10 show a flow of a preferred packaging method.
Referring to fig. 1, a packaging process may begin with providing a substrate 1. The substrate 1 has opposite first and second surfaces 101 and 102 (see fig. 2). In the example of fig. 1, a plurality of first metal pads 12 and a first insulating layer 11 insulating each first metal pad 12 are provided on the first surface 101, and a plurality of second metal pads 14 and a second insulating layer 13 insulating each second metal pad 14 are provided on the second surface 102.
Referring to fig. 2, filter chips 2, 3 are provided to the first surface 101. The filter chip 2, 3 comprises a first chip body 21, 31 and a first bump 22, 32, a first cavity 23, 33 is formed between the first chip body 21, 31 and the first surface 101, and the first bump 22, 32 is located in the first cavity 23, 33.
Referring again to fig. 2, the first bumps 22, 32 are connected to the first surface 101. Illustratively, each first bump 22, 32 may be electrically connected to each first metal pad 12 on the first surface 101 by flip-chip bonding.
Referring to fig. 3, an isolation layer 4 covering the filter chips 2, 3 is formed on the first surface 101. The spacer 4 may be a dry film, and may be an epoxy film, for example.
Referring to fig. 4, a first molding compound layer 51 is formed to encapsulate the filter chips 2 and 3 and the isolation layer 4 on the first surface 101, and the first molding compound layer 51 is isolated from the first cavities 23 and 33 by the isolation layer 4, so that the first molding compound layer 51 is prevented from filling the first cavities 23 and 33, and the filter chips 2 and 3 can realize filtering.
Referring to fig. 5, a solder ball 6 is formed on the second surface 102, and the solder ball 6 is electrically connected to the second metal pad 14. For example, a BGA ball-mounting process may be used to form solder balls 6 on the second surface 102.
Referring to fig. 6, the non-filter chip 7 is provided to the second surface 102, the non-filter chip 7 includes a second chip body 71 and a second bump 72, a second cavity 73 is formed between the second chip body 71 and the second surface 102, and the second bump 72 is located in the second cavity 73.
Referring again to fig. 6, second bump 72 is connected to second surface 102. Illustratively, each second bump 72 may be electrically connected to each second metal pad 14 on the second surface 102 by flip-chip bonding.
Referring to fig. 7, a second molding compound layer 52 encapsulating the non-filter chip 7 and the solder balls 6 on the second surface 102 is formed, and the second molding compound layer 52 fills the second cavity 73 (see fig. 8), so as to wrap and protect the second bump 72, thereby avoiding the situation that the second bump 72 of the non-filter chip 7 flows after being melted in the reliability test process to cause poor contact with the substrate, avoiding the second bump 72 from having local cracks, and improving the reliability of the chip module.
Referring to fig. 8, a portion of the second molding layer 52 on the solder ball 6 is removed, so that a portion of the solder ball 6 is exposed outside the second molding layer 52. When removing part of the second molding layer 52, it is necessary to ensure that the non-filter function chip 7 is still completely wrapped by the second molding layer 52. For example, a substrate back grinding process may be used to remove a portion of the second molding layer 52 on the solder balls 6.
Referring to fig. 9, a portion of the second molding layer 52 around the solder ball 6 is removed, so that a gap 8 is formed between the outer peripheral wall of the solder ball 6 and the second molding layer 52. For example, a laser cutting machine may be used to cut away a portion of the second molding layer 52 around the solder ball 6 to form the void 8.
Referring to fig. 9 again, solder paste 9 is printed on the surface of the solder ball 6.
Referring to fig. 10, reflow soldering is performed to complete the package. After reflow soldering, the solder paste 9 and the solder balls 6 are melted again to form new solder ball salient points, which is more suitable for the weldability of subsequent products.
Embodiments of the second aspect
Embodiments of the second aspect of the present application provide a circuit board, which includes the chip module package structure described in the embodiments of the first aspect. Since the structure of the chip module package structure has been described in detail in the embodiment of the first aspect, the contents of which are incorporated herein, the description is omitted here.
The above description is only an example of the present specification, and is not intended to limit the present specification. Various modifications and alterations to this description will become apparent to those skilled in the art. Any modification, equivalent replacement, improvement or the like made within the spirit and principle of the present specification should be included in the scope of the claims of the present specification.
Claims (10)
1. A chip module package structure, comprising:
a substrate having opposing first and second surfaces;
the filter chip comprises a first chip body and a first bump, wherein a first cavity is formed between the first chip body and the first surface, and the first bump is electrically connected with the first surface;
the non-filter chip comprises a second chip body and a second bump, wherein a second cavity is formed between the second chip body and the second surface, and the second bump is electrically connected with the second surface and is positioned in the second cavity;
the isolating layer covers the filter chip on the first surface so as to seal the first cavity;
the first plastic packaging layer is used for packaging the filter chip and the isolation layer on the first surface and isolated from the outer side of the first cavity by the isolation layer;
and the second plastic packaging layer is used for packaging the non-filter chip on the second surface and filling the second cavity.
2. The chip module package structure according to claim 1,
the first surface is provided with at least two filter chips, and the isolation layer extends continuously between the at least two filter chips.
3. The chip module package structure according to claim 1,
the height of the first cavity is not less than the height of the first bump.
4. The chip module package structure according to claim 3,
the height of the first cavity is 50-60 μm.
5. The chip module package structure according to claim 3,
the thickness of the isolation layer is not more than 20 μm.
6. The chip module package structure according to claim 1,
the filter chip comprises a plurality of first salient points at intervals, a plurality of first metal pads corresponding to the first salient points are arranged on the first surface, and the first salient points are electrically connected with the corresponding first metal pads;
any two adjacent first metal pads are separated by a first insulating layer arranged on the first surface, and the first insulating layer isolates the first surface from the isolating layer covering the first surface.
7. The chip module package structure of claim 1, further comprising:
the solder ball is arranged on the second surface, one part of the solder ball is exposed out of the second plastic packaging layer, and the other part of the solder ball is encapsulated on the second surface by the second plastic packaging layer.
8. The chip module package structure according to claim 7,
the non-filter chip comprises a plurality of second salient points at intervals, a plurality of second metal pads corresponding to the solder balls and the second salient points are arranged on the second surface respectively, and the solder balls and the second salient points are electrically connected with the corresponding second metal pads respectively; any two adjacent second metal pads are separated by a second insulating layer arranged on the second surface, and the second insulating layer isolates the second surface from the second plastic packaging layer.
9. The chip module package structure according to claim 1,
the entire first bump is located in the first cavity.
10. A circuit board comprising the chip module package structure according to any one of claims 1 to 9.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202223121331.XU CN218769494U (en) | 2022-11-23 | 2022-11-23 | Chip module packaging structure and circuit board |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202223121331.XU CN218769494U (en) | 2022-11-23 | 2022-11-23 | Chip module packaging structure and circuit board |
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| CN218769494U true CN218769494U (en) | 2023-03-28 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117240251A (en) * | 2023-11-16 | 2023-12-15 | 成都频岢微电子有限公司 | Miniaturized layout structure of filter in module |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117240251A (en) * | 2023-11-16 | 2023-12-15 | 成都频岢微电子有限公司 | Miniaturized layout structure of filter in module |
| CN117240251B (en) * | 2023-11-16 | 2024-01-30 | 成都频岢微电子有限公司 | Miniaturized layout structure of filter in module |
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