CN114974102A - Display panel and display device - Google Patents
Display panel and display device Download PDFInfo
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- CN114974102A CN114974102A CN202210760520.7A CN202210760520A CN114974102A CN 114974102 A CN114974102 A CN 114974102A CN 202210760520 A CN202210760520 A CN 202210760520A CN 114974102 A CN114974102 A CN 114974102A
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- signal line
- power supply
- display panel
- spacer region
- line
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
- G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
- G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
- G09F9/33—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements being semiconductor devices, e.g. diodes
Abstract
The embodiment of the invention provides a display panel and a display device, relates to the technical field of display, and optimizes the wiring design of the display panel under a narrow frame or no frame. The display panel includes: a display region including pixel regions and spacer regions alternately arranged in a first direction; the driving circuit is at least positioned in the pixel area and is electrically connected with the driving signal line; a first power signal line located in the spacer region; wherein the spacer includes a first spacer and a second spacer, the driving signal line is located in the first spacer, and a line width of the first power signal line in the first spacer is smaller than a line width of the first power signal line in the second spacer.
Description
[ technical field ] A method for producing a semiconductor device
The invention relates to the technical field of display, in particular to a display panel and a display device.
[ background ] A method for producing a semiconductor device
A Light Emitting Diode (LED) display panel has the advantages of self-luminescence, low driving voltage, high luminous efficiency, short response time, high definition and contrast, and the like, and is widely used in various electronic devices.
In recent years, narrow-frame and even frameless designs of display panels have become a development trend, and how to optimize the wiring design of the display panels under the narrow-frame or frameless designs is a technical problem to be solved urgently at present.
[ summary of the invention ]
In view of this, embodiments of the present invention provide a display panel and a display apparatus, which optimize the layout design of the display panel under a narrow frame or no frame.
In one aspect, an embodiment of the present invention provides a display panel, including:
a display region including pixel regions and spacer regions alternately arranged in a first direction;
the driving circuit is at least positioned in the pixel area and is electrically connected with the driving signal line;
a first power signal line located in the spacer region;
wherein the spacer region includes a first spacer region and a second spacer region, the driving signal line is located in the first spacer region, and a line width of the first power supply signal line in the first spacer region is smaller than a line width of the first power supply signal line in the second spacer region.
In another aspect, an embodiment of the present invention provides a display device, including the display panel described above.
One of the above technical solutions has the following beneficial effects:
according to the embodiment of the invention, the driving signal lines electrically connected with the driving circuit are arranged in the display area, so that the driving signal lines can be prevented from occupying space in the frame area of the display panel, and the ultra-narrow frame or frameless design of the display panel can be better realized.
Further, according to the embodiments of the present invention, by differentially designing the line widths of the first power signal lines in the first and second spacer regions, a space can be set for the driving signal line release by reducing the line width of the first power signal line in the first spacer region. On the one hand, the first spacer region can have enough space to accommodate the driving signal line, so that the driving signal line is prevented from occupying the setting space of the sub-pixels in the pixel region, and the arrangement of the sub-pixels is prevented from being influenced. On the other hand, after the line width of the first power signal line in the first spacer region is reduced, the distance between the driving signal line and the first power signal line can be increased to a certain extent, and the phenomenon that the driving signal line and the first power signal line are too close to each other to generate large parasitic capacitance can be avoided. For example, when the driving signal line and the first power supply signal line are disposed on the same layer, the horizontal distance therebetween can be increased, and when the driving signal line and the first power supply signal line are disposed on different layers, the overlapping in the longitudinal direction can be prevented. Therefore, the delay, the voltage drop and the like of the driving signal transmitted on the driving signal line can be effectively reduced, and the reliability of the working state of the driving circuit is improved.
Therefore, in the embodiment of the invention, the line widths of the first power signal lines in the first spacing region and the second spacing region are designed differently, so that the wiring design of the narrow-frame or frameless display panel can be better optimized.
[ description of the drawings ]
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a display panel according to an embodiment of the present invention;
fig. 2 is a schematic partial top view of a display panel according to an embodiment of the present invention;
FIG. 3 is a cross-sectional view taken along line A1-A2 of FIG. 2;
fig. 4 is a schematic circuit diagram of a shift circuit according to an embodiment of the present invention;
fig. 5 is a schematic partial top view of a display panel according to an embodiment of the invention;
fig. 6 is a schematic diagram of a partial top view structure of a display panel according to an embodiment of the present invention;
fig. 7 is a schematic circuit structure diagram of a pixel circuit according to an embodiment of the invention;
fig. 8 is a schematic diagram of a partial top view structure of a display panel according to an embodiment of the present invention;
fig. 9 is a schematic circuit diagram of another pixel circuit according to an embodiment of the invention;
fig. 10 is a schematic diagram of a partial top view structure of a display panel according to an embodiment of the invention;
fig. 11 is a schematic diagram of a partial top view structure of a display panel according to an embodiment of the invention;
fig. 12 is a schematic partial top view illustrating a display panel according to an embodiment of the present invention;
fig. 13 is a schematic structural diagram of a display device according to an embodiment of the present invention.
[ detailed description ] embodiments
For better understanding of the technical solutions of the present invention, the following detailed descriptions of the embodiments of the present invention are provided with reference to the accompanying drawings.
It should be understood that the described embodiments are only some embodiments of the invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The terminology used in the embodiments of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used in the examples of the present invention and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.
It should be understood that the term "and/or" as used herein is merely one type of association that describes an associated object, meaning that three relationships may exist, e.g., a and/or B may mean: a exists alone, A and B exist simultaneously, and B exists alone. In addition, the character "/" herein generally indicates that the former and latter related objects are in an "or" relationship.
The embodiment of the invention provides a display panel, which can be an LED display panel, in particular a mini LED display panel or a micro LED display panel.
As shown in fig. 1 and fig. 2, fig. 1 is a schematic structural diagram of a display panel according to an embodiment of the present invention, and fig. 2 is a schematic partial top-view structural diagram of the display panel according to the embodiment of the present invention, the display panel includes a display area 1, and the display area 1 includes pixel areas 2 and spacing areas 3 alternately arranged along a first direction x.
The display panel further includes a driving circuit 4 at least at the pixel region 2 and a first power signal line 5 at the spacer region 3. Wherein the driving circuit 4 is electrically connected to the driving signal line 6, the spacer region 3 includes a first spacer region 7 and a second spacer region 8, the driving signal line 6 is located in the first spacer region 7, and a line width of the first power supply signal line 5 in the first spacer region 7 is smaller than a line width of the first power supply signal line 5 in the second spacer region 8. Here, the line width of the first power signal line 5 refers to the length of the first power signal line 5 in the first direction x.
According to the embodiment of the invention, the driving signal lines 6 electrically connected with the driving circuit 4 are arranged in the display area 1, so that the driving signal lines 6 can be prevented from occupying space in a frame area of the display panel, and therefore, the ultra-narrow frame or frameless design of the display panel is better realized. Further, the embodiment of the invention can release the setting space for the driving signal line 6 by reducing the line width of the first power signal line 5 in the first spacer region 7 by differentially designing the line widths of the first power signal line 5 in the first spacer region 7 and the second spacer region 8. On one hand, the first spacer region 7 can have enough space to accommodate the driving signal line 6, so that the driving signal line 6 is prevented from occupying the setting space of the sub-pixels in the pixel region 2, and the arrangement of the sub-pixels is prevented from being influenced. On the other hand, when the line width of the first power signal line 5 in the first spacer region 7 is decreased, the distance between the driving signal line 6 and the first power signal line 5 can be increased to some extent, and thus, a large parasitic capacitance caused by a too close distance between the driving signal line 6 and the first power signal line 5 can be avoided. For example, when the driving signal line 6 is disposed on the same layer as the first power supply signal line 5, the horizontal distance therebetween can be increased, and when the driving signal line 6 is disposed on a different layer from the first power supply signal line 5, it can be prevented from overlapping in the longitudinal direction. Thus, the delay and voltage drop of the driving signal transmitted on the driving signal line 6 can be effectively reduced, and the reliability of the operating state of the driving circuit 4 can be improved.
Therefore, in the embodiment of the invention, by performing differential design on the line widths of the first power signal lines 5 in the first spacing regions 7 and the second spacing regions 8, the wiring design of the narrow-frame or frameless display panel can be better optimized.
Further, it should be noted that, in the embodiment of the present invention, even if the line width of the first power supply signal line 5 is reduced, the power supply signal transmitted in the display panel is not greatly affected because: in the structural design of the display panel, the line width of the power signal lines is much larger than the line width of other signal lines such as Data lines, and the power signal lines in the display panel are usually designed in a grid shape. For example, referring to fig. 6, taking a negative power supply signal line as an example, the negative power supply signal line includes a plurality of first negative power supply signal lines PVEE1 extending in the second direction y and a plurality of second negative power supply signal lines PVEE2 extending in the second direction y, and the plurality of first negative power supply signal lines PVEE1 and the plurality of second negative power supply signal lines PVEE2 cross in a horizontal and vertical direction to form a grid-like structure having an entire surface. When the first power supply signal line 5 includes the first negative power supply signal line PVEE1, even if the line width of one or some of the first negative power supply signal lines PVEE1 is reduced to make room for the driving signal line 6, the load of the negative power supply signal line as a whole is not greatly affected, and thus the transmission of the negative power supply signal is not greatly affected.
Further, as shown in fig. 3, fig. 3 is a cross-sectional view taken along a direction a1-a2 in fig. 2, and in the embodiment of the invention, the driving signal line 6 is disposed in the same layer as the first power signal line 5.
As described above, since the embodiment of the present invention can release more space to accommodate the driving signal line 6 with the first power signal line 5 in the first spacer 7, the driving signal line 6 has a sufficient arrangement space even if the driving signal line 6 is arranged in the same layer as the first power signal line 5, and the driving signal line 6 and the first power signal line 5 can have a sufficient distance therebetween to reduce the parasitic capacitance generated between the driving signal line 6 and the first power signal line 5. In this structure, the driving signal line 6 and the first power signal line 5 are formed by the same patterning process, and the process flow is relatively simple.
In a possible implementation manner, in conjunction with fig. 1 and 2, the display panel further includes a shift register 9, and the shift register 9 is electrically connected to the sub-pixels for transmitting a scan signal or a light emitting signal to the sub-pixels. The shift register 9 includes a plurality of shift circuits 10 arranged in cascade.
In the embodiment of the present invention, the driving circuit 4 may include a shift circuit 10, and at this time, the driving signal line 6 includes a first driving signal line 11 electrically connected to the shift circuit 10. That is, in the first spacer region 7 where the first driving signal line 11 is located, the line width of the first power supply signal line 5 in the first spacer region 7 is smaller than the line width of the first power supply signal line 5 in the second spacer region 8.
As shown in fig. 4 and fig. 5, fig. 4 is a schematic circuit structure diagram of a shift circuit 10 according to an embodiment of the present invention, and fig. 5 is a schematic partial top view structure diagram of a display panel according to an embodiment of the present invention, where the shift circuit 10 specifically includes a latch module 12, a logic module 13, and a buffer module 14, and the logic module 13 is electrically connected between the latch module 12 and the buffer module 14.
The latch module 12 may specifically include first through twelfth transistors M1 through M12, the logic module 13 may specifically include thirteenth through sixteenth transistors M13 through M16, and the buffer module 14 may specifically include a plurality of cmos devices 15, where each cmos device 15 includes one P-type transistor Mp and one N-type transistor Mn. The connection mode and function of the above devices are the same as those of the prior art, and are not described herein again.
In the embodiment of the present invention, the shift circuit 10 is disposed in the pixel region 2, and the first driving signal line 11 electrically connected to the shift circuit 10 is disposed in the first spacing region 7, so that the shift circuit 10 and the first driving signal line 11 can be prevented from occupying the left and right frame space, which is more beneficial to the display panel to realize the ultra-narrow frame design or the frameless frame design. Moreover, in this arrangement, the first driving signal line 11 is closer to the shift circuit 10, so that the length of the connection trace between the first driving signal line and the shift circuit can be reduced, and the overlap between the connection trace and other signal lines in the display area 1, such as data lines, can be reduced to reduce coupling.
In addition, the embodiment of the invention utilizes the first power signal line 5 in the first spacer region 7, and can also release a larger setting space for the first driving signal line 11, thereby effectively optimizing the wiring design in the display region 1 of the first driving signal line 11.
Further, In conjunction with fig. 4, In order to realize the normal operation of the shift register 9, the shift circuit 10 is electrically connected to the shift control signal line In, the first clock signal line CK1, and the second clock signal line CK2, respectively, and at this time, the first driving signal line 11 includes at least one of the shift control signal line In, the first clock signal line CK1, and the second clock signal line CK 2. For example, referring to fig. 1 and 2, the embodiment of the invention is illustrated by taking as an example that the first driving signal line 11 includes a first clock signal line CK1 and a second clock signal line CK 2.
It should be noted that, when the first driving signal line 11 includes the shift control signal line In, the first clock signal line CK1 and the second clock signal line CK2, these signal lines may be dispersedly disposed In different first spacers 7, so as to avoid the number of signal lines required to be disposed In one of the first spacers 7 from being too large, and further avoid the first power signal line 5 In the first spacer 7 from being too narrow.
In a possible implementation manner, as shown in fig. 6, fig. 6 is a schematic partial top view structure of a display panel according to an embodiment of the present invention, in which the pixel region 2 includes a plurality of pixel units 16 arranged along a second direction y, the pixel units 16 include a plurality of sub-pixels 17, the sub-pixels 17 include electrically connected pixel circuits 18 and light emitting diodes 19, and the second direction y intersects with the first direction x.
In the embodiment of the present invention, the driving circuit 4 may include a pixel circuit 18, and in this case, the driving signal line 6 includes a second driving signal line 20 electrically connected to the pixel circuit 18. That is, in the first spacer region 7 where the second driving signal line 20 is located, the line width of the first power supply signal line 5 in the first spacer region 7 is smaller than the line width of the first power supply signal line 5 in the second spacer region 8.
The embodiment of the invention can also release some setting space for the second driving signal line 20 electrically connected to the pixel circuit 18 by reducing the line width of the first power signal line 5 in the first spacer region 7, and at this time, can also optimize the wiring design of the driving signal line in the display region 1.
In a possible implementation manner, as shown in fig. 7 and 8, fig. 7 is a schematic circuit structure of the pixel circuit 18 according to the embodiment of the present invention, fig. 8 is a schematic partial top view structure of the display panel according to the embodiment of the present invention, the pixel circuit 18 is electrically connected to the first reset signal line Vref1, and the second driving signal line 20 includes the first reset signal line Vref 1. That is, in the first spacer region 7 where the first reset signal line Vref1 is located, the line width of the first power signal line 5 in the first spacer region 7 is smaller than the line width of the first power signal line 5 in the second spacer region 8.
Illustratively, the pixel circuit 18 may specifically include a first storage capacitor C1, a first second transistor T1 through a ninth second transistor T9.
The gates of the fourth transistor T4 and the fifth second transistor T5 are electrically connected to the first Scan signal line Scan1, the first pole of the fourth transistor T4 is electrically connected to the first reset signal line Vref1, the second pole of the fourth transistor T4 is electrically connected to the first pole of the fifth second transistor T5, and the second pole of the fifth second transistor T5 is electrically connected to the gate of the third second transistor T3.
The gate of the eighth second transistor T8 is electrically connected to the second Scan signal line Scan2, the first pole of the eighth second transistor T8 is electrically connected to the first reset signal line Vref1, and the second pole of the eighth second transistor T8 is electrically connected to the light emitting diode 19. Gates of the sixth second transistor T6 and the seventh second transistor T7 are electrically connected to the second Scan signal line Scan2, respectively, a first pole of the seventh second transistor T7 is electrically connected to a first pole of the third second transistor T3, a second pole of the seventh second transistor T7 is electrically connected to a first pole of the sixth second transistor T6, and a second pole of the sixth second transistor T6 is electrically connected to a gate of the third second transistor T3.
The gates of the first second transistor T1 and the ninth second transistor T9 are electrically connected to the emission control signal line Emit, respectively, the first pole of the first second transistor T1 is electrically connected to the first positive power supply signal line PVDD1, the second pole of the first second transistor T1 is electrically connected to the first pole of the third second transistor T3, the first pole of the ninth second transistor T9 is electrically connected to the second pole of the third second transistor T3, and the second pole of the ninth second transistor T9 is electrically connected to the light emitting diode 19.
A first plate of the first storage capacitor C1 is electrically connected to the first positive power signal line PVDD1, and a first plate of the second storage capacitor C2 is electrically connected to the gate of the third transistor T3.
Note that the first reset signal line Vref1 as described above refers to a reset signal line extending in the second direction y within the first space region 7, and referring to fig. 8, the display panel may further include a second reset signal line Vref2 extending in the first direction x, and the second reset signal line Vref2 is electrically connected to the first reset signal line Vref 1. So set up, can make the whole latticed structure that is of reset signal line among the display panel to reduce reset signal line's the load of walking the line, reduce the pressure drop.
In the embodiment of the invention, by reducing the line width of the first power signal line 5 in the first space area 7, it is possible to leave a sufficient disposition space for the first reset signal line Vref1, thereby disposing the first reset signal line Vref1 better in the first space area 7, so that the first reset signal line Vref1 and the second reset signal line Vref2 form a grid-like structure with a lower load.
In a possible implementation manner, as shown in fig. 9 and 10, fig. 9 is another circuit structure schematic diagram of the pixel circuit 18 according to the embodiment of the present invention, fig. 10 is another partial top view structure schematic diagram of the display panel according to the embodiment of the present invention, the pixel circuit 18 is electrically connected to the first voltage-controlled power signal line VH2, and the second driving signal line 20 may also include the first voltage-controlled power signal line VH 2. That is, in the first spacer region 7 where the first voltage-controlled power signal line VH2 is located, the line width of the first power signal line 5 in the first spacer region 7 is smaller than the line width of the first power signal line 5 in the second spacer region 8.
In conjunction with fig. 9, the pixel circuit 18 may specifically include a pulse modulation circuit 40 and a voltage control sub-circuit 41, which are electrically connected. The voltage-controlled sub-circuit 41 is used for modulating the gate potential of the driving transistor in the pulse modulation circuit 40, so as to improve the stability of the operating state of the driving transistor in the pulse modulation circuit 40, and further improve the operating reliability of the whole pixel circuit 18.
The pulse modulation circuit 40 includes a second storage capacitor C2, a tenth second transistor T10 to a sixteenth second transistor T16, and these components are similar to the connection manner of the components in the pixel circuit shown in fig. 7, and are not described herein again.
The voltage-controlled sub-circuit 41 includes a third storage capacitor C3, a seventeenth transistor T17 to a twenty-second transistor T22.
The gate of the seventeenth transistor T17 is electrically connected to the first Scan signal line Scan1, the first pole of the seventeenth transistor T17 is electrically connected to the first reset signal line Vref1, and the second pole of the seventeenth transistor T17 is electrically connected to the gate of the eighteenth transistor T18.
Gates of the nineteenth second transistor T19 and the twentieth transistor T20 are electrically connected to the second Scan signal line Scan2, respectively, a first pole of the nineteenth second transistor T19 is electrically connected to the driving signal line DW, and a second pole of the nineteenth second transistor T19 is electrically connected to the first pole of the eighteenth second transistor T18; a first pole of the twenty-second transistor T20 is electrically connected to a second pole of the eighteenth second transistor T18, and a second pole of the twentieth transistor T20 is electrically connected to the gate of the eighteenth second transistor T18.
Gates of the twenty-first second transistor T21 and the twenty-second transistor T22 are electrically connected to the emission control signal line Emit, respectively, a first pole of the twenty-first second transistor T21 is electrically connected to the first voltage-controlled power supply signal line VH2, and a second pole of the twenty-first second transistor T21 is electrically connected to the first pole of the eighteenth second transistor T18; a first pole of the twenty-second transistor T22 is electrically connected to a second pole of the eighteenth second transistor T18, and a second pole of the twenty-second transistor T22 is electrically connected to a gate of the eleventh second transistor T11 in the pulse modulation circuit 40.
A first plate of the third storage capacitor C3 is electrically connected to the Sweep signal line Sweep, and a second plate of the third storage capacitor C3 is electrically connected to a gate of the eighteenth transistor T18.
Note that the first voltage-controlled power supply signal line VH2 described above refers to a voltage-controlled power supply signal line extending in the second direction y within the first spacer 7, and referring to fig. 11, the display panel may further include a second voltage-controlled power supply signal line VH2 'extending in the first direction x, the second voltage-controlled power supply signal line VH 2' being electrically connected to the first voltage-controlled power supply signal line VH 2. By the arrangement, the voltage control power signal lines in the display panel are integrally in a grid structure, so that the wiring load of the sweep frequency signal lines is reduced, and the voltage drop is reduced.
In the embodiment of the invention, by reducing the line width of the first power signal line 5 in the first spacer 7, it is possible to leave a sufficient arrangement space for the first voltage-controlled power signal line VH2, thereby better arranging the first voltage-controlled power signal line VH2 in the first spacer 7, so that the first voltage-controlled power signal line VH2 and the second voltage-controlled power signal line VH 2' form a grid-like structure with a lower load.
In a possible implementation manner, as shown in fig. 11, fig. 11 is a schematic diagram of a partial top view structure of a display panel provided by an embodiment of the invention, in which the first power signal line 5 includes a first positive power signal line PVDD1 for providing a positive power signal, and a line width d3 of the first positive power signal line PVDD1 in the first spacing region 7 is smaller than a line width d4 of the first positive power signal line PVDD1 in the second spacing region 8.
It should be noted that the first positive power signal line PVDD1 refers to a positive power signal line extending in the second direction y in the first spacing area 7, and in conjunction with fig. 8, the display panel may further include a second positive power signal line PVDD2, the second positive power signal line PVDD2 extends in the first direction x, and the second positive power signal line PVDD2 is electrically connected to the first positive power signal line PVDD1 and crosses to form a grid structure, so as to reduce the load of the positive power signal line as a whole.
By reducing the line width of the first positive power supply signal line PVDD1 in the first spacer region 7, more setting space can be reserved for the driving signal line 6, and the wiring design of the driving signal line 6 can be optimized.
In one possible implementation, referring to fig. 2 and 6, the first power supply signal line 5 includes a first negative power supply signal line PVEE1 for providing a negative power supply signal, and a line width of the first negative power supply signal line PVEE1 in the first spacer region 7 is smaller than a line width of the first negative power supply signal line PVEE1 in the second spacer region 8.
It should be noted that the first negative power supply signal line PVEE1 refers to a negative power supply signal line extending in the second direction y within the first spacer 7, and in conjunction with fig. 8, the display panel may further include a second negative power supply signal line PVEE2, the second negative power supply signal line PVEE2 extends in the first direction x, and the second negative power supply signal line PVEE2 is electrically connected to the first negative power supply signal line PVEE1 and crosses to form a grid structure, so as to reduce the load of the negative power supply signal line as a whole.
By reducing the line width of the first negative power supply signal line PVEE1 in the first spacer region 7, more setting space can be reserved for the driving signal line 6, and the wiring design of the driving signal line 6 can be optimized.
In addition, it should be noted that when the line width of the first positive power supply signal line PVDD1 or the first negative power supply signal line PVEE1 in the first spacer 7 is decreased, the load of the first positive power supply signal line PVDD1 or the first negative power supply signal line PVEE1 is slightly increased. This difference can be compensated by adjusting the resistivity of the film or adjusting the power supply voltage supplied by the driver chip to the first positive power signal line PVDD1 or the first negative power signal line PVEE 1.
It is understood that the luminance of the led 19 is determined by the voltage difference between the positive electrode and the negative electrode thereof, and as can be seen from fig. 7 and 8, the positive electrode of the led 19 does not directly receive the positive power signal, but receives a driving voltage converted by the pixel circuit 18 according to the data signal and the positive power signal, but the negative electrode of the led 19 directly receives the negative power signal. That is, the influence of the positive power supply signal on the light emission luminance of the light emitting diode 19 is indirect, whereas the influence of the negative power supply signal on the light emission luminance of the light emitting diode 19 is direct, and therefore, the line width of the first negative power supply signal line PVEE1 in the first spacer 7 is reduced to make a space for the driving signal line 6, which is then simpler when compensating for the load of the first negative power supply signal line PVEE 1.
In a possible implementation manner, as shown in fig. 12, fig. 12 is a schematic diagram of a partial top view structure of a display panel according to an embodiment of the present invention, and the first power signal line 5 includes a first positive power signal line PVDD1 for providing a positive power signal and a first negative power signal line PVEE1 for providing a negative power signal.
The line width d3 of the first positive power supply signal line PVDD1 in the first spacer region 7 is smaller than the line width d4 of the first positive power supply signal line PVDD1 in the second spacer region 8, and the line width d1 of the first negative power supply signal line PVEE1 in the first spacer region 7 is smaller than the line width d2 of the first negative power supply signal line PVEE1 in the second spacer region 8.
When the first spacer region 7 is provided with the first positive power supply signal line PVDD1 and the first negative power supply signal line PVEE1 at the same time, by reducing the line widths of the first positive power supply signal line PVDD1 and the first negative power supply signal line PVEE1 at the same time, it is possible to avoid an excessively narrow arrangement of the first positive power supply signal line PVDD1 or the first negative power supply signal line PVEE1, and thus reduce the load difference from the first positive power supply signal line PVDD1 or the first negative power supply signal line PVEE1 in the second spacer region 8.
In one possible embodiment, referring to fig. 2, to avoid the first power signal line 5 being too narrow and having a large influence on the trace load, in the first spacing region 7, the line width of the first power signal line 5 may be larger than the line width of the driving signal line 6.
Based on the same inventive concept, an embodiment of the present invention further provides a display device, as shown in fig. 13, fig. 13 is a schematic structural diagram of the display device provided in the embodiment of the present invention, and the display device includes the display panel 100. The specific structure of the display panel 100 has been described in detail in the above embodiments, and is not described herein again. Of course, the display device shown in fig. 13 is only a schematic illustration, and the display device may be any electronic device with a display function, such as a mobile phone, a tablet computer, a notebook computer, an electronic book, or a television.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and should not be taken as limiting the scope of the present invention, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present invention should be included in the scope of the present invention.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.
Claims (12)
1. A display panel, comprising:
a display region including pixel regions and spacer regions alternately arranged in a first direction;
the driving circuit is at least positioned in the pixel area and is electrically connected with the driving signal line;
a first power signal line located in the spacer region;
wherein the spacer region includes a first spacer region and a second spacer region, the driving signal line is located in the first spacer region, and a line width of the first power supply signal line in the first spacer region is smaller than a line width of the first power supply signal line in the second spacer region.
2. The display panel according to claim 1,
the driving signal line and the first power signal line are disposed in the same layer.
3. The display panel according to claim 1,
the display panel further comprises a shift register, wherein the shift register comprises cascaded multi-stage shift circuits;
wherein the driving circuit includes the shift circuit, and the driving signal line includes a first driving signal line electrically connected to the shift circuit.
4. The display panel according to claim 3,
the shift circuit is electrically connected to a shift control signal line, a first clock signal line, and a second clock signal line, respectively, and the first driving signal line includes at least one of the shift control signal line, the first clock signal line, and the second clock signal line.
5. The display panel according to claim 1,
the pixel region includes a plurality of pixel units arranged along a second direction, the pixel units include a plurality of sub-pixels, the sub-pixels include electrically connected pixel circuits and light emitting diodes, and the second direction intersects the first direction;
wherein the driving circuit includes the pixel circuit, and the driving signal line includes a second driving signal line electrically connected to the pixel circuit.
6. The display panel according to claim 5,
the pixel circuit is electrically connected to a first reset signal line, and the second driving signal line includes the first reset signal line.
7. The display panel according to claim 5,
the pixel circuit is electrically connected to a first voltage-controlled power signal line, and the second driving signal line includes the first voltage-controlled power signal line.
8. The display panel according to claim 1,
the first power supply signal line comprises a first positive power supply signal line for providing a positive power supply signal;
a line width of the first positive power signal line in the first spacer region is smaller than a line width of the first positive power signal line in the second spacer region.
9. The display panel according to claim 1,
the first power supply signal line includes a first negative power supply signal line for supplying a negative power supply signal;
a line width of the first negative power supply signal line in the first spacer region is smaller than a line width of the first negative power supply signal line in the second spacer region.
10. The display panel according to claim 1,
the first power supply signal line includes a first positive power supply signal line for providing a positive power supply signal and a first negative power supply signal line for providing a negative power supply signal;
a line width of the first positive power signal line in the first spacer region is smaller than a line width of the first positive power signal line in the second spacer region, and a line width of the first negative power signal line in the first spacer region is smaller than a line width of the first negative power signal line in the second spacer region.
11. The display panel according to claim 1,
in the first spacer, a line width of the first power supply signal line is greater than a line width of the driving signal line.
12. A display device comprising the display panel according to any one of claims 1 to 11.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210760520.7A CN114974102A (en) | 2022-06-29 | 2022-06-29 | Display panel and display device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210760520.7A CN114974102A (en) | 2022-06-29 | 2022-06-29 | Display panel and display device |
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| Publication Number | Publication Date |
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| CN114974102A true CN114974102A (en) | 2022-08-30 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN202210760520.7A Pending CN114974102A (en) | 2022-06-29 | 2022-06-29 | Display panel and display device |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115830998A (en) * | 2022-11-29 | 2023-03-21 | 上海天马微电子有限公司 | Display panel and splicing display device |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115830998A (en) * | 2022-11-29 | 2023-03-21 | 上海天马微电子有限公司 | Display panel and splicing display device |
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