CN114944374A - 半导体装置和制造半导体装置的方法 - Google Patents

半导体装置和制造半导体装置的方法 Download PDF

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CN114944374A
CN114944374A CN202210131845.9A CN202210131845A CN114944374A CN 114944374 A CN114944374 A CN 114944374A CN 202210131845 A CN202210131845 A CN 202210131845A CN 114944374 A CN114944374 A CN 114944374A
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semiconductor device
die
leadframe
pad
encapsulant
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周安乐
王飞莹
贺伟鸿
闭香红
萧喜铭
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Nexperia BV
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Abstract

本发明涉及一种半导体装置，该半导体装置包括引线框、金属焊盘，其中该金属焊盘经由引线框与半导体装置的背侧连接。该半导体装置还包括：管芯焊盘，其中该管芯焊盘经由管芯附接材料附接到引线框；以及设置在引线框的顶面的密封剂。该密封剂使该金属焊盘与该管芯焊盘隔离。

Description

半导体装置和制造半导体装置的方法
技术领域
本发明涉及一种半导体装置。本发明还涉及一种制造半导体装置的方法。
背景技术
功率四方扁平无引线(QFN，quad-flat no-leads)或功率双扁平无引线(DFN，dual-flat no-leads)封装是本领域公知的。典型的功率QFN封装包括功率管芯和具有向下突出的外部端子的QFN结构。引线框管芯焊垫可以作为用于与印刷电路板(PCB)连接的热焊盘暴露出来。功率管芯和端子之间的互连通常是引线接合或夹片接合。这种互连引入了额外的电阻和电感，从而对最终产品的电性能产生不利影响。
在本领域中还已知的是，功率管芯焊盘可以作为端子暴露出来。专利US9214416B1公开了一种具有暴露管芯焊盘和成型件表面的功率QFN/DFN。该专利描述了一种功率DFN和功率QFN封装结构，该封装结构使凸起芯片管芯和其它元件容纳在矩阵引线框的底侧上的空腔中。此技术也适用于如球栅格阵列(Ball Grid Array，BGA)和焊盘栅格阵列(LandGrid Array，LGA)等层压基板封装。
这种材料适合于如氮化镓GaN和碳化硅SiC等高速功率化合物半导体装置。该封装允许配置单个和多个电源开关，以及控制良好的高速电源管芯开关的并联。该封装使得如级联开关、栅极驱动器、隔离器和保护装置等相关元件的共同封装必须以高开关速度紧密耦合实现。
该构架容纳引线框顶侧上的元件，并允许具有极低的互连电感和电阻的多芯片功能，以及较高的电路和功率密度。
该封装构架利用从功率管芯的两侧到外部底侧焊盘的平行热路径提供了较低的封装热阻，并且提供了补充的隔离和非隔离的顶侧散热。
这种封装结构的缺点在于，引线框结构必须使用模塑法来封装，其中端子高度的对准成为关键的制造挑战，并且由于需要额外的设计和工艺，因此制造复杂度显著增加。
发明内容
各种示例性实施例是针对如上所述的缺点和/或从以下公开内容可以变得明显的其它缺点的。
根据本发明的实施例，半导体装置包括引线框、金属焊盘，其中金属焊盘经由引线框与半导体装置的背侧连接。该半导体装置还包括管芯焊盘，其中该管芯焊盘经由管芯附接材料附接到引线框。密封剂设置在引线框的顶面上，其中该密封剂使该金属焊盘与该管芯焊盘隔离。
该引线框用作散热器。
引线框可以预镀有例如NiPdAu等适当的表面抛光。
管芯附接材料可以是导电管芯附接膜、银环氧树脂或者烧结材料。
本发明还涉及一种制造半导体装置的方法，其中该方法包括以下步骤：
--在引线框的顶侧上形成金属焊盘；
--通过管芯附接材料使管芯焊盘附接到引线框；
--使密封剂施加/点胶在引线框的顶部上，其中密封剂使金属焊盘与管芯焊盘隔离；以及
--对半导体装置进行切单。
该方法还可以包括除飞边的步骤，以便从金属焊盘和管芯焊盘去除密封剂。
根据本发明实施例的新的无引线引线框封装，进一步使两端子DFN封装小型化，这是非常有益的。使用引线框结构作为到管芯的一个互连，使得能够消除如本领域中已知的常规引线接合或夹片接合。此外，由于减小电阻和电感，半导体装置的电性能得到改善。顶部散热器特征提供增强的热性能，并且引线框焊盘构造还充当良好的瞬态热缓冲器。该引线框分块设计能够支持密封剂的模制或喷射点胶，并且不需要QFN/DFN引线框的传统胶带粘贴。
本发明的实施例提供了半导体装置的进一步小型化。与诸如DSN的芯片级封装相比，新的封装是五侧保护的，并且由于垂直电流而支持更高的功率。
附图说明
为了能够详细地理解本公开的特征，参考实施例进行更具体的描述，其中一些实施例在附图中示出。然而，应当注意，附图仅示出了典型的实施例，因此不应被认为是对本发明范围的限制。附图是为了便于理解本公开，因此不一定按比例绘制。在结合附图阅读本说明书之后，所要求保护的主题的优点对于本领域技术人员将变得显而易见，
在附图中，相同的附图标记用于表示相同的元件，并且其中：
图1示出了根据本发明的实施例的半导体装置；
图2示出了根据本发明的实施例的半导体装置；
图3示出了根据本发明的实施例的半导体装置的制造方法；
图4示出了根据本发明的实施例的半导体装置；
图5a、5b和5c示出了根据本发明实施例的半导体装置。
具体实施方式
本发明的关键特征是通过使用引线框结构作为互连来提供半导体装置的进一步小型化，使得不需要引线或夹片来实现该互连。此外，与已知的例如DSN等芯片级封装相比，根据本发明的封装是五侧保护的，并且由于垂直电流而支持更高的功率。
图1示出了本发明的一个实施例。半导体装置100包括同样用作散热器的引线框102、位于引线框102顶部的密封剂104、管芯焊盘106和金属焊盘108，所述管芯焊盘106和金属焊盘108位于密封剂104的顶部。
在该实施例中，半导体装置100的引线框结构102用作互连件。因此，半导体装置不使用引线或夹片来实现互连。
如图1所示，半导体装置100顶部的正面触点是管芯焊盘106和金属焊盘108。金属焊盘108是引线框结构102的一部分，金属焊盘108通过引线框结构102与管芯的背侧连接，从而不需要诸如引线接合或夹片之类的附加互连。这种互连方法支持管芯的垂直电流。金属焊盘108的尺寸被设计成支持瞬态热冲击。
在切单后，由该暴露的引线框形成顶部散热器。该散热器增强了半导体装置封装的热性能。
使用点胶技术，仅在引线框的一个表面上封装引线框。从五侧保护管芯。
根据本发明的实施例，一种制造半导体装置的方法包括以下步骤：
--附接管芯，
--施加/点胶(dispensing)，
--除飞边(deflash)，以及
--切单(singulate)。
根据图2所示的本发明的实施例，引线框114被分成若干块，在该特定示例中，引线框被分成四个块。这可以应用于QFN/DFN引线框设计。引线框结构通过引线框制造中的典型蚀刻工艺形成。为了便于无胶带的封装，仅在每个块内的引线框的一个表面上进行蚀刻，使得在随后的封装工艺期间密封剂不会流到引线框的另一表面。可通过适当的管芯附接方法(例如导电管芯附接膜、银环氧树脂或烧结)来附接管芯。然后使用点胶使每个块封装到与接触焊盘相同的高度水平。可包括去飞边工艺以去除接触焊盘表面上的任何密封剂飞边。由于引线框预先镀有适当的表面光洁度(例如，镍钯金NiPdAu)，因此不需要进一步的电镀工艺。最后，使用典型的切割工艺来切单。
根据图3所示的本发明的实施例，一种制造半导体装置的方法包括以下步骤：
附图标记200：在引线框102的顶侧形成金属焊盘108结构；
附图标记202：通过管芯附接材料将管芯焊盘106附接到引线框上；
附图标记204：将密封剂104施加(点胶)在引线框102的顶部；以及
附图标记206：对半导体装置100的封装件进行切单
以这种方式制造的半导体装置的封装具有由引线框结构制成的端子和暴露的管芯焊盘。
该引线框结构在封装端子与管芯焊盘的连接上起到必要作用。因此，不需要额外的引线接合或夹片接合。
同时，以这种方式制造的半导体装置在与端子相对的表面上具有顶部散热器，顶部散热器也是引线框结构的必不可少的部分。与本领域已知的典型功率QFN相比，典型功率QFN仅提供底部中心焊盘，并且在期望顶部散热器的情况下需要额外的散热板附接工艺。
根据本发明的实施例，点胶用于在引线框的顶面上封装。通过点胶，可以更容易地实现金属焊盘与管芯焊盘之间的端子高度对准。成型件需要紧密的焊盘高度对准，或者额外的管芯焊盘金属化厚度需要后续的研磨工艺的来去除模具飞边。与现有技术中已知的传统功率QFN封装相比，成型件用于在引线框和胶带的两个表面上进行封装，或者需要膜以实现高度对准，因此工艺复杂得多。
根据本发明的实施例产生的封装可以用于各种半导体装置，例如用于垂直装置的功率DFN封装(典型的为二极管)。然而，该封装也可以应用于任何其它可应用的半导体装置(例如MOSFET装置、双极晶体管装置、具有多于3个输入/输出(I/O)的装置等)。
根据本发明的实施例，可以使用引线框的替代设计(例如在引线框的两侧上进行差别蚀刻)，这样不同散热器轮廓可以产生新的封装外形。
图4中示出了本发明的该实施例。在引线框的与金属焊盘相对的另一侧蚀刻引线框，以便产生新的额外散热结构或增强元件切割分离。
上述实施例不限于所给出的示例。例如，本发明的实施例也可应用于具有2个管芯焊盘的垂直半导体装置，使得功率DFN可以是3端子封装。图5a、图5b和图5c示出了本发明的一些示例性实施例。
图5a中所示的本发明的实施例示出了作为MOSFET晶体管装置300的半导体装置。
图5b中所示的本发明的实施例示出了作为双极晶体管装置302的半导体装置。
图5c中所示的本发明的实施例示出了具有多于三个的多I/O的半导体装置304。
本发明的特定和优选方面在所附的独立权利要求中进行阐述。从属和/或独立权利要求的特征的组合可以适当地组合，而不仅仅是如权利要求中所阐述的。
本公开的范围包括其中明确地或隐含地公开的任何新颖特征或特征的组合或其任何概括，而不管其是否涉及所要求保护的发明或减轻本发明解决的任何或所有问题。由此提请申请人注意，在本申请或从其导出的任何这种进一步申请的审查期间，可以针对这些特征提出新的权利要求。特别地，参考所附权利要求，来自从属权利要求的特征可以与独立权利要求的特征组合，并且来自各个独立权利要求的特征可以以任何适当的方式组合，而不仅仅是在权利要求中列举的特定组合。
在单独实施例的上下文中描述的特征也可以在单个实施例中组合提供。相反，为了简洁起见，在单个实施例的上下文中描述的各种特征也可以单独地或以任何合适的子组合提供。
术语“包括”不排除其它元件或步骤，术语“一”或“一个”不排除多个。权利要求中的附图标记不应被解释为限制权利要求的范围。

Claims (7)

1.一种半导体装置，包括：
--引线框，
--金属焊盘，其中所述金属焊盘经由所述引线框与所述半导体装置的背侧连接，
--管芯焊盘，其中所述管芯焊盘经由管芯附接材料附接到所述引线框，以及
--设置在所述引线框的顶面的密封剂，其中所述密封剂使所述金属焊盘与所述管芯焊盘隔离。
2.如权利要求1所述的半导体装置，其中，所述引线框用作散热器。
3.根据前述权利要求中任一项所述的半导体装置，其中所述引线框预镀有例如NiPdAu等适当表面抛光处理。
4.根据前述权利要求中任一项所述的半导体装置，其中，所述管芯附接材料是导电管芯附接膜、银环氧树脂或者烧结材料。
5.如前述权利要求中的任一项所述的半导体装置，其中，所述半导体装置是二极管、或MOSFET晶体管、或双极晶体管、或具有三个以上I/O的半导体装置。
6.一种制造半导体装置的方法，其中所述方法包括以下步骤：
--在引线框的顶侧形成金属焊盘；
--通过管芯附接材料将管芯焊盘附接到所述引线框；
--将密封剂施加在所述引线框的顶部，其中所述密封剂使所述金属焊盘与所述管芯焊盘隔离；以及
--对半导体装置进行切单。
7.根据权利要求6所述的制造半导体装置的方法，其中所述方法还包括除飞边的步骤，以便从所述金属焊盘和从所述管芯焊盘去除所述密封剂。
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