CN114938568A - Circuit board structure and circuit testing method - Google Patents
Circuit board structure and circuit testing method Download PDFInfo
- Publication number
- CN114938568A CN114938568A CN202210675479.3A CN202210675479A CN114938568A CN 114938568 A CN114938568 A CN 114938568A CN 202210675479 A CN202210675479 A CN 202210675479A CN 114938568 A CN114938568 A CN 114938568A
- Authority
- CN
- China
- Prior art keywords
- pad
- circuit board
- board structure
- pads
- resistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000012360 testing method Methods 0.000 title claims abstract description 83
- 239000000758 substrate Substances 0.000 claims abstract description 22
- 238000012795 verification Methods 0.000 abstract description 7
- 238000000034 method Methods 0.000 description 8
- 238000013461 design Methods 0.000 description 6
- 238000010586 diagram Methods 0.000 description 6
- 238000012938 design process Methods 0.000 description 5
- 239000002699 waste material Substances 0.000 description 5
- 230000009471 action Effects 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000005476 soldering Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 230000002452 interceptive effect Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/111—Pads for surface mounting, e.g. lay-out
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2801—Testing of printed circuits, backplanes, motherboards, hybrid circuits or carriers for multichip packages [MCP]
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
Abstract
The application discloses a circuit board structure and a circuit testing method. The circuit board structure includes: the testing circuit comprises a substrate, a functional bus, a bridging resistor and at least two testing circuits, wherein the functional bus is distributed on the substrate and comprises a first bonding pad; at least two test circuits are distributed on the substrate, and each test circuit comprises a second bonding pad; the bridging resistor is arranged on the substrate, a first end of the bridging resistor is connected with the first bonding pad, and a second end of the bridging resistor is connected with any one of the second bonding pads. According to the embodiment that this application provided, the circuit board structure that this application provided can satisfy multiple verification demand, reduces the preparation quantity of circuit board structure to a certain extent, reduces the wasting of resources.
Description
Technical Field
The application belongs to the technical field of circuit testing, and particularly relates to a circuit board structure and a circuit testing method.
Background
A plurality of functional modules are often required to be disposed in the display panel, and the functional modules are electrically connected to each other to implement a desired function. In the design process of the display panel, it is often necessary to design different Circuit board structures according to different schematic diagrams to verify the functional module in order to debug or verify whether functions such as an IC Chip (Integrated Circuit Chip), a clock signal and the like meet design requirements, and one schematic diagram corresponds to one Circuit board structure. In the design process of the display panel, various circuit board structures for testing can be generated, and each circuit board structure has a single verification function, so that the resource waste is caused.
Therefore, a new circuit board structure and a circuit testing method are needed.
Disclosure of Invention
The embodiment of the application provides a circuit board structure and a circuit testing method, and aims to solve the problem of resource waste of the circuit board structure in the design process of a display panel.
An embodiment of a first aspect of the present application provides a circuit board structure, including:
a substrate;
the functional bus is distributed on the substrate and comprises a first bonding pad;
at least two test circuits distributed on the substrate, the test circuits including second pads;
and the bridging resistor is arranged on the substrate, a first end of the bridging resistor is connected with the first bonding pad, and a second end of the bridging resistor is connected with any one of the second bonding pads.
According to an embodiment of the first aspect of the present application, the plurality of second bonding pads are arranged at intervals around the first bonding pad.
According to any one of the preceding embodiments of the first aspect of the present application, the pitch between two adjacent second pads is equal among the plurality of second pads.
According to any one of the preceding embodiments of the first aspect of the present application, the pitch between two adjacent second pads is equal among the plurality of second pads.
According to any of the preceding embodiments of the first aspect of the present application, the area of the first pad is larger than the area of the second pad.
According to any one of the preceding embodiments of the first aspect of the present application, the substrate includes a first region and a second region, the first region is disposed around the first pad, the second region is disposed around the first region, and a part of the plurality of second pads is disposed at intervals in the first region, and another part is disposed at intervals in the second region.
According to any one of the preceding embodiments of the first aspect of the present application, the cross-over resistor is a chip resistor.
According to any one of the previous embodiments of the first aspect of the present application, the first pads are equally spaced from any one of the second pads.
According to any of the preceding embodiments of the first aspect of the present application, a functional bus comprises a plurality of first pads, the number of the cross-over resistors is multiple, and each first pad is connected to a different test circuit through a different cross-over resistor.
According to any of the preceding embodiments of the first aspect of the present application, the number of the functional buses is plural, and each functional bus is electrically connected to different test circuits through at least one first pad and at least one bridge resistor, respectively.
An embodiment of the second aspect of the present application further provides a circuit testing method, which is applied to the circuit board structure provided in any embodiment of the first aspect, and a functional bus is connected to a functional module to be tested, where the method includes:
connecting a bridge resistor to the first pad and a second pad of the first test circuit, testing the functional module connected to the functional bus, the at least two test circuits including the first test circuit;
separating the cross-over resistor from the second pad of the first test circuit;
connecting a cross-over resistor to the first pad and to a second pad of a second test circuit, testing the functional module connected to the functional bus, the at least two test circuits including the second test circuit.
In the circuit board structure and the circuit testing method provided by the embodiment of the application, the first bonding pad and the second bonding pad are arranged, and the first bonding pad and the second bonding pad are connected through the bridging resistor, so that the functional bus is electrically communicated with different testing circuits, one circuit board structure can meet various verification requirements, the preparation quantity of the circuit board structure is reduced to a certain extent, and the resource waste is reduced; the bridging resistor is arranged to connect the first bonding pad and the second bonding pad, so that compared with the jumper pin, the bridging resistor can avoid high-frequency interference caused by the jumper pin to a certain extent.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed to be used in the embodiments of the present application will be briefly described below, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a schematic cross-sectional view of a circuit board structure according to an embodiment of the first aspect of the present application;
fig. 2 is a schematic partial cross-sectional view of another circuit board structure provided in an embodiment of the first aspect of the present application;
FIG. 3 is a schematic cross-sectional view of a portion of another circuit board structure provided in an embodiment of the first aspect of the present application
Fig. 4 is a schematic partial cross-sectional view of another circuit board structure provided in an embodiment of the first aspect of the present application;
fig. 5 is a schematic flowchart of a circuit testing method according to an embodiment of the second aspect of the present application.
Reference numerals are as follows:
100. a circuit board structure; 1. a substrate; 11. a first region; 12. a second region; 2. a functional bus; 21. a first pad; 22. a first conductive line; 3. a test circuit; 31. a second pad; 32. a second conductive track 4, across the resistor.
Detailed Description
Features and exemplary embodiments of various aspects of the present application will be described in detail below, and in order to make objects, technical solutions and advantages of the present application more apparent, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are intended to be illustrative only and are not intended to be limiting. It will be apparent to one skilled in the art that the present application may be practiced without some of these specific details. The following description of the embodiments is merely intended to provide a better understanding of the present application by illustrating examples thereof.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
In a display panel in the prior art, a plurality of functional modules are often required to be arranged, and the functional modules are electrically connected with each other to realize required functions. In the design process of the display panel, it is often necessary to design different Circuit board structures according to different schematic diagrams to verify the functional module in order to debug or verify whether functions such as an IC Chip (Integrated Circuit Chip), a clock signal and the like meet design requirements, and one schematic diagram corresponds to one Circuit board structure. In the design process of the display panel, various circuit board structures for testing can be generated, and each circuit board structure has a single verification function, so that the resource waste is caused.
To solve the above problem, an embodiment of the first aspect of the present application provides a circuit board structure 100.
Referring to fig. 1, a schematic structural diagram of a circuit board structure 100 according to an embodiment of the present application is shown. The circuit board structure 100 includes: the testing circuit comprises a substrate 1, a functional bus 2, a cross-over resistor 4 and at least two testing circuits 3, wherein the functional bus 2 is distributed on the substrate 1, and the functional bus 2 comprises a first bonding pad 21; at least two test circuits 3 are distributed on the substrate 1, the test circuits 3 including second pads 31; the bridge resistor 4 is provided on the substrate 1, a first end of the bridge resistor 4 is connected 21 to the first pad, and a second end of the bridge resistor 4 is connected to any one of the second pads 31.
It will be appreciated by those skilled in the art that the functional bus 2 may further comprise a first conductive trace 22 disposed on the substrate 1, the first conductive trace 22 being connected to the first pad 21. The first conductive traces 22 can also be electrically connected to at least one functional module by connecting wires (not shown), or the first conductive traces 22 can be directly electrically connected to at least one functional module. In the case where the first conductive line 22 is electrically conducted with a functional module, the function of the functional module can be verified and debugged by the test circuit 3 designed in advance. In the case where the first conductive line 22 is electrically conducted with a plurality of functional blocks, the function of the combination of the plurality of functional blocks can be verified and debugged by the test circuit 3 designed in advance.
The test circuit 3 further includes a second conductive trace 32 provided on the substrate 1, the second conductive trace 32 being connected to the second pad 31. Different second conductive tracks 32 in different test circuits 3 may be designed according to different schematic diagrams in order to verify different circuit design principles by different test circuits 3. Those skilled in the art can design the second conductive line 32 to have different circuit configurations as desired.
The cross-over resistor 4 is also referred to as zero ohm resistance. A zero-ohm resistor is not a true resistor with zero value, and an ohm resistor is actually a resistor with a very small resistance value. The first pad 21 and the second pad 31 can be connected by the bridge resistor 4, one being an input terminal and one being an output terminal among the first terminal and the second terminal of the bridge resistor 4, and the functional bus 2 and one of the test circuits 3 can be electrically conducted. Since the bridge resistor 4 has a package structure, the bridge resistor 4 can avoid high-frequency interference caused by the jumper pin to a certain extent, compared with the jumper pin.
In the present application, which test circuit 3 needs to be used for testing, the flying resistor 4 is connected to the second pad 31 of the test circuit 3. For example: a test circuit A connected with a 5V power supply and a test circuit B connected with a 12V power supply are provided, and in the case that the 5V voltage needs to be verified, the test circuit A and the first bonding pad 21 are connected by a cross resistor 4. In the case where the verification of the 12V voltage is required, the test circuit B and the first pad 21 are connected across the resistor 4.
In the application, the functional bus 2 is electrically communicated with different test circuits 3 by arranging the first bonding pad 21 and the second bonding pad 31 and connecting the first bonding pad 21 and the second bonding pad 31 through the bridging resistor 4, so that one circuit board structure 100 can meet various verification requirements, the preparation quantity of the circuit board structure 100 is reduced to a certain extent, and the resource waste is reduced; the jumper resistor 4 is provided to connect the first pad 21 and the second pad 31, so that the jumper resistor 4 can avoid high-frequency interference caused by a jumper pin to some extent, as compared with the jumper pin.
In one embodiment, the plurality of second pads 31 are spaced around the first pad 21. The plurality of second pads 31 are disposed at a distance to avoid the adjacent second pads 31 from interfering with each other to some extent and to reduce the electrical conduction across the resistor 4 to some extent to the non-target second pads 31, which are the second pads 31 that are not currently required to be in conduction with the first pads 21. A plurality of second pads 31 are provided around the first pad 21 to facilitate switching the connection of the crossover resistor 4 to different second pads 31. Optionally, the plurality of second pads 31 are disposed on two sides of the first pad 21 opposite to each other, so that the second pads 31 are distributed more regularly.
In one embodiment, the distance between two adjacent second pads 31 in the plurality of second pads 31 is equal, so as to minimize the probability that each second pad 31 is interfered by the adjacent second pads 31.
Please refer to fig. 2, which is a schematic partial cross-sectional view of another display panel according to an embodiment of the present application. The area of the first pad 21 is larger than that of the second pad 31. To facilitate connection of the bridge resistor 4 to the first pad 21 and to increase the spacing between adjacent second pads 31.
The substrate 1 includes a first region 11 and a second region 12, the first region 11 being disposed around the first pad 21, the second region 12 being disposed around the first region 11, and a part of the plurality of second pads 31 being disposed at intervals in the first region 11, and another part being disposed at intervals in the second region 12. It will be appreciated that the distance from the second pad 31 located in the first region 11 to the first pad 21 is different from the distance from the second pad 31 located in the second region 12 to the first pad 21, so that more second pads 31 can be placed around the first pad 21 and a certain spacing distance between adjacent second pads 31 is ensured. In order to facilitate the connection of the first pad 21 and the second pad 31 by the bridge resistor 4, the second pad 31 located in the first region 11 and the second pad 31 located in the second region 12 may be staggered, that is, the connection line from the second pad 31 located in the first region 11 to the first pad 21 is not in the same line as the connection line from the second pad 31 located in the second region 12 to the first pad 21.
Optionally, the cross-over resistor 4 is a chip resistor, thereby facilitating connection of the first pad 21 and the second pad 31 by a chip mounter and a component mounter. The cross-over resistor 4 includes a first end connected to the first pad 21 and a second end connected to the second pad 31.
Referring to fig. 3, in an embodiment, the distance between the first end and the second end is not variable, the distance from the second pad 31 located in the first region 11 to the first pad 21 is different from the distance from the second pad 31 located in the second region 12 to the first pad 21, and the first pad 21 and the second pad 31 can be connected by the bridge resistor 4 with different specifications. It is also possible to provide the first pad 21 with a large area so that the first pad 21 and the second pad 31 having different spacing distances can be connected by the same specification of the bridge resistor 4. Illustratively, the cross-over resistor 4 may have one end connected to the second pad 31 located in the first region 11 and the other end connected to one end of the first pad 21 close to the second pad 31; the same size of the bridge resistor 4 may also be connected at one end to the second pad 31 at the second area 12 and at the other end to the end of the first pad 21 facing away from the second pad 31.
In another embodiment, the first pad 21 and any one of the second pads 31 are spaced apart by the same distance, so that the connection between the first pad 21 and each of the second pads 31 can be realized by the same-specification bridge resistor 4.
Referring to fig. 4, in an embodiment, one functional bus 2 includes a plurality of first pads 21, the number of the cross-over resistors 4 is plural, and each of the first pads 21 is connected to different test circuits 3 through different cross-over resistors 4.
In another embodiment, the number of the functional buses 2 is plural, and each of the functional buses 2 is electrically connected to the test circuit 3 through at least one first pad 21 and at least one bridge resistor 4, respectively.
The number of the functional buses 2 may also be plural, so that the plural functional buses 2 can be electrically connected to different test circuits 3, respectively, and the functional modules connected to the plural functional buses 2 can be tested by using the plural test circuits 3 at the same time.
Referring to fig. 5, an embodiment of the second aspect of the present application further provides a circuit testing method, applied to the circuit board structure as described above, in which a function bus is connected to a function module to be tested, the method includes:
s1, connecting the bridging resistor with the first pad and the second pad of the first test circuit, testing the functional module connected with the functional bus, wherein the at least two test circuits comprise a first test circuit;
s2, separating the bridging resistor from the second bonding pad of the first test circuit;
and S3, connecting the bridging resistor with the first bonding pad and a second bonding pad of a second test circuit, and testing the functional modules connected with the functional bus, wherein the at least two test circuits comprise the second test circuit.
In the circuit testing method provided by the present application, the bridge resistor may be connected to the first test circuit and the first pad by soldering in S1, and then the solder between the bridge resistor and the second pad of the first test circuit needs to be removed and separated in S2. The bridge resistor may also be connected to the second test circuit and the first pad by soldering in S3.
The beneficial effects of the manufacturing method of the display panel in this embodiment are the same as those of the circuit board structure, and the description of this embodiment is omitted here.
It should be understood that various forms of the flows shown above may be used, with steps reordered, added, or deleted. For example, the steps described in the present invention may be executed in parallel, sequentially, or in different orders, and are not limited herein as long as the desired result of the technical solution of the present invention can be achieved.
In accordance with the embodiments of the present invention as set forth above, these embodiments are not exhaustive and do not limit the invention to the precise embodiments disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the application and its practical application, to thereby enable others skilled in the art to best utilize the application and its various modifications as are suited to the particular use contemplated. The application is limited only by the claims and their full scope and equivalents.
Claims (10)
1. A circuit board structure, characterized in that the circuit board structure comprises:
a substrate;
the functional bus is distributed on the substrate and comprises a first bonding pad;
at least two test circuits distributed on the substrate, the test circuits including second pads;
and the bridging resistor is arranged on the substrate, a first end of the bridging resistor is connected with the first bonding pad, and a second end of the bridging resistor is connected with any one of the second bonding pads.
2. The circuit board structure of claim 1, wherein a plurality of the second pads are spaced around the first pad.
3. The circuit board structure according to claim 2, wherein a pitch between adjacent two of the second pads is equal among the plurality of second pads.
4. The circuit board structure of claim 1, wherein the first pad has an area larger than that of the second pad.
5. The circuit board structure of claim 4, wherein the substrate includes a first region and a second region, the first region being disposed around the first pad, the second region being disposed around the first region, and a portion of the plurality of second pads being disposed at intervals within the first region, another portion being disposed at intervals within the second region.
6. The circuit board structure of claim 1, wherein the shunt resistor is a chip resistor.
7. The circuit board structure of claim 1, wherein each of the second pads is spaced apart from the first pad by an equal distance.
8. The circuit board structure according to claim 1, wherein one functional bus includes a plurality of the first pads, the number of the bridge resistors is plural, and each of the first pads is connected to a different one of the test circuits through a different one of the bridge resistors.
9. The circuit board structure according to claim 1, wherein the number of the functional buses is plural, and each of the functional buses is electrically connected to a different one of the test circuits through at least one of the first pads and at least one of the bridge resistors, respectively.
10. A circuit testing method applied to a circuit board structure as claimed in any one of claims 1 to 9, the functional bus connecting functional modules to be tested, comprising:
connecting the cross-over resistor to the first pad and a second pad of a first test circuit, testing the functional module connected to the functional bus, the at least two test circuits including the first test circuit;
separating the bridge resistor from a second pad of the first test circuit;
connecting the bridge resistor to the first pad and a second pad of a second test circuit, testing the functional module connected to the functional bus, the at least two test circuits including the second test circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210675479.3A CN114938568A (en) | 2022-06-15 | 2022-06-15 | Circuit board structure and circuit testing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210675479.3A CN114938568A (en) | 2022-06-15 | 2022-06-15 | Circuit board structure and circuit testing method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN114938568A true CN114938568A (en) | 2022-08-23 |
Family
ID=82866439
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210675479.3A Pending CN114938568A (en) | 2022-06-15 | 2022-06-15 | Circuit board structure and circuit testing method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN114938568A (en) |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN203675437U (en) * | 2013-12-27 | 2014-06-25 | 乐视致新电子科技（天津）有限公司 | Circuit board and electronic device comprising same |
| US20160270226A1 (en) * | 2015-03-09 | 2016-09-15 | James Michael Parascandola | Shared resistor pad bypass |
| CN108668434A (en) * | 2018-06-22 | 2018-10-16 | 晶晨半导体（深圳）有限公司 | Without branch's alternative resistance circuit plate and electronic device |
| CN210274688U (en) * | 2019-07-12 | 2020-04-07 | 合肥联宝信息技术有限公司 | Circuit structure of printed circuit board |
| US20200342795A1 (en) * | 2017-06-20 | 2020-10-29 | HKC Corporation Limited | Test circuit and test method for display panels |
| CN113395828A (en) * | 2021-05-27 | 2021-09-14 | 合肥鑫晟光电科技有限公司 | Printed circuit board, display panel and electronic equipment |
| CN114189980A (en) * | 2021-12-15 | 2022-03-15 | 摩尔线程智能科技(北京)有限责任公司 | Circuit board assembly |
-
2022
- 2022-06-15 CN CN202210675479.3A patent/CN114938568A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN203675437U (en) * | 2013-12-27 | 2014-06-25 | 乐视致新电子科技（天津）有限公司 | Circuit board and electronic device comprising same |
| US20160270226A1 (en) * | 2015-03-09 | 2016-09-15 | James Michael Parascandola | Shared resistor pad bypass |
| US20200342795A1 (en) * | 2017-06-20 | 2020-10-29 | HKC Corporation Limited | Test circuit and test method for display panels |
| CN108668434A (en) * | 2018-06-22 | 2018-10-16 | 晶晨半导体（深圳）有限公司 | Without branch's alternative resistance circuit plate and electronic device |
| CN210274688U (en) * | 2019-07-12 | 2020-04-07 | 合肥联宝信息技术有限公司 | Circuit structure of printed circuit board |
| CN113395828A (en) * | 2021-05-27 | 2021-09-14 | 合肥鑫晟光电科技有限公司 | Printed circuit board, display panel and electronic equipment |
| CN114189980A (en) * | 2021-12-15 | 2022-03-15 | 摩尔线程智能科技(北京)有限责任公司 | Circuit board assembly |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4878155A (en) | High speed discrete wire pin panel assembly with embedded capacitors | |
| US6564355B1 (en) | System and method for analyzing simultaneous switching noise | |
| US3939381A (en) | Universal burn-in fixture | |
| JPH07193096A (en) | Device for interconnection of stepped multilayer | |
| US6787920B2 (en) | Electronic circuit board manufacturing process and associated apparatus | |
| US5923529A (en) | Card slot unit for a personal computer | |
| US20060288567A1 (en) | Sacrificial component | |
| CN109075130B (en) | Intermediate connector, the semiconductor device including intermediate connector and the method for manufacturing intermediate connector | |
| US4674811A (en) | Apparatus for connecting pin grid array devices to printed wiring boards | |
| CN109935248B (en) | Memory module card | |
| JP4115484B2 (en) | LCD panel inspection equipment | |
| US9414490B2 (en) | Electrical circuit board trace pattern to minimize capacitor cracking and improve reliability | |
| CN114938568A (en) | Circuit board structure and circuit testing method | |
| CN1469130A (en) | Electric conduction structure and method for realizing circuit change on printing circuit board | |
| CN109587933B (en) | Circuit adapter plate and testing device | |
| CN210274688U (en) | Circuit structure of printed circuit board | |
| CN110519918B (en) | Circuit board and electronic equipment | |
| CN210042351U (en) | PCB single board and PCB makeup | |
| CN214481491U (en) | Circuit board | |
| Sasaki et al. | High-Density, High-Pin-Count Flexible SMD Connector for High-Speed Data Bus | |
| CN115119401B (en) | Printed circuit board and electronic equipment | |
| CN215911425U (en) | Power module and household electrical appliance | |
| CN219678793U (en) | Printed circuit board and wiring structure thereof | |
| CN220473650U (en) | Aging board suitable for SOT23-3 packaged chip aging test | |
| JPH04324920A (en) | Mounting method for surface mounting part |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |