CN114937695A - Double-channel LDMOS device, preparation method thereof and chip - Google Patents

Double-channel LDMOS device, preparation method thereof and chip Download PDF

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Publication number
CN114937695A
CN114937695A CN202210875537.7A CN202210875537A CN114937695A CN 114937695 A CN114937695 A CN 114937695A CN 202210875537 A CN202210875537 A CN 202210875537A CN 114937695 A CN114937695 A CN 114937695A
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region
drift region
body region
dielectric layer
metal
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CN114937695B (en
Inventor
陈燕宁
赵东艳
王于波
董广智
付振
刘芳
余山
郁文
邓永峰
王凯
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Beijing Smartchip Microelectronics Technology Co Ltd
Beijing Core Kejian Technology Co Ltd
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Beijing Smartchip Microelectronics Technology Co Ltd
Beijing Core Kejian Technology Co Ltd
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    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
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Abstract

The invention provides a double-channel LDMOS device, a preparation method thereof and a chip, and belongs to the technical field of semiconductor integrated circuits. The LDMOS device comprises a semiconductor substrate, a drift region, a body region, a source region, a drain region and a grid structure, wherein the drift region, the body region, the source region, the drain region and the grid structure are arranged on the semiconductor substrate; the grid structure is arranged above the semiconductor substrate, one end of the lower surface of the grid structure is connected with the first body region, and the other end of the lower surface of the grid structure is connected with the first drift region; one end of the upper surface of the grid structure is connected with the second body region, and the other end of the upper surface of the grid structure is connected with the second drift region; the second body area is positioned above the first body area; the second drift region is positioned above the first drift region; a first drain region formed in the first drift region and a second drain region formed in the second drift region; a first source region formed in the first body region and a second source region formed in the second body region; the first drain region is communicated with the second drain region through the first metal connecting structure, and the first source region is communicated with the second source region through the second metal connecting structure.

Description

Double-channel LDMOS device, preparation method thereof and chip
Technical Field
The invention relates to the technical field of semiconductor integrated circuits, in particular to a double-channel LDMOS device, a preparation method of the double-channel LDMOS device and a chip.
Background
With the development of the times, the application fields of semiconductors have also been expanded from traditional industrial control, communication, computers, consumer electronics to new fields such as new energy, smart grid, rail transit, automotive electronics, and the like. The power semiconductor device pursues the handling of electric energy, and is required to have high withstand voltage and large current characteristics itself. LDMOS (Lateral Double-Diffused MOSFET) as a Lateral power device has the advantages of high voltage resistance, large gain, good linearity, high efficiency, good broadband matching performance and the like, and is widely applied to power integrated circuits, especially low-power and high-frequency circuits.
What is more important is that the quality of the LDMOS structure design and the reliability of the operation of the LDMOS determine the performance of the whole power integrated circuit. Therefore, it is highly desirable to fully secure the electrical characteristics and reliability of the device through the optimized design and process improvement of the device.
Disclosure of Invention
The LDMOS device shares a grid structure, has a double-layer channel and has larger on-state current, so that the driving capability of the device is improved, and the working speed of a circuit is favorably improved; the source regions of different channels are conducted, the drain regions of different channels are conducted, and the source region and the drain region are equivalently shared.
In order to achieve the above object, a first aspect of the present invention provides a dual-channel LDMOS device, including a semiconductor substrate, and a drift region, a body region, a source region, a drain region and a gate structure disposed on the semiconductor substrate, the drift region including a first drift region and a second drift region, the body region including a first body region and a second body region, the drain region including a first drain region and a second drain region, the source region including a first source region and a second source region; the grid structure is arranged above the semiconductor substrate, one end of the lower surface of the grid structure is connected with the first body region, and the other end of the lower surface of the grid structure is connected with the first drift region; one end of the upper surface of the grid structure is connected with the second body region, and the other end of the upper surface of the grid structure is connected with the second drift region; the second body region is located above the first body region; the second drift region is located above the first drift region; the first drain region is formed within the first drift region and the second drain region is formed within the second drift region; the first source region is formed within the first body region and the second source region is formed within the second body region; the first drain region is communicated with the second drain region through a first metal connecting structure, and the first source region is communicated with the second source region through a second metal connecting structure.
Further, a silicon dioxide layer is filled between the first body region and the second body region and between the first drift region and the second drift region, a first through hole and a second through hole are formed in the silicon dioxide layer, a first metal connection structure is formed in the first through hole, and a second metal connection structure is formed in the second through hole. The silicon dioxide layer separates the first body region and the first drift region from the second body region and the second drift region to form a double-channel structure.
Further, the double-channel LDMOS device further comprises a silicon layer, wherein the silicon layer is deposited above the grid structure and the silicon dioxide layer; the second drift region and the second body region are formed within the silicon layer. The silicon layer is used for subsequent ion implantation to form a second drift region, a second body region, a second source region and a second drain region.
Furthermore, the grid structure comprises a high-K dielectric layer and a metal electrode; the high-K dielectric layer comprises a first high-K dielectric layer and a second high-K dielectric layer, the first high-K dielectric layer is connected with the first body region and the first drift region, the metal electrode is arranged above the first high-K dielectric layer, and the second high-K dielectric layer is arranged above the metal electrode and connected with the second body region and the second drift region. The metal electrodes help to increase the operating speed of the circuit.
Further, the high-K dielectric layer is made of high-K metal oxide; the metal electrode is made of the same metal element as the high-K metal oxide. The metal gate electrode has strong gate control capability, the gate structure formed by combining the metal electrode layer and the high-K dielectric layer can improve the temperature stability of the device under the extremely cold and hot conditions, the high-K dielectric layer has few dielectric defects and good insulating property, and the reliability of the device is favorably improved. The metal electrode is made of the same metal elements as the high-K metal oxide, so that the matching degree and compatibility of the metal electrode layer and the high-K dielectric layer can be improved, and the metal electrode has better interface characteristics.
The second aspect of the present invention provides a method for manufacturing a double-channel LDMOS device, the method comprising:
forming a first drift region and a first body region in the semiconductor substrate by adopting an ion implantation process;
preparing a gate structure over the semiconductor substrate;
forming a first drain region in the first drift region by adopting an ion implantation process, and forming a first source region in the first body region;
growing a silicon dioxide layer, and preparing a first metal connecting structure and a second metal connecting structure in the silicon dioxide layer;
forming a silicon layer over the gate structure and the silicon dioxide layer;
forming a second drift region and a second body region in the semiconductor substrate by adopting an ion implantation process;
and forming a second drain region in the second drift region and a second source region in the second body region by adopting an ion implantation process. The method has simple process and high compatibility with the prior process.
Further, the preparing the gate structure above the semiconductor substrate includes:
preparing a first high-K dielectric layer above the semiconductor substrate;
growing a metal material above the first high-K dielectric layer, and photoetching and etching to define a metal electrode;
and preparing a second high-K dielectric layer above the metal electrode.
Furthermore, the first high-K dielectric layer and the second high-K dielectric layer are prepared by an ALD process.
Further, the growing a silicon dioxide layer and preparing a first metal connection structure and a second metal connection structure in the silicon dioxide layer includes:
growing a silicon dioxide layer, and forming a first through hole and a second through hole on the silicon dioxide layer by adopting a photoetching process;
respectively depositing Ti/TiN in the first through hole and the second through hole to be used as bonding layers;
depositing tungsten in the first via and the second via;
and removing tungsten outside the first through hole and the second through hole by adopting chemical mechanical polishing to form a first metal connecting structure and a second metal connecting structure. And TiN layers are deposited on the side walls and the bottoms of the through holes, tungsten is filled in the through holes to form a metal connecting structure, and the metal connecting structure and the TiN layers are good in adhesion and not easy to fall off.
Further, the forming the first drift region and the first body region inside the semiconductor substrate by using the ion implantation process includes:
defining a region corresponding to the first drift region above the semiconductor substrate by photoetching;
implanting ions by adopting an ion implantation process to form a first drift region;
defining a region corresponding to the first body region above the semiconductor substrate by photoetching;
and implanting ions by adopting an ion implantation process to form a first body region.
The third aspect of the invention provides a chip, and the chip adopts the double-channel LDMOS device. The chip adopting the double-channel LDMOS device has higher working speed.
Through the technical scheme, the LDMOS device provided by the invention has the advantages that the shared grid structure has the double-layer channel with larger on-state current, the driving capability of the device is improved, and the working speed of a circuit is favorably improved; the source regions of different channels are conducted, the drain regions of different channels are conducted, and the source region and the drain region are equivalently shared.
Additional features and advantages of embodiments of the invention will be set forth in the detailed description which follows.
Drawings
The accompanying drawings, which are included to provide a further understanding of the embodiments of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the embodiments of the invention and do not limit the embodiments. In the drawings:
fig. 1 is a schematic structural diagram of a double-channel LDMOS device according to an embodiment of the present invention;
FIG. 2 is a flow chart of a method for fabricating a double-channel LDMOS device according to an embodiment of the present invention;
FIG. 3A is a first schematic step of a method for manufacturing a double-channel LDMOS device according to an embodiment of the present invention;
FIG. 3B is a schematic diagram of a second step of a method for manufacturing a double-channel LDMOS device according to an embodiment of the present invention;
fig. 3C is a schematic diagram of a third step of a method for manufacturing a double-channel LDMOS device according to an embodiment of the invention;
fig. 3D is a schematic diagram illustrating a fourth step of a method for manufacturing a dual-channel LDMOS device according to an embodiment of the present invention;
fig. 3E is a schematic step diagram of a method for manufacturing a double-channel LDMOS device according to an embodiment of the invention;
fig. 3F is a sixth schematic step view of a method for manufacturing a double-channel LDMOS device according to an embodiment of the invention.
Description of the reference numerals
1-a semiconductor substrate, 201-a first body region, 202-a second body region, 301-a first drift region, 302-a second drift region, 401-a first source region, 402-a second source region, 501-a first drain region, 502-a second drain region, 6-a silicon dioxide layer, 701-a first metal connection structure, 702-a second metal connection structure, 8-a silicon layer, 901-a first high-K dielectric layer, 902-a second high-K dielectric layer, 10-a metal gate.
Detailed Description
The following detailed description of embodiments of the invention refers to the accompanying drawings. It should be understood that the detailed description and specific examples, while indicating the present invention, are given by way of illustration and explanation only, not limitation.
In this application, unless stated to the contrary, the use of directional terms such as "up, down, left and right" generally refers to the orientation or positional relationship shown in the drawings or the orientation or positional relationship in which the product is conventionally placed when in use.
The terms "first," "second," "third," and the like are used solely to distinguish one from another and are not to be construed as indicating or implying relative importance.
The terms "horizontal", "vertical", "overhang" and the like do not imply that the components are required to be absolutely horizontal, vertical or overhang, but may be slightly inclined. For example, "horizontal" merely means that the direction is more horizontal than "vertical" and does not mean that the structure must be perfectly horizontal, but may be slightly inclined.
In the description of the present application, it is also to be noted that the terms "disposed," "mounted," "connected," and "connected" are to be construed broadly unless otherwise specifically stated or limited.
Example one
Fig. 1 is a schematic structural diagram of a double-channel LDMOS device according to an embodiment of the present invention. As shown in fig. 1, the double-channel LDMOS device includes: a semiconductor substrate 1 and a drift region, a body region, a source region, a drain region and a gate structure arranged on the semiconductor substrate 1, the drift region comprising a first drift region 301 and a second drift region 302, the body region comprising a first body region 201 and a second body region 202, the drain region comprising a first drain region 501 and a second drain region 502, the source region comprising a first source region 401 and a second source region 402; the gate structure is arranged above the semiconductor substrate 1, and one end of the lower surface of the gate structure is connected with the first body region 201, and the other end of the lower surface of the gate structure is connected with the first drift region 301; one end of the upper surface of the gate structure is connected with the second body region 202, and the other end is connected with the second drift region 302; the second body region 202 is located above the first body region 201; the second drift region 302 is located above the first drift region 301; the first drain region 501 is formed in the first drift region 301, and the second drain region 502 is formed in the second drift region 302; the first source region 401 is formed within the first body region 201, and the second source region 402 is formed within the second body region 202; the first drain region 501 and the second drain region 502 are communicated through a first metal connection structure 701, and the first source region 401 and the second source region 402 are communicated through a second metal connection structure 702.
In this embodiment, a silicon dioxide layer 6 is filled between the first body region 201 and the second body region 202, and between the first drift region 301 and the second drift region 302, a first through hole and a second through hole are formed in the silicon dioxide layer 6, a first metal connection structure 701 is formed in the first through hole, and a second metal connection structure 702 is formed in the second through hole. The silicon dioxide layer 6 isolates the first body region 201 and the first drift region 301 from the second body region 202 and the second drift region 302, forming a double channel structure.
In this embodiment, the double-channel LDMOS device further includes a silicon layer 8, the silicon layer 8 being deposited over the gate structure and the silicon dioxide layer 6; the second drift region 302 and the second body region 202 are formed in the silicon layer 8. The silicon layer 8 is used for subsequent ion implantation to form the second drift region 302, the second body region 202, the second source region 402, and the second drain region 502.
In this embodiment, the gate structure includes a high-K dielectric layer and a metal electrode; the high-K dielectric layers include a first high-K dielectric layer 901 and a second high-K dielectric layer 902, the first high-K dielectric layer 901 is connected to the first body region 201 and the first drift region 301, the metal electrode is disposed above the first high-K dielectric layer 901, and the second high-K dielectric layer 902 is disposed above the metal electrode and connected to the second body region 202 and the second drift region 302. The metal electrodes help to increase the operating speed of the circuit.
In this embodiment, the high-K dielectric layer is made of a high-K metal oxide; the metal electrode is made of the same metal element as the high-K metal oxide. The metal gate electrode has strong gate control capability, the temperature stability of the device under extreme cold and extreme heat conditions can be improved by the gate structure formed by combining the metal electrode layer and the high-K dielectric layer, the defects of the high-K dielectric layer are few, the insulating property is good, and the reliability of the device is favorably improved. The metal electrode is made of the same metal elements as the high-K metal oxide, so that the matching degree and compatibility of the metal electrode layer and the high-K dielectric layer can be improved, and the interface characteristic is better. For example, the high-K dielectric layer is made of Al 2 O 3 The metal electrode layer is made of Al metal to obtain better interface characteristics; in another example, the high-K dielectric layer is made of HfO 2 If the metal electrode layer is made of Hf metal; and the following steps: the high-K dielectric layer adopts ZrO 2 And the metal electrode layer is made of Zr metal.
Example two
Fig. 2 is a flowchart of a method for manufacturing a double-channel LDMOS device according to an embodiment of the present invention, as shown in fig. 2, the method includes:
s1: forming a first drift region 301 and a first body region 201 inside the semiconductor substrate 1 by using an ion implantation process, including:
s101: defining a region corresponding to the first drift region 301 above the semiconductor substrate 1 by photoetching;
s102: implanting ions into a region corresponding to the first drift region 301 by using an ion implantation process to form the first drift region 301, and then removing the photoresist;
s103: defining a region corresponding to the first body region 201 above the semiconductor substrate 1 by photoetching;
s104: ions are implanted into a region corresponding to the first body region 201 by an ion implantation process to form the first body region 201, and then the photoresist is removed, and the structure after the preparation is as shown in fig. 3A.
The semiconductor substrate 1, having completed the two-region ion implantation, is then annealed, enabling simultaneous annealing of the first drift region 301 and the first body region 201. Different ions can be implanted according to different requirements of the device to form the first drift region 301 and the first body region 201 with different conductivity types. For example, if the N-type first drift region 301 needs to be formed, phosphorus ions may be implanted, and if the P-type first drift region 301 needs to be formed, boron ions may be implanted. Similarly, boron implantation is adopted for the first body region 201 of the NLDMOS device, and phosphorus implantation is adopted for the first body region 201 of the PLDMOS device.
In this embodiment, the photolithography technique includes sequentially performing photoresist throwing, exposure, and development.
S2: preparing a gate structure above the semiconductor substrate 1, specifically comprising:
s201: a first high-K dielectric layer 901 is prepared above the semiconductor substrate 1, and in this embodiment, the first high-K dielectric layer 901 is prepared by using an ALD process.
S202: and growing a metal material above the first high-K dielectric layer 901, and photoetching and etching to define a metal electrode. In this embodiment, a sputtering process is used to grow a metal material above the first high-K dielectric layer 901, and then a pattern of a metal electrode is defined by photolithography, and excess metal is removed by etching to form the metal electrode.
S203: a second high-K dielectric layer 902 is prepared over the metal electrode. In this embodiment, an ALD process is used to fabricate the second high-K dielectric layer 902, and the structure is shown in fig. 3B after the fabrication is completed.
In the present application, the high-K dielectric layer is made of a high-K metal oxide; the metal electrode is made of the same metal element as the high-K metal oxide. The metal gate electrode has strong gate control capability, the gate structure formed by combining the metal electrode layer and the high-K dielectric layer can improve the temperature stability of the device under the extremely cold and hot conditions, the high-K dielectric layer has few dielectric defects and good insulating property, and the reliability of the device is favorably improved. The metal electrode is made of the same metal elements as the high-K metal oxide, so that the matching degree and compatibility of the metal electrode layer and the high-K dielectric layer can be improved, and the interface characteristic is better. For example, the high-K dielectric layer is made of Al 2 O 3 The metal electrode layer is made of Al metal to obtain better interface characteristics; in another example, the high-K dielectric layer is made of HfO 2 If the metal electrode layer is made of Hf metal; the following steps are repeated: the high-K dielectric layer adopts ZrO 2 And the metal electrode layer is made of Zr metal.
S3: a first drain region 501 is formed in the first drift region 301 by an ion implantation process, and a first source region 401 is formed in the first body region 201, and the structure after the preparation is shown in fig. 3C.
In some embodiments, the positions of the first source region 401 and the first drain region 501 are first defined by using a photolithography technique, phosphorus ion and arsenic ion implantation is used for an NLDMOS device, boron ion implantation is used for a PLDMOS device, and then rapid annealing is performed on the source region and the drain region.
S4: growing a silicon dioxide layer 6, and preparing a first metal connection structure 701 and a second metal connection structure 702 in the silicon dioxide layer 6, specifically including:
s401: growing a silicon dioxide layer 6, forming a first through hole and a second through hole on the silicon dioxide layer 6 by adopting a photoetching process, and depositing Si by adopting PECVD in the embodimentO 2 。
S402: respectively depositing Ti/TiN in the first through hole and the second through hole to be used as bonding layers;
s403: depositing tungsten in the first via and the second via;
s404: and removing tungsten outside the first through hole and the second through hole by adopting chemical mechanical polishing to form a first metal connecting structure 701 and a second metal connecting structure 702, wherein the prepared structure is shown as fig. 3D. And TiN layers are deposited on the side walls and the bottoms of the through holes, tungsten is filled in the through holes to form a metal connecting structure, and the metal connecting structure and the TiN layers are good in adhesion and not easy to fall off.
S5: a silicon layer 8 is formed over the gate structure and the silicon dioxide layer 6. in this embodiment, the silicon layer 8 is formed by deposition over the gate structure and the silicon dioxide layer 6. the completed structure is shown in fig. 3E.
S6: the second drift region 302 and the second body region 202 are formed inside the semiconductor substrate 1 using an ion implantation process. The steps of forming the second drift region 302 and the second body region 202 in this embodiment are the same as the steps of forming the first drift region 301 and the first body region 201, and are not described again here.
S7: an ion implantation process is performed to form a second drain region 502 in the second drift region 302 and a second source region 402 in the second body region 202, and the completed structure is shown in fig. 3F. The steps of forming the second drain region 502 and the second source region 402 in this embodiment are the same as the steps of forming the first drain region 501 and the first source region 401, and are not described again. The method has simple process and high compatibility with the prior process.
The third aspect of the invention provides a chip, and the chip adopts the double-channel LDMOS device. The chip adopting the double-channel LDMOS device has higher working speed.
It should be noted that, in the art, a material having a dielectric constant greater than 3.9 belongs to the high-K material. The dielectric constant of the high-K metal oxide in the present application meets the above range.
The double-channel LDMOS device provided by the invention has double-layer channels and shares a grid, a source and a drain, so that large on-state current is obtained, the driving capability of the device is improved, and the working speed of a circuit is further improved. The metal gate electrode is adopted, so that the resistance is small, the gate control capability is strong, the working speed of a circuit is favorably improved, and the temperature stability of the high-K dielectric layer is good.
While the embodiments of the present invention have been described in detail with reference to the accompanying drawings, the embodiments of the present invention are not limited to the details of the above embodiments, and various simple modifications can be made to the technical solution of the embodiments of the present invention within the technical idea of the embodiments of the present invention, and the simple modifications are within the scope of the embodiments of the present invention. It should be noted that the various features described in the above embodiments may be combined in any suitable manner without departing from the scope of the invention. In order to avoid unnecessary repetition, the embodiments of the present invention will not be described separately for the various possible combinations.
In addition, any combination of the various embodiments of the present invention is also possible, and the same should be considered as disclosed in the embodiments of the present invention as long as it does not depart from the spirit of the embodiments of the present invention.

Claims (11)

1. A dual-channel LDMOS device comprising: a semiconductor substrate (1) and a drift region, a body region, a source region, a drain region and a gate structure arranged on the semiconductor substrate (1), characterized in that the drift region comprises a first drift region (301) and a second drift region (302), the body region comprises a first body region (201) and a second body region (202), the drain region comprises a first drain region (501) and a second drain region (502), the source region comprises a first source region (401) and a second source region (402); the grid structure is arranged above the semiconductor substrate (1), one end of the lower surface of the grid structure is connected with the first body region (201), and the other end of the lower surface of the grid structure is connected with the first drift region (301); one end of the upper surface of the grid structure is connected with the second body region (202), and the other end of the upper surface of the grid structure is connected with the second drift region (302); the second body region (202) is located above the first body region (201); the second drift region (302) is located above the first drift region (301); the first drain region (501) is formed within the first drift region (301) and the second drain region (502) is formed within the second drift region (302); the first source region (401) is formed within the first body region (201), the second source region (402) is formed within the second body region (202); the first drain region (501) is communicated with the second drain region (502) through a first metal connecting structure (701), and the first source region (401) is communicated with the second source region (402) through a second metal connecting structure (702).
2. The double-channel LDMOS device according to claim 1, wherein a silicon dioxide layer (6) is filled between the first body region (201) and the second body region (202) and between the first drift region (301) and the second drift region (302), a first through hole and a second through hole are formed in the silicon dioxide layer (6), a first metal connection structure (701) is formed in the first through hole, and a second metal connection structure (702) is formed in the second through hole.
3. The double-channel LDMOS device of claim 2, further comprising a silicon layer (8), wherein the silicon layer (8) is deposited over the gate structure and the silicon dioxide layer (6); the second drift region (302) and second body region (202) are formed within the silicon layer (8).
4. The dual-channel LDMOS device set forth in claim 1 wherein said gate structure comprises a high K dielectric layer and a metal electrode; the high-K dielectric layer comprises a first high-K dielectric layer (901) and a second high-K dielectric layer (902), the first high-K dielectric layer (901) is connected with the first body region (201) and the first drift region (301), the metal electrode is arranged above the first high-K dielectric layer (901), and the second high-K dielectric layer (902) is arranged above the metal electrode and connected with the second body region (202) and the second drift region (302).
5. The double-channel LDMOS device of claim 4, wherein the high-K dielectric layer is made of a high-K metal oxide; the metal electrode is made of the same metal elements as the high-K metal oxide.
6. A preparation method of a double-channel LDMOS device is characterized by comprising the following steps:
forming a first drift region (301) and a first body region (201) inside a semiconductor substrate (1) by adopting an ion implantation process;
preparing a gate structure above the semiconductor substrate (1);
forming a first drain region (501) inside a first drift region (301) and a first source region (401) inside the first body region (201) by adopting an ion implantation process;
growing a silicon dioxide layer (6), and preparing a first metal connecting structure (701) and a second metal connecting structure (702) in the silicon dioxide layer (6);
forming a silicon layer (8) over the gate structure and the silicon dioxide layer (6);
forming a second drift region (302) and a second body region (202) inside the semiconductor substrate (1) by adopting an ion implantation process;
a second drain region (502) is formed inside the second drift region (302) and a second source region (402) is formed inside the second body region (202) using an ion implantation process.
7. The method for manufacturing a double-channel LDMOS device according to claim 6, wherein the manufacturing of the gate structure over the semiconductor substrate (1) comprises:
preparing a first high-K dielectric layer (901) above the semiconductor substrate (1);
growing a metal material above the first high-K dielectric layer (901), and photoetching and etching to define a metal electrode;
a second high-K dielectric layer (902) is prepared over the metal electrode.
8. The method for manufacturing the double-channel LDMOS device as claimed in claim 7, wherein the first high-K dielectric layer (901) and the second high-K dielectric layer (902) are manufactured by an ALD process.
9. The method for manufacturing a double-channel LDMOS device as claimed in claim 6, wherein the growing a silicon dioxide layer (6) and the manufacturing a first metal connection structure (701) and a second metal connection structure (702) in the silicon dioxide layer (6) comprises:
growing a silicon dioxide layer (6), and forming a first through hole and a second through hole on the silicon dioxide layer (6) by adopting a photoetching process;
respectively depositing Ti/TiN in the first through hole and the second through hole to be used as bonding layers;
depositing tungsten in the first via and the second via;
and removing tungsten outside the first through hole and the second through hole by adopting chemical mechanical polishing to form a first metal connecting structure (701) and a second metal connecting structure (702).
10. The method for manufacturing a double-channel LDMOS device as claimed in claim 6, wherein the forming the first drift region (301) and the first body region (201) inside the semiconductor substrate (1) by using an ion implantation process comprises:
defining a region corresponding to the first drift region (301) above the semiconductor substrate (1) by photoetching;
implanting ions by adopting an ion implantation process to form a first drift region (301);
defining a region corresponding to the first body region (201) above the semiconductor substrate (1) by photoetching;
ions are implanted using an ion implantation process to form a first body region (201).
11. A chip employing the double channel LDMOS device of any one of claims 1 to 5.
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Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0066068A2 (en) * 1981-05-19 1982-12-08 International Business Machines Corporation Structure and process for fabrication of stacked complementary MOS field effect transistor devices
JP2000077614A (en) * 1998-08-28 2000-03-14 Nec Corp Field-effect transistor
US20060027869A1 (en) * 2003-07-24 2006-02-09 Samsung Electronics Co., Ltd. Vertical double-channel silicon-on-insulator transistor and method of manufacturing the same
CN101241934A (en) * 2007-02-08 2008-08-13 台湾积体电路制造股份有限公司 Semiconductor devices and fabrication methods thereof
CN102097327A (en) * 2009-12-02 2011-06-15 万国半导体股份有限公司 Dual channel trench LDMOS transistors and BCD process with deep trench isolation
US20130009217A1 (en) * 2011-07-06 2013-01-10 Haizhou Yin Transistor, Method for Manufacturing Transistor, and Semiconductor Chip Comprising the Transistor
CN107546204A (en) * 2016-06-24 2018-01-05 英飞凌科技股份有限公司 Semiconductor devices and its manufacture method and LDMOS transistors including LDMOS transistors
US20180040695A1 (en) * 2016-08-08 2018-02-08 Tokyo Electron Limited Three-dimensional semiconductor device and method of fabrication
US20190172828A1 (en) * 2017-12-04 2019-06-06 Tokyo Electron Limited Semiconductor apparatus having stacked gates and method of manufacture thereof
US11024749B1 (en) * 2020-06-15 2021-06-01 Taiwan Semiconductor Manufacturing Company Limited Dual channel transistor device and methods of forming the same

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0066068A2 (en) * 1981-05-19 1982-12-08 International Business Machines Corporation Structure and process for fabrication of stacked complementary MOS field effect transistor devices
JP2000077614A (en) * 1998-08-28 2000-03-14 Nec Corp Field-effect transistor
US20060027869A1 (en) * 2003-07-24 2006-02-09 Samsung Electronics Co., Ltd. Vertical double-channel silicon-on-insulator transistor and method of manufacturing the same
CN101241934A (en) * 2007-02-08 2008-08-13 台湾积体电路制造股份有限公司 Semiconductor devices and fabrication methods thereof
CN102097327A (en) * 2009-12-02 2011-06-15 万国半导体股份有限公司 Dual channel trench LDMOS transistors and BCD process with deep trench isolation
US20130009217A1 (en) * 2011-07-06 2013-01-10 Haizhou Yin Transistor, Method for Manufacturing Transistor, and Semiconductor Chip Comprising the Transistor
CN107546204A (en) * 2016-06-24 2018-01-05 英飞凌科技股份有限公司 Semiconductor devices and its manufacture method and LDMOS transistors including LDMOS transistors
US20180040695A1 (en) * 2016-08-08 2018-02-08 Tokyo Electron Limited Three-dimensional semiconductor device and method of fabrication
US20190172828A1 (en) * 2017-12-04 2019-06-06 Tokyo Electron Limited Semiconductor apparatus having stacked gates and method of manufacture thereof
US11024749B1 (en) * 2020-06-15 2021-06-01 Taiwan Semiconductor Manufacturing Company Limited Dual channel transistor device and methods of forming the same

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
李欢,陈骏骥，陈星弼: "一种基于扩展栅的改进的双通道ＯＰＴＶＬＤｐ－ＬＤＭＯＳ", 《微电子学》 *

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