TW202013460A - Shielded gate mosfet and fabricating method thereof - Google Patents

Abstract

A fabricating method of shielded gate MOSFET is provided. First, it is forming a trench on a semiconductor substrate, and a sacrifice oxide layer which covers at least the side wall of the trench is formed. Then, a source is formed in the trench, and an isolation oxide layer is formed above the source, providing that the source is totally wrapped by the sacrifice oxide layer and the isolation oxide layer. Next, the trench is refilled by polycrystalline silicon, after that, the back etching process is carried out to control the thickness of isolation oxide layer above the source. In addition, a gate oxide layer which covers at least the side wall of the trench is formed. Finally, a gate is formed in the trench, and ion implantation is made to form the body layer and heavily doped region around the trench.

Description

Shielded gate-type metal-oxygen half-field effect transistor and manufacturing method thereof

The present invention relates to a trench metal oxide semi-field effect transistor and a manufacturing method thereof. More specifically, it is a shielded gate metal oxide semi-field effect transistor capable of controlling the thickness of an oxide layer And its manufacturing method.

Metal-oxygen half-field effect transistors are widely used in switching devices of power devices, such as power supplies, rectifiers, or low-voltage motor controllers. Today's metal oxide half-field effect transistors are mostly designed with vertical structures, such as trench metal oxide half-field effect transistors, in order to increase device density. Shielded gate metal oxide half field effect transistor, or split-gate metal oxide half field effect transistor, this structure is commonly used in the industry to improve the conventional trench metal oxide half field effect The excessive gate-drain capacitance in the transistor structure can reduce the switching loss.

Shielded gate-type metal-oxide half-field effect transistor, one of the structures is to separate the gate and the shield electrode in the trench-type metal-oxide half-field effect transistor by a dielectric layer or an oxide layer, which is divided into two potentials. The upper gate is used for channel formation of the metal-oxide half-field effect transistor, the lower electrode is electrically connected to the source potential, and the gate and the source are insulated from each other by a dielectric layer or an oxide layer. The oxide layer must have sufficient quality and thickness to maintain the necessary voltage between the gate and the source.

At present, there are two conventional manufacturing methods of shielded gate-type metal oxide half-field effect transistors. One manufacturing method is that when depositing or oxidizing to form a gate oxide layer, an isolated oxide layer between the source and the gate is simultaneously generated The advantage of this method is that the manufacturing process is simple, but the thickness of the isolation oxide layer is thin, and the uniformity of the isolation oxide layer is not controlled, so that the insulation between the gate and the source is poor, and the chip yield is low. In order to improve this problem, the oxide layer is bound to be thickened, which in turn will cause the threshold voltage of the metal-oxide half-field effect transistor to increase, which limits the types and applications of the products.

Another manufacturing method is to deposit a thick oxide layer between the gate and the source, and then etch back to the depth set by the gate, and then form the gate oxide layer and perform the gate polysilicon Backfill, this method can avoid uneven thickness of isolation oxide layer. However, this method can only be carried out on expensive special machines, and the depth control of the etch back must be quite fine. Therefore, the industry currently needs a simple and low-cost manufacturing method to effectively maintain the insulation between the gate and the source, to ensure the thickness of the oxide layer, and to maintain the yield of the chip.

In view of the above-mentioned conventional problems, the object of the present invention is to provide a shielded gate type metal oxide semi-field effect transistor which is simpler and can effectively control the thickness of the oxide layer without using a special machine and a manufacturing method thereof.

In order to achieve the above object, the present invention provides a method for manufacturing a shielded gate metal oxide semiconductor field effect transistor, which includes the following steps: forming a semiconductor substrate with a trench; forming a sacrificial oxide layer in the trench by oxidation, the sacrificial oxide layer is at least Covering the sidewalls of the trench; forming the source polysilicon region in the trench; forming an insulating oxide layer by oxidation on the source polysilicon region so that the source polysilicon region is completely covered by the sacrificial oxide layer and the insulating oxide layer; filled with polysilicon deposition Go into the trench and etch back to control the thickness of the insulating oxide layer above the source polysilicon region; form the gate oxide layer in the trench by oxidation, the gate oxide layer covers at least the sidewall of the trench; form the gate polysilicon region in the trench ; And ion implantation to form the base layer and heavily doped region surrounding the trench.

In one embodiment, the manufacturing method of the shielded gate metal oxide semiconductor field effect transistor further includes the following steps: before forming the gate oxide layer, the trench is filled with polysilicon deposition and etched back to form a buffered polysilicon region to control the source polysilicon The thickness of the insulating oxide layer above the area.

In one embodiment, the manufacturing method of the shielded gate metal oxide semiconductor field effect transistor further includes the following steps: when the gate oxide layer is formed by oxidation, the buffer polysilicon region is oxidized to form a part of the gate oxide layer to control the source The thickness of the insulating oxide layer and gate oxide layer above the extremely polysilicon region.

In one embodiment, the manufacturing method of the shielded gate metal oxide semiconductor field effect transistor further includes the following steps: providing a semiconductor substrate; depositing a hard mask layer on the semiconductor substrate; and patterning trenches on the semiconductor substrate and the hard mask layer Build; and dry etching to form trenches.

In one embodiment, the manufacturing method of the shielded gate metal oxide semiconductor field effect transistor further includes the following steps: electrically connecting the polysilicon deposition to the source electrode, and replacing the electrodes of the polysilicon region in the middle and lower layers of the trench to form the source polysilicon region.

In one embodiment, the method for manufacturing a shielded gate metal oxide semiconductor field effect transistor further includes the following steps: forming a well region and a heavily doped region on the base layer by ion implantation; forming an inner region above the gate polysilicon region Interlayer dielectric (ILD) and Boro-Phospho-Silicate Glass (BPSG); contact etching, implantation of contact areas, and formation of metal layers and metal mask layers.

The invention also provides a shielded gate-type metal oxide half-field effect transistor, which includes a semiconductor substrate, an isolation oxide layer, a source polysilicon region, a gate polysilicon region, and a gate oxide layer. The semiconductor substrate has a trench. The isolation oxide layer is located in the trench. The source polysilicon region is located in the first part of the trench with a deeper depth and is covered by an insulating oxide layer. The gate polysilicon region is located in the second part of the trench with a shallow depth. The gate oxide layer is located between the gate polysilicon region and the source polysilicon region. The isolation oxide layer and the gate oxide layer are used to isolate the gate polysilicon region and the source polysilicon region, and the thicknesses of the isolation oxide layer and the gate oxide layer are controlled by the polysilicon deposition more than once into the trench and the etching process.

In one embodiment, the shielded gate-type metal-oxide half-field effect transistor further includes a buffered polysilicon region between the isolation oxide layer and the gate oxide layer.

In one embodiment, the materials used in the gate polysilicon region and the source polysilicon region include polysilicon, doped polysilicon, metal, amorphous silicon, or a combination thereof, and the materials used to isolate the oxide layer and the gate oxide layer It is silicon oxide.

In one embodiment, the semiconductor substrate includes a base and an epitaxial layer. The epitaxial layer grows epitaxially above the substrate.

In the drawings, for clarity, the relative thickness and position of the film layers, regions, and/or structural elements may be reduced or enlarged, and some conventional elements are omitted.

FIGS. 1A to 1E are, in sequence, simplified cross-sectional views illustrating various stages in the process of forming a trench 110 and a sacrificial oxide layer 108 according to an embodiment of the invention. As shown in FIG. 1A, a semiconductor substrate is provided in this embodiment. The semiconductor substrate may include a base 100 and an epitaxial layer 102. The substrate 100 is formed by ion implantation of a first conductive type heavy dopant on a silicon substrate. The epitaxial layer 102 is epitaxially grown on the substrate 100 and is formed by ion implantation of the first conductive type light dopant. For example, in one embodiment, the first conductivity type is N-type, and the second conductivity type is P-type. In another embodiment, the first conductivity type is P-type and the second conductivity type is N-type. Next, as shown in FIG. 1B, a hard mask layer 104 is deposited on the epitaxial layer 102. As shown in FIG. 1C, the photoresist 106 is coated on the hard mask layer 104. As shown in FIG. 1D, the hard mask curtain layer 104 is first etched by the photoresist 106 and then the photoresist 106 is removed to define the location and range of the trench, and then the hard mask curtain layer 104 is used as a mask to expose A portion of the epitaxial layer 102 is etched, such as dry etching, to complete trench pattern layout to form the trench 110, and then remove the hard mask layer 104. As shown in FIG. 1E, a sacrificial oxide layer 108 is formed in the trench 110 by oxidation, and the sacrificial oxide layer 108 covers at least the sidewall of the trench 110.

2A to 2C are, in sequence, simplified cross-sectional views illustrating various stages in the process of forming the source polysilicon region 114 according to an embodiment of the invention. As shown in FIG. 2A, using conventional polysilicon deposition techniques, such as chemical vapor deposition (CVD), physical vapor deposition (PVD) or other suitable film-forming processes, sacrificial oxidation in the trench 110 Polysilicon 113 is deposited on layer 108 and fills trench 110. As shown in FIG. 2B, a conventional etching process, such as anisotropic etching, etch back, dry etching, etc., is used to thin the polysilicon 113 to form the source polysilicon region 114. For example, the polysilicon deposition is electrically connected to the external source, and the polysilicon region in the middle and lower layers of the trench replaces the electrode to form the source polysilicon region 114. This process can convert the original gate-drain capacitance to drain-source capacitance, which can greatly reduce the Miller capacitance and improve the switching efficiency and speed of the device. As shown in FIG. 2C, an insulating oxide layer 112 is formed by oxidation on the source polysilicon region 114, so that the source polysilicon region 114 is completely covered by the sacrificial oxide layer 108 and the insulating oxide layer 112. It should be noted that the present invention has buffer polysilicon deposition and etching steps (detailed in FIGS. 3A to 3C later) before the upper gate polysilicon deposition in the manufacturing process, so the gate oxide polysilicon is not directly deposited to form the gate polysilicon Region, so that the thickness of the insulating oxide layer 112 can be controlled and a uniform thickness can be maintained.

In the first preferred embodiment, after the processes shown in FIGS. 1A to 1E and 2A to 2C are sequentially executed, the processes shown in FIGS. 3A and 3B, 4A to 4C, and FIG. The process shown in 5A to 5D. 3A and 3B are sequentially simplified cross-sectional views illustrating various stages in the process of forming the buffer polysilicon region 116 according to an embodiment of the present invention, and FIGS. 4A to 4C are sequentially formed according to an embodiment of the present invention. Simplified cross-sectional views of various stages in the process of the gate polysilicon region 120. FIG. 5A to FIG. 5D are sequentially simplified cross-sectional views illustrating the stages of the process of forming the base layer 122 and the heavily doped region 124 according to an embodiment of the present invention. . Since the sacrificial oxide layer 108, the insulating oxide layer 112 and the gate oxide layer 118 shown in FIGS. 4A to 4C are all oxide layers, they are only generated at different stages in the manufacturing process. For clarity, in FIGS. 5A to 5D Treat them as one and delete their boundaries and symbols.

In the first preferred embodiment, as shown in FIG. 3A, polysilicon 115 is deposited on the insulating oxide layer 112 and etched back to form a buffered polysilicon region 116 as shown in FIG. 3B. It should be noted that the depth of the etch back can be controlled very accurately. If the etch back as shown in FIG. 3B makes the buffer polysilicon region 116 have a thinner thickness, then as shown in FIG. 4A, the gate oxide layer is formed by oxidation When 118 is in the trench 110, the buffer polysilicon region 116 is completely oxidized to form a part of the gate oxide layer 118, thereby controlling the thickness of the oxide layer. The gate oxide layer 118 covers at least the sidewall of the trench 110. At the same time, the doping concentration of the buffer polysilicon region 116 can be adjusted to adjust the thickness of the grown gate oxide layer 118. As shown in FIGS. 4B and 4C, polysilicon 119 is then deposited and etched again to form gate polysilicon region 120 in trench 110.

Next, as shown in FIG. 5A, a blanket body implantation and drive-in process is performed to form a base layer 122 along the upper half of the epitaxial layer 102, such as a P-type well region. As shown in FIG. 5B, a blanket body implantation and drive-in process is performed to form a heavily doped region 124, such as an N+ source region, along the base layer 122. As shown in FIG. 5C, an inner dielectric layer 126 and a borophosphosilicate glass 128 are formed over the gate polysilicon region 120. As shown in FIG. 5D, contact etching, implantation of contact regions, and formation of a metal layer and a metal mask layer 132 are performed.

In the second preferred embodiment, after the processes shown in FIGS. 1A to 1E and 2A to 2C are sequentially executed, the processes shown in FIGS. 3A and 3B, 6A to 6C, and FIG. Processes shown in 7A to 7D. 3A and 3B are sequentially simplified cross-sectional views illustrating various stages in the process of forming the buffered polysilicon region 116 according to an embodiment of the present invention, and FIGS. 6A to 6C are sequentially illustrated according to another embodiment of the present invention. Simplified cross-sectional views of various stages in the process of forming the gate polysilicon region 120. FIG. 7A to FIG. 7D sequentially illustrate the simplification of each stage in the process of forming the base layer 122 and the heavily doped region 124 according to another embodiment of the present invention. Sectional view. Since the sacrificial oxide layer 108, the insulating oxide layer 112 and the gate oxide layer 118 shown in FIGS. 6A to 6C are all oxide layers, they are only generated at different stages in the manufacturing process. For clarity, in FIGS. 7A to 7D Treat them as one and delete their boundaries and symbols.

In the second preferred embodiment, as shown in FIG. 3A, polysilicon 115 is deposited on the insulating oxide layer 112 and etched back to form a buffered polysilicon region 116 as shown in FIG. 3B. As shown in FIG. 6A, a gate oxide layer 118 is formed in the trench 110 by oxidation, and the gate oxide layer 118 covers at least the sidewall of the trench 110. As shown in FIGS. 6B and 6C, polysilicon 119 is deposited and etched again to form gate polysilicon region 120 in trench 110. It should be noted that the depth of the etch back can be controlled without precision. If the etch back makes the buffer polysilicon region 116 have a thickness, a sandwich structure is formed, and there are two oxide layers between the source and the drain, namely the gate oxide layer 118 With insulating oxide layer 112. Furthermore, the buffered polysilicon region 116 is floating potential, and even if it is short-circuited with the upper gate polysilicon region 120, there will be no electrical problems, which further leads to yield problems.

Next, as shown in FIG. 7A, a blanket body implantation and drive-in process are performed to form a base layer 122, such as a P-type well, along the upper half of the epitaxial layer 102. As shown in FIG. 7B, a blanket body implantation and drive-in process is performed to form a heavily doped region 124, such as an N+ source region, along the base layer 122. As shown in FIG. 7C, an inner dielectric layer 126 and a borophosphosilicate glass 128 are formed over the gate polysilicon region 120. As shown in FIG. 7D, contact etching, implantation of contact regions, and formation of a metal layer and a metal mask layer 132 are performed.

In the third preferred embodiment, after the processes shown in FIGS. 1A to 1E and 2A to 2C are sequentially executed, the processes shown in FIGS. 3A to 3C, 4A to 4C, and FIG. The process shown in 5A to 5D. 3A to 3C are, in order, a simplified cross-sectional view illustrating various stages in the process of forming the buffer polysilicon region 116 according to an embodiment of the present invention.

In the third preferred embodiment, as shown in FIG. 3A, polysilicon 115 is deposited on the insulating oxide layer 112 and etched back, and due to the accuracy of the etch back, a buffered polysilicon region 116 as shown in FIG. 3B is formed Then, the buffer polysilicon region 116 is completely etched away to form the structure shown in FIG. 3C. As shown in FIG. 4A, a gate oxide layer 118 is formed in the trench 110 by oxidation. The gate oxide layer 118 at least covers the sidewall of the trench 110. As shown in FIGS. 4B and 4C, polysilicon 119 is then deposited and etched again to form gate polysilicon region 120 in trench 110. It should be noted that even if the deposited buffer polysilicon is completely etched away, the thick and thick points of the previous insulating oxide layer 112 can still ensure the insulation of the gate polysilicon region 120 and the source polysilicon region 114, and the subsequent gate oxide layer 118 It is still possible to grow thinner points so that the gate oxide layer 118 on the sidewall of the trench 110 is thinner and has a lower starting voltage.

Next, as shown in FIG. 5A, a blanket body implantation and drive-in process is performed to form a base layer 122 along the upper half of the epitaxial layer 102, such as a P-type well region. As shown in FIG. 5B, a blanket body implantation and drive-in process is performed to form a heavily doped region 124, such as an N+ source region, along the base layer 122. As shown in FIG. 5C, an inner dielectric layer 126 and a borophosphosilicate glass 128 are formed over the gate polysilicon region 120. As shown in FIG. 5D, contact etching, implantation of contact regions, and formation of a metal layer and a metal mask layer 132 are performed.

In one embodiment, as shown in FIG. 4C or FIG. 5D, the shielded gate metal oxide semiconductor field effect transistor includes a semiconductor substrate, an insulating oxide layer (including a sacrificial oxide layer 108 and an insulating oxide layer 112), and a source polysilicon region 114 , Gate polysilicon region 120 and gate oxide layer 118. The semiconductor substrate has a trench. The isolation oxide layer is located in the trench. The source polysilicon region 114 is located in the first part of the trench with a deeper depth and is covered by an insulating oxide layer. The gate polysilicon region 120 is located in the second part of the trench with a shallow depth. The gate oxide layer 118 is located between the gate polysilicon region 120 and the source polysilicon region 114. The isolation oxide layer and the gate oxide layer 118 are used to isolate the gate polysilicon region 120 and the source polysilicon region 114, and the thickness of the isolation oxide layer and the gate oxide layer 118 can be filled into the trench through more than one polysilicon deposition and performed Controlled by the etching process. In another embodiment, as shown in FIG. 6C or FIG. 7D, a buffer polysilicon region 116 is formed between the isolation oxide layer and the gate oxide layer through the process of filling the trench with more than one polysilicon deposition and etching.

In one embodiment, the materials used in the gate polysilicon region and the source polysilicon region include polysilicon, doped polysilicon, metal, amorphous silicon, or a combination thereof, and the materials used to isolate the oxide layer and the gate oxide layer It is silicon oxide.

The above purpose is for explanation, and various specific details are provided to provide a thorough understanding of the present invention. Those skilled in the art of the present invention should be able to implement the present invention without certain specific details. In other embodiments, the conventional structures and devices are not shown in the block diagram. Intermediate structures may be included between graphic elements. The described elements may contain additional inputs and outputs, which are not depicted in detail in the drawings.

If there is an element A connected (or coupled) to the element B, the element A may be directly connected (or coupled) to the element B, or indirectly connected (or coupled) to the element B via the element C. If the specification states that an element, feature, structure, program, or characteristic A will result in an element, feature, structure, program, or characteristic B, it means that A is at least part of the reason for B, or it indicates that there are other elements, features, structures, programs, or procedures Or characteristic assistance caused B. The word "may" mentioned in the description, its elements, features, procedures or characteristics are not limited to the description; the number mentioned in the description is not limited to the words "one" or "one".

The present invention, regardless of its purpose, means and efficacy, shows its characteristics very different from the conventional technology, which is a major breakthrough. It should be noted that the above-mentioned embodiments are only illustrative of the principles and effects of the present invention, rather than limiting the scope of the present invention. Although the specific embodiments and the disclosed applications have been clarified and explained here, the embodiments are not intended to be limited to precise explanations, and anyone skilled in the art can implement the technology without departing from the technical principles and spirit of the present invention. Examples of modifications and changes. It should also be understood that, without departing from the spirit and scope disclosed by the present invention, the elements disclosed herein and their various modifications, changes, extensions, operations, and methods of arrangement that are obvious to those skilled in the art The details, as well as the devices and methods disclosed herein will not be limited and should be included in the scope of the following patent applications.

100: substrate 102: epitaxial layer 104: hard mask layer 106: photoresist 108: sacrificial oxide layer 110: trench 112: insulating oxide layer 113: polysilicon 114: source polysilicon region 115: polysilicon 116: buffer polysilicon region 118: Gate oxide layer 119: polysilicon 120: gate polysilicon region 122: base layer 124: heavily doped region 126: inner dielectric layer 128: borophosphosilicate glass 132: metal mask layer

FIGS. 1A to 1E are, in sequence, simplified cross-sectional views illustrating various stages in the process of forming trenches and sacrificial oxide layers according to an embodiment of the present invention. 2A to 2C are, in sequence, simplified cross-sectional views illustrating various stages in the process of forming a source polysilicon region according to an embodiment of the invention. 3A to 3C are, in sequence, simplified cross-sectional views illustrating various stages in the process of forming a buffered polysilicon region according to an embodiment of the invention. 4A to 4C are, in sequence, simplified cross-sectional views illustrating various stages in the process of forming a gate polysilicon region according to an embodiment of the invention. 5A to 5D are, in sequence, simplified cross-sectional views illustrating various stages in the process of forming a base layer and a heavily doped region according to an embodiment of the invention. 6A to 6C are, in sequence, simplified cross-sectional views illustrating various stages in the process of forming a gate polysilicon region according to another embodiment of the present invention. 7A to 7D are, in sequence, simplified cross-sectional views illustrating various stages in the process of forming the base layer and the heavily doped region according to another embodiment of the present invention.

100: base

102: Epitaxial layer

108: Sacrificial oxide layer

112: insulating oxide layer

114: Source polysilicon area

116: Buffer polysilicon area

118: Gate oxide layer

120: Gate polysilicon area

Claims (10)

A method for manufacturing a shielded gate-type metal oxide half-field effect transistor includes the following steps: forming a semiconductor substrate having a trench; forming a sacrificial oxide layer in the trench by oxidation, the sacrificial oxide layer covering at least the trench Side walls; forming a source polysilicon region in the trench; forming an insulating oxide layer over the source polysilicon region by oxidation, so that the source polysilicon region is completely covered by the sacrificial oxide layer and the insulating oxide layer; Filling the trench with polysilicon deposition and etching back to control the thickness of the insulating oxide layer above the source polysilicon region; forming a gate oxide layer in the trench by oxidation, the gate oxide layer covering at least the trench Sidewalls; forming a gate polysilicon region in the trench; and ion implantation to form a base layer and a heavily doped region surrounding the trench. The method for manufacturing a shielded gate metal oxide semiconductor field effect transistor as described in item 1 of the scope of patent application further includes the following steps: before forming the gate oxide layer, the trench is filled with polysilicon deposition and etched back to form a The buffer polysilicon region controls the thickness of the insulating oxide layer above the source polysilicon region. The method for manufacturing a shielded gate metal oxide half field effect transistor as described in item 2 of the scope of patent application further includes the following steps: when the gate oxide layer is formed by oxidation, the buffer polysilicon region is completely oxidized to form the gate A part of the polar oxide layer controls the thickness of the insulating oxide layer and the gate oxide layer above the source polysilicon region. The method for manufacturing a shielded gate-type metal oxide half field effect transistor as described in item 1 of the scope of patent application further includes the following steps: providing the semiconductor substrate; depositing a hard mask layer on the semiconductor substrate; on the semiconductor substrate And the hard mask curtain layer is used for trench pattern layout; and dry etching is performed to form the trench. The method for manufacturing a shielded gate type metal oxide semi-field effect transistor as described in item 1 of the scope of the patent application further includes the following steps: electrically connecting the polysilicon deposition to the source electrode and forming a replacement electrode for the polysilicon region in the middle and lower layers of the trench The source polysilicon region. The method for manufacturing a shielded gate type metal oxide half field effect transistor as described in item 1 of the scope of patent application further includes the following steps: forming the well region and the heavily doped region by ion implantation; above the gate polysilicon region Forming inner dielectric layer and borophosphosilicate glass; and performing contact etching, implanting contact area and forming metal layer and metal mask layer. A shielded gate-type metal-oxide half-field effect transistor includes: a semiconductor substrate with a trench; an insulating oxide layer located in the trench; a source polysilicon region located in a first part of the trench with a deeper depth, Covered by the insulating oxide layer; a gate polysilicon region located in a second part of the trench with a shallow depth; and a gate oxide layer located between the gate polysilicon region and the source polysilicon region; The isolation oxide layer and the gate oxide layer are used to isolate the gate polysilicon region and the source polysilicon region, and the thicknesses of the isolation oxide layer and the gate oxide layer are filled into the trench through more than one polysilicon deposition And controlled by the etching process. The shielded gate-type metal-oxide half-field effect transistor as described in item 7 of the patent application scope further includes a buffer polysilicon region between the insulating oxide layer and the gate oxide layer. The shielded gate-type metal oxide half-field effect transistor as described in item 7 of the patent application scope, wherein the materials used in the gate polysilicon region and the source polysilicon region include polysilicon, doped polysilicon, metal, amorphous silicon or The above combination, and the material used for the insulating oxide layer and the gate oxide layer is silicon oxide. The shielded gate metal oxide semiconductor field effect transistor as described in item 7 of the patent application scope, wherein the semiconductor substrate includes: a substrate; and an epitaxial layer, epitaxially grown on the substrate.

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