CN111986998B - LDMOS device and preparation method thereof - Google Patents

Abstract

The present application discloses an LDMOS device and a preparation method thereof. The device comprises: a silicon substrate; an epitaxial layer formed on the silicon substrate with a thickness greater than 30 microns, wherein a drift region and a channel region are formed, and the drift region An active region and a body region are formed in the middle, and a drain region is formed on one side of the channel region; a gate oxide layer, which is formed on the epitaxial layer; a gate, which is formed on the gate oxide layer; a first metal silicide layer , which is formed on the gate; an oxide layer, which is formed on the first metal silicide layer and the epitaxial layer; a second metal silicide layer, which is formed on the oxide layer; an interlayer dielectric, which is formed on the oxide layer and the second metal silicide layer; a deep contact hole is formed in the interlayer dielectric, the epitaxial layer and the silicon substrate, and its bottom end is in contact with the silicon substrate. In the present application, the technical effect of reducing high-frequency loss can be achieved without setting a high-resistivity substrate, so the connection between the contact hole and the high-resistivity substrate does not need to be realized by using a TSV process.

Description

LDMOS device and its preparation method

technical field

The present application relates to the technical field of semiconductor manufacturing, in particular to a laterally-diffused metal-oxide semiconductor (LDMOS) device and a manufacturing method thereof.

Background technique

LDMOS devices, especially radio frequency (RF) LDMOS devices, are widely used in radio frequency high-power fields such as base stations, radio and television, etc. LDMOS devices are usually synthesized with other devices, and the output power of its products can reach more than 500 watts (W) . Among them, the chip products used in the fifth generation mobile communication technology (5th generation mobile networks, 5G) need to increase the signal bandwidth from 40 megahertz (MHz) of long term evolution (LTE) to 200MHz. Performance at high frequencies places high demands on it.

At high frequency, the loss of capacitance and inductance directly affects the performance of LDMOS devices. As the frequency increases, the skin effect of the resistance line becomes more and more obvious, the resistance of the wire becomes larger, and the loss of the inductance increases; at the same time, in order to reduce the thermal resistance, LDMOS devices usually use heavily doped substrates, and at high frequencies, the losses caused by heavily doped substrates are also more obvious.

In the related art, in order to reduce the inductance loss at high frequency, the contact hole of the LDMOS device usually uses a thick metal layer or a copper wire with high conductivity. In order to reduce the substrate loss, a substrate with high resistivity (such as a glass substrate) is usually used. Bottom), the contact hole and the substrate are connected through a through silicon via (through silicon via, TSV) process.

However, the process of realizing the contact hole and the substrate connection through the TSV process is relatively complicated and the yield rate is low, which leads to high manufacturing cost of the device.

Contents of the invention

The present application provides an LDMOS device and a preparation method thereof, which can solve the problem of high manufacturing cost of the LDMOS device provided in the related art.

On the one hand, the embodiment of the present application provides a method for fabricating an LDMOS device, including:

forming an epitaxial layer on a silicon substrate, the epitaxial layer having a thickness greater than 30 microns;

sequentially forming a gate oxide layer, a gate and a first metal silicide layer on the epitaxial layer;

forming a drift region in the epitaxial layer by ion implantation;

forming a channel region in the epitaxial layer by ion implantation;

forming a source region and a body region in the channel region by ion implantation, and forming a drain region on one side of the drift region in the epitaxial layer;

forming an oxide layer on the first metal silicide layer and the epitaxial layer, and forming a second metal silicide layer on the oxide layer;

forming an interlayer dielectric on the oxide layer and the second metal silicide layer;

A deep contact hole is formed in the interlayer dielectric, the epitaxial layer and the silicon substrate, and the bottom end of the deep contact hole is in contact with the silicon substrate.

Optionally, forming a deep contact hole in the interlayer dielectric, the epitaxial layer and the silicon substrate includes:

forming a trench in the interlayer dielectric;

forming at least two vias in the epitaxial layer and the silicon substrate;

A metal tungsten layer is filled in the groove and the through hole, and the metal tungsten layer is planarized to form the deep contact hole.

Optionally, a plurality of deep contact holes are formed on the silicon substrate, and the top view shape of the deep contact holes is a rectangle, and the silicon substrate includes a plurality of unit regions, each of which is formed with The deep contact holes are distributed parallel to each other, and the deep contact holes between each unit area are perpendicular to each other.

Optionally, forming a gate oxide layer, a gate and a first metal silicide layer sequentially on the epitaxial layer includes:

forming an oxide on the epitaxial layer by a furnace tube oxidation process;

forming a polysilicon layer on the oxide;

forming a metal layer on the polysilicon layer, reacting the metal layer with the polysilicon layer to form a metal silicide through heat treatment, and performing planarization treatment on the metal layer to remove the redundant metal layer;

The area corresponding to the gate is defined by a photolithography process, and the metal silicide, polysilicon layer and oxide in the exposed area are etched to remove, the remaining metal silicide forms the first metal silicide layer, and the remaining polysilicon layer forms For the gate, the remaining oxide forms the gate oxide layer.

On the other hand, an embodiment of the present application provides an LDMOS device, including:

Silicon substrate;

An epitaxial layer, the epitaxial layer is formed on the silicon substrate, the thickness of the epitaxial layer is greater than 30 microns, a drift region and a channel region are formed in the epitaxial layer, and an active region is formed in the channel region and a body region, a drain region is formed on one side of the drift region;

a gate oxide layer, the gate oxide layer is formed on the epitaxial layer;

a gate, the gate is formed on the gate oxide layer;

a first metal silicide layer, the first metal silicide layer is formed on the gate;

an oxide layer formed on the first metal silicide layer and the epitaxial layer;

a second metal silicide layer formed on the oxide layer;

an interlayer dielectric formed on the oxide layer and the second metal silicide layer;

A deep contact hole is formed in the interlayer dielectric, the epitaxial layer and the silicon substrate, and the bottom end of the deep contact hole is in contact with the silicon substrate.

Optionally, the deep contact hole includes tungsten.

Optionally, a plurality of deep contact holes are formed on the silicon substrate, the top view shape of the deep contact holes is a rectangle, and the silicon substrate includes a plurality of regions, each region is formed with Distributed deep contact holes, the deep contact holes between each area are perpendicular to each other.

Optionally, the first metal silicide layer includes titanium metal silicide.

Optionally, the second metal silicide layer includes tungsten metal silicide.

Optionally, the depth of the deep contact hole is greater than 40 microns.

The technical solution of the present application at least includes the following advantages:

By forming an epitaxial layer with a thickness greater than 30 microns on the silicon substrate, deep contact holes are formed in the interlayer dielectric, the epitaxial layer, and the silicon substrate, and the source region of the device is connected to the silicon substrate through the deep contact holes. The micron epitaxial layer can reduce the high-frequency loss of the silicon substrate, so the technical effect of reducing the high-frequency loss can be achieved without setting a high-resistivity substrate, so there is no need to use the TSV process to realize contact holes and high-resistivity substrates The connection reduces the process complexity of the device and reduces the manufacturing cost of the device to a certain extent.

Description of drawings

In order to more clearly illustrate the specific embodiments of the present application or the technical solutions in the prior art, the following will briefly introduce the accompanying drawings that need to be used in the description of the specific embodiments or prior art. Obviously, the accompanying drawings in the following description The drawings are some implementations of the present application, and those skilled in the art can obtain other drawings based on these drawings without creative work.

Fig. 1 is the flowchart of the preparation method of the LDMOS device provided by an exemplary embodiment of the present application;

2 to 7 are schematic diagrams of the preparation process of an LDMOS device provided by an exemplary embodiment of the present application;

Fig. 8 is a top view of distribution of deep contact holes of an LDMOS device provided by an exemplary embodiment of the present application.

Detailed ways

The technical solutions in this application will be clearly and completely described below in conjunction with the accompanying drawings. Apparently, the described embodiments are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the scope of protection of this application.

In the description of this application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer" etc. The indicated orientation or positional relationship is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the referred device or element must have a specific orientation, use a specific orientation construction and operation, therefore should not be construed as limiting the application. In addition, the terms "first", "second", and "third" are used for descriptive purposes only, and should not be construed as indicating or implying relative importance.

In the description of this application, it should be noted that unless otherwise specified and limited, the terms "installation", "connection", and "connection" should be understood in a broad sense, for example, it can be a fixed connection or a detachable connection. Connection, or integral connection; it may be mechanical connection or electrical connection; it may be direct connection or indirect connection through an intermediary, or it may be the internal communication of two components, which may be wireless connection or wired connection connect. Those of ordinary skill in the art can understand the specific meanings of the above terms in this application in specific situations.

In addition, the technical features involved in the different embodiments of the present application described below may be combined as long as they do not constitute a conflict with each other.

With reference to Fig. 1, it shows the flow chart of the preparation method of the LDMOS device that an exemplary embodiment of the present application provides, and this method can be used in the manufacture of RFLDMOS device, and this method comprises:

In step 101, an epitaxial layer is formed on a silicon substrate, and the thickness of the epitaxial layer is greater than 30 microns.

Referring to FIG. 2 , it shows a schematic cross-sectional view of forming an epitaxial layer on a silicon substrate. As shown in FIG. 2 , the X-axis and the Y-axis are defined by the plane where the surface of the substrate 210 is located, and the Z-axis is defined by the direction where the thickness of the substrate 210 is located. In the embodiment of the present application, the epitaxial layer 220 with a thickness h1 greater than 30 micrometers can be grown on the silicon substrate 210 by epitaxial growth. Wherein, the doped ions in the silicon substrate 210 and the epitaxial layer 220 are the first type of ions, and the silicon substrate 210 is a heavily doped substrate, and its ion doping concentration is higher than that of the epitaxial layer 220 .

Step 102, sequentially forming a gate oxide layer, a gate electrode and a first metal silicide layer on the epitaxial layer.

Step 103, forming a drift region in the epitaxial layer by ion implantation.

Step 104, forming a channel region in the epitaxial layer by ion implantation.

Step 105, forming a source region and a body region in the channel region by ion implantation, and forming a drain region on one side of the drift region in the epitaxial layer.

Step 106, forming an oxide layer on the first metal silicide layer and the epitaxial layer, and forming a second metal silicide layer on the oxide layer.

Step 107, forming an interlayer dielectric on the oxide layer and the second metal silicide layer.

Referring to FIG. 3 , it shows a schematic cross-sectional view of the resulting structure formed before forming the deep contact hole. As shown in Figure 3, a channel region 201 and a drift region 202 are formed in the epitaxial layer 220, an active region 203 and a body region 204 are formed in the channel region 201, a drain region 205 is formed on one side of the drift region 202, and the epitaxial layer A gate oxide layer 230 is formed on the gate oxide layer 220, a gate 240 is formed on the gate oxide layer 230, a first metal silicide layer 251 is formed on the gate 240, an oxide layer is formed on the epitaxial layer 220 and the first metal silicide layer 251 260 , the second metal silicide layer 252 is formed on the oxide layer 260 .

Optionally, in this embodiment of the present application, step 102 includes but is not limited to: forming an oxide on the epitaxial layer 220 through a furnace tube oxidation process; forming a polysilicon layer on the oxide; forming a metal layer on the polysilicon layer, and making The metal layer reacts with the polysilicon layer to form a metal silicide, and the metal layer is planarized to remove the redundant metal layer; the area corresponding to the gate 240 is defined by a photolithography process, and the metal silicide, the polysilicon layer and the exposed area are etched and removed. oxide, the remaining metal silicide forms the first metal silicide layer 251 , the remaining polysilicon layer forms the gate 240 , and the remaining oxide forms the gate oxide layer 230 . Wherein, the first metal silicide layer 251 includes titanium metal silicide.

Exemplarily, after forming the gate oxide layer 230, the gate 240 and the first metal silicide layer 251, the second type of ion implantation can be performed to form the channel region 201, and the first type of ion implantation can be performed to form the drift region 202, The second type of ion implantation is performed to form the source region 203 and the drain region 205 , and the first type of ion implantation is performed to form the body region 204 .

Exemplarily, an oxide layer 260 may be formed on the epitaxial layer 220 by a chemical vapor deposition (CVD) process, a metal layer is formed on the oxide layer 260, and the metal layer reacts with the polysilicon layer by heat treatment to form a metal silicide The metal layer is planarized to remove the redundant metal layer, the area corresponding to the second metal silicide layer 252 is defined by photolithography, the metal silicide in the exposed area is etched and removed, and the remaining metal silicide forms the second metal silicide layer. The metal silicide layer 252 is deposited on the oxide layer 260 and the second metal silicide layer 252 by a CVD process to form an interlayer dielectric 270 . Wherein, the second metal silicide layer 252 includes tungsten metal silicide; the interlayer dielectric 270 includes a high dielectric constant material (a material with a dielectric constant k greater than 4, such as silicon dioxide SiO ₂ ).

Optionally, in the implementation of the present application, before forming the oxide layer 260, it also includes: forming a third metal silicide layer 253 in the source region 203 and the body region 204, and forming a fourth metal silicide layer in the drain region 205 254. For the method of forming the third metal silicide layer 253 and the fourth metal silicide layer 254 , reference may be made to the above-mentioned embodiments, which will not be repeated here.

Step 108, forming a deep contact hole in the interlayer dielectric, the epitaxial layer and the silicon substrate, and the bottom of the deep contact hole is in contact with the silicon substrate.

Optionally, step 108 includes but is not limited to: forming a trench in the interlayer dielectric; forming at least two via holes in the epitaxial layer and the silicon substrate; filling the trenches and via holes with a metal tungsten layer, and The layer is planarized to form deep contact holes.

Referring to FIG. 4 , it shows a schematic cross-sectional view of forming trenches in the interlayer dielectric. Exemplarily, as shown in FIG. 4, the region corresponding to the trench 271 can be defined on the interlayer dielectric 270 by photolithography, and the interlayer dielectric in the exposed region can be removed by etching to form the trench 271. The bottom of the trench 271 The epitaxial layer 220 is exposed.

Referring to FIG. 5 , it shows a schematic cross-sectional view of forming at least two via holes in the epitaxial layer and the silicon substrate. Exemplarily, as shown in FIG. 5 , regions corresponding to at least two through holes 221 (two through holes 221 are used for illustration in FIG. 5 ) may be defined on the epitaxial layer 220 by a photolithography process for etching and removal. A region of the epitaxial layer 220 and a target depth of the silicon substrate 210 are exposed to form a via hole 221 .

Optionally, in this embodiment of the present application, before filling the trenches and via holes with the metal tungsten layer, the method further includes: growing a barrier layer on sidewalls of the trenches and via holes.

Referring to FIG. 6 , it shows a schematic cross-sectional view of growing a diffusion barrier layer on the sidewalls of trenches and via holes; referring to FIG. 7 , it shows a schematic cross-sectional view of forming a deep contact hole. Exemplarily, as shown in FIG. 6, a diffusion barrier layer 281 is grown on the sidewalls of the trench 271 and the through hole 221; as shown in FIG. The metal tungsten layer is planarized to obtain the deep contact hole 280 . Optionally, the depth h2 of the deep contact hole 280 is greater than 40 microns.

Referring to FIG. 8 , it shows a top view of an optional distribution of deep contact holes. As shown in FIG. 7, a plurality of deep contact holes 280 are formed on the silicon substrate 210, and the top view shape of the deep contact holes 280 is a rectangle. The silicon substrate 210 includes a plurality of unit regions 211, and each unit region 211 is formed with The deep contact holes 280 are distributed parallel to each other, and the deep contact holes 280 between each unit area 211 are perpendicular to each other. By arranging the deep contact holes 280 between each unit area 211 to be perpendicular to each other, the problem of substrate warpage caused by parallel deep contact holes distributed on the substrate in the related art can be solved, and the yield rate can be improved.

To sum up, in the embodiment of the present application, by forming an epitaxial layer with a thickness greater than 30 microns on the silicon substrate, a deep contact hole is formed in the interlayer dielectric, the epitaxial layer, and the silicon substrate, and the device is connected through the deep contact hole. The source region is connected to the silicon substrate. Since the epitaxial layer larger than 30 microns can reduce the high-frequency loss of the silicon substrate, the technical effect of reducing the high-frequency loss can be achieved without setting a high-resistivity substrate. Therefore, it is not necessary to use The TSV process realizes the connection between the contact hole and the high-resistivity substrate, reduces the process complexity of the device, and reduces the manufacturing cost of the device to a certain extent.

Referring to FIG. 7 , it shows a schematic cross-sectional view of an LDMOS device provided by an exemplary embodiment of the present application. As shown in Figure 7, the LDMOS device includes:

Silicon substrate 210;

The epitaxial layer 220, which is formed on the silicon substrate 210, has a thickness greater than 30 microns, wherein a channel region 201 and a drift region 202 are formed, an active region 203 and a body region 204 are formed in the channel region 201, and the drift region 202 A drain region 205 is formed on one side;

a gate oxide layer 230 formed on the epitaxial layer 220;

a gate 240 formed on the gate oxide layer 230;

a first metal silicide layer 251 formed on the gate 230;

an oxide layer 260 formed on the first metal silicide layer 251 and the epitaxial layer 220;

a second metal silicide layer 252 formed on the oxide layer 260;

an interlayer dielectric 270 formed on the oxide layer 260 and the second metal silicide layer 251;

The deep contact hole 280 is formed in the interlayer dielectric 270 , the epitaxial layer 220 and the silicon substrate 210 , and its bottom end is in contact with the silicon substrate 210 .

Optionally, deep contact hole 280 includes tungsten.

Optionally, referring to FIG. 8 , a plurality of deep contact holes 280 are formed on the silicon substrate 210. The top view shape of the deep contact holes 280 is a rectangle. The silicon substrate 210 includes a plurality of regions 211, and each region 211 is formed with The deep contact holes 280 are distributed parallel to each other, and the deep contact holes 280 between each region 211 are perpendicular to each other.

Optionally, the first metal silicide layer 251 includes titanium metal silicide.

Optionally, the second metal silicide layer 252 includes tungsten metal silicide.

Optionally, the depth h2 of the deep contact hole 280 is greater than 40 microns.

Apparently, the above-mentioned embodiments are only examples for clear description, rather than limiting the implementation. For those of ordinary skill in the art, other changes or changes in different forms can be made on the basis of the above description. It is not necessary and impossible to exhaustively list all the implementation manners here. However, the obvious changes or changes derived therefrom are still within the protection scope of the invention of the present application.

Claims (10)

1. A preparation method of an LDMOS device, characterized in that, comprising: forming an epitaxial layer on a silicon substrate, the epitaxial layer having a thickness greater than 30 microns; sequentially forming a gate oxide layer, a gate and a first metal silicide layer on the epitaxial layer; forming a drift region in the epitaxial layer by ion implantation; forming a channel region in the epitaxial layer by ion implantation; forming a source region and a body region in the channel region by ion implantation, and forming a drain region on one side of the drift region in the epitaxial layer; forming an oxide layer on the first metal silicide layer and the epitaxial layer, and forming a second metal silicide layer on the oxide layer; forming an interlayer dielectric on the oxide layer and the second metal silicide layer; A deep contact hole is formed in the interlayer dielectric, the epitaxial layer and the silicon substrate, and the bottom end of the deep contact hole is in contact with the silicon substrate. 2. The method according to claim 1, wherein the forming a deep contact hole in the interlayer dielectric, the epitaxial layer and the silicon substrate comprises: forming a trench in the interlayer dielectric; forming at least two vias in the epitaxial layer and the silicon substrate; A metal tungsten layer is filled in the groove and the through hole, and the metal tungsten layer is planarized to form the deep contact hole. 3. The method according to claim 2, wherein a plurality of the deep contact holes are formed on the silicon substrate, the top view shape of the deep contact holes is a rectangle, and the silicon substrate includes multiple Each unit area is formed with deep contact holes parallel to each other, and the deep contact holes between each unit area are perpendicular to each other. 4. The method according to any one of claims 1 to 3, wherein the sequentially forming a gate oxide layer, a gate and a first metal silicide layer on the epitaxial layer comprises: forming an oxide on the epitaxial layer by a furnace tube oxidation process; forming a polysilicon layer on the oxide; forming a metal layer on the polysilicon layer, reacting the metal layer with the polysilicon layer to form a metal silicide through heat treatment, and performing planarization treatment on the metal layer to remove the redundant metal layer; The area corresponding to the gate is defined by a photolithography process, and the metal silicide, polysilicon layer and oxide in the exposed area are etched to remove, the remaining metal silicide forms the first metal silicide layer, and the remaining polysilicon layer forms For the gate, the remaining oxide forms the gate oxide layer. 5. A LDMOS device, characterized in that, comprising: Silicon substrate; An epitaxial layer, the epitaxial layer is formed on the silicon substrate, the thickness of the epitaxial layer is greater than 30 microns, a drift region and a channel region are formed in the epitaxial layer, and an active region is formed in the channel region and a body region, a drain region is formed on one side of the drift region; a gate oxide layer, the gate oxide layer is formed on the epitaxial layer; a gate, the gate is formed on the gate oxide layer; a first metal silicide layer, the first metal silicide layer is formed on the gate; an oxide layer formed on the first metal silicide layer and the epitaxial layer; a second metal silicide layer formed on the oxide layer; an interlayer dielectric formed on the oxide layer and the second metal silicide layer; A deep contact hole is formed in the interlayer dielectric, the epitaxial layer and the silicon substrate, and the bottom end of the deep contact hole is in contact with the silicon substrate. 6. The device of claim 5, wherein the deep contact hole comprises tungsten. 7. The device according to claim 6, wherein a plurality of the deep contact holes are formed on the silicon substrate, the top view shape of the deep contact holes is a rectangle, and the silicon substrate includes multiple Each region is formed with deep contact holes parallel to each other, and the deep contact holes between each region are perpendicular to each other. 8. The device according to any one of claims 5 to 7, wherein the first metal silicide layer comprises titanium metal silicide. 9. The device of claim 8, wherein the second metal suicide layer comprises tungsten metal suicide. 10. The device according to claim 9, wherein the depth of the deep contact hole is greater than 40 microns.

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