CN114936178B - Positive connector, negative connector, data transmission system and method - Google Patents
Positive connector, negative connector, data transmission system and method Download PDFInfo
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- CN114936178B CN114936178B CN202210696350.0A CN202210696350A CN114936178B CN 114936178 B CN114936178 B CN 114936178B CN 202210696350 A CN202210696350 A CN 202210696350A CN 114936178 B CN114936178 B CN 114936178B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/017509—Interface arrangements
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
- H04L9/08—Key distribution or management, e.g. generation, sharing or updating, of cryptographic keys or passwords
- H04L9/0861—Generation of secret information including derivation or calculation of cryptographic keys or passwords
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Abstract
The invention discloses a positive connector, a reverse connector, a data transmission system and a method, which relate to the field of connectors, wherein the positive connector is provided with a positive input port, a positive output port and a gate circuit, the positive input port is provided with N positive input terminals, and the positive output port is provided with N-1 positive output terminals; the N positive input terminals are respectively N-1 conventional positive input terminals and 1 reference terminal, and one positive output terminal is a positive multiplexing terminal; the gate data input ends in the gate circuit are respectively connected with the conventional positive input terminals; the gate result output ends in the gate circuit are respectively connected with the positive output terminal; the reference terminal is connected to the gate reference input of each gate and to the positive multiplexing terminal, respectively. The invention provides a positive connector, a negative connector, a data transmission system and a method, which utilize the characteristic that a gate circuit processes signals and has relative delay compared with direct data transmission, and extract data in parallel data is transmitted in advance so as to realize the function of simplifying the data.
Description
Technical Field
The invention relates to the field of connectors, in particular to a positive connector, a negative connector, a data transmission system and a data transmission method.
Background
In the field of data transmission, when data transmission is performed, bandwidth is limited, and in order to reduce bandwidth occupation or reduce the number of transmission lines, data needs to be reduced in form, and the data reduction mainly has two improvement directions.
The first improvement is to change the description mode of the data, in the field of data processing, the data is not compressible, what is commonly known in the art as the compression essence of the data means that the data is described by different description methods, and the data is simplified from the description form. The method has the advantages that the change of the transmitted data in the data quantity is realized through the description form commonly defined by the transmitting equipment and the receiving equipment during data transmission, and the defects of the data compaction mode in practical application include the defects of poor universality (the transmitting equipment and the receiving equipment need to have the commonly defined description form), high equipment cost (the data needs to be processed by corresponding encoders and decoders in the generating equipment and the receiving equipment), large data delay (the data delay time and the equipment cost are hooked, and the high equipment cost is needed to overcome the problem of large data delay) and the like.
The second improvement direction is to change the bandwidth by time, namely, the parallel data is transmitted in a time-sharing way, and when the data is transmitted, the multi-bit data is in a form of dispersing in a time span, so that the purposes of reducing the bandwidth use and reducing the number of transmission lines are realized.
In the second improvement direction, the data is converted in serial-parallel mode by adopting a special chip, and in the industrial field, especially in the high-precision field, complex chips are generally needed to be avoided, so that a simple and reliable component is needed to realize related functions.
In addition, the problem of security and reliability of data in transmission is one of factors to be considered when data is reduced.
Disclosure of Invention
The invention provides a positive connector, a negative connector, a data transmission system and a method, which utilize the characteristic that a gate circuit processes signals and has relative delay compared with direct data transmission, extract data in parallel data and transmit the extracted data in advance so as to realize the function of simplifying the data.
Accordingly, the present invention provides a positive connector having a positive input port and a positive output port,
the positive input has N positive input terminals, and the positive output has N-1 positive output terminals; the N positive input terminals are respectively N-1 conventional positive input terminals and 1 reference terminal, and one positive output terminal of the N-1 positive output terminals is a positive multiplexing terminal;
n-1 gates are arranged between the positive input and the positive output; each gate circuit comprises a gate reference input end, a gate data input end and a gate result output end;
the gate data input ends of the N-1 gate circuits are respectively connected with the N-1 conventional positive input terminals; the gate result output ends of the N-1 gate circuits are respectively connected with N-1 positive output terminals;
the reference terminal is respectively connected with a gate reference input end of each gate circuit, and the reference terminal is directly connected with the positive multiplexing terminal;
the gate circuit satisfies the following condition: knowing the data of the gate reference input and the gate result output, uniquely determining the data of the gate data input;
n is a positive integer greater than or equal to 2.
In an alternative embodiment, the gate result output ends of the N-1 gates are respectively connected with N-1 positive output terminals, and the method includes:
a group of signal compensation structures are arranged between each gate result output end and the corresponding positive output terminal;
the signal compensation structure comprises an electric-optical signal conversion element and an optical-electrical signal conversion element;
the input end of the photoelectric signal conversion element is connected with the gate result output end, and the output end of the photoelectric signal conversion element is connected with the positive output terminal;
the output end of the photoelectric signal conversion element and the input end of the photoelectric signal conversion element are arranged in a space position in a right opposite mode.
In an alternative embodiment, the gate result output ends of the N-1 gates are respectively connected with N-1 positive output terminals, and the method includes:
the N-1 gate circuits and the corresponding electric-optical signal conversion elements are arranged on the first connecting piece;
the N-1 positive output terminals and the corresponding photoelectric signal conversion elements are arranged on the second connecting piece;
the first connector and the second connector are connected to each other.
Accordingly, the present invention provides a counter connector having a counter input port and a counter output port;
the back input port is provided with N-1 back input terminals, and the back output port is provided with N back output terminals;
one of the N-1 reverse input terminals is a repeated terminal;
a register and a decoder are arranged between the counter input port and the counter output port;
the decoder is provided with a mode switching control end, N-1 second input ends and N second output ends;
the N-1 inverse input terminals are respectively connected with the N-1 second input ends;
the N second output ends are respectively connected with the N inverse output terminals;
the repeated terminal is connected with the register, and the register is connected with the mode switching control end;
n is a positive integer greater than or equal to 2.
In an alternative embodiment, the decoder includes N-1 tunable logic, and the second input terminal and the second output terminal are disposed on the tunable logic;
each adjustable logic device has one said second input, one comparison input and one said second output;
the register is also connected to each of the comparison inputs.
In an alternative embodiment, the inverse connector further comprises a clock controller;
the clock controller is connected with the register.
Accordingly, the present invention provides a data transmission system comprising the positive connector and the negative connector;
the N-1 positive output terminals are respectively connected with the N-1 negative input terminals, wherein a positive multiplexing terminal in the N-1 positive output terminals is connected with the N-1 negative input terminals through repeated terminals.
Correspondingly, the invention provides a data transmission method, which is realized based on the data transmission system and comprises the following steps:
the positive input of the positive connector receives N-bit parallel data, one bit of the N-bit parallel data is set as reference data, and the rest parallel data are set as normal data according to the hardware structure of the positive connector;
the reference data is output through a positive multiplexing terminal;
the reference data and each bit of conventional data are processed through a preset gate circuit respectively to obtain a gate result, the gate result is output through a corresponding positive output terminal, and the output of the gate result lags behind the output of the reference data;
after the inverse connector receives the reference data through an inverse multiplexing terminal, the reference data is stored in the register, and the operation mode of the decoder is switched based on the reference data stored in the register;
after the operation mode of the decoder is switched based on the reference data stored in the register, the N-1 counter input terminals respectively receive corresponding gate results;
each bit gate result enters the decoder from the corresponding second input end, is decoded by the decoder and is restored into normal data to be output from the corresponding second output end.
In an alternative embodiment, when the inverse connector further includes a clock controller, the operation mode switching speed of the register is controlled based on the clock controller.
In an alternative embodiment, the gate signal is sequentially processed by the electro-optical conversion element and the photoelectric conversion element, and then the gate result is output through the corresponding positive output terminal.
The invention provides a positive connector, a negative connector, a data transmission system and a method, which utilize the characteristic that a gate circuit processes signals and has relative delay compared with direct data transmission, extract data in parallel data and transmit the extracted data in advance so as to realize the function of simplifying the data.
In summary, the invention provides a positive connector, a negative connector, a data transmission system and a method, wherein the positive connector delays data transmission in a gate circuit setting mode, and the complete data is split and transmitted on a time span in a hardware implementation mode, so that the purpose of simplifying the data is realized; one bit of data in the data is used as a reference to be sent and the gate circuit operation for participating in the data of the other bits is carried out, so that the data of the other bits and the data of the bit serving as the reference generate relativity, and a certain encryption function can be realized; compared with other data, the data serving as the reference reaches the inverse connector firstly to guide the operation mode of a decoder of the inverse connection machine, so that the inverse connector can perform proper data analysis on the subsequent data, and the data recovery function is realized; by the matched arrangement of the positive connector and the reverse connector, the self-forming system of the data transmission system can be ensured, and the data can be reliably transmitted without depending on the preset value structures of the sending equipment and the receiving equipment.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained by those skilled in the art without the need of inventive effort.
Fig. 1 is a schematic diagram of a data transmission system according to an embodiment of the present invention.
Fig. 2 is a schematic perspective view of a front connector according to an embodiment of the present invention.
Fig. 3 is a flowchart of a data transmission method according to an embodiment of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Fig. 1 shows a schematic diagram of a data transmission system according to an embodiment of the present invention, and since the data transmission system includes a front connector and a back connector, for convenience of explanation and simplification of the drawings, the front connector, the back connector and the data transmission system are described with reference to the schematic diagram of fig. 1.
Specifically, the positive connector according to the embodiment of the invention is provided with a positive input port and a positive output port, wherein the positive input port is provided with N positive input terminals, and the positive output port is provided with N-1 positive output terminals; the N positive input terminals are respectively N-1 conventional positive input terminals and 1 reference terminal, and one of the N-1 positive output terminals is a positive multiplexing terminal;
n-1 gates are arranged between the positive input and the positive output; each gate circuit comprises a gate reference input end, a gate data input end and a gate result output end;
the gate data input ends of the N-1 gate circuits are respectively connected with the N-1 conventional positive input terminals; the gate result output ends of the N-1 gate circuits are respectively connected with N-1 positive output terminals;
the reference terminal is respectively connected with a gate reference input end of each gate circuit, and the reference terminal is directly connected with the positive multiplexing terminal;
the gate circuit satisfies the following condition: knowing the data at the gate reference input and gate result output, the data at the gate data input is uniquely determined.
Specifically, according to the implementation principle of the embodiment of the present invention, N is a positive integer greater than or equal to 2.
Specifically, for the physical structure of the positive connector, the positive inlet of the positive connector is provided with N positive input terminals, the positive output end of the positive connector is provided with N-1 positive output terminals, and the number of the terminals is reduced by 1.
For the data transmission mode, one of the positive input terminals is a reference terminal, and data of the reference terminal can be output through a positive multiplexing terminal (positive output terminal) directly connected to the reference terminal.
The other positive input terminals except the reference terminal are conventional terminals, and the data of each conventional terminal is required to be output through the positive output terminal after being processed through a corresponding gate circuit with the data of the reference terminal. Specifically, the gate circuit is a circuit structure consisting of a series of basic electronic components such as capacitors, switches and the like, the processing of signals by the gate circuit is dependent on the change time of the electrical signals, and the delay time of the gate circuit is represented, so that compared with the mode of directly transmitting data through the reference terminal and the positive multiplexing terminal, the data is delayed after being output through the gate circuit.
Related content related to data restoration is not discussed first, and as for the positive connector, a gate circuit is utilized to actively delay part of data, so that the data is distributed on a time span; in addition, the preceding data and the following data are processed and exported through the gate circuit, and the data can be converted according to the requirement and can be used for realizing the encryption processing of the data.
The above description is presented to illustrate the related structural content of one positive connector, and in practical implementation, multiple positive connectors may be used in series. In the embodiment of the invention, the number of the positive input end terminals of the positive connectors is defined as N, in the serial connection of a plurality of positive connectors, the number of the positive input end terminals of the first positive connector is defined as N, the number of the positive input end terminals of the second positive connector is defined as N-1, and the like, and N bits are disassembled bit by bit on a time span from the data format; because of the existence of the gate circuit, in each positive connector, the data on the conventional terminal takes the data on the reference terminal as a reference, and after being processed by the gate circuit, the data can be used for representing non-data per se, and the data on the conventional terminal is encrypted by different gate circuits based on the difference of the gate circuits.
Further, the gate circuit satisfies the following condition: knowing the data at the gate reference input and gate result output, the data at the gate data input is uniquely determined. The purpose of this constraint is to guarantee the data reducibility. Since the processing of the signal by the gate circuit may change the data at the gate data input, the gate reference input, the gate result output, and the gate data input should be uniquely identified if both are known, which ensures the data to be restored. On the basis, the half adder can meet the use requirement of the embodiment of the invention by taking the sum output end as the gate data input end.
Fig. 2 shows a perspective schematic view of a front connector according to an embodiment of the present invention, and various implementation structures of the front connector are based on the foregoing principle, and one implementation structure of the embodiment of the present invention is provided for reference to the related description.
In an alternative embodiment, the gate result output ends of the N-1 gates are respectively connected with N-1 positive output terminals, and the method includes:
a group of signal compensation structures are arranged between each gate result output end and the corresponding positive output terminal;
the signal compensation structure comprises an electro-optical signal conversion element 5 and an electro-optical signal conversion element 4;
the input end of the photoelectric signal conversion element 5 is connected with the gate result output end, and the output end of the photoelectric signal conversion element 4 is connected with the positive output terminal;
the output end of the electro-optical signal conversion element 5 and the input end of the photoelectric signal conversion element 4 are arranged opposite to each other in space position.
In an alternative embodiment, the gate result output ends of the N-1 gates are respectively connected with N-1 positive output terminals, and the method includes:
the N-1 gates and the corresponding electric-optical signal conversion elements are arranged on the first connecting piece 2;
the N-1 positive output terminals and the corresponding photoelectric signal conversion elements are arranged on the second connecting piece 1;
the first connector 2 and the second connector 1 are connected to each other.
Specifically, when compensation is not performed, the signal generated after the gate circuit processes the signal generates a little attenuation, and in order to ensure the stability of data (the stability of potential), the form of photoelectric conversion is utilized after the photoelectric conversion, so that the stability of the potential can be ensured. Further, the connector generally needs to have a detachable connection function, so that the electric-optical signal conversion element and the photoelectric conversion element can be separately arranged on two detachable connectors on the basis; further, since the electro-optical signal conversion element and the photoelectric conversion element are respectively related to the respective front and rear end members, the front and rear end members (positive input terminal, gate circuit, etc.) related to the electro-optical signal conversion element are provided on the first connector 2, and the front and rear end members (positive output terminal) related to the photoelectric conversion element are provided on the second connector 1.
It should be noted that, the terminal in the embodiment of the present invention has a solder ball 3 structure, and may be used in a manner of soldering a connecting wire in practical use.
Besides the function of reinforcing signals, the signal compensation structure can realize the contact-free transmission of signals by using the signal compensation structure in a connecting piece combined structure mode, and the repeated use performance of the positive connector is ensured.
Accordingly, the present invention provides a counter connector having a counter input port and a counter output port;
the back input port is provided with N-1 back input terminals, and the back output port is provided with N back output terminals;
one of the N-1 reverse input terminals is a repeated terminal;
a register and a decoder are arranged between the counter input port and the counter output port;
the decoder is provided with a mode switching control end, N-1 second input ends and N second output ends;
the N-1 inverse input terminals are respectively connected with the N-1 second input ends;
the N second output ends are respectively connected with the N inverse output terminals;
the repeated terminal is connected with the register, and the register is connected with the mode switching control end.
Specifically, from the physical structure, for the counter connector, the counter input port has N-1 counter input terminals, the counter output port has N counter output terminals, and 1 terminal is added to the number of terminals.
From the data transmission point of view, N-1 bit of input data can be obtained as output data after passing through a decoder, and the decoding form of the decoder determines the restoration of the data.
In this regard, one of the inverting input terminals is a reuse terminal, data of the reuse terminal may be registered in a register, and the registered data of the register may determine an operation mode of the decoder.
In connection with the above description of the alignment connector, based on the difference in time, the preceding data is first entered into the repetitive use terminal and registered in the register, and at this time, the data of only one terminal of the repetitive use terminal is input to the decoder, and is virtually invalid, and the decoder does not operate; and subsequently, when the subsequent data enter N-1 reverse input terminals in parallel, the decoder processes the related data according to the regulated operation mode and outputs the processed data so as to realize the data reduction.
On the basis, if the number of the front connectors of the front stage is multiple, in practical implementation, according to the number of the front connectors, the number of bits of the register and the number of working modes of the decoder can be correspondingly set, the multi-bit advanced data can be stored in the register bit by bit, and when the register data is full, the confirmation adjustment of the running mode of the decoder is carried out, and when the subsequent data is input in parallel again, the N-bit data can be always output.
Specifically, the action of the register on storing the preceding data affects the operation of the anti-connector, and for the reliability of the operation, the anti-connector further comprises a clock controller in an optional embodiment; the clock controller is connected with the register. The time controller provides precise timing pulse for the register, so that the running stability of the register is ensured.
Specifically, for the arrangement mode of one positive connector, the decoder on the reverse connector can decode according to the corresponding mode, and in an alternative embodiment, the decoder comprises N-1 adjustable logics, and the second input end and the second output end are arranged on the adjustable logics; each adjustable logic device has one said second input, one comparison input and one said second output; the register is also connected to each of the comparison inputs.
Specifically, the tunable logic corresponds to the inverse of the gate on the positive connector, e.g., one gate on the positive connector acts as a known a and B, resulting in C; the function of the adjustable logic is then known as A and C, resulting in B. For example, when the gate of the positive connector employs a half adder, the tunable logic of the inverse connector may be a subtractor.
Accordingly, the present invention provides a data transmission system comprising the positive connector and the negative connector;
the N-1 positive output terminals are respectively connected with the N-1 negative input terminals, wherein a positive multiplexing terminal in the N-1 positive output terminals is connected with the N-1 negative input terminals through repeated terminals.
Fig. 3 shows a flow chart of a data transmission method according to an embodiment of the present invention, based on the implementation of the data transmission system, including:
s101: the positive input of the positive connector receives N-bit parallel data, one bit of the N-bit parallel data is set as reference data, and the rest parallel data are set as normal data according to the hardware structure of the positive connector;
the positive input terminals of the positive connector are substantially equivalent from a data input point of view, and in the positive connector, since one of the positive input terminals is connected with the positive multiplexing terminal, the bit data has a difference in use with the other data; it should be noted that, the selection of the reference data is confirmed for the positive connector, and is relatively random for the object outputting the data, i.e. the selection of the reference terminal is random; the mating design of the counter connector and the positive connector may eliminate the need for the user to know which of the reference terminals is, and the process is implemented in hardware rather than in software.
S102: the reference data is output through a positive multiplexing terminal, the reference data and each bit of conventional data are processed through a preset gate circuit respectively to obtain a gate result, and the gate result is output through a corresponding positive output terminal;
the output of the gate result is always lagging the output of the reference data in terms of the temporal distribution; in practice, the performance differences between the gates will also be different, but the time error between the performance differences of the gates is far smaller than the time difference of the signal transmitted through or not through the gates, so by adjusting the identification time of the data, the time of parallel data can be unified, and the non-parallel data (preceding data) can generate enough time difference with the parallel data (following data) for identification.
S103: after the inverse connector receives the reference data through an inverse multiplexing terminal, the reference data is stored in the register, and the operation mode of the decoder is switched based on the reference data stored in the register;
the time difference between the preceding data and the following data allows the inverse connector sufficient time to process them separately, and specifically, the preceding data, i.e. the reference data, is synchronously output from the repetitive terminal input to the register, where the data is rewritten, and the decoder, where the input data of one bit does not cause its effect.
After the data of the register is rewritten, the operation control mode of the decoder is correspondingly switched to receive the subsequent data
S104: after the operation mode of the decoder is switched based on the reference data stored in the register, the N-1 counter input terminals respectively receive corresponding gate results;
the counter input terminals receive the result data from the corresponding positive output terminals at the same time, at which time the decoder has switched its mode of operation and, since all counter input terminals have input data at the same time, the decoder processes the input data.
S105: each bit gate result enters the decoder from the corresponding second input end, is decoded by the decoder and is restored into normal data to be output from the corresponding second output end.
The register data in the register enables the decoder to work in a corresponding operation mode, and the data of the anti-input terminal can be decoded through the corresponding decoding logic and the corresponding restored data can be obtained and output. The operation logic of the decoder is similar to the function of an AND gate circuit in nature, and is a transformation means for data in practice, so that the actual use requirement needs to be met by a matched design mode.
Based on the foregoing structural description of the system, an alternative embodiment is that, when the anti-connector further includes a clock controller, the operation mode switching speed of the register is controlled based on the clock controller. In addition, in an alternative embodiment, the gate signal is sequentially processed by the electro-optical conversion element and the photoelectric conversion element, and then the gate result is output through the corresponding positive output terminal.
In summary, the invention provides a positive connector, a negative connector, a data transmission system and a method, wherein the positive connector delays data transmission in a gate circuit setting mode, and the complete data is split and transmitted on a time span in a hardware implementation mode, so that the purpose of simplifying the data is realized; one bit of data in the data is used as a reference to be sent and the gate circuit operation for participating in the data of the other bits is carried out, so that the data of the other bits and the data of the bit serving as the reference generate relativity, and a certain encryption function can be realized; compared with other data, the data serving as the reference reaches the inverse connector firstly to guide the operation mode of a decoder of the inverse connection machine, so that the inverse connector can perform proper data analysis on the subsequent data, and the data recovery function is realized; by the matched arrangement of the positive connector and the reverse connector, the self-forming system of the data transmission system can be ensured, and the data can be reliably transmitted without depending on the preset value structures of the sending equipment and the receiving equipment.
The foregoing has described in detail a positive connector, a negative connector, a data transmission system and a method according to embodiments of the present invention, and specific examples have been applied to illustrate the principles and embodiments of the present invention, and the description of the foregoing embodiments is only for aiding in understanding the method and core idea of the present invention; meanwhile, as those skilled in the art will have variations in the specific embodiments and application scope in accordance with the ideas of the present invention, the present description should not be construed as limiting the present invention in view of the above.
Claims (10)
1. A positive connector, characterized in that the positive connector has a positive input port and a positive output port,
the positive input has N positive input terminals, and the positive output has N-1 positive output terminals; the N positive input terminals are respectively N-1 conventional positive input terminals and 1 reference terminal, and one positive output terminal of the N-1 positive output terminals is a positive multiplexing terminal;
n-1 gates are arranged between the positive input and the positive output; each gate circuit comprises a gate reference input end, a gate data input end and a gate result output end;
the gate data input ends of the N-1 gate circuits are respectively connected with the N-1 conventional positive input terminals; the gate result output ends of the N-1 gate circuits are respectively connected with N-1 positive output terminals;
the reference terminal is respectively connected with a gate reference input end of each gate circuit, and the reference terminal is directly connected with the positive multiplexing terminal;
the gate circuit satisfies the following condition: knowing the data of the gate reference input and the gate result output, uniquely determining the data of the gate data input;
n is a positive integer greater than or equal to 2.
2. The positive connector of claim 1, wherein the gate result outputs of the N-1 gates are respectively connected to N-1 positive output terminals, comprising:
a group of signal compensation structures are arranged between each gate result output end and the corresponding positive output terminal;
the signal compensation structure comprises an electric-optical signal conversion element and an optical-electrical signal conversion element;
the input end of the photoelectric signal conversion element is connected with the gate result output end, and the output end of the photoelectric signal conversion element is connected with the positive output terminal;
the output end of the photoelectric signal conversion element and the input end of the photoelectric signal conversion element are arranged in a space position in a right opposite mode.
3. The positive connector of claim 2, wherein the gate result outputs of the N-1 gates are respectively connected to N-1 positive output terminals, comprising:
the N-1 gate circuits and the corresponding electric-optical signal conversion elements are arranged on the first connecting piece;
the N-1 positive output terminals and the corresponding photoelectric signal conversion elements are arranged on the second connecting piece;
the first connector and the second connector are connected to each other.
4. A counter connector, wherein the counter connector has a counter input port and a counter output port;
the back input port is provided with N-1 back input terminals, and the back output port is provided with N back output terminals;
one of the N-1 reverse input terminals is a repeated terminal;
a register and a decoder are arranged between the counter input port and the counter output port;
the decoder is provided with a mode switching control end, N-1 second input ends and N second output ends;
the N-1 inverse input terminals are respectively connected with the N-1 second input ends;
the N second output ends are respectively connected with the N inverse output terminals;
the repeated terminal is connected with the register, and the register is connected with the mode switching control end;
n is a positive integer greater than or equal to 2.
5. The anti-connector of claim 4, wherein said decoder comprises N-1 tunable logic, said second input and said second output being disposed on said tunable logic;
each adjustable logic device has one said second input, one comparison input and one said second output;
the register is also connected to each of the comparison inputs.
6. The anti-connector of claim 4, wherein the anti-connector further comprises a clock controller;
the clock controller is connected with the register.
7. A data transmission system comprising a positive connector according to any one of claims 1 to 3 and a negative connector according to any one of claims 4 to 6;
the N-1 positive output terminals are respectively connected with the N-1 negative input terminals, wherein a positive multiplexing terminal in the N-1 positive output terminals is connected with a repeated terminal in the N-1 negative input terminals.
8. A data transmission method, implemented based on the data transmission system of claim 7, comprising:
the positive input of the positive connector receives N-bit parallel data, one bit of the N-bit parallel data is set as reference data, and the rest parallel data are set as normal data according to the hardware structure of the positive connector;
the reference data is output through a positive multiplexing terminal;
the reference data and each bit of conventional data are processed through a preset gate circuit respectively to obtain a gate result, the gate result is output through a corresponding positive output terminal, and the output of the gate result lags behind the output of the reference data;
after the inverse connector receives the reference data through an inverse multiplexing terminal, the reference data is stored in the register, and the operation mode of the decoder is switched based on the reference data stored in the register;
after the operation mode of the decoder is switched based on the reference data stored in the register, the N-1 counter input terminals respectively receive corresponding gate results;
each bit gate result enters the decoder from the corresponding second input end, is decoded by the decoder and is restored into normal data to be output from the corresponding second output end.
9. The data transmission method of claim 8, wherein when the inverse connector further comprises a clock controller, an operation mode switching speed of the register is controlled based on the clock controller.
10. The data transmission method according to claim 8, wherein the gate signal is sequentially processed through the electro-optical conversion element and the photoelectric conversion element, and then the gate result is outputted through the corresponding positive output terminal.
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