CN114927579A - MOS capacitor and electronic equipment - Google Patents
MOS capacitor and electronic equipment Download PDFInfo
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- CN114927579A CN114927579A CN202210319270.3A CN202210319270A CN114927579A CN 114927579 A CN114927579 A CN 114927579A CN 202210319270 A CN202210319270 A CN 202210319270A CN 114927579 A CN114927579 A CN 114927579A
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- 239000003990 capacitor Substances 0.000 title claims abstract description 125
- 238000009792 diffusion process Methods 0.000 claims abstract description 52
- 230000003071 parasitic effect Effects 0.000 claims abstract description 30
- 239000000758 substrate Substances 0.000 claims abstract description 17
- 238000010586 diagram Methods 0.000 description 4
- 230000009286 beneficial effect Effects 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 238000009434 installation Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/92—Capacitors with potential-jump barrier or surface barrier
- H01L29/94—Metal-insulator-semiconductors, e.g. MOS
Abstract
The invention discloses an MOS capacitor and electronic equipment, and belongs to the technical field of capacitors. The MOS capacitor comprises a P-type substrate, a deep N well formed in the P-type substrate, a first N + diffusion region formed in the deep N-well, a P-well formed in the deep N-well and a first P + diffusion region formed in the P-well, wherein the first N + diffusion region is connected with a first end of a preset first resistor, a second end of the first resistor is connected with a first bias voltage, the first P + diffusion region is connected with a first end of a preset second resistor, and a second end of the second resistor is connected with a second bias voltage and is used for reducing the equivalent parasitic capacitance of the MOS capacitor by connecting the deep N-well with the first bias voltage and connecting the P-well with the second bias voltage. The MOS capacitor can enable the parasitic capacitance between the polar plate of the MOS capacitor and the ground to be equivalent to three capacitors which are connected in series, thereby reducing the equivalent capacitance value of the parasitic capacitance.
Description
Technical Field
The invention relates to the technical field of capacitors, in particular to an MOS capacitor and electronic equipment.
Background
At present, a switched capacitor converter is often used to implement voltage conversion in a circuit, wherein a MOS capacitor is an important component of the switched capacitor converter, but the MOS capacitor has a large parasitic capacitor, and the parasitic capacitor generates a large capacitance loss, thereby affecting the working efficiency of the switched capacitor converter.
Disclosure of Invention
The present invention is directed to solving at least one of the problems of the prior art. Therefore, the invention provides an MOS capacitor, which can reduce the parasitic capacitance loss of the MOS capacitor.
The invention also provides electronic equipment with the MOS capacitor.
According to an embodiment of the first aspect of the present invention, the MOS capacitor includes a P-type substrate, a deep N-well formed in the P-type substrate, a first N + diffusion region formed in the deep N-well, a P-well formed in the deep N-well, and a first P + diffusion region formed in the P-well, the first N + diffusion region is connected to a first end of a preset first resistor, a second end of the first resistor is connected to a first bias voltage, the first P + diffusion region is connected to a first end of a preset second resistor, and a second end of the second resistor is connected to a second bias voltage, and is configured to connect the deep N-well to the first bias voltage and connect the P-well to the second bias voltage, so as to reduce an equivalent parasitic capacitance of the MOS capacitor.
The MOS capacitor provided by the embodiment of the invention at least has the following beneficial effects: the structure of the MOS capacitor is provided with a deep N-well and a P-well, the deep N-well is connected with a first bias voltage, the P-well is connected with a second bias voltage, so that the parasitic capacitance between the polar plate of the MOS capacitor and the ground is equivalent to three capacitors which are connected in series, and the equivalent capacitance value of the parasitic capacitance is reduced.
According to some embodiments of the invention, the first bias voltage has a magnitude of two times a preset input voltage.
According to some embodiments of the invention, the magnitude of the second bias voltage is minus one times the preset input voltage.
According to some embodiments of the present invention, the MOS capacitor further includes an NMOS transistor, and the P-well further has a second N + diffusion region and a third N + diffusion region formed therein, and the second N + diffusion region is connected to the third N + diffusion region and is used as a negative electrode of the MOS capacitor.
According to some embodiments of the invention, the gate of the NMOS transistor is used as the anode of the MOS capacitor.
According to some embodiments of the invention, the second N + diffusion region and the third N + diffusion region have a first capacitance therein.
According to some embodiments of the invention, the second N + diffusion region has a second capacitance with the P-well.
According to some embodiments of the invention, a third capacitance is between the P-well and the deep N-well.
According to some embodiments of the invention, a fourth capacitance is between the deep N-well and the P-type substrate.
An electronic device according to an embodiment of the second aspect of the present invention includes the MOS capacitor according to the embodiment of the first aspect.
According to the electronic equipment provided by the embodiment of the invention, at least the following beneficial effects are achieved: the electronic equipment is formed by adopting the MOS capacitor, the structure of the MOS capacitor is provided with a deep N-well and a P-well, the deep N-well is connected with a first bias voltage, the P-well is connected with a second bias voltage, so that the parasitic capacitance between the polar plate of the MOS capacitor and the ground is equivalent to three capacitors which are connected in series, and the equivalent capacitance value of the parasitic capacitance is reduced.
Additional aspects and advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.
Drawings
The invention is further described with reference to the following figures and examples, in which:
fig. 1 is a schematic structural diagram of a MOS capacitor according to an embodiment of the invention;
fig. 2 is a circuit configuration diagram of a MOS capacitor according to another embodiment of the invention;
fig. 3 is a block diagram of a MOS capacitor according to another embodiment of the invention.
Reference numerals: 310. a deep N-well bias circuit module; 320. a P-well bias circuit module; 330. a double boost circuit module.
Detailed Description
Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the accompanying drawings are illustrative only for the purpose of explaining the present invention and are not to be construed as limiting the present invention.
In the description of the present invention, it should be understood that the orientation or positional relationship referred to in the description of the orientation, such as the upper, lower, front, rear, left, right, etc., is based on the orientation or positional relationship shown in the drawings, and is only for convenience of description and simplification of description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present invention.
In the description of the present invention, the meaning of a plurality is one or more, the meaning of a plurality is two or more, and larger, smaller, larger, etc. are understood as excluding the present numbers, and larger, smaller, inner, etc. are understood as including the present numbers. If the first and second are described for the purpose of distinguishing technical features, they are not to be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated or implicitly indicating the precedence of the technical features indicated.
In the description of the present invention, unless otherwise explicitly limited, terms such as arrangement, installation, connection and the like should be understood in a broad sense, and those skilled in the art can reasonably determine the specific meanings of the above terms in the present invention in combination with the specific contents of the technical solutions.
In the description of the present invention, reference to the description of the terms "one embodiment," "some embodiments," "an illustrative embodiment," "an example," "a specific example," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
At present, a switched capacitor converter is often used as a novel dc converter to realize voltage conversion, but there are a plurality of factors that affect the working efficiency of the switched capacitor converter, wherein the parasitic capacitance loss of the flying capacitor has a great influence on the working efficiency of the switched capacitor converter. The flying capacitor is often formed by a MOS capacitor, and in many cases, a gate oxide layer between a gate and a channel of a MOS transistor is used as an insulating medium, the gate is used as a positive plate or a negative plate, and the source and the drain are connected with three ends of a substrate in a short manner to form the negative plate or the positive plate. However, a large parasitic capacitance always exists between the positive plate or the negative plate of the MOS capacitor and the ground, and the loss caused by the parasitic capacitance greatly reduces the efficiency of the switched capacitor converter.
Therefore, the invention provides an MOS capacitor, which can reduce the parasitic capacitance loss of the MOS capacitor.
In a first aspect, referring to fig. 1 and fig. 2, a MOS capacitor according to an embodiment of the invention includes a P-type substrate, a deep N-well formed in the P-type substrate, a first N + diffusion region formed in the deep N-well, a P-well formed in the deep N-well, and a first P + diffusion region formed in the P-well, the first N + diffusion region is connected to a first end of a preset first resistor R1, a second end of the first resistor R1 is connected to a first bias voltage U1, the first P + diffusion region is connected to a first end of a preset second resistor R2, and a second end of the second resistor R2 is connected to a second bias voltage U2, and is configured to reduce an equivalent parasitic capacitance of the MOS capacitor by connecting the deep N-well to the first bias voltage U1 and connecting the P-well to the second bias voltage U2. Specifically, the specific structure of the MOS capacitor is: a deep N-well is formed in the P-type substrate, a first N + diffusion region is formed in the deep N-well, the first N + diffusion region is connected with a first bias voltage U1 through a first resistor R1, a P-well is formed in the deep N-well, a first P + diffusion region is formed in the P-well, the first P + diffusion region is connected with a second bias voltage U2 through a second resistor R2, in addition, a second N + diffusion region and a third N + diffusion region are formed in the P-well, the second N + diffusion region is connected with the third N + diffusion region and used as a negative electrode of the MOS capacitor, a grid electrode of the MOS transistor is used as a positive electrode of the MOS capacitor, and in addition, a second P + diffusion region is formed in the P-type substrate; the MOS capacitor is provided with a first diode J1, a second diode J2 and a third diode J3, the first diode J1 is arranged in the P-well, the cathode of the first diode J1 is connected with the second N + diffusion region, and the anode of the first diode J1 is connected with the anode of the second diode J2; the second diode J2 is arranged in the deep N-well, and the cathode of the second diode J2 is connected with the cathode of the third triode J3; the third transistor J3 is disposed in the P-type substrate, and the anode of the third transistor J3 is connected to the second P + diffusion region. Fig. 2 shows a circuit structure diagram of an equivalent capacitor of the MOS capacitor of the present application, in which a first capacitor C1 is a gate capacitor, and a parasitic capacitor between a negative plate of the MOS capacitor of the present invention and ground is equivalent to three capacitors, including a second capacitor C2 between a channel of an MOS transistor and a P-well, a third capacitor C3 between the P-well and a deep N-well, and a fourth capacitor C4 between the deep N-well and a P-type substrate. Under the condition of alternating current, because the impedances of the connected first resistor R1 and the second resistor R2 are large, a path from the bottom of the second capacitor C2 to the second bias voltage U2 is equivalent to open circuit, and a path from the bottom of the third capacitor C3 to the first bias voltage U1 is equivalent to open circuit, in this case, the second capacitor C2, the third capacitor C3 and the fourth capacitor C4 are equivalently connected in series, the equivalent parasitic capacitor is a series value of the second capacitor C2, the third capacitor C3 and the fourth capacitor C4, and the equivalent capacitance value is 1/(1/C2+1/C3+ 1/C4). In general, the parasitic capacitance C3 between the P-well and the deep N-well and the parasitic capacitance C4 between the deep N-well and the P-type substrate are much smaller than the parasitic capacitance C2 between the MOS transistor channel and the P-well, so that the equivalent parasitic capacitance after the second capacitance C2, the third capacitance C3 and the fourth capacitance C4 are connected in series will be reduced, thereby reducing the parasitic capacitance loss of the MOS capacitance and further improving the operating efficiency of the switched capacitor converter.
Referring to fig. 2, in some embodiments, the magnitude of the first bias voltage U1 is twice the magnitude of the predetermined input voltage.
A first N + diffusion region connected to the first N + diffusion region during operation of the circuitThe bias voltage U1 is equal to the input MOS capacitor voltage V bias Twice that is, 2V to U1 bias 。
Referring to fig. 2, in some embodiments, the magnitude of the second bias voltage U2 is minus one times the predetermined input voltage. During the operation of the circuit, the second bias voltage U2 connected with the first P + diffusion region is equal to the input MOS capacitor voltage V bias Is negative one times, i.e. U2 ═ V bias . It should be noted that, the principle of adding an external bias voltage: applying a reverse voltage to the PN junction, leading electrons in the N-type semiconductor to a positive electrode and holes in the P-type semiconductor to a negative electrode, and then forming a depletion layer without electrons or holes; if the reverse voltage is reduced, the depletion layer is narrowed, the capacitance of the diode is increased, and 2V is selected bias and-V bias Can generate larger reverse voltage, thereby effectively reducing the capacitance value of parasitic capacitance, and 2V bias and-V bias The voltage is easy to generate through the charge pump circuit, and the applicability of the MOS capacitor is improved.
Referring to fig. 1, in some embodiments, the MOS capacitor further includes an NMOS transistor, and the P-well further has a second N + diffusion region and a third N + diffusion region formed therein, and the second N + diffusion region is connected to the third N + diffusion region and is used as a negative electrode of the MOS capacitor. In the MOS capacitor, two N + diffusion regions are connected and used as the anode of the MOS capacitor.
In some embodiments, the gate of the NMOS transistor is used as the anode of the MOS capacitor. In the MOS capacitor, the grid of the NMOS tube is used as the anode of the MOS capacitor.
Referring to fig. 1, in some embodiments, the second N + diffusion region and the third N + diffusion region have a first capacitance C1 therein. The first capacitor C1 is a gate capacitor, which is a main capacitor between the upper and lower plates of the MOS capacitor.
Referring to fig. 1 and 2, in some embodiments, the second N + diffusion region has a second capacitance C2 with the P-well. The second capacitor C2 is a parasitic capacitor formed on the first diode J1, and in an ac state, because the impedance of the second resistor R2 is large, the path between the second capacitor C2 and the second bias voltage U2 is equivalent to an open circuit, and at this time, the second capacitor C2 is equivalent to a series connection with the third capacitor C3.
Referring to fig. 1 and 2, in some embodiments, a third capacitance C3 is between the P-well and the deep N-well. The third capacitor C3 is a parasitic capacitor formed on the second diode J2, and in an alternating current state, since the impedance of the first resistor R1 is large, the path between the third capacitor C3 and the first bias voltage U1 is equivalent to an open circuit, at this time, the third capacitor C3 and the fourth capacitor C4 are in equivalent series connection, and the second capacitor C2, the third capacitor C3 and the fourth capacitor C4 are in equivalent series connection.
Referring to fig. 1, in some embodiments, a fourth capacitance C4 is provided between the deep N-well and the P-type substrate. The fourth capacitor C4 is a parasitic capacitor formed on the third diode J4.
Referring to fig. 3, in some embodiments, the total operating circuit of the MOS capacitors includes a deep N-well bias circuit module 310, a P-well bias circuit module 320, and a double boost circuit module 330, wherein the double boost circuit module 330 includes four switches S1, S2, S3, S4 and the MOS capacitors, VIN is an input voltage of the circuit, VOUT is an output voltage of the circuit, and GND is a ground terminal. The deep N-well bias circuit block 310 and the P-well bias circuit block 320 provide bias voltages of 2Vbias and-Vbias for the deep N-well and the P-well of the MOS capacitors, respectively. In some embodiments, when the input voltage VIN is 1.2V, the output voltage VOUT eventually settles at 2.4V, the output voltage of the deep N-well bias circuit eventually settles at twice the input voltage (i.e., settles at 2.4V), and the output voltage of the P-well bias circuit eventually settles at minus one time the input voltage (i.e., settles at-1.2V).
In a second aspect, an embodiment of the present invention further provides an electronic device, including the MOS capacitor of the first aspect.
The electronic device is formed by adopting the MOS capacitor of the embodiment, the structure of the MOS capacitor is provided with the deep N-well and the P-well, the deep N-well is connected with the first bias voltage U1, the P-well is connected with the second bias voltage U2, the parasitic capacitance between the polar plate of the MOS capacitor and the ground is equivalent to three capacitors which are connected in series, and therefore the equivalent capacitance value of the parasitic capacitance is reduced.
The embodiments of the present invention have been described in detail with reference to the accompanying drawings, but the present invention is not limited to the above embodiments, and various changes can be made within the knowledge of those skilled in the art without departing from the gist of the present invention. Furthermore, the embodiments of the present invention and the features of the embodiments may be combined with each other without conflict.
Claims (10)
1. An MOS capacitor is characterized by comprising a P-type substrate, a deep N-well formed in the P-type substrate, a first N + diffusion region formed in the deep N-well, a P-well formed in the deep N-well, and a first P + diffusion region formed in the P-well, wherein the first N + diffusion region is connected with a first end of a preset first resistor, a second end of the first resistor is connected with a first bias voltage, the first P + diffusion region is connected with a first end of a preset second resistor, and a second end of the second resistor is connected with a second bias voltage, so that the equivalent parasitic capacitance of the MOS capacitor is reduced by connecting the deep N-well with the first bias voltage and connecting the P-well with the second bias voltage.
2. The MOS capacitor of claim 1, wherein the magnitude of the first bias voltage is twice the magnitude of the predetermined input voltage.
3. The MOS capacitor of claim 2, wherein the magnitude of the second bias voltage is minus one times the magnitude of the predetermined input voltage.
4. The MOS capacitor of claim 3, further comprising an NMOS transistor, wherein a second N + diffusion region and a third N + diffusion region are further formed in the P-well, and the second N + diffusion region is connected to the third N + diffusion region and serves as a cathode of the MOS capacitor.
5. The MOS capacitor of claim 4, wherein the gate of the NMOS transistor is used as the anode of the MOS capacitor.
6. The MOS capacitor of claim 4 or 5, wherein the second N + diffusion region and the third N + diffusion region have a first capacitance therein.
7. The MOS capacitor of claim 6, wherein a second capacitance is provided between the second N + diffusion and the P-well.
8. The MOS capacitor of claim 7, wherein a third capacitance is between the P-well and the deep N-well.
9. The MOS capacitor of claim 8, wherein a fourth capacitor is between the deep N-well and the P-type substrate.
10. An electronic device characterized in that it comprises a MOS capacitor according to any of claims 1 to 9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210319270.3A CN114927579A (en) | 2022-03-29 | 2022-03-29 | MOS capacitor and electronic equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210319270.3A CN114927579A (en) | 2022-03-29 | 2022-03-29 | MOS capacitor and electronic equipment |
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| Publication Number | Publication Date |
|---|---|
| CN114927579A true CN114927579A (en) | 2022-08-19 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210319270.3A Pending CN114927579A (en) | 2022-03-29 | 2022-03-29 | MOS capacitor and electronic equipment |
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|---|---|
| CN (1) | CN114927579A (en) |
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- 2022-03-29 CN CN202210319270.3A patent/CN114927579A/en active Pending
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