CN217086571U

CN217086571U - Chip for preventing reverse connection of power supply

Info

Publication number: CN217086571U
Application number: CN202220780955.3U
Authority: CN
Inventors: 王春华
Original assignee: Nanjing Qinheng Microelectronics Co ltd
Current assignee: Nanjing Qinheng Microelectronics Co ltd
Priority date: 2022-04-06
Filing date: 2022-04-06
Publication date: 2022-07-29
Anticipated expiration: 2032-04-06

Abstract

The utility model discloses a chip for preventing reverse connection of power supply, which comprises a bare chip and a reference potential pin, wherein the bare chip comprises a P-type substrate, a reference potential PAD connection point and an NMOS (N-channel metal oxide semiconductor) with a multi-interdigital structure arranged on the P-type substrate; the source electrode of the NMOS is electrically connected with the P-type substrate, and the drain electrode of the NMOS is electrically connected with a reference potential PAD connection point; the reference potential PAD connecting point is electrically connected with the reference potential pin. The utility model discloses have and prevent the power transposition function, the protection chip is not damaged when the power transposition, has compromise the ESD performance, embedded integral structure, simple structure, the cost is lower.

Description

Chip for preventing reverse connection of power supply

Technical Field

The utility model belongs to the integrated circuit design field especially relates to a prevent CMOS technology chip and prevent power transposition's ideal diode chip's power structure and finished product encapsulation of power transposition.

Background

The chip of the conventional CMOS process comprises a P-type substrate PSUB and an N-well NWELL (the mainstream process also generally includes a P-well PWELL, which can be seen from the potential perspective as PSUB without isolation and is not distinguished in the present description). As shown in fig. 1, the package substrate 01 and the P-type substrate 02 are electrically connected through a conductive adhesive 05, and during normal operation, power is supplied in a forward direction, the N-wells and the source terminals 03 of the common PMOS transistors disposed in the N-wells are connected to a positive power supply terminal VDD, and the P-type substrate 02 and the P-wells and the source terminals 04 of the common NMOS transistors disposed in the P-type substrate or the P-wells are connected to a zero-voltage potential terminal GND (or a negative power supply terminal). The parasitic devices that are native to standard CMOS processes are represented in dashed lines. When connection errors occur in application or experiments, and the positive power supply end and the zero voltage potential end are connected and adjusted oppositely, the reverse power supply is called, namely, the power supply is reversely connected. Because the P-type substrate (P trap) and the N trap naturally form a trap-lined PN junction diode, when a power supply is reversely connected, the reverse voltage far exceeds the conduction voltage of the trap-lined diode, so that a high current of a plurality of amperes is generated far exceeding the design parameters of chips with only dozens of mA or even uA of forward power supply, the power is high, and the chips or the packaging connecting wires thereof can be burnt in a short time.

In order to avoid damaging a target chip when a power supply is reversely connected, the existing mainstream solution is as follows: firstly, a Schottky diode or a silicon diode is added outside a target chip to be connected in series, but the diode consumes 0.3V to 0.8V of voltage drop when being conducted, so that the electric energy loss is large. Secondly, an ideal diode chip is added outside the target chip to be connected in series, the voltage drop is lower than tens of mV when the target chip is conducted, at least 3 pins are respectively an input end (anode), an output end (cathode) and a zero voltage potential end GND, the ideal diode belongs to the CMOS technology, a P-type substrate (P-well) and a well substrate diode of an N-well still exist between the input end of the ideal diode and the GND, and the ideal diode is easy to damage when reversely connected with a power supply. And thirdly, a PMOS tube is added outside the target chip, but the cost and the volume are increased. For example, a 3-pin packaged low-power low-dropout linear voltage reducer LDO target chip with a selling price of about 0.2 yuan is taken, a scheme of additionally adding a 3-pin PMOS (P-channel metal oxide semiconductor) tube is lack of cost competitiveness, the ESD antistatic performance (about 1KV measured by HBM) of a common MOS (metal oxide semiconductor) device is only half of the ESD performance (most basic 2KV) of an integrated circuit chip, and the ESD performance of the whole scheme is reduced when the ESD static-free ESD protection circuit and the integrated circuit chip are connected in series for use.

Disclosure of Invention

The purpose of the invention is as follows: in order to solve the problem that the target chip of the CMOS process with small self forward working current can be damaged by large current when the power supply is reversely connected in the prior art, the utility model provides a chip for preventing the reverse connection of the power supply.

The technical scheme is as follows: a chip for preventing reverse connection of a power supply comprises a bare chip and a reference potential pin, wherein the bare chip comprises a P-type substrate, a reference potential PAD connection point and an NMOS (N-channel metal oxide semiconductor) with a multi-interdigital structure, wherein the NMOS is arranged on the P-type substrate; the source electrode of the NMOS is electrically connected with the P-type substrate, and the drain electrode of the NMOS is electrically connected with a reference potential PAD connection point; the reference potential PAD connecting point is electrically connected with the reference potential pin.

Further, the chip is an ideal diode chip.

Further, the reference potential is a zero voltage potential, and the reference potential pin is a GND pin outside the finished chip package.

Further, the NMOS is an ESD type NMOS.

Furthermore, the chip further comprises a first resistor, and the grid of the NMOS is connected with the positive power supply end of the chip through the first resistor.

And further, the device also comprises a secondary ESD protection device, wherein one end of the secondary ESD protection device is connected with the NMOS grid electrode, and the other end of the secondary ESD protection device is connected with the P-type substrate.

The device further comprises a second resistor, wherein one end of the second resistor is connected with a reference potential PAD connection point, and the other end of the second resistor is connected with the P-type substrate; the resistance value of the second resistor is larger than 100 omega.

And one end of the capacitor is connected with a positive power supply end of the chip, and the other end of the capacitor is connected with the P-type substrate.

The packaging bottom plate is connected with the P-type substrate of the bare chip through a non-conductive bonding material and is insulated from the P-type substrate.

Further, when the chip is an ideal diode chip, the chip further comprises an MOS tube with low on-resistance, an operational amplifier, a first resistor, an input pin and an output pin; the input end of the MOS tube with low on-resistance is connected with the input pin, the output end of the MOS tube with low on-resistance is connected with the output pin, and the drive end of the MOS tube with low on-resistance is connected with the output end of the operational amplifier; the negative power supply end of the operational amplifier is connected with the source electrode of the NMOS and the P-type substrate; the reference potential pin is a common terminal pin of the chip and is connected with a drain electrode of the NMOS; and the grid electrode of the NMOS is connected with an input pin of the chip through a first resistor.

Compared with the prior art, the utility model provides a prevent chip of power transposition has following beneficial effect:

(1) the power supply framework that the default of a P-type substrate in the conventional chip design is the zero-voltage reference potential is abandoned, and the drain electrode of the NMOS is used as the zero-voltage reference potential of the whole chip and connected to the external GND pin of the chip package through an ESD type NMOS device with a newly added multi-interdigital structure and a reference potential PAD connection point;

(2) the ESD performance is considered, and the ESD protection circuit has the advantage of exceeding the ESD index of an external MOS tube no matter whether the power supply is in positive connection or reverse connection;

(3) the substrate parasitic triode effect and the LATCH current LATCH-up effect are further reduced through the second resistor;

(4) the embedded integrated structure has simple structure and lower cost;

(5) the method avoids large current caused by reverse connection of a chip power supply, and is particularly suitable for a target chip of a CMOS (complementary metal oxide semiconductor) process with small self forward working current and more gradual working current change;

(6) the ideal diode chip has the function of preventing the reverse connection of the power supply, and can be connected in series with the positive power supply end of the target chip to protect the target chip from being damaged by the reverse connection of the power supply.

Drawings

FIG. 1 is a schematic diagram of a prior art CMOS process chip;

FIG. 2 is a schematic diagram of a chip for preventing reverse connection of power supply according to an embodiment;

FIG. 3 is a schematic diagram of a chip with reverse power connection prevention according to an embodiment;

FIG. 4 is a simplified diagram of a chip with power supply reverse connection prevention according to a second embodiment;

fig. 5 is a schematic diagram of an ideal diode chip with reverse connection of a three-prevention power supply according to an embodiment.

Detailed Description

The invention will be further explained with reference to the drawings and the specific embodiments.

The first embodiment is as follows:

a chip for preventing reverse connection of power supply is disclosed, as shown in FIG. 2, comprising a package baseboard 11, a bare chip and a reference potential pin outside the package of a finished chip, wherein the bare chip comprises a P-type substrate 12, a reference potential PAD connection point and an NMOS of a multi-interdigital structure arranged on the P-type substrate; as shown in the QFN package base plate of fig. 2, the package base plate 11 and the P-type substrate 12 of the bare chip are connected by the non-conductive adhesive material 15, and they are insulated from each other, instead of the conventional product in which the P-type substrate and the package base plate are electrically connected by the conductive adhesive; the source 14 of the NMOS and the P-type substrate are connected to the same potential, as in PSUB in fig. 3, the drain 16 of the NMOS is electrically connected to the reference potential PAD connection point, the reference potential PAD connection point is electrically connected to the reference potential pin, and may be further electrically connected to the package substrate 11 according to the application requirement, and in some package forms, the package substrate 11 is used as the reference potential pin. The resulting parasitic devices are indicated in dashed lines in the figure.

The reference potential in the chip is a zero voltage potential GND, and the reference potential pin is a GND pin outside the finished chip package, or a negative power supply VSS pin and is used for connecting a zero voltage end or a negative voltage end of a power supply system.

The NMOS is preferably an ESD type NMOS. The distance between the drain CONTACT hole and the GATE is large, typically more than 3 times larger than the relevant dimension of the normal minimum design rule NMOS. For example, the distance between the drain and the gate of a 3.3V common NMOS is about 0.3um, the advanced process can reach 0.1um, while the distance between the drain and the gate of an ESD NMOS is more than 1.2um, even 3um, and generally comprises a plurality of NMOS with interdigital structures, wherein the W of a unit NMOS is not less than 20um, and the logarithm of the interdigital is not less than 6. Regarding the structure and performance of the ESD type NMOS, when a chip is impacted by ESD with forward voltage, the presence of the NMOS is equivalent to connecting a forward diode (parasitic from the drain of the NMOS and the substrate) in series in the original ESD structure, and it is known that the ESD performance is excellent when the diode is in the forward direction; when the chip is impacted by ESD of reverse voltage, the ESD device is formed by connecting an NMOS and a well-substrate diode in series, the NMOS works in a GGNMOS or GRNMOS mode, the ESD performance is good, the well-substrate diode is in a forward working state, and the ESD performance is excellent. No matter the ESD impacts positively and negatively, the ESD indexes far surpass those of the external MOS tube.

As shown in fig. 3, the chip may further include a first resistor R1, and the gate of the NMOS is connected to the positive power terminal of the chip through a first resistor R1. The first resistor R1 is used for NMOS gate protection, and further comprises a secondary ESD protection device connected between the NMOS gate and the P-type substrate. The gate may be connected to other equivalent relatively high potential in addition to the positive power supply VDD, which is intended to turn on the NMOS when the power is supplied in the forward direction, so that the potential of the P-type substrate is as equal as possible to the reference potential outside the finished chip package.

As shown in FIG. 3, a second resistor R2 may be further included, wherein one end of the second resistor R2 is connected to the PAD connection point and the other end is connected to the P-type substrate. The resistance value of the second resistor is hundreds of ohms to dozens of kilohms, and in the embodiment, 5k omega is adopted for enabling current to flow through the resistor as much as possible when power is supplied in the positive direction, so that excessive voltage drop generated on a positive diode parasitic between an NMOS drain electrode and a substrate is avoided, and the current of a substrate parasitic triode and even the LATCH effect are avoided. When the unexpected power supply is reversely connected, the second resistor can generate microampere or milliampere current, but the current accords with the design parameters of a chip, the power is low, and permanent damage cannot be caused.

As shown in fig. 3, a capacitor may be further included, where one end of the capacitor is connected to the positive power terminal of the chip, and the other end is connected to the P-type substrate. The capacitor is used for reducing the voltage ripple of the positive power supply of the chip relative to the P-type substrate and improving the performance of the analog chip during weak signal processing.

In this embodiment, in consideration of the case of a package base plate, that is, when there is a package base plate, the package base plate 11 and the P-type substrate 12 of the bare chip need to be connected through the non-conductive adhesive material 15, so that the package base plate 11 and the P-type substrate 12 are insulated from each other, instead of the conventional product in which the P-type substrate and the package base plate are electrically connected through a conductive adhesive. In some applications, however, there may be no package substrate or the package substrate may be insulated from the outside, and the connection need not be considered.

Example two:

compared with the first embodiment, the second embodiment is a chip with a simple structure and capable of preventing reverse connection of a power supply, and comprises a bare chip and a reference potential pin outside a finished chip package, wherein the bare chip comprises a P-type substrate, a reference potential PAD connection point and an NMOS (N-channel metal oxide semiconductor) with a multi-interdigital structure arranged on the P-type substrate; the source electrode of the NMOS and the P-type substrate are connected to the same potential, the drain electrode of the NMOS is electrically connected with a reference potential PAD connection point, and the reference potential PAD connection point is electrically connected with a reference potential pin.

As shown in fig. 4, the reference potential in the chip is a zero voltage potential GND, and the reference potential pin is a GND pin outside the finished chip package, or a negative power supply VSS pin for connecting a zero voltage terminal or a negative voltage terminal of a power supply system.

In order to protect the gate of the NMOS, the chip further comprises a first resistor R1, and the gate of the NMOS is connected with a positive power supply end of the chip through a first resistor R1.

Example three:

the third embodiment is different from the first embodiment or the second embodiment in that the first embodiment and the second embodiment do not limit the specific functions of the chip, and the chip has the function of preventing the reverse connection of the power supply as long as the chip has the above structure, and the third embodiment further limits the chip to be an ideal diode chip.

The traditional ideal diode chip can realize one-way conduction with extremely low voltage drop, but does not have the function of preventing the reverse connection of a power supply. The power reversal connection preventing ideal diode chip of this embodiment, based on the utility model discloses a power framework for preventing power reversal connection combines with the one-way electric conduction of ideal diode, realizes that embedded power reversal connection preventing ideal diode, and it has self prevents power reversal connection function, also can be used to establish ties at the positive power supply end of self third party target chip that does not prevent reverse connection, avoids target chip power reversal connection to cause the damage.

The ideal diode chip for preventing the reverse connection of power supply in the third embodiment includes the package substrate, the bare chip, the reference potential pin outside the finished chip package, and the first resistor as shown in the first embodiment. As shown in fig. 5, the device further includes a MOS transistor Q1 with low on-resistance, an operational amplifier, an internal power supply alternative unit, an external input pin, an external output pin, and a common pin after the finished product is packaged, where the common pin is a reference potential pin.

Further, a second resistance, secondary ESD protection unit may be included, which is connected in the same manner as in the first embodiment.

And the source electrode of the NMOS and the P-type substrate are connected to a negative power supply end of the operational amplifier, and the drain electrode of the NMOS is connected with a reference potential PAD connection point and then connected with an external common terminal pin after the finished product is packaged. The grid of the NMOS is connected with an input pin of the chip through a first resistor; one end of the secondary ESD protection device is connected with the NMOS grid electrode, and the other end of the secondary ESD protection device is connected with the P-type substrate; one end of the second resistor is connected with a reference potential PAD connecting point, and the other end of the second resistor is connected with the P-type substrate.

The input end of the MOS transistor Q1 with low on-resistance is connected with the input pin, the output end is connected with the output pin, and the driving end is connected with the output end of the operational amplifier. In this embodiment, Q1 is a large-sized MOS transistor with low on-resistance, and the on-resistance is in the range of several m Ω to several hundreds m Ω. In fig. 5, Q1 is PMOS, the structure is simple but the area is large, Q1 can be replaced by NMOS, and a charge pump booster circuit is added to adjust the polarity of the operational amplifier to drive the gate of the NMOS. In this embodiment, two anti-backflow units are provided, for example, a well of the MOS transistor Q1 with low on-resistance is provided with a well anti-backflow unit, so as to ensure that the parasitic diode between the source and the drain of Q1 and the well does not affect the overall one-way conduction function, two butt diodes are only used as an illustration in fig. 5, and the actual circuit has various available structures. Next, a gate of the MOS transistor Q1 with low on-resistance is provided with a gate anti-backflow unit to ensure that the Q1 is turned off when the power is reversely supplied, which is only illustrated by Q2 and a current-limiting protection resistor R3 in fig. 5, and VOUT voltage is higher than VIN when the power is reversely supplied, so that the Q2 is turned on to ensure that the gate of the Q1 is at a high potential to turn off the Q1. The specific implementation circuit of the backflow prevention unit has various available structures, and is not limited herein.

The two butt diodes used as the internal power supply unit in the embodiment of fig. 5 are only illustrated, and the actual circuit has various available structures, and the switching is usually realized by using a comparator and a MOS. The secondary ESD protection unit in this embodiment is merely an illustration, and the actual circuit has various available structures.

In application, the positive power terminal of the third party target chip which is not in reverse connection with the power supply is connected with the output terminal of the ideal diode which is in reverse connection with the power supply. When the voltage of the input terminal VIN is 0 and the voltage of the output terminal VOUT is present, and at this time Q1 is turned off, the consumed current of the whole ideal diode chip is several mA even below 1uA, and the resistor R2 is used for providing such a small current path between the P-type substrate and the external GND. When the input end of the ideal diode is reversely connected with the power supply between the common GND of all the chips, the ideal diode cannot be damaged, the current of the output end and the input end is cut off, and the damage of a third-party target chip caused by the overcurrent of the internal trap-substrate diode is avoided.

Claims

1. A chip for preventing reverse connection of a power supply comprises a bare chip and a reference potential pin, wherein the bare chip comprises a P-type substrate, a reference potential PAD connection point and an NMOS (N-channel metal oxide semiconductor) with a multi-interdigital structure, wherein the NMOS is arranged on the P-type substrate; the source electrode of the NMOS is electrically connected with the P-type substrate, and the drain electrode of the NMOS is electrically connected with a reference potential PAD connection point; the reference potential PAD connecting point is electrically connected with the reference potential pin.

2. The chip for preventing reverse connection of power supply of claim 1, wherein the chip is an ideal diode chip.

3. The chip for preventing reverse connection of power supply as claimed in claim 1 or 2, wherein the reference potential is zero voltage potential, and the reference potential pin is a GND pin outside the finished chip package.

4. The chip for preventing reverse connection of power supply as claimed in claim 1 or 2, wherein the NMOS is an ESD type NMOS.

5. The chip for preventing reverse connection of power supply of claim 1 or 2, further comprising a first resistor, wherein the gate of the NMOS is connected to the positive power supply terminal of the chip through the first resistor.

6. The chip for preventing reverse connection of power supply of claim 5, further comprising a secondary ESD protection device, wherein one end of the secondary ESD protection device is connected with the NMOS grid electrode, and the other end of the secondary ESD protection device is connected with the P-type substrate.

7. The chip for preventing reverse connection of power supply of claim 1 or 2, further comprising a second resistor, wherein one end of the second resistor is connected with a reference potential PAD connection point, and the other end is connected with a P-type substrate; the resistance value of the second resistor is larger than 100 omega.

8. The chip for preventing reverse connection of power supply of claim 1 or 2, further comprising a capacitor, wherein one end of the capacitor is connected with a positive power supply end of the chip, and the other end of the capacitor is connected with the P-type substrate.

9. The chip for preventing reverse connection of power supply of claim 1 or 2, further comprising a package base plate, wherein the package base plate and the P-type substrate of the bare chip are connected through a non-conductive adhesive material and are insulated from each other.

10. The chip for preventing reverse connection of power supply of claim 2, further comprising a MOS tube with low on-resistance, an operational amplifier, a first resistor, an input pin and an output pin; the input end of the MOS tube with low on-resistance is connected with the input pin, the output end of the MOS tube with low on-resistance is connected with the output pin, and the drive end of the MOS tube with low on-resistance is connected with the output end of the operational amplifier; the negative power supply end of the operational amplifier is connected with the source electrode of the NMOS and the P-type substrate; the reference potential pin is a common terminal pin of the chip and is connected with a drain electrode of the NMOS; and the grid electrode of the NMOS is connected with an input pin of the chip through a first resistor.