CN217086571U - A chip against reverse power supply - Google Patents

Abstract

The utility model discloses a chip for preventing reverse connection of power supply, which comprises a bare chip and a reference potential pin, wherein the bare chip comprises a P-type substrate, a reference potential PAD connection point and an NMOS (N-channel metal oxide semiconductor) with a multi-interdigital structure arranged on the P-type substrate; the source electrode of the NMOS is electrically connected with the P-type substrate, and the drain electrode of the NMOS is electrically connected with a reference potential PAD connection point; the reference potential PAD connecting point is electrically connected with the reference potential pin. The utility model discloses have and prevent the power transposition function, the protection chip is not damaged when the power transposition, has compromise the ESD performance, embedded integral structure, simple structure, the cost is lower.

Description

A chip against reverse power supply

technical field

The utility model belongs to the field of integrated circuit design, in particular to a power supply structure and a finished product package of a CMOS process chip capable of preventing power reverse connection and an ideal diode chip preventing power reverse connection.

Background technique

A chip of conventional CMOS process includes a P-type substrate PSUB and an N-well NWELL (the mainstream process usually also has a P-well PWELL. When there is no isolation, the P-well can be regarded as a PSUB from the perspective of potential, and will not be distinguished in this description). As shown in FIG. 1 , an electrical connection is formed between the package bottom plate 01 and the P-type substrate 02 through a conductive glue 05, which is a forward power supply during normal operation, and the sources of several N wells and several ordinary PMOS transistors arranged in the N wells The terminal 03 will be connected to the positive power supply terminal VDD, the source terminal 04 of the P-type substrate 02 and several P-wells and several ordinary NMOSs arranged in the P-type substrate or P-well will be connected to the zero-voltage potential terminal GND (or negative power supply terminal). The dashed line in the figure represents the parasitic devices that are native to standard CMOS processes. When there is a connection error in the application or experiment, which causes the connection of the positive power supply terminal and the zero-voltage potential terminal to be reversed, it is called reverse power supply, that is, the power supply is reversed. Since the P-type substrate (P-well) and the N-well naturally form a well-lined PN junction diode, when the power supply is reversely connected, the reverse voltage far exceeds the turn-on voltage of the well-lined diode, so a large voltage of several amperes will be generated. The current far exceeds the design parameters of those chips whose forward power supply is only tens of mA or even several uA, and the power is large, so the chip or its package connection wire can be burned in a short time.

In order to avoid damage to the target chip when the power supply is reversely connected, the existing mainstream solutions: ① is to add a Schottky or silicon diode in series outside the target chip, but because the diode itself consumes a voltage drop of 0.3V to 0.8V when it is turned on , so the power loss is large. ② is to add an ideal diode chip in series outside the target chip, the voltage is reduced to several tens of mV when turned on, and there are at least 3 pins, which are the input terminal (anode), the output terminal (cathode), and the zero-voltage potential terminal GND, The ideal diode belongs to the CMOS process, and there are still P-type substrate (P-well) and N-well well-lined diodes between its own input and GND, and it is vulnerable when the power is reversely connected. ③ is to add a PMOS tube outside the target chip, but it increases the cost and volume. Taking a 3-pin packaged low-power low-dropout linear buck LDO target chip that sells for about 0.2 yuan as an example, the solution of adding an additional 3-pin PMOS tube is not cost-competitive, and the cost of ordinary MOS devices is low. The ESD anti-static performance (about 1KV according to HBM) is only half of the ESD performance of integrated circuit chips (the most basic 2KV). The use of the two in series reduces the ESD performance of the overall solution during normal operation.

SUMMARY OF THE INVENTION

Purpose of the invention: In order to solve the problem in the prior art that the target chip of the CMOS process with a small forward working current itself will be damaged due to a large current when the power supply is reversely connected, the utility model provides a chip that prevents the reverse connection of the power supply .

Technical solution: a chip against reverse power supply, comprising a bare chip and a reference potential pin, the bare chip comprising a P-type substrate, a reference potential PAD connection point and a multi-finger structure arranged on the P-type substrate NMOS; the source of the NMOS is electrically connected to the P-type substrate, the drain of the NMOS is electrically connected to the reference potential PAD connection point; the reference potential PAD connection point is electrically connected to the reference potential pin.

Further, the chip is an ideal diode chip.

Further, the reference potential is zero voltage potential, and the reference potential pin is a GND pin outside the package of the finished chip.

Further, the NMOS is an ESD type NMOS.

Further, a first resistor is also included, and the gate of the NMOS is connected to the positive power supply terminal of the chip through the first resistor.

Further, a secondary ESD protection device is also included, one end of the secondary ESD protection device is connected to the NMOS gate, and the other end is connected to the P-type substrate.

Further, it also includes a second resistor, one end of the second resistor is connected to the reference potential PAD connection point, and the other end is connected to the P-type substrate; the resistance value of the second resistor is greater than 100Ω.

Further, it also includes a capacitor, one end of the capacitor is connected to the positive power supply terminal of the chip, and the other end is connected to the P-type substrate.

Further, a package bottom plate is also included, and the package bottom plate and the P-type substrate of the bare chip are connected by a non-conductive adhesive material and are insulated from each other.

Further, when the chip is an ideal diode chip, it also includes a low on-resistance MOS tube, an operational amplifier, a first resistor, an input pin and an output pin; the input end of the low on-resistance MOS tube is connected to the input lead. pin, the output terminal is connected to the output pin, and the driving terminal is connected to the output terminal of the operational amplifier; the negative power supply terminal of the operational amplifier is connected to the source of the NMOS and the P-type substrate; the reference potential pin is the common terminal pin of the chip, connected to The drain of the NMOS; the gate of the NMOS is connected to the input pin of the chip through the first resistor.

Compared with the prior art, the utility model provides a chip for preventing the reverse connection of the power supply, which has the following beneficial effects:

(1) Abandoning the power supply structure of the P-type substrate in the conventional chip design, which is a zero-voltage reference potential by default, but by adding an ESD-type NMOS device with a multi-finger structure and a reference potential PAD connection point, the drain of the NMOS is connected. As the zero-voltage reference potential of the entire chip and connected to the GND pin outside the chip package;

(2) Taking into account the ESD performance, whether the power supply is connected directly or reversely, it has the advantage of far exceeding the ESD index of the external MOS tube;

(3) The parasitic triode effect of the substrate and the latch-up effect of the LATCH current are further reduced by the second resistance;

(4) Embedded integrated structure, simple structure and low cost;

(5) Avoid the large current caused by the reverse connection of the chip power supply, especially suitable for the target chip of the CMOS process whose forward working current is not large and the working current changes relatively gently;

(6) To provide an ideal diode chip with anti-power reverse connection, which has the function of anti-power reverse connection, and can also be connected in series with the positive power supply terminal of the target chip to protect the target chip from being damaged by the reverse power connection.

Description of drawings

1 is a schematic structural diagram of a prior art CMOS process chip;

FIG. 2 is a schematic structural diagram of a chip for preventing power reverse connection in Embodiment 1;

FIG. 3 is a schematic diagram of a chip for preventing reverse connection of the power supply in the first embodiment;

Fig. 4 is the simplest structure diagram of the chip for preventing the reverse connection of the power supply in the second embodiment;

FIG. 5 is a schematic diagram of an ideal diode chip for preventing reverse connection of the power supply according to the third embodiment.

Detailed ways

The present utility model will be further explained below in conjunction with the accompanying drawings and specific embodiments.

Example 1:

A chip for preventing reverse power connection, as shown in FIG. 2, includes a package bottom plate 11, a bare chip and reference potential pins outside the package of the finished chip, and the bare chip includes a P-type substrate 12, a reference potential PAD connection point and a reference potential pin. An NMOS with a multi-finger structure arranged on a P-type substrate; as shown in the QFN package bottom plate in Figure 2, the package bottom plate 11 and the P-type substrate 12 of the bare chip are connected by a non-conductive adhesive material 15, and the two are insulated from each other. In non-traditional products, the P-type substrate and the package bottom plate are electrically connected through conductive glue; the source electrode 14 of the NMOS and the P-type substrate are connected to the same potential, such as the PSUB in FIG. 3, the drain electrode 16 of the NMOS It is electrically connected to the reference potential PAD connection point, the reference potential PAD connection point is electrically connected to the reference potential pin, and can be electrically connected to the package bottom plate 11 according to application requirements. In other package forms, the package bottom plate 11 is used as the reference potential pin. The dotted line in the figure represents the resulting parasitic device.

The reference potential in the chip is zero voltage potential GND, and the reference potential pin is the GND pin outside the package of the finished chip, or the negative power VSS pin, which is used to connect the zero voltage terminal or the negative voltage terminal of the power supply system.

The NMOS is preferably an ESD type NMOS. The distance between the drain CONTACT hole and the gate GATE is large, usually more than 3 times larger than the relative size of the NMOS of the common minimum design rule. For example, the distance between the drain and gate of 3.3V ordinary NMOS is about 0.3um, and the advanced process can reach 0.1um, while the distance between the drain and gate of ESD NMOS is more than 1.2um, or even 3um, which is usually composed of multiple interdigitated NMOS structures. Composition, the W of the unit NMOS is not less than 20um, and the interdigital logarithm is not less than 6. As far as the structure and performance of ESD type NMOS are concerned, when the chip is impacted by ESD with forward voltage, the existence of NMOS is equivalent to connecting a forward diode in series in the original ESD structure (parasitic from the drain of NMOS and the substrate), As we all know, the ESD performance of the diode is excellent in the forward direction; when the chip is impacted by the ESD of the reverse voltage, the ESD device is a series connection of NMOS and a diode such as a well liner. The NMOS works in the GGNMOS or GRNMOS mode and has good ESD performance. The liner diode is in forward operation and has excellent ESD performance. Regardless of the positive and negative ESD impact, there are far more ESD indicators than the external MOS tube.

As shown in FIG. 3 , the chip may further include a first resistor R1, and the gate of the NMOS is connected to the positive power supply terminal of the chip through the first resistor R1. The first resistor R1 is used for NMOS gate protection, and further includes a secondary ESD protection device connected between the NMOS gate and the P-type substrate. In addition to the positive power supply VDD, the gate can also be connected to other equivalent relatively high potentials. The purpose is to enable the NMOS to turn on when the power is forwarded, so that the potential of the P-type substrate is as equal as possible to that outside the finished chip package. the reference potential.

As shown in FIG. 3 , a second resistor R2 may also be included, one end of the second resistor R2 is connected to the reference potential PAD connection point, and the other end is connected to the P-type substrate. The resistance value of the second resistor is hundreds of ohms to tens of thousands of ohms. In this embodiment, 5kΩ is used to allow the current to flow through this resistor as much as possible when the power is forwarded, so as to avoid parasitics between the NMOS drain and the substrate. Excessive voltage drop is generated on the forward diode, causing substrate parasitic triode current and even LATCH effect. When the accidental power supply is reversed, the existence of the second resistor will generate a current of microampere or milliampere level, but it conforms to the design parameters of the chip, and the power is also small, which will not cause permanent damage.

As shown in FIG. 3 , a capacitor may also be included, one end of the capacitor is connected to the positive power supply terminal of the chip, and the other end is connected to the P-type substrate. The capacitor is used to reduce the voltage ripple of the chip's positive power supply relative to the P-type substrate, and to improve the performance of the analog chip during weak signal processing.

In this embodiment, considering the situation of the package bottom plate, that is, when there is a package bottom plate, it is necessary to connect the package bottom plate 11 and the P-type substrate 12 of the bare chip through a non-conductive adhesive material 15, so that the package bottom plate 11 and the P-type substrate are connected 12. They are insulated from each other, and the P-type substrate and the package bottom plate are electrically connected through conductive glue in non-traditional products. However, in some applications, there may not be a package backplane or the package backplane is already insulated from the outside, and the connection method does not need to be considered.

Embodiment 2:

Compared with the first embodiment, the second embodiment is a chip with a simple structure to prevent the reverse connection of the power supply, including a bare chip and reference potential pins outside the package of the finished chip, and the bare chip includes a P-type substrate and a reference potential PAD. The connection point and the NMOS of the multi-finger structure arranged on the P-type substrate; the source of the NMOS and the P-type substrate are connected to the same potential, and the drain of the NMOS is electrically connected to the reference potential PAD connection point, refer to The potential PAD connection point is electrically connected to the reference potential pin.

As shown in Figure 4, the reference potential in the chip is zero voltage potential GND, and the reference potential pin is the GND pin outside the package of the finished chip, or the negative power VSS pin, which is used to connect the zero voltage of the power supply system terminal or negative voltage terminal.

In order to protect the gate of the NMOS, a first resistor R1 is also included, and the gate of the NMOS is connected to the positive power supply terminal of the chip through the first resistor R1.

Embodiment three:

The difference between Embodiment 3 and Embodiment 1 or Embodiment 2 is that Embodiment 1 and Embodiment 2 do not limit the specific functions of the chip. Three further restricts the chip to an ideal diode chip.

The traditional ideal diode chip can realize unidirectional conduction with a very low voltage drop, but it does not have the function of preventing power reverse connection. The ideal diode chip with anti-power reverse connection in this embodiment is based on the power supply structure with anti-power reverse connection of the present invention, combined with the unidirectional conduction of the ideal diode, to realize the embedded ideal diode for anti-power reverse connection, which itself has The anti-power reverse connection function can also be used to connect in series with the positive power supply terminal of a third-party target chip that does not prevent reverse connection itself, so as to avoid damage caused by reverse power supply of the target chip.

The ideal diode chip with anti-power reverse connection in the third embodiment includes the package base plate shown in the first embodiment, the bare chip and the reference potential pins outside the package of the finished chip, and the first resistor. As shown in Figure 5, it also includes a low on-resistance MOS transistor Q1, an operational amplifier, an internal power supply unit selected from two alternatives, external input pins, output pins and common terminal pins after the finished product is packaged. The common terminal leads to The pin is the reference potential pin.

Further, a second resistor and a second-level ESD protection unit may also be included, and the connection method is the same as that in the first embodiment.

The source of the NMOS and the P-type substrate are connected to the negative power supply terminal of the operational amplifier, the drain of the NMOS is connected to the reference potential PAD connection point, and then connected to the external common terminal pin after the finished product is packaged. The gate of the NMOS is connected to the input pin of the chip through the first resistor; one end of the secondary ESD protection device is connected to the NMOS gate, and the other end is connected to the P-type substrate; one end of the second resistor is connected to the reference potential PAD connection point, and the other end is connected to the P-type substrate.

The input end of the low on-resistance MOS transistor Q1 is connected to the input pin, the output end is connected to the output pin, and the drive end is connected to the output end of the operational amplifier. In this embodiment, Q1 is a MOS transistor with a large size and low on-resistance, and the on-state impedance ranges from several mΩ to several hundreds of mΩ. In Figure 5, Q1 is a PMOS, with a simple structure but a large area. Q1 can also be replaced with an NMOS, and a charge pump boost circuit is added and the polarity of the op amp is adjusted to drive the gate of the NMOS. In this embodiment, two anti-backflow units are provided. For example, the well of the MOS transistor Q1 with low on-resistance is provided with a well anti-backflow unit to ensure that the parasitic diode between the source and drain of Q1 and the well does not affect the overall unidirectional conduction. Function, the use of two butted diodes in Figure 5 is for illustration only, and there are many available structures in the actual circuit. Secondly, the gate of the low on-resistance MOS transistor Q1 is provided with a gate anti-backflow unit to ensure that Q1 is turned off during reverse power supply. In Figure 5, Q2 and current limiting protection resistor R3 are used for illustration only, and the VOUT voltage is high during reverse power supply. At VIN, so Q2 turns on ensuring that the gate of Q1 is high to turn off Q1. The specific implementation circuit of the anti-backflow unit has various available structures, which are not limited here.

As shown in FIG. 5 , the use of two butt diodes for the internal power supply two-to-one unit in this embodiment is only for illustration. There are many available structures in the actual circuit, and the switching is usually realized by a comparator and a MOS. The secondary ESD protection unit in this embodiment is only for illustration, and there are many available structures in the actual circuit.

In the application, the positive power supply terminal of the third-party target chip that is not protected against reverse power supply is connected to the output terminal of the ideal diode that is protected against reverse power supply. When the input terminal VIN voltage is 0 and the output terminal VOUT has voltage, Q1 is turned off at this time, the consumption current of the entire ideal diode chip is several mA or even 1uA or less, and the resistor R2 is used to provide this between the P-type substrate and the external GND. a small current channel. When the power supply between the input terminal of the ideal diode and the common GND of all chips is reversed, not only the ideal diode itself will not be damaged, but it also turns off the current between the output terminal and the input terminal, avoiding the third-party target chip due to internal wells. The liner diode is damaged due to overcurrent.

Claims (10)

1. A chip for preventing reverse connection of a power supply comprises a bare chip and a reference potential pin, wherein the bare chip comprises a P-type substrate, a reference potential PAD connection point and an NMOS (N-channel metal oxide semiconductor) with a multi-interdigital structure, wherein the NMOS is arranged on the P-type substrate; the source electrode of the NMOS is electrically connected with the P-type substrate, and the drain electrode of the NMOS is electrically connected with a reference potential PAD connection point; the reference potential PAD connecting point is electrically connected with the reference potential pin.

2. The chip for preventing reverse connection of power supply of claim 1, wherein the chip is an ideal diode chip.

3. The chip for preventing reverse connection of power supply as claimed in claim 1 or 2, wherein the reference potential is zero voltage potential, and the reference potential pin is a GND pin outside the finished chip package.

4. The chip for preventing reverse connection of power supply as claimed in claim 1 or 2, wherein the NMOS is an ESD type NMOS.

5. The chip for preventing reverse connection of power supply of claim 1 or 2, further comprising a first resistor, wherein the gate of the NMOS is connected to the positive power supply terminal of the chip through the first resistor.

6. The chip for preventing reverse connection of power supply of claim 5, further comprising a secondary ESD protection device, wherein one end of the secondary ESD protection device is connected with the NMOS grid electrode, and the other end of the secondary ESD protection device is connected with the P-type substrate.

7. The chip for preventing reverse connection of power supply of claim 1 or 2, further comprising a second resistor, wherein one end of the second resistor is connected with a reference potential PAD connection point, and the other end is connected with a P-type substrate; the resistance value of the second resistor is larger than 100 omega.

8. The chip for preventing reverse connection of power supply of claim 1 or 2, further comprising a capacitor, wherein one end of the capacitor is connected with a positive power supply end of the chip, and the other end of the capacitor is connected with the P-type substrate.

9. The chip for preventing reverse connection of power supply of claim 1 or 2, further comprising a package base plate, wherein the package base plate and the P-type substrate of the bare chip are connected through a non-conductive adhesive material and are insulated from each other.

10. The chip for preventing reverse connection of power supply of claim 2, further comprising a MOS tube with low on-resistance, an operational amplifier, a first resistor, an input pin and an output pin; the input end of the MOS tube with low on-resistance is connected with the input pin, the output end of the MOS tube with low on-resistance is connected with the output pin, and the drive end of the MOS tube with low on-resistance is connected with the output end of the operational amplifier; the negative power supply end of the operational amplifier is connected with the source electrode of the NMOS and the P-type substrate; the reference potential pin is a common terminal pin of the chip and is connected with a drain electrode of the NMOS; and the grid electrode of the NMOS is connected with an input pin of the chip through a first resistor.

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