CN114925011B - Method and device for solving problem that PCIE hot plug slot position cannot identify equipment - Google Patents

Method and device for solving problem that PCIE hot plug slot position cannot identify equipment Download PDF

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Publication number
CN114925011B
CN114925011B CN202210575680.4A CN202210575680A CN114925011B CN 114925011 B CN114925011 B CN 114925011B CN 202210575680 A CN202210575680 A CN 202210575680A CN 114925011 B CN114925011 B CN 114925011B
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pcie
cpld
logic buffer
power
hot plug
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CN114925011A (en
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王明磊
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Suzhou Inspur Intelligent Technology Co Ltd
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Suzhou Inspur Intelligent Technology Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G06F13/4081—Live connection to bus, e.g. hot-plugging
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/266—Arrangements to supply power to external peripherals either directly from the computer or under computer control, e.g. supply of power through the communication port, computer controlled power-strips
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The invention provides a method, a system, a device and a storage medium for solving the problem that PCIE hot plug slots cannot identify devices, wherein the method comprises the following steps: setting a logic buffer between a CPLD and a chip, and controlling the logic buffer through the CPLD; the method comprises the steps of responding to the first card starting of a server, confirming that PCIE equipment is in place, and controlling a hot plug slot to be normally powered on; in response to performing the hot plug of the PCIE equipment, the logic buffer is controlled to be turned on or turned off by the CPLD so as to control the power on and power off of the PCIE equipment; and responding to the starting of the server without the card, starting the logic buffer through the CPLD, and keeping the PCIE slot in a non-power-on state. The invention can solve the problem that the PCIE hot plug slot can not identify the equipment, and improves the universality and the effectiveness of the server design.

Description

Method and device for solving problem that PCIE hot plug slot position cannot identify equipment
Technical Field
The invention relates to the field of servers, in particular to a method, a system, equipment and a storage medium for solving the problem that equipment cannot be identified by PCIE hot plug slots.
Background
With the faster and faster of social development, people have higher requirements on safety and reliability of data. The server is used as a data carrier, so that the data is ensured to be safe and reliable, and the server needs to run stably and uninterruptedly for a long time; when a PCIE (Peripheral Component Interconnect express, a high-speed serial computer expansion bus standard) device on a server fails and needs to be replaced, if the power-off processing is performed, uninterrupted operation of the server cannot be guaranteed; PCIE slot setting supporting HOT-PLUG (Hot PLUG, allowing a user to take out and replace damaged PCIE equipment without shutting down the system and cutting off the power supply) on a server is increasingly widely used; when the PCIE equipment of the server fails, the power supply of the failure PCIE slot can be independently disconnected, the power supply of the slot can be recovered after the new PCIE equipment is replaced, and the PCIE equipment can work again by reloading the drive, so that the complete machine of the server can be ensured to run uninterruptedly and reliably. When a server is designed, the situation that PCIE equipment is powered on abnormally and cannot be identified and HOT PLUG cannot be realized due to unstable power-on enabling signals of PCIE slots supporting HOT-PLUG during power-on is often encountered.
In the existing server design, the HOT-PLUG power-on enabling signal is directly sent to the CPLD to control the power-on of the PCIE equipment, and if the PWREN signal (the signal used for enabling the power-on the HOT PLUG slot of the server main board) is unstable, the PCIE equipment may have abnormal power-on. The unstable difference of the PWREN signal is large during the power-on period, and the CPLD receiving the PWREN signal needs a targeted modification scheme to solve the problem, so that the implementation is complex, non-uniform and poor in flexibility, and the later maintenance is affected.
Disclosure of Invention
In view of the above, an object of the embodiments of the present invention is to provide a method, a system, a computer device and a computer readable storage medium for solving the problem that PCIE hot-plug slots cannot identify devices, where a logic buffer is added between a chip and a CPLD in the prior art, and the CPLD controls on and off of the logic buffer, so that the problem that PCIE hot-plug slots cannot identify devices is solved, and versatility and effectiveness of server design are improved.
Based on the above objective, an aspect of the embodiments of the present invention provides a method for solving the problem that PCIE hot plug slots cannot identify devices, including the following steps: setting a logic buffer between a CPLD and a chip, and controlling the logic buffer through the CPLD; the method comprises the steps of responding to the first card starting of a server, confirming that PCIE equipment is in place, and controlling a hot plug slot to be normally powered on; in response to performing the hot plug of the PCIE equipment, the logic buffer is controlled to be turned on or turned off by the CPLD so as to control the power on and power off of the PCIE equipment; and responding to the starting of the server without the card, starting the logic buffer through the CPLD, and keeping the PCIE slot in a non-power-on state.
In some embodiments, the confirming that the PCIE device is in place includes: and disabling the logic buffer enable signal through the CPLD, enabling the power supply enable signal to be inactive, and detecting that the preset signal is low level to confirm that the PCIE equipment is in place.
In some embodiments, the controlling the normal powering up of the hot plug slots includes: and in response to identifying the PCIE device, enabling the logic buffer enabling signal through the CPLD and enabling a power supply signal.
In some embodiments, the controlling, by the CPLD, the logic buffer to be turned on or turned off to control powering up and powering down of the PCIE device includes: and notifying the hot-unplugged information to the mainboard through the CPLD to remove the resources of the unplugged PCIE device, or notifying the hot-plugged information to the mainboard through the CPLD to increase the resources of the plugged PCIE device.
In some embodiments, the controlling, by the CPLD, the logic buffer to be turned on or turned off to control powering up and powering down of the PCIE device includes: starting the logic buffer through the CPLD, and outputting a low-level power supply signal to control the PCIE equipment to be powered down; or the logic buffer is turned off through the CPLD, and a high-level power supply signal is output to control the PCIE equipment to be powered on.
In some embodiments, the maintaining the PCIE slot in the unpowered state includes: and detecting whether the prediction signal is at a high level by the CPLD, and controlling the PCIE slot to be in a non-power-on state in response to the CPLD detecting that the prediction signal is at the high level.
In some embodiments, the method further comprises: and in response to the completion of power-on, performing hot plug, pulling down a prediction signal to detect that the PCIE device is in place.
In another aspect of the embodiments of the present invention, a system for solving a problem that PCIE hot plug slots cannot identify devices is provided, including: the setting module is configured to set a logic buffer between the CPLD and the chip and control the logic buffer through the CPLD; the control module is configured to respond to the first card startup of the server, confirm that PCIE equipment is in place and control the normal power-on of the hot plug slot; the plug-in module is configured to respond to the hot plug of the PCIE equipment and control the logic buffer to be opened or closed through the CPLD so as to control the power on and power off of the PCIE equipment; and the holding module is configured to respond to the starting of the server without a card, start the logic buffer through the CPLD and keep the PCIE slot in a non-power-on state.
In yet another aspect of the embodiment of the present invention, there is also provided a computer apparatus, including: at least one processor; and a memory storing computer instructions executable on the processor, which when executed by the processor, perform the steps of the method as above.
In yet another aspect of the embodiments of the present invention, there is also provided a computer-readable storage medium storing a computer program which, when executed by a processor, implements the method steps as described above.
The invention has the following beneficial technical effects: by adding a logic buffer between a chip and a CPLD in the prior art and controlling the on and off of the logic buffer by the CPLD, the problem that the PCIE hot plug slot cannot identify equipment is solved, and the universality and the effectiveness of the server design are improved.
Drawings
In order to more clearly illustrate the embodiments of the invention or the technical solutions in the prior art, the drawings that are necessary for the description of the embodiments or the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the invention and that other embodiments may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic diagram of an embodiment of a method for solving the problem that PCIE hot plug slots cannot identify devices according to the present invention;
fig. 2 is a schematic diagram of an embodiment of a system for solving the problem that PCIE hot plug slots cannot identify devices according to the present invention;
fig. 3 is a schematic hardware structure of an embodiment of a computer device for solving the problem that PCIE hot plug slot cannot identify a device according to the present invention;
fig. 4 is a schematic diagram of an embodiment of a computer storage medium for solving the problem that PCIE hot plug slot cannot identify devices.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the following embodiments of the present invention will be described in further detail with reference to the accompanying drawings.
It should be noted that, in the embodiments of the present invention, all the expressions "first" and "second" are used to distinguish two entities with the same name but different entities or different parameters, and it is noted that the "first" and "second" are only used for convenience of expression, and should not be construed as limiting the embodiments of the present invention, and the following embodiments are not described one by one.
In a first aspect of the embodiment of the present invention, an embodiment of a method for solving the problem that a PCIE hot plug slot cannot identify a device is provided. Fig. 1 is a schematic diagram of an embodiment of a method for solving the problem that PCIE hot plug slots cannot identify devices. As shown in fig. 1, the embodiment of the present invention includes the following steps:
s1, setting a logic buffer between a CPLD and a chip, and controlling the logic buffer through the CPLD;
s2, responding to the first card starting of the server, confirming that PCIE equipment is in place, and controlling the hot plug slot to be normally powered on;
s3, in response to performing hot plug of the PCIE equipment, the logic buffer is controlled to be opened or closed through the CPLD so as to control power on and power off of the PCIE equipment; and
and S4, responding to the starting of the server without the card, starting the logic buffer through the CPLD, and keeping the PCIE slot in a non-power-on state.
In the prior art, the logic control of the power-on of HOT-PLUG PCIE equipment is as follows: after the CPU of the main board is transmitted to the 9555 chip through the VPP signal and analyzed into PWREN, the PWREN signal is directly transmitted to the CPLD to control the power-on of the PCIE equipment VR, and when the PWREN signal is unstable, abnormal power-off of the PCIE equipment can be caused, so that the PCIE equipment cannot be identified normally. Therefore, the influence caused by the instability of the PWREN signal needs to be solved, namely, the influence caused by the instability of the PWREN signal is eliminated by controlling whether the PWREN signal is effective or not by the CPLD in the power-on process of the tape card.
And setting a logic buffer between the CPLD and the chip, and controlling the logic buffer through the CPLD. In the prior art, a logic buffer is newly added between the 9555 chip and the CPLD, and the CPLD is used for controlling the on and off of the logic buffer so as to control whether the PWREN signal takes effect.
And responding to the first card startup of the server, confirming that PCIE equipment is in place, and controlling the hot plug slot to be normally powered on.
In some embodiments, the confirming that the PCIE device is in place includes: and disabling the logic buffer enable signal through the CPLD, enabling the power supply enable signal to be inactive, and detecting that the preset signal is low level to confirm that the PCIE equipment is in place. When the server is started with the card for the first time, the CPLD can disable the BUFFER_EN (Logic BUFFER enable) signal, the Logic BUFFER is disconnected, PWREN is not in effect, at the moment, the CPLD detects the preset signal PRSNT2# (detects that PCIE equipment is in-place signal, high level is not in place, low level is in place), namely, confirms that the PCIE equipment is in place, and controls HOT-PLUG slot to be powered on normally.
In some embodiments, the controlling the normal powering up of the hot plug slots includes: and in response to identifying the PCIE device, enabling the logic buffer enabling signal through the CPLD and enabling a power supply signal. After the PCIE device is normally identified, the CPLD enables the buffer_en signal after the PWREN signal stabilizes, and the PWREN signal is asserted.
And in response to the hot plug of the PCIE equipment, the CPLD controls the logic buffer to be turned on or turned off so as to control the power on and power off of the PCIE equipment.
In some embodiments, the controlling, by the CPLD, the logic buffer to be turned on or turned off to control powering up and powering down of the PCIE device includes: and notifying the hot-unplugged information to the mainboard through the CPLD to remove the resources of the unplugged PCIE device, or notifying the hot-plugged information to the mainboard through the CPLD to increase the resources of the plugged PCIE device.
In some embodiments, the controlling, by the CPLD, the logic buffer to be turned on or turned off to control powering up and powering down of the PCIE device includes: starting the logic buffer through the CPLD, and outputting a low-level power supply signal to control the PCIE equipment to be powered down; or the logic buffer is turned off through the CPLD, and a high-level power supply signal is output to control the PCIE equipment to be powered on.
When the PCIE device is hot plugged, the CPLD informs the system of hot plug information, and the system firstly removes bus resources, memory resources and the like owned by the PCIE device, so that no flow is ensured to access the PCIE device. Because the PWREN signal is stable in this process, the CPLD turns on the Logic buffer, and outputs a pwren_l (low level power supply) signal to the CPLD, and the CPLD further controls the power-down operation of the PCIE device by determining the Logic level of the pwren_l, and the hot plug flow is opposite to the hot plug.
And responding to the starting of the server without the card, starting the logic buffer through the CPLD, and keeping the PCIE slot in a non-power-on state.
In some embodiments, the maintaining the PCIE slot in the unpowered state includes: and detecting whether the prediction signal is at a high level by the CPLD, and controlling the PCIE slot to be in a non-power-on state in response to the CPLD detecting that the prediction signal is at the high level.
When the machine is started without a card, the CPLD can enable BUFFER_EN, namely the Logic BUFFER is started; however, the CPLD detects that the prsnt2# signal is not asserted when the CPLD is asserted, and the CPLD does not control the PCIE slot to power up, so the PWREN will not affect the power up timing even if the signal is unstable during power up.
In some embodiments, the method further comprises: and in response to the completion of power-on, performing hot plug, pulling down a prediction signal to detect that the PCIE device is in place. When the power-on is started, the PWREN signal is stable, and when hot plug is carried out, PRSNT2# is pulled down, PCIE equipment is detected to be in place, and hot plug operation can be normally carried out.
It should be noted that, in the above embodiments of the method for solving the problem that the PCIE hot-plug slot cannot identify a device, the steps may be intersected, replaced, added, and deleted, so that the method for solving the problem that the PCIE hot-plug slot cannot identify a device by using the reasonable permutation and combination transformation should also belong to the protection scope of the present invention, and the protection scope of the present invention should not be limited to the embodiments.
Based on the above objective, a second aspect of the embodiments of the present invention provides a system for solving the problem that PCIE hot plug slots cannot identify devices. As shown in fig. 2, the system 200 includes the following modules: the setting module is configured to set a logic buffer between the CPLD and the chip and control the logic buffer through the CPLD; the control module is configured to respond to the first card startup of the server, confirm that PCIE equipment is in place and control the normal power-on of the hot plug slot; the plug-in module is configured to respond to the hot plug of the PCIE equipment and control the logic buffer to be opened or closed through the CPLD so as to control the power on and power off of the PCIE equipment; and the holding module is configured to respond to the starting of the server without a card, start the logic buffer through the CPLD and keep the PCIE slot in a non-power-on state.
In some embodiments, the control module is configured to: and disabling the logic buffer enable signal through the CPLD, enabling the power supply enable signal to be inactive, and detecting that the preset signal is low level to confirm that the PCIE equipment is in place.
In some embodiments, the control module is configured to: and in response to identifying the PCIE device, enabling the logic buffer enabling signal through the CPLD and enabling a power supply signal.
In some embodiments, the plug module is configured to: and notifying the hot-unplugged information to the mainboard through the CPLD to remove the resources of the unplugged PCIE device, or notifying the hot-plugged information to the mainboard through the CPLD to increase the resources of the plugged PCIE device.
In some embodiments, the plug module is configured to: starting the logic buffer through the CPLD, and outputting a low-level power supply signal to control the PCIE equipment to be powered down; or the logic buffer is turned off through the CPLD, and a high-level power supply signal is output to control the PCIE equipment to be powered on.
In some embodiments, the retention module is configured to: and detecting whether the prediction signal is at a high level by the CPLD, and controlling the PCIE slot to be in a non-power-on state in response to the CPLD detecting that the prediction signal is at the high level.
In some embodiments, the system further comprises a detection module configured to: and in response to the completion of power-on, performing hot plug, pulling down a prediction signal to detect that the PCIE device is in place.
In view of the above object, a third aspect of the embodiments of the present invention provides a computer device, including: at least one processor; and a memory storing computer instructions executable on the processor, the instructions being executable by the processor to perform the steps of: s1, setting a logic buffer between a CPLD and a chip, and controlling the logic buffer through the CPLD; s2, responding to the first card starting of the server, confirming that PCIE equipment is in place, and controlling the hot plug slot to be normally powered on;
s3, in response to performing hot plug of the PCIE equipment, the logic buffer is controlled to be opened or closed through the CPLD so as to control power on and power off of the PCIE equipment; and S4, responding to the starting of the server without the card, starting the logic buffer through the CPLD, and keeping the PCIE slot in a non-power-on state.
In some embodiments, the confirming that the PCIE device is in place includes: and disabling the logic buffer enable signal through the CPLD, enabling the power supply enable signal to be inactive, and detecting that the preset signal is low level to confirm that the PCIE equipment is in place.
In some embodiments, the controlling the normal powering up of the hot plug slots includes: and in response to identifying the PCIE device, enabling the logic buffer enabling signal through the CPLD and enabling a power supply signal.
In some embodiments, the controlling, by the CPLD, the logic buffer to be turned on or turned off to control powering up and powering down of the PCIE device includes: and notifying the hot-unplugged information to the mainboard through the CPLD to remove the resources of the unplugged PCIE device, or notifying the hot-plugged information to the mainboard through the CPLD to increase the resources of the plugged PCIE device.
In some embodiments, the controlling, by the CPLD, the logic buffer to be turned on or turned off to control powering up and powering down of the PCIE device includes: starting the logic buffer through the CPLD, and outputting a low-level power supply signal to control the PCIE equipment to be powered down; or the logic buffer is turned off through the CPLD, and a high-level power supply signal is output to control the PCIE equipment to be powered on.
In some embodiments, the maintaining the PCIE slot in the unpowered state includes: and detecting whether the prediction signal is at a high level by the CPLD, and controlling the PCIE slot to be in a non-power-on state in response to the CPLD detecting that the prediction signal is at the high level.
In some embodiments, the steps further comprise: and in response to the completion of power-on, performing hot plug, pulling down a prediction signal to detect that the PCIE device is in place.
Fig. 3 is a schematic hardware structure of an embodiment of a computer device for solving the problem that PCIE hot plug slot cannot identify devices according to the present invention.
Taking the example of the device shown in fig. 3, a processor 301 and a memory 302 are included in the device.
The processor 301 and the memory 302 may be connected by a bus or otherwise, for example in fig. 3.
The memory 302 is used as a non-volatile computer readable storage medium, and may be used to store a non-volatile software program, a non-volatile computer executable program, and a module, such as a program instruction/module corresponding to a method for solving the problem that PCIE hot plug slot cannot identify a device in the embodiment of the present application. The processor 301 executes the nonvolatile software programs, instructions and modules stored in the memory 302, thereby executing various functional applications and data processing of the server, that is, implementing a method for solving the problem that PCIE hot plug slots cannot identify devices.
Memory 302 may include a storage program area that may store an operating system, at least one application program required for functionality, and a storage data area; the store data area may store data created according to the use of a method of resolving PCIE hot plug slots failing to identify devices, etc. In addition, memory 302 may include high-speed random access memory, and may also include non-volatile memory, such as at least one magnetic disk storage device, flash memory device, or other non-volatile solid-state storage device. In some embodiments, memory 302 may optionally include memory located remotely from processor 301, which may be connected to the local module via a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.
One or more computer instructions 303 corresponding to a method for resolving a PCIE hot plug slot failure to identify a device are stored in the memory 302, and when executed by the processor 301, perform the method for resolving a PCIE hot plug slot failure to identify a device in any of the method embodiments described above.
Any embodiment of the computer equipment for executing the method for solving the problem that the PCIE hot plug slot position can not identify the equipment can achieve the same or similar effect as the corresponding any embodiment of the method.
The invention also provides a computer readable storage medium storing a computer program which when executed by a processor performs a method for solving the problem that a PCIE hot plug slot cannot identify equipment.
Fig. 4 is a schematic diagram of an embodiment of a computer storage medium for solving the problem that PCIE hot plug slot cannot identify devices according to the present invention. Taking a computer storage medium as shown in fig. 4 as an example, the computer readable storage medium 401 stores a computer program 402 that when executed by a processor performs the above method.
Finally, it should be noted that, as one of ordinary skill in the art can understand that implementing all or part of the above-mentioned embodiments of the method may be implemented by instructing related hardware by a computer program, and the program for implementing the method for solving the problem that PCIE hot-plug slot cannot identify a device may be stored in a computer readable storage medium, where the program may include the steps of the embodiments of the methods when executed. The storage medium of the program may be a magnetic disk, an optical disk, a read-only memory (ROM), a random-access memory (RAM), or the like. The computer program embodiments described above may achieve the same or similar effects as any of the method embodiments described above.
The foregoing is an exemplary embodiment of the present disclosure, but it should be noted that various changes and modifications could be made herein without departing from the scope of the disclosure as defined by the appended claims. The functions, steps and/or actions of the method claims in accordance with the disclosed embodiments described herein need not be performed in any particular order. Furthermore, although elements of the disclosed embodiments may be described or claimed in the singular, the plural is contemplated unless limitation to the singular is explicitly stated.
It should be understood that as used herein, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly supports the exception. It should also be understood that "and/or" as used herein is meant to include any and all possible combinations of one or more of the associated listed items.
The foregoing embodiment of the present invention has been disclosed with reference to the number of embodiments for the purpose of description only, and does not represent the advantages or disadvantages of the embodiments.
It will be understood by those skilled in the art that all or part of the steps for implementing the above embodiments may be implemented by hardware, or may be implemented by a program for instructing relevant hardware, and the program may be stored in a computer readable storage medium, where the storage medium may be a read-only memory, a magnetic disk or an optical disk, etc.
Those of ordinary skill in the art will appreciate that: the above discussion of any embodiment is merely exemplary and is not intended to imply that the scope of the disclosure of embodiments of the invention, including the claims, is limited to such examples; combinations of features of the above embodiments or in different embodiments are also possible within the idea of an embodiment of the invention, and many other variations of the different aspects of the embodiments of the invention as described above exist, which are not provided in detail for the sake of brevity. Therefore, any omission, modification, equivalent replacement, improvement, etc. of the embodiments should be included in the protection scope of the embodiments of the present invention.

Claims (9)

1. The method for solving the problem that the PCIE hot plug slot position cannot identify the equipment is characterized by comprising the following steps:
setting a logic buffer between a CPLD and a chip, and controlling the logic buffer through the CPLD;
the method comprises the steps of responding to the first card starting of a server, confirming that PCIE equipment is in place, and controlling a hot plug slot to be normally powered on;
in response to performing the hot plug of the PCIE equipment, the logic buffer is controlled to be turned on or turned off by the CPLD so as to control the power on and power off of the PCIE equipment; and
responding to the starting of the server without a card, starting the logic buffer through the CPLD, keeping the PCIE slot in a non-power-on state,
the controlling, by the CPLD, the logic buffer to be turned on or turned off to control power on or power off of the PCIE device includes:
starting the logic buffer through the CPLD, and outputting a low-level power supply signal to control the PCIE equipment to be powered down; or alternatively
And turning off the logic buffer through the CPLD and outputting a high-level power supply signal to control the PCIE equipment to be powered on.
2. The method of claim 1, wherein the confirming that a PCIE device is in place comprises:
and disabling the logic buffer enable signal through the CPLD, enabling the power supply enable signal to be inactive, and detecting that the preset signal is low level to confirm that the PCIE equipment is in place.
3. The method of claim 1, wherein controlling the normal powering up of the hot plug slots comprises:
and in response to identifying the PCIE device, enabling the logic buffer enabling signal through the CPLD and enabling a power supply signal.
4. The method of claim 1, wherein controlling the logic buffer to be turned on or off by the CPLD to control powering up and powering down of the PCIE device comprises:
and notifying the hot-unplugged information to the mainboard through the CPLD to remove the resources of the unplugged PCIE device, or notifying the hot-plugged information to the mainboard through the CPLD to increase the resources of the plugged PCIE device.
5. The method of claim 1, wherein the maintaining the PCIE slot in the unpowered state comprises:
and detecting whether the prediction signal is at a high level by the CPLD, and controlling the PCIE slot to be in a non-power-on state in response to the CPLD detecting that the prediction signal is at the high level.
6. The method according to claim 1, wherein the method further comprises:
and in response to the completion of power-on, performing hot plug, pulling down a prediction signal to detect that the PCIE device is in place.
7. A system for resolving a PCIE hot plug slot failure to identify a device, comprising:
the setting module is configured to set a logic buffer between the CPLD and the chip and control the logic buffer through the CPLD;
the control module is configured to respond to the first card startup of the server, confirm that PCIE equipment is in place and control the normal power-on of the hot plug slot;
the plug-in module is configured to respond to the hot plug of the PCIE equipment and control the logic buffer to be opened or closed through the CPLD so as to control the power on and power off of the PCIE equipment; and
a holding module configured to respond to the startup of the server without a card, start the logic buffer through the CPLD, and hold the PCIE slot in a non-powered state,
the plug module is further configured to:
starting the logic buffer through the CPLD, and outputting a low-level power supply signal to control the PCIE equipment to be powered down; or alternatively
And turning off the logic buffer through the CPLD and outputting a high-level power supply signal to control the PCIE equipment to be powered on.
8. A computer device, comprising:
at least one processor; and
a memory storing computer instructions executable on the processor, which when executed by the processor, perform the steps of the method of any one of claims 1-6.
9. A computer readable storage medium storing a computer program, characterized in that the computer program when executed by a processor implements the steps of the method of any one of claims 1-6.
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107203448A (en) * 2017-05-24 2017-09-26 郑州云海信息技术有限公司 A kind of method and system of test PCIe switch chip violence warm connection functions
CN108519955A (en) * 2018-04-13 2018-09-11 郑州云海信息技术有限公司 A kind of plug method and system of hot plug module and a kind of PCIe interface
CN109388604A (en) * 2018-11-01 2019-02-26 郑州云海信息技术有限公司 A kind of hot plug control method based on PCIe, device and storage medium
CN112825011A (en) * 2019-11-20 2021-05-21 中兴通讯股份有限公司 Power-on and power-off control method and system of PCIe device

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111143898B (en) * 2018-11-05 2022-06-14 瑞昱半导体股份有限公司 Data protection method for pluggable memory device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107203448A (en) * 2017-05-24 2017-09-26 郑州云海信息技术有限公司 A kind of method and system of test PCIe switch chip violence warm connection functions
CN108519955A (en) * 2018-04-13 2018-09-11 郑州云海信息技术有限公司 A kind of plug method and system of hot plug module and a kind of PCIe interface
CN109388604A (en) * 2018-11-01 2019-02-26 郑州云海信息技术有限公司 A kind of hot plug control method based on PCIe, device and storage medium
CN112825011A (en) * 2019-11-20 2021-05-21 中兴通讯股份有限公司 Power-on and power-off control method and system of PCIe device

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