CN114916141B - Sunken circuit board manufacturing method and circuit board - Google Patents
Sunken circuit board manufacturing method and circuit board Download PDFInfo
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- CN114916141B CN114916141B CN202210593585.7A CN202210593585A CN114916141B CN 114916141 B CN114916141 B CN 114916141B CN 202210593585 A CN202210593585 A CN 202210593585A CN 114916141 B CN114916141 B CN 114916141B
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
- H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/05—Patterning and lithography; Masks; Details of resist
- H05K2203/0502—Patterning and lithography
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- Microelectronics & Electronic Packaging (AREA)
- Manufacturing Of Printed Circuit Boards (AREA)
Abstract
The invention relates to a manufacturing method of a sunken circuit board, wherein the circuit board comprises a first circuit formed on a board surface, a second circuit formed on a groove bottom and a third circuit formed on a groove wall, one end of the third circuit is connected with the first circuit, and the other end of the third circuit is connected with the second circuit, and the manufacturing method is characterized by comprising the following steps: providing a substrate with a groove; depositing copper on the substrate; filling a first wet film on the substrate; exposing and developing the first wet film to etch the groove wall to form the third circuit and etch away other copper layers; and filling a second wet film on the substrate, exposing and developing, and electroplating to form a first circuit and a second circuit. And cleaning the second wet film and the second dry film, so that the time for forming a third circuit by etching and the time for forming a first circuit and a second circuit by electroplating are respectively regulated and controlled, and the precision of the circuits on the groove wall and the groove bottom is simultaneously ensured.
Description
Technical Field
The invention relates to the technical field of circuit board manufacturing, in particular to a circuit board and a manufacturing method thereof.
Background
The circuit board is used as a carrier of the electronic element, and the electronic element needs to occupy a certain thickness when arranged on the circuit board, so that the existing circuit board is also provided with a groove according to the requirement and is embedded in the groove, and a line needs to be formed on the groove wall and the groove bottom. However, in the existing copper deposition process, it is difficult to ensure that the thicknesses of the copper layers on the groove wall and the groove bottom are the same. In addition, in the process of etching the copper layer to form a circuit, the etching precision of the copper layer on the groove wall and the groove bottom is difficult to ensure. Particularly, in the process of forming the groove wall circuit, the spray type etching with less side etching cannot be adopted, only the immersion type etching which easily causes the side etching can be adopted, once the etching time is too long, the side etching is easily caused, and the etching time is too short, so that the short circuit of the circuit is easily caused. Therefore, it is difficult to grasp the etching time, and the accuracy of the line on the groove wall and the groove bottom cannot be ensured at the same time.
Therefore, it is necessary to provide a manufacturing method of a sunken circuit board to ensure the precision of the circuit on the groove wall and the groove bottom.
Disclosure of Invention
The invention aims to provide a manufacturing method of a sunken circuit board, which can simultaneously form a substrate circuit on the surface of a substrate and the bottom of a groove.
The invention provides a manufacturing method of a sunken circuit board, wherein the circuit board comprises a first circuit formed on a board surface, a second circuit formed on a groove bottom and a third circuit formed on a groove wall, one end of the third circuit is connected with the first circuit, and the other end of the third circuit is connected with the second circuit, and the method comprises the following steps:
providing a substrate with a groove;
depositing copper on the substrate, and respectively forming copper layers on the plate surface, the groove wall and the groove bottom;
filling a first wet film on the substrate, covering the groove and the plate surface with the first wet film, and pressing a first dry film on the first wet film;
exposing and developing the first wet film and the first dry film to etch the groove wall to form the third circuit and etch away other copper layers;
cleaning the first wet film and the first dry film, filling a second wet film on the substrate, covering the groove and the plate surface with the second wet film, and pressing the second dry film on the second wet film;
exposing and developing the second wet film and the second dry film, electroplating on the board surface to form a first circuit, and electroplating at the bottom of the groove to form a second circuit;
cleaning the second wet film and the second dry film.
More preferably, the copper layer comprises:
a first copper layer formed on the board surface;
a second copper layer formed on the bottom of the trench;
a third copper layer formed on the trench wall;
the thickness of the first copper layer is recorded as D1, the thickness of the second copper layer is recorded as D2, and the thickness of the third copper layer is recorded as D3, wherein D1= D2; d1 > D3; d2 > D3;
the thickness direction of a third copper layer on the groove wall is marked as a first direction, and the line width direction of the third line is marked as a second direction;
exposing and developing the first wet film and the first dry film to form a plurality of third circuit patterns, wherein the third circuit patterns are used for etching to form a plurality of third circuits, the size of the third circuit patterns in the first direction is recorded as C1, the size of the third circuit patterns in the second direction is recorded as C2, the line width of the third circuits is recorded as D4, and the relation formula is satisfied:
C1＞D3；
C2＞D4。
preferably, the etching rate of the etching solution for etching the copper layer is recorded as V, the time required for the etching solution to finish etching the third copper layer is recorded as T1, the etching solution continues to etch after finishing etching the third copper layer, and the time for finishing etching the first copper layer and the second copper layer is recorded as T2, which satisfies the following relation:
VT1+VT2＝D1＝D2；
VT1＝D3；
C2-D4＝2(VT2)。
more preferably, the line distance of the third line is denoted as D5, and the relationship is satisfied:
C2-D4＜D5。
more preferably, the relation:
C1-D3＝VT1+VT2。
preferably, the second wet film and the second dry film are exposed and developed to form a plurality of first line patterns for forming a plurality of first lines by electroplating and a plurality of second line patterns for forming a plurality of second lines by electroplating,
the second line extends in a first direction of the groove bottom, the size of the groove in the first direction is marked as A1, the size of the second line pattern in the first direction is marked as C3, and the relation is satisfied:
A1-2C1＝C3。
more preferably, the line distance of the second line is denoted as D6, the line distance of the first line is denoted as D7, and the following relation is satisfied:
D5＝D6；
D5＝D7。
preferably, the substrate is formed by laminating at least two substrates, the thickness of any one substrate is recorded as H, the depth of the groove is recorded as U, and the relationship is satisfied: u is more than H.
More preferably, the step of cleaning the second wet film and the dry film further comprises:
performing automatic optical inspection of the substrate;
carrying out solder mask treatment on the substrate;
performing silk filling characters on the substrate;
performing surface gold immersion treatment on the substrate;
performing a flying probe test on the substrate;
and carrying out molding treatment on the substrate.
The invention also provides a circuit board which is manufactured by the circuit board manufacturing method.
The implementation of the embodiment of the invention has the following beneficial effects:
forming a copper layer on the groove wall by copper deposition, filling a first wet film and pressing a first dry film, exposing and developing to etch a third circuit formed on the groove wall, and matching with the design and etching time of a third circuit pattern; and then, a first circuit on the board surface and a second circuit on the groove bottom are electroplated by filling a second wet film and pressing a second dry film, and exposure and development, and the time for forming the first circuit and the second circuit by electroplating is respectively regulated and controlled, so that the effect of simultaneously ensuring the circuit precision on the groove wall and the groove bottom of the circuit board groove is achieved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts.
Fig. 1 is a schematic perspective view of a circuit board according to an embodiment of the invention;
FIG. 2 is a top view of FIG. 1;
FIG. 3 isbase:Sub>A schematic cross-sectional view taken along line A-A of FIG. 1;
FIG. 4 is a schematic illustration of a copper layer formed on a substrate;
fig. 5 is a schematic perspective view illustrating a third circuit pattern formed on the first wet film and the first dry film;
FIG. 6 is a top view of FIG. 5;
fig. 7 is a schematic perspective view illustrating a first line pattern and a second line pattern formed on a second wet film and a second dry film;
FIG. 8 is a top view of FIG. 7;
fig. 9 is a schematic view of a three-dimensional structure of the circuit board obtained after the second wet film and the second dry film are cleaned;
FIG. 10 is a schematic view of a process for depositing copper on a substrate;
FIG. 11 is a schematic view of a process for filling a first wet film and pressing a first dry film;
fig. 12 is a schematic view of a process of forming a third circuit pattern on the first wet film and the first dry film by exposure and development;
FIG. 13 is a schematic diagram of a process for forming a third circuit based on the third circuit pattern;
FIG. 14 is a schematic view showing a process for filling a second wet film and pressing a second dry film;
fig. 15 is a schematic view of a process of forming a first circuit pattern and a second circuit pattern on the second wet film and the second dry film by exposure and development;
FIG. 16 is a schematic diagram of a flow structure for etching a first line and a second line based on a first line pattern and a second line pattern;
fig. 17 is a schematic view of a flow structure of a formed circuit board.
The reference numbers illustrate: 100. a circuit board; 110. plate surface; 10. a first line; 310. the bottom of the tank; 20. a second line; 320. a trench wall; 30. a third line; 300. a groove; 120. a substrate; 121. a single-layer substrate; 400. a copper layer; 510. a first wet film; 520. a first dry film; 530. a second wet film; 540. a second dry film; 410. a first copper layer; 420. a second copper layer; 430. a third copper layer; 431. a first front side; 432. a first side surface; 630. a third line pattern; 610. a first line pattern; 620. a second line pattern; f1, a first direction; f2, a second direction; f3, a third direction; 631. a first part; 632. a second part.
Detailed Description
To facilitate an understanding of the invention, the invention will now be described more fully with reference to the accompanying drawings. Preferred embodiments of the present invention are shown in the drawings. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
It will be understood that when an element is referred to as being "secured to" another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present. The terms "vertical," "horizontal," "left," "right," and the like as used herein are for illustrative purposes only.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
Referring to fig. 1 to 17, an embodiment of the invention provides a method for manufacturing a sunken circuit board 100, where the circuit board 100 includes: a first line 10, a second line 20, a third line 30.
Specifically, the first circuit 10, the second circuit 20, and the third circuit 30 are formed on the substrate 120, the substrate 120 may be understood as a substrate 120 formed by laminating a plurality of single-layer substrates 121 in a conventional sense, and may be any one of three types of single-sided boards, double-sided boards, or multi-layer circuit boards, the substrate 120 in this embodiment is formed by adding a sunken groove 300 to the three types of substrates 120, and the sunken groove 300 may be understood as a sunken accommodating cavity with an upward opening formed by digging out a solid portion on the surface of the substrate 120. To facilitate understanding of those skilled in the art, the present embodiment only illustrates the method for manufacturing the circuit board 100 by way of a single panel.
Specifically, the substrate 120 is formed by laminating at least two substrates 120, the thickness of any substrate 120 is denoted as H, the depth of the groove 300 is denoted as U, and the following relation is satisfied: u > H, to distinguish from the conventional shallow depth of the recess 300, the present embodiment, with the deeper recess 300, can be used to embed larger, more, and more complex electronic components. In this embodiment, the substrate 120 is formed by laminating two substrates 120 having the same thickness, and the thickness of each substrate 120 is H.
Specifically, in an application scenario of the larger-sized circuit board 100, for example, an electronic chip packaged by a BGA is adopted, the electronic chip belongs to an electronic component with a larger volume, and a pin of the chip packaged by the BGA is a spherical pin, and the spherical pin is disposed at the bottom of the packaged chip.
Specifically, in the application scenario of the larger-sized circuit board 100, for example, a chip packaged by a PLCC is adopted, the volume of the chip is larger than that of an electronic component used for embedding in the prior art, and the pins of the chip packaged by the PLCC are inner-buckled pins which can also be used for electrical connection on the side surface of the chip, and the chip packaged by the PLCC can be directly embedded in the groove 300 of the present embodiment, which has a depth larger than the sum of the thicknesses of the plurality of substrates 120, so that the height of the whole circuit board 100 is reduced, and simultaneously, the substrate 120 circuit formed by the groove wall 320 of the groove 300 in the present embodiment can be directly connected with the inner-buckled pins of the chip packaged by the BGA, thereby embedding the chip packaged by the PLCC on the circuit board 100.
Specifically, the first circuit 10 is formed on the plate surface 110, the second circuit 20 is formed on the groove bottom 310, the third circuit 30 is formed on the groove wall 320, one end of the third circuit 30 is connected to the first circuit 10, and the other end of the third circuit 30 is connected to the second circuit 20.
The method in this embodiment comprises the steps of:
s10: providing a substrate 120 formed with a recess 300;
specifically, the groove 300 includes a groove wall 320 and a groove bottom 310, and the groove wall 320 connects the groove bottom 310 of the groove 300 with the plate surface 110 of the substrate 120. The groove bottom 310 refers to the bottom of the groove 300 for supporting the electronic component in the groove 300, the groove bottom 310 is parallel to the plate surface 110 of the substrate 120, and the groove wall 320 refers to the inner side surface of the groove 300 for supporting the side surface of the electronic component.
It should be noted that, in the present embodiment, before the step of digging the groove 300, the two substrates 120 are pressed in advance, so as to avoid deformation of the groove 300 caused by applying a pressing force to the substrates 120 in the pressing process, thereby ensuring the shape and precision of the groove 300.
Specifically, in the present embodiment, the substrate 120 is dug by a conventional drilling and milling method, and the groove 300 is a single-sided board in the present embodiment, referring to fig. 10, the groove 300 is uniformly disposed on the board surface 110 of the substrate 120, that is, the upward surface of the substrate 120 in fig. 10. It can be understood that, in an application scenario where a double-sided board is adopted, the grooves 300 may also be disposed on the upper board surface and the lower board surface of the substrate 120, respectively, in a staggered manner; in the application scenario of the substrate 120 formed by laminating the multilayer circuit board, the depth of the groove 300 can be set to be different depths of the groove 300 according to actual requirements. It is understood that the grooves 300 of the present embodiment may be provided as grooves 300 of different depths.
S20: depositing copper on the substrate 120 to form a copper layer 400 on the plate surface 110, the groove wall 320 and the groove bottom 310;
specifically, a thick copper layer is plated on the surface 110 of the substrate 120 and the bottom 310 and the walls 320 of the recess 300 by a conventional electroless copper plating method to form the copper layer 400.
Specifically, the copper layer 400 includes a first copper layer 410 on the board surface 110, a second copper layer 420 on the groove bottom 310, and a third copper layer 430 on the groove wall 320, in this embodiment, the circuits are respectively formed on the board surface 110 of the substrate 120, the groove bottom 310 of the groove 300, and the groove wall 320 of the groove 300, so that the copper layer 400 should be formed on at least the board surface 110 of the substrate 120, the groove wall 320 of the groove 300, and the groove bottom 310 at the copper deposition stage.
Specifically, the thickness of the first copper layer 410 is denoted as D1, the thickness of the second copper layer 420 is denoted as D2, and the thickness of the third copper layer 430 is denoted as D3, wherein D1= D2 since the copper deposition speed of the board surface 110 and the tank bottom 310 are the same; because the speed of copper deposition on the groove wall 320 is slower than that of the plate surface 110 and the groove bottom 310, D1 is larger than D3, and D2 is larger than D3; this results in the difference between the thickness of the copper layer 400 on the groove wall 320 and the thickness of the copper layer 400 on the groove bottom 310, resulting in the difference between the etching time for etching the copper layer 400 on the groove wall 320 and the etching time for etching the copper layer 400 on the groove bottom 310, and it is difficult to ensure the accuracy of the third and second circuits 30 and 20 and the first circuit 10 at the same time.
S30: filling a first wet film 510 on the substrate 120, wherein the first wet film 510 covers the groove 300 and the plate surface 110, and pressing a first dry film 520 on the first wet film 510;
specifically, the first wet film 510 is filled on the board surface 110 of the substrate 120, so that the first wet film 510 completely covers the groove 300 and the board surface 110 of the substrate 120. The first wet film 510 is relative to the first dry film 520, the first wet film 510 in this embodiment is an exposure ink, the exposure ink is a conventional exposure ink in the art, the first wet film 510 can be tightly combined with the board surface 110 of the substrate 120, especially with the groove bottom 310 and the groove wall 320 of the groove 300, by utilizing the good filling property of the first wet film 510, and the first wet film 510 is higher than the surface of the substrate 120 after filling, so that the wet film after pattern transfer can be directly used for etching the circuit of the substrate 120 forming the groove bottom 310, the groove wall 320 and the board surface 110 of the substrate 120.
Specifically, since the first wet film 510 is coated with ink, in order to avoid the decrease of the circuit precision caused by the uneven thickness of the first wet film 510 during the coating process, the first wet film 510 is dried after the substrate 120 is filled with the first wet film 510, and then the first dry film 520 is pressed on the first wet film 510, so that the circuit forming precision is improved by utilizing the excellent flatness of the first dry film 520.
S40: exposing and developing the first wet film 510 and the first dry film 520 to etch the third wiring 30 at the trench wall 320 and etch away the other copper layer 400;
specifically, the designed third line pattern 30 is transferred onto the first wet film 510 and the first dry film 520 by a pattern transfer technique. The present embodiment employs a pattern transfer technique that is conventional in the art, and sets regions corresponding to the third line patterns 30 on the first wet film 510 and the first dry film 520 to regions that block etching by the etching solution through negative exposure, thereby forming the third lines 30 in the regions corresponding to the third line patterns 30 after a subsequent etching process.
Specifically, the first wet film 510 and the first dry film 520 are exposed and developed to form a plurality of third line patterns 30, and the plurality of third line patterns 30 are used to etch the plurality of third lines 30.
The thickness direction of the third copper layer 430 on the trench wall 320 is denoted as a first direction F1, and the line width direction of the third circuit 30 is denoted as a second direction F2; the depth direction of the groove 300 is denoted as a third direction F3.
A dimension of the third line pattern 30 in the first direction F1 is denoted as C1, a dimension of the third line pattern 30 in the second direction F2 is denoted as C2, a line width of the third line 30 is denoted as D4, and a thickness D3 of the third copper layer 430 is equal to a thickness of the third line 30, which satisfy the relation:
C1＞D3；
C2＞D4。
by setting the dimension C1 of the third circuit pattern 30 in the first direction F1 to be greater than the thickness D3 of the third copper layer 430, the etching solution will only etch away the other third copper layer 430 during the etching process for forming the third circuit pattern 30, and will not etch the portion of the third copper layer 430 where the third circuit pattern 30 is to be formed. Referring to fig. 12, since the dimension C1 of the third circuit pattern 30 in the first direction F1 is set to be greater than the thickness D3 of the third copper layer 430, the etching solution does not laterally contact the third copper layer 430 in fig. 12, thereby leaving the third copper layer 430 to form the third circuit 30.
It should be noted that, since the dimension C1 of the third circuit pattern 30 in the first direction F1 is set to be larger than the thickness D3 of the third copper layer 430, the etching solution will also cover a portion of the second copper layer 420 of the groove bottom 310 with a portion of C1 > D3 during the process of forming the third circuit pattern 30, which results in etching a small portion of the second circuit pattern 20 during the process of forming the third circuit pattern 30 by etching, and therefore, the second circuit pattern 20 that has been formed needs to be considered in the design level during the subsequent process of forming the second circuit pattern.
Specifically, in this step, the etching solution etches all the copper layers 400 including the first copper layer 410, the second copper layer 420 and the third copper layer 430 except the third wires 30 on the trench walls 320 and the small portion of the second wires 20.
In one embodiment, in order to avoid over-etching the third circuit 30 along the second direction F2 by the etching solution, the rate at which the etching solution etches the copper layer 400 is denoted as V, the time required for the etching solution to finish etching the third copper layer 430 is denoted as T1, the etching solution continues to etch after finishing etching the third copper layer 430, and the time for finishing etching the first copper layer 410 and the second copper layer 420 is denoted as T2, which satisfies the following relation:
VT1+VT2＝D1＝D2；
VT1＝D3；
wherein the content of the first and second substances,
C2-D4＝2(VT2)，
therefore, during the process of etching to form the third circuit 30, the etching solution will only etch away the other third copper layer 430, and will not etch the portion of the third copper layer 430 where the third circuit 30 is to be formed. Referring to fig. 5 and 6, when the etching solution finishes etching the first copper layer 410 and the second copper layer 420, the etching solution etches the excess third copper layer 430 from both sides of the third circuit 30, respectively, and only the portion of the third circuit 30 remains when the above relationship is satisfied.
Specifically, in the etching process, the etching solution contacts the first copper layer 410, the second copper layer 420, and the third copper layer 430, which need to be etched away, through the first dry film 520 and the third circuit pattern 30 on the first wet film 510.
Wherein the etching solution etches the third copper layer 430 along the first direction F1, i.e., the third copper layer 430 is etched away along the horizontal direction in fig. 3. Meanwhile, the etching solution etches away the first and second copper layers 410 and 420 in the third direction F3, that is, the first and second copper layers 410 and 420 in the vertical direction in fig. 3, and since the thicknesses of the first and second copper layers 410 and 420 are greater than that of the third copper layer 430, the time required for the etching solution to etch away the first and second copper layers 410 and 420 is greater than that of the etching solution to etch away the third copper layer 430.
The time required for the etching solution to etch the first copper layer 410 and the second copper layer 420 is denoted as T, the time required for the etching solution to etch the third copper layer 430 is denoted as T1, the etching solution continues to etch after the etching solution finishes etching the third copper layer 430, and the time required for the etching to finish the first copper layer 410 and the second copper layer 420 is denoted as (T-T1) and denoted as T2.
Specifically, during the etching process, when the time point is at T1, the portion of the third copper layer 430 that needs to be etched away along the first direction F1 is completely etched by the etching solution, and the side surface of the third copper layer 430, i.e., the side surface of the portion of the third copper layer 430 corresponding to the third circuit 30 is exposed, and the etching solution is in contact with the side surface of the third copper layer 430, so that after the time point T1, i.e., during the time period T2, the etching solution etches the side surface of the third copper layer 430 along the second direction F2, see fig. 6.
Further, in order to realize the two-stage etching of T1 and T2 to form the third line 30, the third line pattern 630 includes a first portion 631 and a second portion 632.
Specifically, referring to fig. 6, the first portion 631 is disposed on a side of the third copper layer 430 away from the slot wall 320, referring to fig. 12, the first portion 631 extends into the groove 300 from a side of the first dry film 520 away from the substrate 120 and contacts with a side of the third copper layer 430 away from the slot wall 320, and a portion of the third copper layer 430 contacting with the first portion 631 corresponds to the third circuit 30. During etching, the first portion 631 protects the portion of the third copper layer 430 in contact therewith from the etching solution. That is, during the etching process at the stage T1, the portion of the third copper layer 430 in contact with the first portion 631 is not etched by the etching solution.
Specifically, referring to fig. 6, the second portion 632 is disposed on two sides of the third circuit 30, and more specifically, referring to fig. 12, the second portion 632 extends from a side of the first dry film 520 away from the substrate 120 to above the third copper layer 430 and contacts with the top of the third copper layer 430, so as to prevent the portion of the third copper layer 430 contacting with the second portion from being etched by the etching solution from above. That is, during the etching process in the stage T1, the first portion 631 prevents the portion of the third copper layer 430 corresponding to the third wire 30 from being etched in the first direction F1 in fig. 12, and the second portion 632 prevents the portion of the third copper layer 430 corresponding to the third wire 30 from being etched in the third direction F3 in fig. 12.
Specifically, in the etching at stage T1, referring to fig. 6, in the present embodiment, two adjacent third lines 30 are designed and formed on one trench wall 320, and each third line 30 corresponds to one third line pattern 630. In the etching at the stage T1, the etching solution etches away the third copper layer 430 between the two third circuit patterns 630, and etches away the third copper layer 430 between the two third circuit patterns 630 and the left and right groove walls in fig. 6. Wherein the first portion 631 protects the third copper layer 430 in contact therewith from etching from the first direction F1, see fig. 12, and the second portion 632 protects the third copper layer 430 in contact therewith from etching from the third direction F3. In the T1 stage, the third copper layer 430 between and on both sides of the two third line patterns 630 is etched away, so that the side surface of the third copper layer 430, i.e., the surface of the third copper layer 430 under the second portion 632, which is in contact with the etching liquid, is exposed. The surface of the third copper layer 430 corresponding to the third line 30, which is in contact with the first portion 631, is referred to as a first front surface 431, and the side surface of the third copper layer 430 exposed at the stage T1 is referred to as a first side surface 432.
Specifically, in the T2 phase, referring to fig. 12, since the second portion 632 is located above the third copper layer 430, when the side surface of the third copper layer 430 is exposed and contacts with the etching solution, the second portion 632 cannot function to protect the third copper layer 430, so that the etching solution etches the third copper layer 430 of the first side surface 432 along the second direction F2 in fig. 6, and the first portion 631 still functions to protect the first front surface 431, therefore, in the T2 phase, the etching amount of the etching solution to the third copper layer 430 is equivalent to VT2, and since the etching solution etches the third traces 30 from both sides simultaneously, the etching amount is equivalent to 2 (VT 2) for each third trace 30, so that an amount of 2 (VT 2) needs to be reserved for etching by the etching solution, namely, the size of the third trace pattern 630 in the second direction F2 should satisfy C2-D4=2 (VT 2).
Specifically, in the T1 stage, the etching solution etches the third copper layer 430 from the first direction F1 and the third direction F3 simultaneously, and since the thickness of the third copper layer 430 in the third direction F3 is thicker, the etching solution etches away the third copper layer 430 along the first direction F1 before the etching solution etches through the third copper layer 430 along the third direction F3, and therefore, only the time required for the etching solution to etch the third copper layer 430 along the first direction F1 needs to be considered. In the T2 stage, the etching solution mainly etches the first side surface 432 along the second direction F2, and therefore, only the time required for the etching solution to etch the third copper layer 430 along the second direction F2 needs to be considered. However, due to the inherent characteristics of the etching solution, in the T1 stage, the etching solution etches the third copper layer 430 along the first direction F1 and also causes the undercutting along the second direction F2, but the first side surface 432 is not completely exposed, so the amount of the undercutting is much smaller than that of the etching along the second direction F2 in the second stage, but in order to reduce the influence of the undercutting, in the present embodiment, an etching solution with small undercutting, such as a nitric acid type etching solution, is used.
In one embodiment, in order to avoid short-circuiting two adjacent third lines 30, the relationship is satisfied by taking the line pitch of the third lines 30 as D5:
C2-D4＜D5。
specifically, in the etching process, in order to avoid that two adjacent third circuit patterns 30 are connected in the second direction F2, wherein the two adjacent third circuit patterns 30 correspond to the two connected third circuits 30, and the etching solution cannot etch the portion of the third copper layer 430 between the two third circuits 30, so as to short-circuit the two adjacent third circuits 30, in the present embodiment, the pitch of the third circuits 30 is defined to satisfy the relation: C2-D4 < D5, such that a third copper layer 430, which needs to be etched away by the etching solution, exists between the two adjacent third line patterns 30.
In one embodiment, in order to avoid the etching solution from over-etching the third line 30 along the first direction F1, the following relation is satisfied:
C1-D3＝VT1+VT2。
therefore, during the process of etching to form the third circuit 30, the etching solution will only etch away the other third copper layer 430, and will not etch the portion of the third copper layer 430 where the third circuit 30 is to be formed.
In the present embodiment, the line width D4=8mil =203.2um of the third line 30, where 1mil =0.0254mm =25.4um, the thickness D3=20um of the third line 30, and the line width D4=8mil =203.2um of the third line 30.
S50: cleaning the first wet film 510 and the first dry film 520, filling the second wet film 530 on the substrate 120, the second wet film 530 covering the recess 300 and the board 110, and pressing the second dry film 540 on the second wet film 530;
specifically, the first wet film 510 and the first dry film 520 are cleaned, and the plate surface 110 and the grooves 300 of the substrate 120 are cleaned due to the residues generated by the etching process in S40, resulting in the substrate 120 having the third lines 30 formed on the groove walls 320.
Specifically, the second wet film 530 is filled on the board surface 110 of the substrate 120, so that the second wet film 530 completely covers the groove 300 and the board surface 110 of the substrate 120, and particularly covers the third circuit 30. The second wet film 530 is an exposure ink, the exposure ink is a conventional exposure ink in the art, the second wet film 530 has good filling property, so that the second wet film 530 can be tightly combined with the board surface 110 of the substrate 120, especially with the groove bottom 310 and the groove walls 320 of the groove 300, and the second wet film 530 is higher than the surface of the substrate 120 after filling, so that the pattern-transferred wet film can be directly used for etching the circuit of the substrate 120 forming the groove bottom 310, the groove walls 320 and the board surface 110 of the substrate 120.
Specifically, since the second wet film 530 is coated with ink, in order to avoid the reduction of the circuit precision caused by uneven thickness when the second wet film 530 is coated, the second wet film 530 is dried after the substrate 120 is filled with the second wet film 530, and then the second dry film 540 is pressed on the second wet film 530, so that the circuit forming precision is improved by using the excellent flatness of the second dry film 540. Since the second wet film 530 is used to cover the third circuit 30, the second wet film 530 plays a role in protecting the third circuit 30 during the process of pressing the second dry film 540, so as to prevent the acting force from directly acting on the third circuit 30 during the pressing process, thereby ensuring the integrity of the third circuit 30.
S60: exposing and developing the second wet film 530 and the second dry film 540, and electroplating on the board surface 110 to form a first circuit 10, and electroplating on the groove bottom 310 to form a second circuit 20;
specifically, the designed first and second line patterns 10 and 20 are transferred onto the second wet film 530 and the second dry film 540 by a pattern transfer technique. The present embodiment employs a pattern transfer technique that is conventional in the art, and sets the areas corresponding to the first and second wirings 10 and 20 on the wet film as areas that allow plating by positive exposure, thereby forming the first and second wirings 10 and 20 on the areas corresponding to the first and second wiring patterns 10 and 20, respectively, after a subsequent plating process.
Specifically, the second wet film 530 and the second dry film 540 are exposed and developed to form a plurality of first line patterns 10 and a plurality of second line patterns 20, the plurality of first line patterns 10 are used for electroplating to form a plurality of first lines 10, the plurality of second line patterns 20 are used for electroplating to form a plurality of second lines 20,
in one embodiment, in order to avoid the second lines 20 of the groove bottom 310 from being disconnected from the third lines 30 of the groove wall 320, especially in the case where a small portion of the second lines 20 is formed at the groove bottom 310 at the same time in the process of forming the third lines 30, the second lines 20 are arranged to extend in the first direction F1 at the groove bottom 310, and the dimension of the groove 300 in the first direction F1 is denoted as A1, and the dimension of the second line pattern 20 in the first direction F1 is denoted as C3, so that the relationship:
A1-2C1＝C3。
thereby, the second wiring 20 formed by electroplating is connected to the third wiring 30.
In one embodiment, in order to improve the connection accuracy between the first line 10 and the third line 30 and the connection accuracy between the second line 20 and the third line 30, the pitch of the second line 20 is denoted as D6, the pitch of the first line 10 is denoted as D7, and the following relation is satisfied:
D5＝D6；
D5＝D7。
specifically, since a small portion of the second wires 20 connected to the third wires 30 has been formed at the groove bottom 310 during the etching process to form the third wires 30, in order to improve the accuracy of the connection of the second wires 20 to the third wires 30, the pitch of the second wires 20 is set to be equal to the pitch of the third wires 30 to engage the second wires 20 with the third wires 30 when the second wires 20 are formed by plating. Meanwhile, since the third circuit 30 extends on the groove wall 320 along the third direction F3, that is, in a direction vertically downward in fig. 3, the groove wall 320 extends, in order to make the third circuit 30 and the first circuit 10 more accurately connected, the pitch of the first circuit 10 is set to be equal to the pitch of the third circuit 30, so as to improve the connection accuracy between the first circuit 10 and the third circuit 30.
S70: the second wet film 530 and the second dry film 540 are cleaned.
Specifically, after the second and third wirings 20 and 30 are formed, the second wet film 530 and the second dry film 540 are cleaned.
Specifically, the method further includes the steps of, after cleaning the second wet film 530 and the second dry film 540:
s81: performing automated optical inspection of the substrate 120;
s82: performing solder mask processing on the substrate 120;
s83: silk-filling characters into the substrate 120;
s84: performing surface gold immersion treatment on the substrate 120;
s85: performing a flying probe test on the substrate 120;
s86: the substrate 120 is subjected to a molding process.
The present embodiment further provides a circuit board 100, and the circuit board 100 is manufactured by the circuit board 100 manufacturing method.
Thereby, a copper layer 400 is formed on the trench wall 320 by copper deposition, and the third circuit 30 formed on the trench wall 320 is etched by filling the first wet film 510 and pressing the first dry film 520, and exposing and developing; the first circuit 10 on the board surface 110 and the second circuit 20 on the tank bottom 310 are electroplated by filling the second graphite and pressing the second dry film 540, and exposing and developing, so as to respectively regulate and control the time for forming the third circuit 30 by etching and the time for forming the first circuit 10 and the second circuit 20 by electroplating, thereby simultaneously ensuring the precision of the circuits on the tank wall 320 and the tank bottom 310.
The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the claims. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (10)
1. A method for manufacturing a sunken circuit board, wherein the circuit board comprises a first circuit formed on a board surface, a second circuit formed on the bottom of a groove and a third circuit formed on the groove wall, one end of the third circuit is connected with the first circuit, and the other end of the third circuit is connected with the second circuit, the method is characterized by comprising the following steps:
providing a substrate with a groove;
depositing copper on the substrate, and respectively forming copper layers on the plate surface, the groove wall and the groove bottom;
filling a first wet film on the substrate, covering the groove and the plate surface with the first wet film, and pressing a first dry film on the first wet film;
exposing and developing the first wet film and the first dry film to etch the groove wall to form the third circuit and etch away other copper layers;
cleaning the first wet film and the first dry film, filling a second wet film in the substrate, covering the groove and the plate surface with the second wet film, and pressing the second dry film on the second wet film;
exposing and developing the second wet film and the second dry film, electroplating on the board surface to form a first circuit, and electroplating at the bottom of the groove to form a second circuit;
cleaning the second wet film and the second dry film.
2. The method of claim 1, wherein the copper layer comprises:
a first copper layer formed on the board surface;
a second copper layer formed on the bottom of the trench;
a third copper layer formed on the trench wall;
the thickness of the first copper layer is recorded as D1, the thickness of the second copper layer is recorded as D2, and the thickness of the third copper layer is recorded as D3, wherein D1= D2; d1 > D3; d2 > D3;
the thickness direction of a third copper layer on the groove wall is marked as a first direction, and the line width direction of the third line is marked as a second direction;
exposing and developing the first wet film and the first dry film to form a plurality of third circuit patterns, wherein the third circuit patterns are used for etching to form a plurality of third circuits, the size of the third circuit patterns in the first direction is recorded as C1, the size of the third circuit patterns in the second direction is recorded as C2, the line width of the third circuits is recorded as D4, and the relation formula is satisfied:
C1＞D3；
C2＞D4。
3. the method for manufacturing a sunken circuit board according to claim 2, wherein the etching rate of the etching solution to etch the copper layer is denoted as V, the time required for the etching solution to etch the third copper layer is denoted as T1, the etching solution continues to etch the third copper layer after the etching solution finishes etching the third copper layer, and the time to etch the first copper layer and the second copper layer is denoted as T2, which satisfies the relation:
VT1+VT2＝D1＝D2；
VT1＝D3；
C2-D4＝2(VT2)。
4. the method for manufacturing a sunken circuit board according to claim 3, wherein the line pitch of the third line is D5, and satisfies the following relation:
C2-D4＜D5。
5. the method of claim 3, wherein the following relationship is satisfied:
C1-D3＝VT1+VT2。
6. the method of claim 2, wherein the second wet film and the second dry film are exposed and developed to form a plurality of first circuit patterns and a plurality of second circuit patterns, the plurality of first circuit patterns are used for forming a plurality of first circuits by electroplating, the plurality of second circuit patterns are used for forming a plurality of second circuits by electroplating,
the second line extends in a first direction of the groove bottom, the size of the groove in the first direction is marked as A1, the size of the second line pattern in the first direction is marked as C3, and the relation is satisfied:
A1-2C1＝C3。
7. the method for manufacturing a sunken circuit board according to claim 2, wherein the line distance of the second line is D6, the line distance of the first line is D7, and the relationship is satisfied:
D5＝D6；
D5＝D7。
8. the method for manufacturing a sunken circuit board according to claim 1, wherein the substrate is formed by laminating at least two substrates, the thickness of any one substrate is recorded as H, the depth of the groove is recorded as U, and the relational expression is satisfied: u is more than H.
9. The method of claim 1, further comprising the steps of, after cleaning the second wet film and the dry film:
performing automated optical inspection of the substrate;
carrying out solder resist treatment on the substrate;
performing silk filling characters on the substrate;
performing surface gold immersion treatment on the substrate;
performing a flying probe test on the substrate;
and carrying out molding treatment on the substrate.
10. A circuit board characterized in that it is produced by the circuit board production method according to any one of claims 1 to 9.
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