CN114912392B - Connectivity detection configuration system for design data - Google Patents
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Abstract
The invention relates to a connectivity detection configuration system of design data, which comprises a design mapping relation library, a display interface, a memory and a processor, wherein the memory and the processor are used for storing computer programs, the design mapping relation library comprises M pieces of pre-generated design mapping information, and the design mapping information comprises father node component identifiers, level identifiers of father nodes, child node component identifiers and level identifiers of child nodes; the display interface is used for presenting a configuration interface, the configuration interface comprises M pieces of configuration information, the configuration information comprises a father node component identification data segment, a son node component identification data segment, a hierarchy identification information data segment, a detection mode data segment, an error range data segment and a detection identification data segment, and the hierarchy identification information data segment is used for storing a hierarchy identification where the father node component is located and a hierarchy identification where the son node component is located. The invention improves the accuracy and flexibility of the connectivity detection of the design data.
Description
Technical Field
The invention relates to the technical field of electronic design, in particular to a connectivity detection configuration system of design data.
Background
In designs (devices) such as a PCB (Printed Circuit Board), a Package, an Interposer (Package carrier), an IC (integrated Circuit), and the like, different manufacturers typically manufacture the devices independently, so that each design data is independent, and networks configured by different design data may differ based on a Device connectivity detection system, a pin name, a pin number, and the like between different design data. In the design data detection process, all the design data are required to be nested together for detection. With the development of electronic technology, tens of thousands or even tens of designs may be involved in a system to form a multi-level interconnection, and components of different types of design data may be suitable for different detection standards. CN113919252A discloses a system for detecting connectivity of components among different design data, but connectivity of components in design data can only be detected by a uniform standard, which is low in accuracy and poor in flexibility. Therefore, how to improve the accuracy and flexibility of the design data connectivity detection becomes a technical problem to be solved urgently.
Disclosure of Invention
The invention aims to provide a connectivity detection configuration system of design data, which improves the accuracy and flexibility of the connectivity detection of the design data.
The invention provides a connectivity detection configuration system of design data, which comprises a design mapping relation library, a display interface, a memory and a processor, wherein the memory and the processor are used for storing computer programs, the design mapping relation library comprises M pieces of pre-generated design mapping information, and the design mapping information comprises father node component identifiers, level identifiers of father nodes, child node component identifiers and level identifiers of child nodes; the display interface is used for presenting a configuration interface, the configuration interface comprises M pieces of configuration information, the configuration information comprises a father node element identification data segment, a son node element identification data segment, a hierarchy identification information data segment, a detection mode data segment, an error range data segment and a detection identification data segment, the hierarchy identification information data segment is used for storing a hierarchy identification where the father node element is located and a hierarchy identification where the son node element is located, and the detection identification data segment is used for storing an identification needing to be detected and an identification needing not to be detected;
when the processor executes the computer program, the following steps are implemented:
step S1, receiving a first connectivity detection configuration instruction;
step S2, calling the design mapping relation library based on the first connectivity detection to present an initial configuration interface on the display interface, wherein in the initial configuration interface, all detection modes corresponding to M pieces of configuration information are set as default detection modes, all error range data segments are set as default error ranges, and all detection identification data segments are set as identification needing to be detected;
step S3, receiving a second connectivity detection configuration instruction, and determining configuration information to be modified and corresponding target modification information based on the second connectivity detection configuration instruction, wherein the target modification information includes at least one of a change detection mode, a change error range and whether a change is displayed;
step S4, modifying the configuration information to be modified based on the target modification information to generate target configuration information;
and step S5, performing connectivity detection of the design data based on the target configuration information.
Compared with the prior art, the invention has obvious advantages and beneficial effects. By the technical scheme, the connectivity detection configuration system of the design data provided by the invention can achieve considerable technical progress and practicability, has wide industrial utilization value and at least has the following advantages:
the invention can flexibly set the connectivity detection configuration information between any two components positioned at any two adjacent levels, and improves the accuracy and the flexibility of the connectivity detection of design data based on the corresponding configuration information memorability connectivity detection.
The foregoing description is only an overview of the technical solutions of the present invention, and in order to make the technical means of the present invention more clearly understood, the present invention may be implemented in accordance with the content of the description, and in order to make the above and other objects, features, and advantages of the present invention more clearly understood, the following preferred embodiments are described in detail with reference to the accompanying drawings.
Drawings
Fig. 1 is a schematic diagram of a connectivity detection configuration system for design data according to an embodiment of the present invention.
Detailed Description
To further illustrate the technical means and effects of the present invention adopted to achieve the predetermined objects, the following detailed description will be given to a specific embodiment of a connectivity check configuration system for design data and its effects according to the present invention with reference to the accompanying drawings and preferred embodiments.
An embodiment of the present invention provides a connectivity detection configuration system for design data, as shown in fig. 1, including a design mapping relationship library, a display interface, a memory storing a computer program, and a processor, where the design mapping relationship library includes M pieces of pre-generated design mapping information, and M is a positive integer greater than or equal to 2. The design mapping information comprises father node component identifiers, level identifiers of father nodes, child node component identifiers and level identifiers of child nodes. The display interface is used for presenting a configuration interface, the configuration interface comprises M pieces of configuration information, the configuration information comprises a father node component identification data segment, a son node component identification data segment, a hierarchy identification information data segment, a detection mode data segment, an error range data segment and a detection identification data segment, and the hierarchy identification information data segment is used for storing a hierarchy identification where the father node component is located and a hierarchy identification where the son node component is located; the detection identification data segment is used for storing identification needing detection and identification needing no detection. It should be noted that the detection-needed identifier means that the corresponding design mapping information needs to be detected for connectivity detection, and may be specifically set to "Ignore YES". The detection-free identification means that the connectivity detection is performed without detecting corresponding design mapping information, and may be specifically set to "Ignore NO".
As an embodiment, the configuration interface may include a plurality of column regions, where a father node component identifier data segment, a child node component identifier data segment, a hierarchy identifier information data segment, a detection mode data segment, an error range data segment, and a detection identifier data segment occupy one column region respectively, and a hierarchy identifier pair is formed by a hierarchy identifier of the father node component and a hierarchy identifier of the child node component, and placed in one column region.
When the processor executes the computer program, the following steps are implemented:
and step S1, receiving a first connectivity detection configuration instruction.
And step S2, calling the design mapping relation library based on the first connectivity detection to present an initial configuration interface on the display interface, wherein in the initial configuration interface, all detection modes corresponding to M pieces of configuration information are set as default detection modes, all error range data segments are set as default error ranges, and all detection identification data segments are set as identification needing to be detected.
Step S3, receiving a second connectivity check configuration instruction, and determining configuration information to be modified and corresponding target modification information based on the second connectivity check configuration instruction, where the target modification information includes at least one of a change detection mode, a change error range, and whether to change the display.
And step S4, modifying the configuration information to be modified based on the target modification information to generate target configuration information.
And step S5, performing connectivity detection of the design data based on the target configuration information.
As an embodiment, the detection mode includes a pin center corresponding mode and a pin area corresponding mode; if the detection mode data segment is set to be in a mode corresponding to the pin center, the error range data segment is configured to be in a modifiable mode; and if the detection mode data segment is set to be in a pin area corresponding mode, configuring the error range data segment into a non-modifiable mode and setting the error range data segment as a default error range all the time. As a preferred embodiment, the default error ranges are all 0.
The component types include a Printed Circuit Board (PCB), a Package, an Interposer, an Integrated Circuit (IC), and other design (Device) types. The component identification includes component type information and numbering information, such as pkg _0820, pcb _0821, it being understood that the identification of each component is unique, but the numbering information may not be unique. And determining a corresponding detection mode and an error range based on the component type information corresponding to the component identification and the detection precision requirement.
When the M value is small, the M pieces of configuration information may be directly configured, but when the M value is large and it is necessary to reserve a certain piece of configuration information for subsequent reuse, the configuration information may also be stored and then directly loaded for use, as an embodiment, the system further includes a configuration file library for storing the template configuration file, and the step S4 is followed by:
and step S41, receiving a template configuration file saving instruction.
And step S42, generating a corresponding template configuration file based on the target configuration information, and storing the template configuration file into the configuration file library.
It is understood that step S4 may be executed multiple times, or the template configuration file may be saved after any configuration information modification is completed, so as to improve the efficiency and flexibility of configuration.
As an embodiment, the step S42 is followed by:
step S43, receiving a third connectivity detection configuration instruction, and determining a target template configuration file based on the third connectivity detection configuration instruction.
Step S44, obtaining the target template configuration file from the configuration file library, presenting the corresponding configuration information in the configuration interface, and then returning to execute step S3, or directly executing step S5 based on the current configuration information as the target configuration information.
It can be understood that, after the configuration information corresponding to the target template configuration file is directly presented on the configuration interface, connectivity detection can be directly performed based on the current configuration information, and the configuration information can be further modified on the basis, thereby improving configuration efficiency and flexibility.
Based on the configuration interface, the information of connectivity detection can be flexibly configured, and the following detailed description is given by several specific embodiments:
the first embodiment,
The step S3 includes:
step S31, parsing out the father node component identifier to be modified, the child node component identifier to be modified, the father node component level identifier to be modified, the child node component level identifier to be modified, and the corresponding target modification information from the second connectivity detection configuration instruction.
Step S32, retrieving configuration information in the current configuration interface, and determining the configuration information with father node component identification data segment as the father node component identification to be modified, child node component identification data segment as the child node component identification to be modified, the level identification of the father node component as the level identification of the father node component to be modified, and the level identification of the child node component as the level identification of the child node component to be modified as the configuration information to be modified.
And step S33, modifying all the configuration information to be modified based on the target modification information.
It should be noted that, when the steps S31 to S33 are executed once, only one piece of corresponding configuration information may be modified, but the steps may be executed multiple times, and multiple pieces of corresponding configuration information may be modified one by one, so that the same parent node device and child node device are combined in the same adjacent hierarchy and different adjacent hierarchies, or different parent node devices and child node devices are combined in the same adjacent hierarchy and different adjacent hierarchies, and the configuration information for connectivity detection may be independently and flexibly set in each of the different adjacent hierarchies, without affecting each other.
Example II,
The step S3 includes:
step S31 ， And analyzing the father node component identifier to be modified, the child node component identifier to be modified and the corresponding target modification information from the second connectivity detection configuration instruction.
Step S32 ， And retrieving the configuration information in the current configuration interface, and determining the configuration information of which all father node component identification data segments are the father node component identifications to be modified and all child node component identification data segments are the child node component identifications to be modified as the configuration information to be modified.
Step S33 ， And uniformly modifying all the configuration information to be modified based on the target modification information.
It should be noted that, in a system design, there may exist a set of identical parent node components and child node components located at different adjacent levels, and in some application scenarios, the same set of parent node components and child node componentsIt may be necessary to set the same connectivity check configuration information, so it is possible to pass through step S31 ， Step S33 ， Batch modification is realized, and the connectivity detection configuration efficiency is improved.
Example III,
The step S3 includes:
step S31 ，， And analyzing the father node component level identifier to be modified, the child node component level identifier to be modified and corresponding target modification information from the second connectivity detection configuration instruction.
Step S32 ，， And retrieving the configuration information in the current configuration interface, and determining the configuration information of which the father node component level identifier in all the level identification information data segments is the father node component level identifier to be modified and the level identifier of the child node component is the child node component level identifier to be modified as the configuration information to be modified.
Step S33 ，， And uniformly modifying all the configuration information to be modified based on the target modification information.
It should be noted that, in some application scenarios, in one system design, all parent node components and child node component combinations in the same adjacent hierarchy may exist, and the same connectivity detection configuration information needs to be set, which may be performed through step S31 ，， Step S33 ，， Batch modification is realized, and the connectivity detection configuration efficiency is improved.
As an example, the step S5 includes:
and S51, analyzing the detection identification data segment into target configuration information needing to be detected, and acquiring a target father node component identification, a target child node component identification, a target father node component level identification, a target child node component level identification, a target detection mode and a target error range, wherein if the target detection mode is a pin center corresponding mode, the step S52 is executed, and if the target detection mode is a pin area corresponding mode, the step S53 is executed.
Step S52, determining coordinates corresponding to the pin center of the target father node component based on the target father node component identifier and the target father node component level identifier, determining coordinates corresponding to the pin center of the target child node based on the target child node component identifier and the target child node component level identifier, if the coordinate corresponding to the pin center of the target father node and the coordinate error corresponding to the pin center of the target child node are within the target error range, determining that the pin of the target father node is communicated with the pin corresponding to the target child node, and otherwise, determining that the pin is not communicated.
Step S53, a pin area corresponding to the pin center of a target father node component is determined based on the target father node component identification and the target father node component level identification, a pin area corresponding to the pin center of a target child node is determined based on the target child node component identification and the target child node component level identification, if the pin area of the target father node and the pin area corresponding to the target child node component have intersection, the pin of the target father node and the pin corresponding to the target child node are determined to be connected, otherwise, the pin is determined to be disconnected.
The display interface is further configured to present a connectivity detection report, and the step S5 further includes:
and step S54, generating the connectivity detection report based on all target father node component identifiers, target child node component identifiers, target father node component level identifiers, target child node component level identifiers, target father node pins and target child node corresponding pin connectivity detection results, and displaying the connectivity detection report on the display interface.
It should be noted that, the step S54 may be specifically implemented by a method disclosed in CN113935272A or by other methods, and specific implementation manners are not described herein again.
The system provided by the embodiment of the invention can flexibly set the connectivity detection configuration information between any two components positioned at any two adjacent levels, and improves the accuracy and flexibility of the connectivity detection of design data based on the corresponding configuration information memorability connectivity detection.
It should be noted that, after the detection configuration information is set, connectivity detection can be performed on any interconnected component, but in the prior art, connectivity detection is performed on one-to-one components, and in some interconnection design data, there are cases where there is one-to-many, for example, a plurality of ICs may be set on a PCB, if a one-to-one connectivity detection method is adopted, system performance may be greatly reduced, a unified connectivity detection report cannot be generated for the PCB, and detection efficiency is low, based on which, the embodiment of the present invention makes further improvements:
when the processor executes the computer program, the following steps are also implemented:
step C1, acquiring one-to-many component combination { D ] based on the design mapping relation library 1 ，D 2 ，…D N }, D n For the nth group of one-to-many component combinations, D n =（A n ,B 1 n ,B 2 n ,…B f(n) n ）, A n 、B 1 n 、B 2 n 、…B f(n) n Is a component, B 1 n ,B 2 n ,…B f(n) n At the same level, A n At B 1 n ,B 2 n ,…B f(n) n At the adjacent level of the level, N ranges from 1 to N, f (N) is equal to A n The number of interconnected components at the same level, f (n), is a function of n.
Step C2, adding D n Corresponding design data are imported into a preset coordinate system to establish A n 、B 1 n 、B 2 n 、…B f(n) n And A n To generate A n 、B 1 n 、B 2 n 、…B f(n) n Pin coordinate information of (2).
Wherein, each component can be firstly arranged at the origin of coordinates, and then A is established by operations such as moving, overturning and/or rotating n 、B 1 n 、B 2 n 、…B f(n) n And A n The interconnection relationship of (c).
Step C3 based on B i n Pin information determination of (B) i n Of (2) a bounding box P i n Based on P i n And A n Pin coordinate information of from A n Selecting B from the pins i n Corresponding pin set AX i n I ranges from 1 to f (n).
It should be noted that all the existing bounding box calculation methods fall within the scope of the present invention, and are not described herein again. By calculating B i n Of (2) a bounding box P i n Can be directly from A n Selecting B from the pins i n Corresponding pin set AX i n Avoid B i n For A n All the pins are calculated, so that the calculation amount is greatly reduced, and the system performance is improved.
Step C4, based on B i n And AX i n Pin coordinate information pair B i n And A n And carrying out connectivity detection.
In step C4, each group B can be individually identified i n And A n Connectivity detection is carried out, and a plurality of groups B can be parallelly detected i n And A n Performing connectivity check, as a preferred embodiment, in the step C4, based on all B i n And AX i n Pin coordinate information of (a), performing B in parallel 1 n 、B 2 n 、…B f(n) n And A n And the connectivity detection efficiency is improved.
As an embodiment, the system further includes a display interface, and the step C4 is followed by:
step C5 based on B 1 n 、B 2 n 、…B f(n) n And A n To generate A as a result of the connectivity test n The connectivity detection report is presented on the display interface.
It should be noted that, if the prior art is adopted, one-to-one correspondence is adoptedThe detection mode of the components can only calculate each group B respectively i n And A n Connectivity check, and need to be for A n All the pins in the system are calculated, the calculation efficiency is low, the performance is poor, and the final presented result can only present B i n And A n Results of connectivity check, for B i n Is complete, but for A n In terms of display only part, not intuitive, and relative to the display due to A n Relative to B i n There are a large number of unconnected pins, which also results in a very large number of unconnected pins being generated, and a pin with a real defect cannot be found intuitively. The embodiment of the invention selects B i n Corresponding pin set AX i n The above problems can be solved as a preferred embodiment: the step C5 includes:
step C51, based on B i n And A n The connectivity detection result generates a set BA of connected pin pairs i n And A is n AT of an unconnected pin set i n The connection pin pair comprises B i n And a pin in A communicating with the pin n Of the pin of (a).
Step C52, based on all BAs i n Generation of A n Is reported to the institute AT i n Pooling based on AT i n Generating A n A non-connected sub-report of (a); the connected sub report comprises a pin name of a connected pin pair and a corresponding network identification name; the non-unicom sub-report comprises A n Pin names which are not successfully connected and corresponding connection failure prediction information.
Step C53, displaying A on the display interface n And/or a n Is reported.
Through the steps C51-C53, A can be generated quickly and intuitively n The accuracy and the efficiency of the connectivity check are improved.
As an example, B i n Pin of (2) includes { pB 1 ni ,pB 2 ni ,…pB g(i) ni }，PB j ni Is B i n J is 1 to g (i), and g (i) is B i n G (i) is a function of i, said step C4 includes:
step C41, adding AX i n Corresponding region division into E 1 A first sub-area, PB j ni The corresponding first sub-region is taken as a first target sub-region, E 1 The number of the divided areas is preset first.
Step C42, dividing the y-th target sub-area into E y A y sub-area, PB j ni The Y target sub-area is determined as the Y target sub-area, the value range of Y is 2 to Y, Y is the total division times, E y The number of regions is divided for the preset y-th.
In addition, E is 1 And E y The values may be the same or different, E 1 、E y And the value of Y is comprehensively determined according to the requirements of the specific application scene such as the calculation efficiency and the calculation accuracy.
Step C43, corresponding AX of the Y-th target sub-region i n Pin coordinate information AXY in i n Is determined as PB j ni And corresponding candidate pin coordinate information.
From AX through step C41-step C43 i n Corresponding pins are selected to obtain the potential sum PB j ni And the communicated candidate pin coordinate information further accelerates the communication detection efficiency and accuracy.
Step C44, PB-based j ni Pin coordinate information of (2) and AXY i n Until PB is determined j ni In A n If AXY is the corresponding connection pin in i n If no corresponding connection pin exists, prompt information is generated.
Wherein PB can be executed in parallel j ni And AXY i n Can be calculated one by one, but each pin can only be communicated with one pin of the same adjacent level, therefore, when the PB can be determined j ni In A n And the calculation can be stopped when the corresponding pin is communicated.
As an example, in the step C44, the information is based on PB j ni Pin coordinate information of (A) and (Y) i n Performing connectivity detection on each pin coordinate information, including:
step C441, based on PB j ni Pin coordinate information of (A) and (Y) i n According to B i n And A n Corresponding connectivity check configuration information for PB j ni Pin coordinate information of (A) and (Y) i n The connectivity detection configuration information comprises detection modes, wherein the detection modes comprise a pin center corresponding mode and a pin area corresponding mode.
It should be noted that the configuration information may be configured flexibly directly based on the detection configuration system described in the embodiment of the present invention.
If the detection mode is the pin center corresponding mode, step C441 includes:
step C4411, PB-based j ni Pin coordinate information of (A) and (Y) i n Obtaining PB for each pin coordinate information in j ni Pin center coordinate information and AXY i n Each pin center coordinate information.
Step C4412, if PB j ni Pin center coordinate information and AXY i n Determines PB if the coordinate information of one pin center is within a preset error range j ni Pin of (2) and corresponding AXY i n The middle pins are communicated, otherwise, the middle pins are determined to be not communicated.
If the detection mode is the pin area corresponding mode, step C441 includes:
step C4411 ， Based on PB j ni Pin coordinate information of (A) and (Y) i n Obtaining PB for each pin coordinate information in j ni Pin area and AXY i n Each pin area of (a).
Step C4411 ， If PB is j ni Pin area and AXY i n If there is an intersection in one of the pin areas, PB is determined j ni Pin of (2) and corresponding AXY i n The middle pins are communicated, otherwise, the middle pins are determined to be not communicated.
The system of the embodiment of the invention obtains the one-to-many component combination based on the design mapping relation library, selects the corresponding pin set from the pins corresponding to the components based on the bounding box, and calculates the one-to-many component connectivity detection according to the selected pin set, thereby greatly reducing the calculation amount and improving the performance and efficiency of the one-to-many component connectivity detection.
It should be noted that some exemplary embodiments are described as processes or methods depicted as flowcharts. Although a flowchart may describe the steps as a sequential process, many of the steps can be performed in parallel, concurrently or simultaneously. In addition, the order of the steps may be rearranged. A process may be terminated when its operations are completed, but may have additional steps not included in the figure. A process may correspond to a method, a function, a procedure, a subroutine, a subprogram, etc.
Although the present invention has been described with reference to a preferred embodiment, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (5)
1. A system for detecting and configuring connectivity of design data,
the design method comprises a design mapping relation library, a display interface, a memory and a processor, wherein the memory stores a computer program, the design mapping relation library comprises M pieces of pre-generated design mapping information, and the design mapping information comprises father node component identifiers, hierarchy identifiers of father nodes, child node component identifiers and hierarchy identifiers of child nodes; the display interface is used for presenting a configuration interface, the configuration interface comprises M pieces of configuration information, the configuration information comprises a father node component identification data segment, a child node component identification data segment, a hierarchy identification information data segment, a detection mode data segment, an error range data segment and a detection identification data segment, the hierarchy identification information data segment is used for storing a hierarchy identification where the father node component is located and a hierarchy identification where the child node component is located, and the detection identification data segment is used for storing an identification needing to be detected and an identification needing not to be detected;
when the processor executes the computer program, the following steps are implemented:
step S1, receiving a first connectivity detection configuration instruction;
step S2, calling the design mapping relation library based on the first connectivity detection configuration instruction to present an initial configuration interface on the display interface, wherein in the initial configuration interface, all detection modes corresponding to M pieces of configuration information are set as default detection modes, all error range data segments are set as default error ranges, and all detection identification data segments are set as identification needing to be detected;
the step of calling the design mapping relation library based on the first connectivity detection configuration instruction to present an initial configuration interface on the display interface comprises the following steps:
obtaining one-to-many component combination { D) based on the design mapping relation library 1 ，D 2 ，…D N }, D n For the nth group of one-to-many component combinations, D n =（A n ,B 1 n ,B 2 n ,…B f(n) n ）, A n 、B 1 n 、B 2 n 、…B f(n) n Is a component, B 1 n ,B 2 n ,…B f(n) n At the same level, A n At B 1 n ,B 2 n ,…B f(n) n At the adjacent level of the level, N ranges from 1 to N, f (N) is equal to A n The number of interconnected components at the same level, f (n) being a function of n, and n presenting a corresponding initial configuration interface on the display interface;
step S3, receiving a second connectivity detection configuration instruction, and determining configuration information to be modified and corresponding target modification information based on the second connectivity detection configuration instruction, where the target modification information includes at least one of a change detection mode, a change error range, and a change detection identifier;
the step S3 includes:
step S31, analyzing father node component identifier to be modified, child node component identifier to be modified, father node component level identifier to be modified, child node component level identifier to be modified and corresponding target modification information from the second connectivity detection configuration instruction;
step S32, retrieving configuration information in the current configuration interface, and determining the configuration information with father node component identification data segment as the father node component identification to be modified, child node component identification data segment as the child node component identification to be modified, the level identification of the father node component as the level identification of the father node component to be modified and the level identification of the child node component as the level identification of the child node component to be modified as the configuration information to be modified;
step S4, modifying the configuration information to be modified based on the target modification information to generate target configuration information;
step S5, performing connectivity detection of the design data based on the target configuration information:
the step S5 specifically includes:
will D n Corresponding design data are imported into a preset coordinate system to establish A n 、B 1 n 、B 2 n 、…B f(n) n And A n The interconnection relationship of (A) is generated n 、B 1 n 、B 2 n 、…B f(n) n Pin coordinate information of (2);
based on B i n Pin information determination of (B) i n Of (2) a bounding box P i n Based on P i n And A n Pin coordinate information of (2) from A n Selecting B from the pins i n Corresponding pin set AX i n I ranges from 1 to f (n);
based on B i n And AX i n Pin coordinate information pair B i n And A n Carrying out connectivity detection;
based on B 1 n 、B 2 n 、…B f(n) n And A n To generate A as a result of the connectivity test n The connectivity detection report is presented on the display interface;
wherein, B i n Pin of (2) includes { pB 1 ni ,pB 2 ni ,…pB g(i) ni }，PB j ni Is B i n J is 1 to g (i), and g (i) is B i n G (i) is a function of i, based on B i n And AX i n Pin coordinate information pair B i n And A n The detecting connectivity specifically comprises:
let AX i n Corresponding region division into E 1 A first sub-area, PB j ni The corresponding first sub-region is taken as a first target sub-region, E 1 The number of the preset first divided areas is set;
dividing the y-th target sub-region into E y A y sub-area, PB j ni The Y target sub-area is determined as the Y target sub-area, the value range of Y is 2 to Y, Y is the total division times, E y Dividing the number of the areas for a preset y;
AX corresponding to the Y-th target subregion i n Pin coordinate information AXY in i n Is determined as PB j ni Corresponding candidate pin coordinate information;
based on PB j ni Pin coordinate information of (A) and (Y) i n Until PB is determined j ni In A n If AXY is the corresponding connection pin in i n If no corresponding connection pin exists, prompt information is generated.
2. The system of claim 1,
the detection mode comprises a pin center corresponding mode and a pin area corresponding mode;
if the detection mode data segment is set to be in a mode corresponding to the pin center, the error range data segment is configured to be in a modifiable mode;
and if the detection mode data segment is set to be in a pin area corresponding mode, configuring the error range data segment into a non-modifiable mode and setting the error range data segment as a default error range all the time.
3. The system of claim 1,
the system further includes a profile library for storing template profiles, and after step S4, the method further includes:
step S41, receiving a template configuration file saving instruction;
and step S42, generating a corresponding template configuration file based on the target configuration information, and storing the template configuration file into the configuration file library.
4. The system of claim 3,
the step S42 is followed by:
step S43, receiving a third connectivity detection configuration instruction, and determining a target template configuration file based on the third connectivity detection configuration instruction;
step S44, obtaining the target template configuration file from the configuration file library, presenting the corresponding configuration information in the configuration interface, and then returning to execute step S3, or directly executing step S5 based on the current configuration information as the target configuration information.
5. The system of claim 1,
the component identification comprises component type information and serial number information, and a corresponding detection mode and an error range are determined based on the component type information corresponding to the component identification and the detection precision requirement.
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