CN114911297B - Drive control circuit for LDO circuit, LDO circuit and chip thereof - Google Patents
Drive control circuit for LDO circuit, LDO circuit and chip thereof Download PDFInfo
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- CN114911297B CN114911297B CN202210560618.8A CN202210560618A CN114911297B CN 114911297 B CN114911297 B CN 114911297B CN 202210560618 A CN202210560618 A CN 202210560618A CN 114911297 B CN114911297 B CN 114911297B
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
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- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
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Abstract
The invention discloses a drive control circuit for an LDO circuit, the LDO circuit and a chip thereof, comprising: the first output end is used for being connected with an external load, and the second output end is used for being connected with the external load through the first output end; a driving voltage source; the input end of the driving circuit is used for being connected with a driving voltage source, and the output end of the driving circuit is connected with the first output end and the second output end respectively; the control circuit is used for detecting the resistance value of the external load and controlling the driving circuit to be communicated with the driving voltage source and the first output end and the driving voltage source and the second output end or to be communicated with the driving voltage source and the second output end and to be disconnected with the driving voltage source and the first output end according to the detected resistance value of the external load. The LDO circuit solves the problem that the existing LDO circuit cannot simultaneously adapt to the working requirements of light load and heavy load.
Description
Technical Field
The present invention relates to the field of semiconductor integrated chips, and more particularly, to a driving control circuit for an LDO circuit, and a chip thereof.
Background
The supply voltage of a digital IO is typically lower than the operating voltage of the chip itself, so a low voltage source is required to be provided inside the chip to power the IO, which is typically generated by an LDO (Low dropout regulator, low dropout linear regulator).
The existing LDO circuit works under heavy load, so that the size of a power tube is required to be large, and the parasitic capacitance of an output node is caused to be large; if the power amplifier needs to work under a light load, the load resistance of the output node is large, and the main pole is arranged at the output node of the error amplifier, so that the capacitance of the output node is small for circuit stability, namely the size of the power tube cannot be too large; the size requirements for power transistors are conflicting under heavy and light loads. Therefore, the existing LDO circuit cannot adapt to the working range. Under the condition of increasingly stringent requirements on low power consumption, the existing LDOs are increasingly difficult to meet actual requirements.
Disclosure of Invention
The invention mainly aims to provide a drive control circuit for an LDO circuit, the LDO circuit and a chip thereof, and aims to solve the problem that the existing LDO circuit cannot simultaneously adapt to the working requirements of light load and heavy load.
To achieve the above object, the present invention provides a drive control circuit for an LDO circuit, comprising: the first output end is used for being connected with an external load, and the second output end is used for being connected with the external load through the first output end;
a driving voltage source;
the input end of the driving circuit is used for being connected with the driving voltage source, and the output end of the driving circuit is respectively connected with the first output end and the second output end;
the control circuit is used for detecting the resistance value of the external load and controlling the driving circuit to be communicated with the driving voltage source and the first output end and the driving voltage source and the second output end or to be communicated with the driving voltage source and the second output end and to be disconnected with the driving voltage source and the first output end according to the detected resistance value of the external load.
Optionally, the driving control circuit further includes a zero adjustment circuit, which is serially arranged between the first output end and the second output end;
the zero point adjusting circuit is used for adjusting a resistance value when the driving circuit is communicated with the driving voltage source and the second output end and is used for switching off the driving voltage source and the first output end so as to adjust the zero point position of the driving control circuit.
Optionally, the driving circuit includes a first driving tube, a second driving tube, the input of the first driving tube is connected with the input of the second driving tube and the driving voltage source respectively, the controlled end of the first driving tube is connected with the control end of the control circuit, the controlled end of the second driving tube is used for connecting the high level, the output of the first driving tube is connected with the first output, and the second driving tube is connected with the second output.
Optionally, the control circuit is specifically configured to control, when detecting that the resistance value of the external load is smaller than a preset resistance value, the first driving tube and the second driving tube to be turned on, so as to connect the driving voltage source with the first output end and connect the driving voltage source with the second output end; when the resistance value of the external load is detected to be larger than a preset resistance value, the first driving tube is controlled to be turned off, and the second driving tube is controlled to be turned on so as to be communicated with the driving voltage source and the second output end and turn off the driving voltage source and the first output end.
Optionally, the controlled end of the zero point adjusting circuit is connected with the controlled end of the second driving tube, and the zero point adjusting circuit is used for adjusting the resistor according to the high-level voltage value connected with the controlled end of the second driving tube.
Optionally, the control circuit includes a first switch and a second switch, a first end of the first switch is used for accessing a high level, a controlled end of the first driving tube is respectively connected with a second end of the first switch and a first end of the second switch, a second end of the second switch is used for accessing a low level, and the first switch and the second switch are used for being turned on/off according to a resistance value of the external load so as to control the on/off of the first driving tube.
Optionally, the first switch is a switch with high level on and low level off, and the second switch is a switch with low level on and high level off; alternatively, the first switch is a switch that is turned on at a low level and turned off at a high level, and the second switch is a switch that is turned on at a high level and turned off at a low level.
The invention provides an LDO circuit, which comprises a drive control circuit and a feedback amplifying circuit, wherein the input end of the drive control circuit and the feedback output end of the drive control circuit are respectively connected with the feedback amplifying circuit.
Optionally, the feedback amplifying circuit includes an amplifier, a first capacitor, a first resistor, a second resistor and a reference input voltage source, where an in-phase input end of the amplifier is connected with the reference input voltage source, an inverting input end of the amplifier is connected with a first end of the first resistor and a first end of the second resistor, a second end of the first resistor is grounded, a second end of the second resistor is connected with a feedback output end of the drive control circuit, and an output end of the amplifier is connected with a first end of the first capacitor and an input end of the drive control circuit, and a second end of the first capacitor is grounded.
The invention proposes an LDO chip comprising a drive control circuit for an LDO circuit as described above.
The drive control circuit for the LDO circuit drives the voltage source, the control circuit and the drive circuit by arranging the first output end and the second output end; the first output end is used for being connected with an external load, the second output end is used for being connected with a driving circuit through the first output end and the external load, the input end of the driving circuit is used for being connected with a driving voltage source, the output end of the driving circuit is respectively connected with the first output end and the second output end, the control circuit is used for detecting the resistance value of the external load and controlling the driving circuit to be communicated with the driving voltage source and the first output end and the driving voltage source and the second output end according to the detected resistance value of the external load, or the driving voltage source is communicated with the second output end and the driving voltage source and the first output end are cut off. When the high-power high-load power control circuit works, the external load is identified as a heavy load when the detected resistance value is smaller, the control circuit controls the driving circuit to be communicated with the driving voltage source and the first output end and the driving voltage source and the second output end, and the first output end and the second output end receive the driving voltage source at the same time so as to provide high power for driving the high load; when the detected resistance value is larger, the external load is identified as a light load, the control circuit controls the driving circuit to be communicated with the driving voltage source and the second output end and to switch off the driving voltage source and the first output end, the first output end does not receive the driving voltage source, the second output end receives the driving voltage source so as to provide low power for driving the low load, and the problem that the stability of the circuit in operation is affected due to the fact that the capacitance of an output node is larger due to the adoption of a high-power driving tube in the operation of the driving of the low load is avoided. By arranging the circuit, the problem that the existing LDO circuit cannot simultaneously adapt to the working requirements of light load and heavy load is solved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to the structures shown in these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a functional block diagram of an embodiment of a drive control circuit for an LDO circuit according to the present invention;
FIG. 2 is a schematic diagram of a driving control circuit for an LDO circuit according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of an embodiment of an LDO circuit according to the present invention;
fig. 4 is a schematic circuit diagram of a zero adjustment circuit according to an embodiment of the present invention.
Reference numerals illustrate:
| reference numerals | Name of the name | Reference numerals | Name of the name |
| 1 | Feedback amplifying circuit | 2 | Drive control circuit |
| 21 | Driving voltage source | 22 | Driving circuit |
| 23 | Control circuit | 24 | A first output end |
| 25 | A second output end | 26 | External load |
| 27 | Zero point adjusting circuit | MN1-MN2 | First driving tube-second driving tube |
| SW1-SW2 | First switch-second switch | C1 | First capacitor |
| AMP | Amplifier | R1-R2 | First resistor-second resistor |
The achievement of the objects, functional features and advantages of the present invention will be further described with reference to the accompanying drawings, in conjunction with the embodiments.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention. It should be noted that, if directional indications (such as up, down, left, right, front, and rear … …) are included in the embodiments of the present invention, the directional indications are merely used to explain the relative positional relationship between the components, the movement condition, and the like in a specific posture (as shown in the drawings), and if the specific posture is changed, the directional indications are correspondingly changed.
In addition, if there is a description of "first", "second", etc. in the embodiments of the present invention, the description of "first", "second", etc. is for descriptive purposes only and is not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In addition, the technical solutions of the embodiments may be combined with each other, but it is necessary to base that the technical solutions can be realized by those skilled in the art, and when the technical solutions are contradictory or cannot be realized, the combination of the technical solutions should be considered to be absent and not within the scope of protection claimed in the present invention.
Referring to fig. 1, in an embodiment of the present invention, the driving control circuit 2 for LDO circuit includes:
a first output end 24 and a second output end 25, wherein the first output end 24 is used for being connected with an external load 26, and the second output end 25 is used for being connected with the external load 26 through the first output end 24;
a driving voltage source 21;
the input end of the driving circuit 22 is used for being connected with the driving voltage source 21, and the output end of the driving circuit 22 is respectively connected with the first output end 24 and the second output end 25;
the control circuit 23, the control end of the control circuit 23 is connected with the controlled end of the driving circuit 22, the control circuit 23 is configured to detect the resistance value of the external load 26, and control the driving circuit 22 to connect the driving voltage source 21 to the first output end 24 and connect the driving voltage source 21 to the second output end 25, or connect the driving voltage source 21 to the second output end 25 and disconnect the driving voltage source 21 to the first output end 24 according to the detected resistance value of the external load 26.
In this embodiment, the input end of the driving circuit 22 is connected to the driving voltage source 21, the output end of the driving circuit 22 is connected to the first output end 24 and the second output end 25, respectively, when the driving voltage source 21 is connected to the first output end 24 or the second output end 25, the first output end 24 or the second output end 25 receives the voltage of the driving voltage source 21, and when the driving voltage source 21 is disconnected from the first output end 24 or the second output end 25, the first output end 24 or the second output end 25 does not receive the voltage of the driving voltage source 21.
The voltages received by the first output terminal 24 and the second output terminal 25 are used to drive the external load 26 to operate. The first output end 24 is directly connected to the external load 26, the received voltage is directly used to drive the external load 26, and the second output end 25 is connected to the external load 26 through the first output end 24, and the received voltage is output to the external load 26 through the first output end 24.
The control circuit 23 controls the driving circuit 22 to connect/disconnect the driving voltage source 21 to/from the first output terminal 24 and the second output terminal 25 according to the detected resistance value of the external load 26, so as to control the first output terminal 24 or the second output terminal 25 to receive/not receive the voltage of the driving voltage source 21.
Specifically, when the detected resistance value of the external load 26 is smaller, the external load 26 is regarded as a heavy load, the control circuit 23 controls the driving circuit 22 to communicate the driving voltage source 21 with the first output terminal 24 and to communicate the driving voltage source 21 with the second output terminal 25, at this time, the first output terminal 24 receives the driving voltage source 21 and the second output terminal 25 receives the driving voltage source 21, and the driving voltage source 21 received by the first output terminal 24 and the second output terminal 25 is connected to the external load 26 through the first output terminal 24 and is used for driving the external load 26 to operate.
When the detected resistance value of the external load 26 is larger, the external load 26 is identified as a light load, the control circuit 23 controls the driving circuit 22 to communicate the driving voltage source 21 with the second output terminal 25 and to turn off the driving voltage source 21 and the first output terminal 24, at this time, the second output terminal 25 receives no driving voltage source 21 from the driving voltage source 21, and the second output terminal 25 receives the driving voltage source 21, and the driving voltage source 21 received by the second output terminal 25 is connected to the external load 26 through the first output terminal 24 for driving the external load 26 to operate.
When the external load 26 is a heavy load, the driving power required for the heavy load is high. The first output terminal 24 and the second output terminal 25 simultaneously receive the driving voltage source 21 for providing high driving power to the external load 26 to drive the heavy load.
When the external load 26 is a light load, the driving power required by the light load is lower, the driving of the light load can be satisfied by the lower driving power, and when the driving power is higher, the size specification of the driving tube required by the driving control circuit 2 is larger, which can result in larger capacitance of the output node, thereby influencing the stability of the circuit during operation. So when the external load 26 is a light load, the second output terminal 25 receives the driving voltage source 21, and the first output terminal 24 does not receive the driving voltage source 21, and provides low driving power to the external load 26 to drive the light load.
The working principle of the embodiment is as follows: the driving circuit 22 is configured to switch on/off the driving voltage source 21 and the first output terminal 24 and the second output terminal 25, and the first output terminal 24 and the second output terminal 25 use the received driving voltage source 21 to drive the external load 26 when the driving voltage source 21 is connected. The control circuit 23 controls the driving circuit 22 to turn on/off the driving voltage source 21 and the first output terminal 24 and the second output terminal 25 according to the detected resistance value of the external load 26. When the detected resistance value is smaller, the external load 26 is identified as a heavy load, and the control circuit 23 controls the driving circuit 22 to communicate the driving voltage source 21 with the first output end 24 and communicate the driving voltage source 21 with the second output end 25, and the first output end 24 and the second output end 25 simultaneously receive the driving voltage source 21 to provide high power for driving the high load; when the detected resistance value is larger, the external load 26 is identified as a light load, the control circuit 23 controls the driving circuit 22 to communicate the driving voltage source 21 with the second output end 25 and to switch off the driving voltage source 21 and the first output end 24, the first output end 24 does not receive the driving voltage source 21, and the second output end 25 receives the driving voltage source 21 to provide low power for driving the low load, so that the problem that the stability of the circuit in operation is affected due to the fact that the capacitance of an output node is larger due to the adoption of a high-power driving tube in the operation of driving the low load is avoided.
The drive control circuit 2 for the LDO circuit drives the voltage source 21, the control circuit 23 and the drive circuit 22 by arranging a first output end 24 and a second output end 25; the first output end 24 is used for being connected with an external load 26, the second output end 25 is used for being connected with the driving circuit 22 through the first output end 24 and the external load 26, the input end of the driving circuit 22 is used for being connected with the driving voltage source 21, the output end of the driving circuit 22 is respectively connected with the first output end 24 and the second output end 25, the control circuit 23, the control end of the control circuit 23 is connected with the controlled end of the driving circuit 22, the control circuit 23 is used for detecting the resistance value of the external load 26 and controlling the driving circuit 22 to be communicated with the driving voltage source 21 and the first output end 24 and the driving voltage source 21 and the second output end 25 or to be communicated with the driving voltage source 21 and the second output end 25 and to be disconnected with the driving voltage source 21 and the first output end 24 according to the detected resistance value of the external load 26. When the detected resistance value is smaller, the external load 26 is identified as a heavy load, the control circuit 23 controls the driving circuit 22 to communicate the driving voltage source 21 with the first output end 24 and communicate the driving voltage source 21 with the second output end 25, and the first output end 24 and the second output end 25 simultaneously receive the driving voltage source 21 so as to provide high power for driving the high load; when the detected resistance value is larger, the external load 26 is identified as a light load, the control circuit 23 controls the driving circuit 22 to communicate the driving voltage source 21 with the second output end 25 and to switch off the driving voltage source 21 and the first output end 24, the first output end 24 does not receive the driving voltage source 21, and the second output end 25 receives the driving voltage source 21 so as to provide low power for driving the low load, and the problem that the stability of the circuit during operation is affected because the capacitance of an output node is larger due to the adoption of a high-power driving tube during the operation of the low load is avoided. By arranging the circuit, the problem that the existing LDO circuit cannot simultaneously adapt to the working requirements of light load and heavy load is solved.
Referring to fig. 1, in an embodiment, the driving control circuit 2 further includes a zero adjustment circuit 27, which is disposed in series between the first output terminal 24 and the second output terminal 25;
the zero point adjusting circuit 27 is configured to adjust a resistance value when the driving circuit 22 communicates the driving voltage source 21 with the second output terminal 25 and turns off the driving voltage source 21 and the first output terminal 24, so as to adjust a zero point position of the driving control circuit 2.
In this embodiment, when the driving control circuit 2 is used in the LDO circuit, the pole generated at the second output terminal 25 is a secondary main pole of the output function of the LDO circuit, and there is one main pole of the output function inside the LDO circuit, the frequency of the secondary main pole is related to the resistance value of the external load 26 and the parasitic capacitance of the driving circuit 22, and the larger the resistance value of the external load 26 and the parasitic capacitance of the driving circuit 22, the smaller the frequency of the secondary main pole is, and the smaller the frequency of the secondary main pole is, so that the circuit system is unstable.
The zero point adjusting circuit 27 is used to cancel or partially cancel the influence of the secondary main pole point by adjusting the position of the zero point when the drive control circuit 2 drives the light load to operate. When the external load 26 is a light load, the load resistance value is larger, so that the frequency of the secondary main pole point is smaller, the secondary main pole point can move to the main pole point to influence the stability of the circuit, and the influence of the position of the secondary main pole point on the circuit is eliminated by adjusting the resistance value of the zero point adjusting circuit 27, so that the drive control circuit 2 stably works when the light load is connected. The influence of the secondary main pole on the loop stability formed by the drive control circuit 2 in the LDO circuit can be offset or partially offset by adjusting the resistance value of the zero adjustment circuit 27.
Referring to fig. 2, in an embodiment, the driving circuit 22 includes a first driving tube MN1 and a second driving tube MN2, where an input end of the first driving tube MN1 is connected to an input end of the second driving tube MN2 and the driving voltage source 21, a controlled end of the first driving tube MN1 is connected to a control end of the control circuit 23, a controlled end of the second driving tube MN2 is used to connect to a high level, an output end of the first driving tube MN1 is connected to the first output end 24, and the second driving tube MN2 is connected to the second output end 25.
In the present embodiment, VDD is a driving voltage source 21 for providing driving voltages to the first driving tube MN1 and the second driving tube MN 2. When the first driving tube MN1 is turned on, the first output end 24 is connected to the driving voltage source 21, and when the second driving tube MN2 is turned on, the second output end 25 is connected to the driving voltage source 21. The controlled end of the second driving tube MN2 is connected to the high level, the second driving tube MN2 is turned on, the second output end 25 is communicated with the driving voltage source 21, and the second output end 25 receives the driving voltage source 21. The operation of the first driving tube MN1 is controlled by the control end output by the control circuit 23, when the control end of the control circuit 23 is at a high level, the first driving tube MN1 is turned on, the first output end 24 cannot receive the driving voltage source 21, and when the control end of the control circuit 23 is at a low level, the first driving tube MN1 is turned off, and the first output end 24 receives the driving voltage source 21.VOUT is used to connect the external load 26, and VOUT provides high power to drive the external load 26 when the first driving tube MN1 is on and the second driving tube MN2 is on, and VOUT provides light power to drive the external load 26 when the first driving tube MN1 is on and the second driving tube MN2 is off.
When the heavy load is driven, the first driving tube and the second driving tube are both conducted, so that the driving capability of the driving control circuit 2 is increased. The driving control circuit 2 may have a plurality of driving tubes connected in parallel, and the plurality of driving tubes connected in parallel are all turned on to drive a heavy load when driving the heavy load.
When driving light load, one driving tube is conducted, the other driving tubes are turned off, and parasitic capacitance of the output end VOUT of the driving control circuit 2 is prevented from being influenced by the high-power driving tubes, so that a loop formed by the driving control circuit 2 in the LDO circuit is reduced in frequency of a corresponding secondary main pole point, and stability of a circuit system is influenced. And the low driving power is adopted during light load, so that the energy loss in the circuit is reduced, and the requirements of low power consumption in electronic equipment are met.
Referring to fig. 2, in an embodiment, the control circuit 23 is specifically configured to control the first driving tube MN1 and the second driving tube MN2 to be turned on when detecting that the resistance value of the external load 26 is smaller than a preset resistance value, so as to communicate the driving voltage source 21 with the first output terminal 24 and communicate the driving voltage source 21 with the second output terminal 25; when the resistance value of the external load 26 is detected to be greater than the preset resistance value, the first driving tube MN1 is controlled to be turned off, and the second driving tube MN2 is controlled to be turned on, so as to connect the driving voltage source 21 with the second output terminal 25 and turn off the driving voltage source 21 with the first output terminal 24.
In the present embodiment, the control circuit 23 controls on/off of the first and second driving pipes MN2 according to the resistance value of the external load 26.
When the resistance value of the external load 26 is detected to be greater than the preset resistance value, the external load 26 is identified as a light load, the control end of the control circuit 23 is at a low level, the first driving tube MN1 is turned off, the second driving tube MN2 is turned on, and the second output end 25 receives the driving voltage source 21 and is used for driving the light load. When the resistance value of the external load 26 is detected to be smaller than the preset resistance value, the external load 26 is identified as a heavy load, the control end of the control circuit 23 is at a high level, the first driving tube MN1 and the second driving tube MN2 are both turned on, and the first output end 24 and the second output end 25 receive the driving voltage source 21 and are used for driving the heavy load.
Referring to fig. 2, in an embodiment, a controlled end of the zero point adjusting circuit 27 is connected to a controlled end of the second driving tube MN2, and the zero point adjusting circuit 27 is configured to adjust a resistance according to a high-level voltage value connected to the controlled end of the second driving tube MN 2.
In this embodiment, the resistance value of the zero point adjusting circuit 27 is dynamically and automatically adjusted, and the adjusted resistance value is controlled by the voltage value at the VO1 terminal. VO1 is a high level signal connected to the controlled end of the second driving tube MN2, and is used for controlling the second driving tube MN2 to be turned on.
Referring to fig. 2, in an embodiment, the control circuit 23 includes a first switch SW1 and a second switch SW2, a first end of the first switch SW1 is used for accessing a high level, a controlled end of the first driving tube MN1 is respectively connected with a second end of the first switch SW1 and a first end of the second switch SW2, a second end of the second switch SW2 is used for accessing a low level, and the first switch SW1 and the second switch SW2 are used for being turned on/off according to a resistance value of the external load 26 so as to control on/off of the first driving tube MN 1.
In this embodiment, VO1 is a high level signal, VL is a low level signal, and the first switch SW1 and the second switch SW2 are turned on/off according to the detected load resistance value, so that the output terminal of the control circuit 23 outputs high level/low level.
When the first switch SW1 is turned on and the second switch SW2 is turned off, the high level signal VO1 received by the first switch SW1 is output to the control terminal of the control circuit 23 to control the first driving tube MN1 of the driving circuit 22 to be turned on. When the first switch SW1 is turned off and the second switch SW2 is turned on, the low level signal VL that the first switch SW1 is connected to is output to the control end of the control circuit 23 to control the first driving tube MN1 of the driving circuit 22 to be turned off.
Referring to fig. 2, in an embodiment, the first switch SW1 is a high-level on and low-level off switch, and the second switch SW2 is a low-level on and high-level off switch; alternatively, the first switch SW1 is a low-level on and high-level off switch, and the second switch SW2 is a high-level on and low-level off switch.
In this embodiment, the first switch SW1 and the second switch SW2 are mutually exclusive switches, one switch is turned on and the other switch is turned off, and a stable high level or low level is output to control the on/off of the first driving tube MN1 when the control circuit 23 works. If the first switch SW1 is a high-level on and low-level off switch, the second switch SW2 is a low-level on and high-level off switch, and MODE is low in light load and high in heavy load.
Referring to fig. 2, in an embodiment, the driving transistor is a transistor, a MOS transistor, or a triode.
In this embodiment, the driving tube is an electronic device with a driving function, such as a transistor, a MOS transistor, or a triode.
The invention provides an LDO circuit.
The LDO circuit comprises the drive control circuit 2 and the feedback amplifying circuit 1, wherein the input end of the drive control circuit 2 and the feedback output end of the drive control circuit 2 are respectively connected with the feedback amplifying circuit 1.
The LDO circuit adopts all the technical schemes of all the embodiments, so that the LDO circuit has at least all the beneficial effects brought by the technical schemes of the embodiments, and is not described in detail herein.
Referring to fig. 3, in an embodiment, the feedback amplifying circuit 1 includes an amplifier AMP, a first capacitor C1, a first resistor R1, a second resistor R2, and a reference input voltage source, where a non-inverting input terminal of the amplifier AMP is connected to the reference input voltage source, an inverting input terminal of the amplifier AMP is connected to a first terminal of the first resistor R1 and a first terminal of the second resistor R2, a second terminal of the first resistor R1 is grounded, a second terminal of the second resistor R2 is connected to a feedback output terminal of the driving control circuit 2, and an output terminal of the amplifier AMP is connected to a first terminal of the first capacitor C1 and an input terminal of the driving control circuit 2, and a second terminal of the first capacitor C1 is grounded.
In this embodiment, VREF is a reference voltage source, VO1 is an input terminal of the driving control circuit 2, VO2 is a feedback output terminal of the driving control circuit 2, and VFB is connected to an inverting input terminal of the amplifier AMP.
The feedback amplifying circuit 1 outputs a corresponding voltage according to a voltage of a non-inverting input terminal and a voltage of an inverting input terminal, wherein the voltage of the non-inverting input terminal is a voltage of an external voltage source, and the voltage of the inverting input terminal is an output voltage of the driving control circuit 2. The driving control circuit 2 outputs a corresponding voltage according to the output voltage of the feedback amplifying circuit 1, so that a feedback loop of the self voltage of the feedback amplifying circuit 1 is realized, and the output voltage value of the feedback amplifying circuit 1 is stabilized.
Referring to fig. 4, in an embodiment, the zero adjustment circuit 27 is a MOS transistor.
In this embodiment, the zero point adjusting circuit 27 may be composed of a variable resistor or a component having a function of adjusting the self resistance value such as a MOS transistor. If the zero adjustment circuit 27 is a MOS transistor, the gate of the MOS transistor is connected to the controlled end of the driving circuit 22, the source of the MOS transistor is connected to the first output end 24, and the drain of the MOS transistor is connected to the second output end 25.
Specifically, when the zero-point adjusting circuit 27 is a MOS transistor, the formula of the resistance value adjusted by the zero-point adjusting circuit 27 is 1/[ μn×cox×w/L (V01-VOUT) ], where μn carrier mobility, W/L is the width-to-length ratio of the driving transistor in the driving control circuit 2, cox is the gate capacitance of the unit area of the driving transistor, V01 is the voltage value of VO1, VOUT is the output voltage of the driving control circuit 2, and when the driving control circuit 2 drives the load to operate, the output voltage VOUT of the dynamic driving control circuit 2 is a fixed voltage value, W/L, μn and Cox are related to the driving transistor specification of the dynamic driving control circuit 2, and the resistance value adjusted by the zero-point adjusting circuit 27 is set according to the voltage value V01 of VO 1.
The invention provides a chip thereof.
The chip comprises the LDO circuit, and all the technical schemes of all the embodiments are adopted, so that the chip at least has all the beneficial effects brought by the technical schemes of the embodiments, and the description is omitted.
The foregoing description is only of the optional embodiments of the present invention, and is not intended to limit the scope of the invention, and all equivalent structural modifications made by the present description and accompanying drawings or direct/indirect application in other related technical fields are included in the scope of the present invention.
Claims (9)
1. A drive control circuit for an LDO circuit, comprising:
the first output end is used for being connected with an external load, and the second output end is used for being connected with the external load through the first output end;
a driving voltage source;
the input end of the driving circuit is used for being connected with the driving voltage source, and the output end of the driving circuit is respectively connected with the first output end and the second output end;
the control circuit is used for detecting the resistance value of the external load and controlling the driving circuit to be communicated with the driving voltage source and the first output end and the driving voltage source and the second output end or to be communicated with the driving voltage source and the second output end and to shut off the driving voltage source and the first output end according to the detected resistance value of the external load;
the drive control circuit further comprises a zero point adjusting circuit which is arranged between the first output end and the second output end in series;
the zero point adjusting circuit is used for adjusting a resistance value when the driving circuit is communicated with the driving voltage source and the second output end and is used for switching off the driving voltage source and the first output end so as to adjust the zero point position of the driving control circuit.
2. The drive control circuit for an LDO circuit of claim 1, wherein the drive circuit comprises a first drive tube, a second drive tube, an input of the first drive tube being connected to an input of the second drive tube and the drive voltage source, respectively, a controlled end of the first drive tube being connected to a control end of the control circuit, a controlled end of the second drive tube being for connecting a high level, an output of the first drive tube being connected to the first output, and the second drive tube being connected to the second output.
3. The drive control circuit for an LDO circuit of claim 2, wherein the control circuit is specifically configured to control the first drive tube and the second drive tube to be turned on to communicate the drive voltage source with the first output terminal and to communicate the drive voltage source with the second output terminal when detecting that the resistance value of the external load is less than a preset resistance value; when the resistance value of the external load is detected to be larger than a preset resistance value, the first driving tube is controlled to be turned off, and the second driving tube is controlled to be turned on so as to be communicated with the driving voltage source and the second output end and turn off the driving voltage source and the first output end.
4. The drive control circuit for an LDO circuit of claim 2, wherein the controlled terminal of the zero adjustment circuit is connected to the controlled terminal of the second drive tube, and wherein the zero adjustment circuit is configured to adjust the resistance according to a high-level voltage value to which the controlled terminal of the second drive tube is connected.
5. The drive control circuit for an LDO circuit of claim 2, wherein the control circuit comprises a first switch and a second switch, wherein a first end of the first switch is used for switching in a high level, a controlled end of the first drive tube is respectively connected with a second end of the first switch and a first end of the second switch, a second end of the second switch is used for switching in a low level, and the first switch and the second switch are used for switching on/off according to a resistance value of the external load so as to control the switching on/off of the first drive tube.
6. The drive control circuit for an LDO circuit of claim 5, wherein the first switch is a high-level on and low-level off switch and the second switch is a low-level on and high-level off switch; alternatively, the first switch is a switch that is turned on at a low level and turned off at a high level, and the second switch is a switch that is turned on at a high level and turned off at a low level.
7. An LDO circuit comprising the drive control circuit and the feedback amplification circuit according to any one of claims 1 to 6, wherein an input terminal of the drive control circuit and a feedback output terminal of the drive control circuit are connected to the feedback amplification circuit, respectively.
8. The LDO circuit of claim 7, wherein the feedback amplification circuit comprises an amplifier, a first capacitor, a first resistor, a second resistor, and a reference input voltage source, wherein a non-inverting input terminal of the amplifier is connected to the reference input voltage source, an inverting input terminal of the amplifier is connected to a first terminal of the first resistor and a first terminal of the second resistor, respectively, a second terminal of the first resistor is grounded, a second terminal of the second resistor is connected to a feedback output terminal of the drive control circuit, and an output terminal of the amplifier is connected to a first terminal of the first capacitor and an input terminal of the drive control circuit, respectively, and a second terminal of the first capacitor is grounded.
9. An LDO chip, characterized in that the chip comprises an LDO circuit according to any of claims 7 to 8.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210560618.8A CN114911297B (en) | 2022-05-23 | 2022-05-23 | Drive control circuit for LDO circuit, LDO circuit and chip thereof |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202210560618.8A CN114911297B (en) | 2022-05-23 | 2022-05-23 | Drive control circuit for LDO circuit, LDO circuit and chip thereof |
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| CN114911297A CN114911297A (en) | 2022-08-16 |
| CN114911297B true CN114911297B (en) | 2023-08-08 |
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| US6765374B1 (en) * | 2003-07-10 | 2004-07-20 | System General Corp. | Low drop-out regulator and an pole-zero cancellation method for the same |
| CN211792163U (en) * | 2020-05-20 | 2020-10-27 | 杭州必易微电子有限公司 | Load drive circuit and load drive control circuit |
| CN215934474U (en) * | 2021-07-30 | 2022-03-01 | 浙江大华技术股份有限公司 | Power supply circuit and power supply |
| CN114265463A (en) * | 2021-12-21 | 2022-04-01 | 广州众诺电子技术有限公司 | Low-dropout voltage stabilizing circuit, equipment, chip and method for controlling output voltage of chip |
| CN114510107A (en) * | 2022-04-21 | 2022-05-17 | 江苏长晶科技股份有限公司 | LDO circuit for improving full-load stability |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100492244C (en) * | 2007-03-21 | 2009-05-27 | 北京中星微电子有限公司 | Voltage regulator with low voltage difference |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6765374B1 (en) * | 2003-07-10 | 2004-07-20 | System General Corp. | Low drop-out regulator and an pole-zero cancellation method for the same |
| CN211792163U (en) * | 2020-05-20 | 2020-10-27 | 杭州必易微电子有限公司 | Load drive circuit and load drive control circuit |
| CN215934474U (en) * | 2021-07-30 | 2022-03-01 | 浙江大华技术股份有限公司 | Power supply circuit and power supply |
| CN114265463A (en) * | 2021-12-21 | 2022-04-01 | 广州众诺电子技术有限公司 | Low-dropout voltage stabilizing circuit, equipment, chip and method for controlling output voltage of chip |
| CN114510107A (en) * | 2022-04-21 | 2022-05-17 | 江苏长晶科技股份有限公司 | LDO circuit for improving full-load stability |
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| CN114911297A (en) | 2022-08-16 |
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