CN114899114A - Processing and preparing process of integrated chip - Google Patents

Processing and preparing process of integrated chip Download PDF

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Publication number
CN114899114A
CN114899114A CN202210492026.7A CN202210492026A CN114899114A CN 114899114 A CN114899114 A CN 114899114A CN 202210492026 A CN202210492026 A CN 202210492026A CN 114899114 A CN114899114 A CN 114899114A
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CN
China
Prior art keywords
chip
etching
wafer
integrated chip
manufacturing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202210492026.7A
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Chinese (zh)
Inventor
谢维
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Jiangsu Dingmao Semiconductor Co ltd
Original Assignee
Jiangsu Dingmao Semiconductor Co ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Jiangsu Dingmao Semiconductor Co ltd filed Critical Jiangsu Dingmao Semiconductor Co ltd
Priority to CN202210492026.7A priority Critical patent/CN114899114A/en
Publication of CN114899114A publication Critical patent/CN114899114A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/52—Mounting semiconductor bodies in containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0231—Manufacturing methods of the redistribution layers

Abstract

The invention belongs to the technical field of chip processing, and discloses a processing and preparation process of an integrated chip, which comprises the following steps of S1: obtaining a Wafer, and taking the Wafer as a substrate; s2: determining an etching area, placing different packaging bodies on the Wafer substrate, and depicting the etching area; s3: etching, namely etching the drawn etching area on the Wafer, wherein the number of the chips which can be placed after etching is at least one; s4: placing a corresponding chip in the etching area; s5: and processing the placed chip. In S2, the etched region is drawn to conform to the shape and size of the package. The invention can realize a highly concentrated packaging body, the whole chip is very firm and not easy to damage, the service life of the whole chip is prolonged, and the invention is convenient for popularization and application. The method does not need gold wires, has better reliability, reduces the conditions that gold wire connection is easy to have faults and signals are disconnected, and is more practical.

Description

Processing and preparing process of integrated chip
Technical Field
The invention belongs to the technical field of chip processing, and particularly relates to a processing and preparation process of an integrated chip.
Background
Chips of different manufacturers or different types are currently used On a Chip On Board, and then gold wires are used for realizing electrical connection.
The existing inherited chips are difficult to concentrate chips of different types and manufacturers on the same wafer, in the prior art, electrical connection is realized through a conventional chip manufacturing process, then an integrated aggregate is cut and separated out to form a new packaging body, but the mode is low in flexibility, difficult to integrate and use according to different chip functions, relatively poor in stability, and the chips are easy to break down and break signals due to connection of gold wires, so that the processing and preparation process of the integrated chips is provided.
Disclosure of Invention
The invention aims to provide a processing and preparation process of an integrated chip, which aims to solve the problems that chips of different types and manufacturers are difficult to be integrated on the same wafer in the conventional inherited chip provided in the background technology, the conventional chip manufacturing process is mostly adopted in the prior art to realize electrical connection, and then the integrated aggregate is cut and separated to form a new packaging body, but the mode has low flexibility, is difficult to be integrated and used according to different chip functions, has relatively poor stability and the like.
In order to achieve the purpose, the invention provides the following technical scheme: a process for preparing integrated chip includes such steps as preparing the substrate,
s1: obtaining a Wafer, and taking the Wafer as a substrate;
s2: determining an etching area, placing different packaging bodies on the Wafer substrate, and depicting the etching area;
s3: etching, namely etching the drawn etching area on the Wafer, wherein the number of the chips which can be placed after etching is at least one;
s4: placing a corresponding chip in the etching area;
s5: and processing the placed chip.
Preferably, in S2, the etched region is drawn to conform to the shape and size of the package.
Preferably, in S3, the Wafer after etching has a recess, wherein the depth of the recess is consistent with the height of the chip to be placed, and when the chip is placed, the top wall of the chip is in the same plane as the top wall of the Wafer.
Preferably, the depth of the groove is 1.0-1.7um, and the width of the substrate etched by the P etching process is 10-25 um.
Preferably, in S5, the chip after placement is processed:
the first step is as follows: generating a passivation layer for covering and fixing the chip;
the second step is that: coating photoresist, developing, exposing and etching to expose the area needing electrical connection;
the third step: metal sputtering, and then repeating the second step again to realize final electrical connection;
the fourth step: and scribing to separate the integrated packaging body.
Preferably, in the first step, the passivation layer is silicon dioxide, and the thickness of the silicon dioxide is 10-100 μm.
Preferably, in the second step, a transparent insulating layer with a thickness of between 500-3000A is deposited on the surface of the chip by using a plasma enhanced chemical vapor deposition device. And the material of the transparent insulating layer is Si 3 N 4 、SiO 2 And Al 2 O 3 One or more of the materials.
Compared with the prior art, the invention has the beneficial effects that:
the invention can realize a highly concentrated packaging body, the whole chip is very firm and not easy to damage, the service life of the whole chip is prolonged, and the invention is convenient for popularization and application.
The method does not need gold wires, has better reliability, reduces the conditions that gold wire connection is easy to have faults and signals are disconnected, and is more practical.
And according to the difference of the function, the corresponding chip is selected at will to carry out integrated package Wafer, so that the new package body is very stable, can be matched for use according to different use requirements, and has higher flexibility.
Drawings
FIG. 1 is a schematic flow diagram of the present invention;
FIG. 2 is a schematic diagram of the structure Wafer of the present invention;
FIG. 3 is a schematic illustration of the Wafer etch area of the present invention;
FIG. 4 is a schematic view of the Wafer groove of the present invention;
FIG. 5 is a schematic diagram of the Wafer of the present invention after placing a chip;
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 1 to 4, the present invention provides a technical solution: a process for preparing integrated chip includes such steps as preparing the substrate,
s1: obtaining a Wafer, and taking the Wafer as a substrate;
s2: determining an etching area, placing different packaging bodies on the Wafer substrate, and depicting the etching area;
s3: etching, namely etching the drawn etching area on the Wafer, wherein the number of the chips which can be placed after etching is at least one;
s4: placing a corresponding chip in the etching area;
s5: and processing the placed chip.
In this embodiment, it is preferable that the etched region drawn in S2 is in conformity with the shape and size of the package.
In this embodiment, it is preferable that in S3, the Wafer after etching has a groove, wherein the depth of the groove is consistent with the height of the chip to be placed, and when the chip is placed, the top wall of the chip is in the same plane as the top wall of the Wafer.
In this embodiment, preferably, the depth of the groove is 1.0-1.7um, and the width of the substrate etched by the P etching process is 10-25 um.
In this embodiment, preferably, in S5, the chip after placement is processed:
the first step is as follows: generating a passivation layer for covering and fixing the chip;
the second step: coating photoresist, developing, exposing and etching to expose the area needing electrical connection;
the third step: metal sputtering, and then repeating the second step again to realize final electrical connection;
the fourth step: and scribing to separate the integrated packaging body.
In the embodiment, preferably, in the first step, the passivation layer is silicon dioxide, and the thickness of the silicon dioxide is 10 to 100 μm.
In this embodiment, preferably, in the second step, a transparent insulating layer with a thickness of between 500-. And the material of the transparent insulating layer is Si 3 N 4 、SiO 2 And Al 2 O 3 One or more of the materials.
The above description is only for the purpose of illustrating the technical solutions of the present invention and not for the purpose of limiting the same, and other modifications or equivalent substitutions made by those skilled in the art to the technical solutions of the present invention should be covered within the scope of the claims of the present invention without departing from the spirit and scope of the technical solutions of the present invention.

Claims (8)

1. A processing and preparation process of an integrated chip is characterized by comprising the following steps: comprises the steps of (a) preparing a mixture of a plurality of raw materials,
s1: obtaining a Wafer, and taking the Wafer as a substrate;
s2: determining an etching area, placing different packaging bodies on the Wafer substrate, and depicting the etching area;
s3: etching, namely etching the drawn etching area on the Wafer, wherein the number of the chips which can be placed after etching is at least one;
s4: placing a corresponding chip in the etching area;
s5: and processing the placed chip.
2. The process for manufacturing an integrated chip according to claim 1, wherein: in S2, the etched region is drawn to conform to the shape and size of the package.
3. The process for manufacturing an integrated chip according to claim 1, wherein: in S3, the Wafer after etching has a recess, wherein the depth of the recess is consistent with the height of the chip to be placed, and the top wall of the chip is in the same plane as the top wall of the Wafer after the chip is placed.
4. The process for manufacturing an integrated chip according to claim 3, wherein: the depth of the groove is 1.0-1.7um, and the width of the substrate etched by the P etching process is 10-25 um.
5. The process for manufacturing an integrated chip according to claim 1, wherein: in S5, the chip after placement is processed:
the first step is as follows: generating a passivation layer for covering and fixing the chip;
the second step is that: coating photoresist, developing, exposing and etching to expose the area needing electrical connection;
the third step: metal sputtering, and then repeating the second step again to realize final electrical connection;
the fourth step: and scribing to separate the integrated packaging body.
6. The manufacturing process of integrated chip as claimed in claim 5, wherein: in the first step, the passivation layer is silicon dioxide, and the thickness of the silicon dioxide is 10-100 μm.
7. The manufacturing process of integrated chip as claimed in claim 5, wherein: in the second step, a transparent insulating layer with the thickness of 500-3000A is deposited on the surface of the chip by using plasma enhanced chemical vapor deposition equipment.
8. The process for manufacturing an integrated chip according to claim 7, wherein: the material of the transparent insulating layer is Si 3 N 4 、SiO 2 And Al 2 O 3 One or more of the materials.
CN202210492026.7A 2022-05-06 2022-05-06 Processing and preparing process of integrated chip Pending CN114899114A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202210492026.7A CN114899114A (en) 2022-05-06 2022-05-06 Processing and preparing process of integrated chip

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202210492026.7A CN114899114A (en) 2022-05-06 2022-05-06 Processing and preparing process of integrated chip

Publications (1)

Publication Number Publication Date
CN114899114A true CN114899114A (en) 2022-08-12

Family

ID=82720791

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202210492026.7A Pending CN114899114A (en) 2022-05-06 2022-05-06 Processing and preparing process of integrated chip

Country Status (1)

Country Link
CN (1) CN114899114A (en)

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