CN114883406A - Enhanced GaN power device and preparation method thereof - Google Patents

Enhanced GaN power device and preparation method thereof Download PDF

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CN114883406A
CN114883406A CN202210796677.5A CN202210796677A CN114883406A CN 114883406 A CN114883406 A CN 114883406A CN 202210796677 A CN202210796677 A CN 202210796677A CN 114883406 A CN114883406 A CN 114883406A
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CN114883406B (en
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武乐可
夏远洋
范晓成
李亦衡
朱廷刚
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Jiangsu Corenergy Semiconductor Co ltd
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Abstract

The invention provides an enhanced GaN power device and a preparation method thereof, and relates to the field of device preparation. The enhancement mode GaN power device comprises: the source electrode, the grid electrode and the drain electrode sequentially comprise a substrate, a buffer layer, an AlGaN layer, a P-GaN layer and a dielectric layer which are grown in MOCVD equipment from bottom to top, and the SiN layer is arranged at the top; the dielectric layer is provided with a first partial groove; the first partial groove extends to the top surface of the P-GaN layer from the top surface of the dielectric layer; the grid electrode is arranged in the grid region; the grid region comprises a first partial groove and a second partial groove; the second partial groove is formed by etching the part of the SiN layer corresponding to the first partial groove; the first part groove is communicated with the second part groove; the source electrode is arranged in the source electrode groove, and the drain electrode is arranged in the drain electrode groove; the invention is simple and high-efficient.

Description

Enhanced GaN power device and preparation method thereof
Technical Field
The invention relates to the field of device preparation, in particular to an enhanced GaN power device and a preparation method thereof.
Background
The gallium nitride (GaN) material has a series of material performance advantages of large forbidden band width, high breakdown field strength, high polarization coefficient, high electron mobility, high electron saturation drift rate and the like, is an optimal material for preparing a new generation of high-performance electronic power device, and has important application prospects. In recent years, GaN-based power electronic devices have been placed in major strategic research projects in developed countries and regions such as the united states, japan, and europe, and have made significant progress. A high electron mobility transistor (HMET) prepared from two-dimensional electron gas generated by polarization effect at an AlGaN/GaN heterojunction interface is a GaN-based power device mainly applied at present and has the advantages of high voltage resistance, high power density, high operating speed and the like. Then relatively complex gate drive circuitry is required in practical applications due to the presence of the two-dimensional electron gas at the heterojunction interface, and fail-safe requirements are not met. Therefore, in GaN-based power electronic device applications, the enhancement-mode GaN-based HEMT becomes an important technical goal. At present, the main technical means for realizing the enhanced GaN HEMT power electronic device comprise a groove gate structure, a p-type gate cap layer, a cascade structure and the like. The depletion of heterojunction interface two-dimensional electron gas is an industrialized mainstream technology by a p-type GaN cap layer structure on the AlGaN/GaN heterojunction, and the p-type GaN cap layer technology has potential advantages in the aspects of interface quality, device switching characteristics and the like and receives more and more attention.
For an enhanced GaN HEMT device, a P-type GaN layer is grown on the surface of AlGaN, and the normally-closed characteristic is realized by the depletion of two-dimensional electron gas below a grid electrode by P-GaN. In the device manufacturing process, the P-GaN has a depletion effect on the two-dimensional electron gas of the whole device region, but the manufacturing purpose is to enable the P-GaN to deplete the two-dimensional electron gas below the grid electrode, and the two-dimensional electron gas of other regions cannot be depleted. This makes it necessary to perform a region etching of the epitaxially grown P-GaN, leaving only the P-GaN layer in the gate region and the P-GaN layer in other regions to be etched away. In the preparation process of the GaN device, the prior art adopts various devices to carry out epitaxial growth by taking Si as a substrate, the operation flow is complex, and the compactness of a medium layer grown by LPCVD is poor.
Disclosure of Invention
The invention aims to provide an enhanced GaN power device and a preparation method thereof, which are used for simply and efficiently improving the performance of the device.
In order to achieve the purpose, the invention provides the following scheme:
an enhanced GaN power device, comprising: the device comprises a substrate, a buffer layer, an AlGaN layer, a P-GaN layer, a dielectric layer, an SiN layer, a source electrode, a grid electrode and a drain electrode;
the buffer layer, the AlGaN layer, the P-GaN layer, the dielectric layer and the SiN layer are sequentially grown on the substrate from bottom to top; the buffer layer, the AlGaN layer, the P-GaN layer and the dielectric layer are all grown in MOCVD equipment;
the dielectric layer is provided with a first partial groove; the first partial groove extends from the top surface of the dielectric layer to the top surface of the P-GaN layer;
the grid electrode is placed in the grid groove; the gate groove comprises a first partial groove and a second partial groove; the second partial groove is formed by etching a part of the SiN layer corresponding to the first partial groove; the first partial groove is communicated with the second partial groove;
the source electrode is placed in the source groove; the source electrode groove is formed by etching downwards from a first region on the SiN layer to the inner part of the buffer layer; the source electrode is connected with a two-dimensional electron gas layer formed in the buffer layer;
the drain electrode is placed in the drain groove; the drain electrode groove is formed by etching downwards from a second region on the SiN layer to the inner part of the buffer layer; the drain electrode is connected with a two-dimensional electron gas layer formed in the buffer layer; the first region is different from the second region.
Optionally, the enhancement mode GaN power device further comprises: a first isolation layer;
etching the first isolation region at one side of the source electrode groove close to the edge; the first isolation region is formed by etching the top surface of the P-GaN layer to the inside of the buffer layer; and an isolation material is placed in the first isolation region to form a first isolation layer.
Optionally, the enhancement mode GaN power device further comprises: a second isolation layer;
etching the second isolation region at one side of the drain electrode groove close to the edge; the second isolation region is formed by etching the top surface of the P-GaN layer to the inside of the buffer layer; and an isolation material is placed in the second isolation region to form a second isolation layer.
Optionally, the thickness of the dielectric layer is 0.1nm-10000 nm.
A preparation method of an enhanced GaN power device, the preparation method being used for preparing the enhanced GaN power device, the preparation method comprising:
growing a buffer layer, an AlGaN layer, a P-GaN layer and a dielectric layer on a substrate from bottom to top in sequence by using MOCVD equipment;
etching from the top surface of the dielectric layer to the top surface of the P-GaN layer downwards to obtain a first partial groove;
growing a SiN layer on the P-GaN layer etched with the first partial groove;
etching a part, corresponding to the first part of groove, on the SiN layer to enable a second part of groove obtained through etching to be communicated with the first part of groove to form a grid groove;
etching a first region on the SiN layer downwards to the inside of the buffer layer to form a source electrode groove; the source electrode groove penetrates through a two-dimensional electronic gas layer formed in the buffer layer;
etching a second region on the SiN layer downwards to the inner part of the buffer layer to form a drain electrode groove; the drain electrode groove penetrates through a two-dimensional electronic gas layer formed in the buffer layer; the first region is different from the second region;
and generating a gate electrode in the gate groove by adopting a sputtering mode, generating a source electrode in the source groove, and generating a drain electrode in the drain groove to obtain the enhanced GaN power device.
Optionally, the preparation method further comprises:
etching the top surface of the P-GaN layer downwards to the inner part of the buffer layer from the top surface of the P-GaN layer on one side of the source electrode groove close to the edge to form a first isolation region;
and placing an isolation material in the first isolation region to form a first isolation layer.
Optionally, the preparation method further comprises:
etching the top surface of the P-GaN layer to the inner part of the buffer layer from the top surface of the P-GaN layer to form a second isolation region on one side of the drain electrode groove close to the edge;
and placing an isolation material in the second isolation region to form a second isolation layer.
Optionally, the generating a gate electrode in the gate groove by using a sputtering method, generating a source electrode in the source groove, and generating a drain electrode in the drain groove specifically includes:
sputtering the SiN layer, the source electrode groove and the drain electrode groove to form an ohmic metal layer;
etching the third area and the fourth area on the ohmic metal layer to obtain a source electrode, a grid electrode and a drain electrode;
wherein the third region is located within a region of the first intermediate layer; the first intermediate layer is an ohmic metal layer between the source electrode groove and the grid electrode groove; the fourth region is located within a region of the second intermediate layer; the second intermediate layer is an ohmic metal layer between the gate groove and the drain groove.
Optionally, the etching from the top surface of the dielectric layer to the top surface of the P-GaN layer to obtain a first partial groove specifically includes:
and etching downwards on the top surface of the dielectric layer by using an ICP etching machine and extending to the top surface of the P-GaN layer, and annealing at a set temperature by using set gas to obtain a first part groove.
Optionally, the set gas is N 2 (ii) a The set temperature was 800 ℃.
According to the specific embodiment provided by the invention, the invention discloses the following technical effects:
the invention provides an enhanced GaN power device and a preparation method thereof, wherein the enhanced GaN power device comprises: the semiconductor device comprises a source electrode, a grid electrode, a drain electrode, a substrate, a buffer layer, an AlGaN layer, a P-GaN layer, a dielectric layer and a SiN layer, wherein the buffer layer, the AlGaN layer, the P-GaN layer, the dielectric layer and the SiN layer are sequentially grown from bottom to top; the buffer layer, the AlGaN layer, the P-GaN layer and the dielectric layer are all grown in MOCVD equipment, so that the preparation method of the power device is simpler, the one-time growth is completed, and the surface of the device can be more smooth. In addition, the dielectric layer is provided with a first partial groove, the first partial groove extends from the top surface of the dielectric layer to the top surface of the P-GaN layer, and the grid electrode is placed in the grid region; the grid region comprises a first partial groove and a second partial groove; the second partial groove is formed by etching a part of the SiN layer corresponding to the first partial groove, and the first partial groove is communicated with the second partial groove; the P-GaN corresponding to the lower part of the groove can be activated by arranging the first part of groove, so that the lower P-GaN plays a depletion role in the two-dimensional electron gas. The source electrode is arranged in a source electrode groove of the source electrode region, the source electrode groove is formed by etching downwards from a first region on the SiN layer to the inside of the buffer layer, and the source electrode is connected with a two-dimensional electron gas layer formed inside the buffer layer; the drain electrode is arranged in a drain electrode groove of the drain electrode area, the drain electrode groove is formed by etching downwards from a second area, different from the first area, on the SiN layer to the inner part of the buffer layer, and the drain electrode is connected with the two-dimensional electronic gas layer formed in the buffer layer, namely the two-dimensional electronic gas of other areas still exists except the grid electrode area, so that the function of the enhanced device is realized; in addition, the thickness of a medium layer grown in the MOCVD equipment is reduced, the compactness is good, and the P-GaN layer can be passivated more effectively, so that no holes are generated in the P-GaN layer, and the performance of the device is improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings without inventive exercise.
Fig. 1 is a structural diagram of an enhanced GaN power device according to an embodiment of the present invention;
FIG. 2 is a flow chart of a method for fabricating an enhanced GaN power device according to an embodiment of the invention;
FIG. 3 is a schematic diagram of process step 1 in the method for fabricating an enhanced GaN power device;
FIG. 4 is a schematic diagram of process step 2 in the method for fabricating an enhanced GaN power device;
FIG. 5 is a schematic diagram of process step 3 in the method for fabricating an enhanced GaN power device;
FIG. 6 is a schematic diagram of process step 4 in the method for fabricating an enhanced GaN power device;
fig. 7 is a schematic diagram of process step 5 in the method for fabricating an enhanced GaN power device.
Description of the symbols:
a source electrode-1, a gate electrode-2, a drain electrode-3, a first isolation layer-4, a second isolation layer-5, a two-dimensional electron gas layer-6, a first partial groove-7, a source groove-8, and a drain groove-9.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The invention aims to provide an enhanced GaN power device and a preparation method thereof, which can simply and efficiently improve the performance of the device; the enhancement mode GaN power device comprises: the semiconductor device comprises a source electrode, a grid electrode, a drain electrode, a substrate, a buffer layer, an AlGaN layer, a P-GaN layer, a dielectric layer and an SiN layer, wherein the buffer layer, the AlGaN layer, the P-GaN layer, the dielectric layer and the SiN layer are sequentially grown from bottom to top; the buffer layer, the AlGaN layer, the P-GaN layer and the dielectric layer are all grown in MOCVD equipment, so that the preparation method of the power device is simpler, the one-time growth is completed, and the surface of the device can be more smooth. In addition, the dielectric layer is provided with a first partial groove, the first partial groove extends from the top surface of the dielectric layer to the top surface of the P-GaN layer, and the grid electrode is placed in the grid region; the grid region comprises a first partial groove and a second partial groove; the second partial groove is formed by etching a part of the SiN layer corresponding to the first partial groove, and the first partial groove is communicated with the second partial groove; the P-GaN corresponding to the lower part of the groove can be activated by arranging the first part of groove, so that the lower P-GaN plays a depletion role in the two-dimensional electron gas. The source electrode is arranged in a source electrode groove of the source electrode region, the source electrode groove is formed by etching downwards from a first region on the SiN layer to the inside of the buffer layer, and the source electrode is connected with a two-dimensional electron gas layer formed inside the buffer layer; the drain electrode is arranged in a drain electrode groove of the drain electrode area, the drain electrode groove is formed by etching downwards from a second area, different from the first area, on the SiN layer to the inner part of the buffer layer, and the drain electrode is connected with the two-dimensional electronic gas layer formed in the buffer layer, namely the two-dimensional electronic gas of other areas still exists except the grid electrode area, so that the function of the enhanced device is realized; in addition, the thickness of a medium layer grown in the MOCVD equipment is reduced, the compactness is good, and the P-GaN layer can be passivated more effectively, so that no holes are generated in the P-GaN layer, and the performance of the device is improved.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in further detail below.
Example 1
As shown in fig. 1, the present embodiment provides an enhancement mode GaN power device including: the structure comprises a substrate, a Buffer (Buffer) layer, an AlGaN layer, a P-GaN layer, a dielectric layer, a SiN layer, a source electrode 1, a grid electrode 2 and a drain electrode 3. The dielectric layer may be an in situ SiN layer.
In the embodiment, a buffer layer, an AlGaN layer, a P-GaN layer, a dielectric layer and a SiN layer are sequentially grown on a substrate from bottom to top; the buffer layer, the AlGaN layer, the P-GaN layer and the dielectric layer are all grown in MOCVD equipment. The AlGaN layer is an aluminum gallium nitride layer, the P-GaN layer is a P-type gallium nitride layer, and the SiN layer is a silicon nitride layer. The silicon nitride layer serves as a passivation layer.
The dielectric layer is provided with a first partial groove; the first partial groove extends from the top surface of the dielectric layer to the top surface of the P-GaN layer.
Specifically, the thickness of the dielectric layer is 0.1nm-10000 nm.
The grid electrode 2 is placed in the grid groove; the grid electrode groove comprises a first partial groove and a second partial groove; the second partial groove is formed by etching the part of the SiN layer corresponding to the first partial groove; the first partial groove and the second partial groove are communicated.
The source electrode 1 is placed in the source groove; the source electrode groove is formed by etching downwards from a first region on the SiN layer to the inner part of the buffer layer; the source electrode 1 is connected to a two-dimensional electron gas layer 6 formed inside the buffer layer.
The drain electrode 3 is placed in the drain groove; the drain electrode groove is formed by etching downwards from the second region on the SiN layer to the inner part of the buffer layer; the drain electrode 3 is connected with a two-dimensional electron gas layer 6 formed inside the buffer layer; the first region is different from the second region.
Specifically, the enhancement mode GaN power device further comprises: a first isolation layer 4; etching a first isolation region at one side of the source electrode groove close to the edge; the first isolation region is formed by etching the top surface of the P-GaN layer to the inside of the buffer layer; an isolation material is placed in the first isolation region to form a first isolation layer 4.
Further, the enhancement mode GaN power device further comprises: a second isolation layer 5; etching a second isolation region at one side of the drain electrode groove close to the edge; the second isolation region is formed by etching the top surface of the P-GaN layer to the inside of the buffer layer; isolation material is placed in the second isolation region to form a second isolation layer 5.
Example 2
As shown in fig. 2, an embodiment of the present invention provides a method for manufacturing an enhanced GaN power device, where the method is used to manufacture any of the enhanced GaN power devices in embodiment 1, and the method includes:
s1: by adopting MOCVD equipment, a buffer layer, an AlGaN layer, a P-GaN layer and a dielectric layer are sequentially grown on a substrate from bottom to top.
S2: and etching the top surface of the dielectric layer downwards to the top surface of the P-GaN layer to obtain a first partial groove. Specifically, an ICP etching machine is used for etching downwards on the top surface of the dielectric layer and extending to the top surface of the P-GaN layer, and set gas is used for annealing at a set temperature to obtain a first partial groove. Further, setting the gas to be N2; the temperature was set at 800 ℃.
S3: and growing a SiN layer on the P-GaN layer etched with the first partial groove.
S4: and etching the part, corresponding to the first part of groove, on the SiN layer, so that the second part of groove obtained by etching is communicated with the first part of groove to form a gate groove.
S5: etching a first region on the SiN layer downwards to the inside of the buffer layer to form a source electrode groove; the source electrode groove penetrates through the two-dimensional electronic gas layer formed inside the buffer layer.
S6: etching a second region on the SiN layer downwards to the inner part of the buffer layer to form a drain electrode groove; the drain electrode groove penetrates through a two-dimensional electronic gas layer formed in the buffer layer; the first region is different from the second region.
S7: and generating a gate electrode in the gate groove by adopting a sputtering mode, generating a source electrode in the source groove, and generating a drain electrode in the drain groove to obtain the enhanced GaN power device.
Specifically, sputtering the SiN layer, the source electrode groove and the drain electrode groove to form an ohmic metal layer; and etching the third area and the fourth area on the ohmic metal layer to obtain a source electrode, a grid electrode and a drain electrode.
Wherein the third region is located within a region of the first intermediate layer; the first intermediate layer is an ohmic metal layer between the source electrode groove and the grid electrode groove; the fourth region is located within the region of the second intermediate layer; the second intermediate layer is an ohmic metal layer between the gate recess and the drain recess.
As an alternative embodiment, the preparation method further comprises: on one side of the source electrode groove close to the edge, etching downwards from the top surface of the P-GaN layer to the inner part of the buffer layer to form a first isolation region; and placing an isolation material in the first isolation region to form a first isolation layer.
Further, the preparation method also comprises the following steps: etching the top surface of the P-GaN layer to the inner part of the buffer layer from one side of the drain electrode groove close to the edge to form a second isolation region; an isolation material is placed in the second isolation region to form a second isolation layer.
MOCVD presented in the examples refers to a new vapor phase epitaxy growth technique developed on the basis of Vapor Phase Epitaxy (VPE). MOCVD is a process of vapor phase epitaxy on a substrate by thermal decomposition reaction to grow a thin layer of single crystal material. MOCVD equipment is equipment employing vapor phase epitaxial growth technology.
In practical application, the specific implementation process steps of the preparation method of the enhanced GaN power device provided by the invention can also be as follows:
the process comprises the following steps: as shown in fig. 3, the Si substrate is placed in MOCVD equipment, and a Buffer layer, an AlGaN layer, and a P-GaN layer are epitaxially grown in this order. And finally, epitaxially growing a dielectric layer (in situ SiN layer) for effectively passivating the P-GaN layer, so that no holes are generated in the P-GaN layer and depletion effect on two-dimensional electron gas is avoided. Meanwhile, the in situ SiN layer grown by using MOCVD has good compactness and can be better used as a dielectric layer on the surface of the epitaxial GaN.
The process step 2: as shown in fig. 4, the in situ SiN layer of the gate region is etched away by using an ICP etcher to expose the underlying P-GaN layer, to form a first partial groove 7, and then high temperature annealing is performed. For example: n of 800 ℃ can be adopted 2 And annealing, wherein after annealing, the P-GaN layer below the grid electrode is activated to provide holes, so that the two-dimensional electron gas below the grid electrode is exhausted (and the two-dimensional electron gas of other areas still exists).
And 3, a process step: as shown in fig. 5, a layer of SiN film is further grown on the surface of the wafer (i.e., the workpiece obtained after performing process step 2) by PECVD, and is used as a protective layer for the subsequent ohmic metal etching process. After the growth of the PECVD-SiN layer (i.e., the SiN layer) is completed, ion implantation is performed on the edge region of the device to isolate the active region.
And 4, a process step: as shown in fig. 6, ICP etching is performed on the respective regions of the source and drain to form a source recess 8 on the left and a drain recess 9 on the right, exposing the sidewalls of the P-GaN layer and the AlGaN layer.
And 5, a process step: as shown in fig. 7, the work piece subjected to the process step 4 is sputtered with an ohmic metal layer in a whole piece, and then subjected to ohmic metal etching to leave only the metal in the source and drain regions, thereby forming the source electrode 1 and the drain electrode 3.
The process step 6: and etching a passivation layer in the gate region, wherein the passivation layer is a silicon nitride layer, and then depositing gate metal to obtain a gate electrode 2, so as to obtain a final enhanced GaN power device, as shown in fig. 1.
In short, the implementation flow of the embodiment of the invention is as follows: firstly, a Buffer layer, an AlGaN layer and a P-GaN layer (epitaxial layer) are epitaxially grown on a Si substrate, and then an in situ SiN layer (dielectric layer) is continuously epitaxially grown on the surface of the P-GaN layer, so that the P-GaN layer is completely passivated. Secondly, etching off the in situ SiN layer in the grid region, and carrying out high-temperature annealing to activate the P-GaN layer below the grid; finally, ion implantation is carried out, and a source electrode, a drain electrode and a gate electrode are manufactured. An in situ SiN layer is epitaxially grown on the surface of the P-GaN layer of the obtained enhanced GaN power device, so that the P-GaN layer is passivated. Meanwhile, the high compactness of the in situ SiN layer can be used as a high-quality medium layer on the surface of the epitaxial layer. Wherein the in situ SiN layer has a thickness in the range of 0.1nm-10000 nm.
The preparation method provided by the invention does not need to carry out difficult P-GaN layer etching, but continues to grow a dielectric layer (i.e. in situ SiN layer) after the P-GaN layer is epitaxially grown, then etches the in situ SiN layer in the grid region in the process of manufacturing the process, carries out high-temperature annealing, and activates the P-GaN below the grid, so that the effect of exhausting two-dimensional electron gas is realized on the whole P-GaN layer and only the P-GaN below the grid, and the function of an enhanced device is realized. The method has simple process, avoids the damage of the P-GaN etching process to the surface of the AlGaN layer, and can realize the preparation of the high-performance enhanced GaN power device. In addition, the AlGaN layer, the P-GaN layer and the dielectric layer are all grown in MOCVD equipment, so that the process of epitaxial growth by adopting various equipment in the prior art is simplified, each layer can be grown at one time, and the surface of a workpiece is smoother. Moreover, compared with the dielectric layer existing in the prior art, the dielectric layer (i.e. the in situ SiN layer) of the enhanced GaN power device is thinner and has better compactness, so that the performance of the device can be improved.
The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other.
The principles and embodiments of the present invention have been described herein using specific examples, which are provided only to help understand the method and the core concept of the present invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, the specific embodiments and the application range may be changed. In view of the above, the present disclosure should not be construed as limiting the invention.

Claims (10)

1. An enhanced GaN power device, comprising: the device comprises a substrate, a buffer layer, an AlGaN layer, a P-GaN layer, a dielectric layer, an SiN layer, a source electrode, a grid electrode and a drain electrode;
the buffer layer, the AlGaN layer, the P-GaN layer, the dielectric layer and the SiN layer are sequentially grown on the substrate from bottom to top; the buffer layer, the AlGaN layer, the P-GaN layer and the dielectric layer are all grown in MOCVD equipment;
the dielectric layer is provided with a first partial groove; the first partial groove extends from the top surface of the dielectric layer to the top surface of the P-GaN layer;
the grid electrode is placed in the grid groove; the gate groove comprises a first partial groove and a second partial groove; the second partial groove is formed by etching a part of the SiN layer corresponding to the first partial groove; the first partial groove is communicated with the second partial groove;
the source electrode is placed in the source groove; the source electrode groove is formed by etching downwards from a first region on the SiN layer to the inner part of the buffer layer; the source electrode is connected with a two-dimensional electron gas layer formed in the buffer layer;
the drain electrode is placed in the drain groove; the drain electrode groove is formed by etching downwards from a second region on the SiN layer to the inner part of the buffer layer; the drain electrode is connected with a two-dimensional electron gas layer formed in the buffer layer; the first region is different from the second region.
2. The enhanced GaN power device of claim 1 further comprising: a first isolation layer;
etching the first isolation region at one side of the source electrode groove close to the edge; the first isolation region is formed by etching the top surface of the P-GaN layer to the inside of the buffer layer; and an isolation material is placed in the first isolation region to form a first isolation layer.
3. The enhanced GaN power device of claim 1 further comprising: a second isolation layer;
etching the second isolation region at one side of the drain electrode groove close to the edge; the second isolation region is formed by etching the top surface of the P-GaN layer to the inside of the buffer layer; and an isolation material is placed in the second isolation region to form a second isolation layer.
4. The enhanced GaN power device of claim 1 wherein the dielectric layer has a thickness of 0.1nm to 10000 nm.
5. A preparation method of an enhanced GaN power device, which is used for preparing the enhanced GaN power device of any of claims 1-4, and comprises the following steps:
growing a buffer layer, an AlGaN layer, a P-GaN layer and a dielectric layer on a substrate from bottom to top in sequence by using MOCVD equipment;
etching from the top surface of the dielectric layer to the top surface of the P-GaN layer downwards to obtain a first partial groove;
growing a SiN layer on the P-GaN layer etched with the first partial groove;
etching a part, corresponding to the first part of groove, on the SiN layer to enable a second part of groove obtained through etching to be communicated with the first part of groove to form a grid groove;
etching a first region on the SiN layer downwards to the inside of the buffer layer to form a source electrode groove; the source electrode groove penetrates through a two-dimensional electronic gas layer formed in the buffer layer;
etching a second region on the SiN layer downwards to the inner part of the buffer layer to form a drain electrode groove; the drain electrode groove penetrates through a two-dimensional electronic gas layer formed in the buffer layer; the first region is different from the second region;
and generating a gate electrode in the gate groove by adopting a sputtering mode, generating a source electrode in the source groove, and generating a drain electrode in the drain groove to obtain the enhanced GaN power device.
6. The method of fabricating an enhanced GaN power device according to claim 5, further comprising:
etching the top surface of the P-GaN layer downwards to the inner part of the buffer layer from the top surface of the P-GaN layer on one side of the source electrode groove close to the edge to form a first isolation region;
and placing an isolation material in the first isolation region to form a first isolation layer.
7. The method of fabricating an enhanced GaN power device according to claim 5, further comprising:
etching the top surface of the P-GaN layer to the inner part of the buffer layer from the top surface of the P-GaN layer to form a second isolation region on one side of the drain electrode groove close to the edge;
and placing an isolation material in the second isolation region to form a second isolation layer.
8. The method according to claim 5, wherein the forming a gate electrode in the gate groove, a source electrode in the source groove, and a drain electrode in the drain groove by sputtering comprises:
sputtering the SiN layer, the source electrode groove and the drain electrode groove to form an ohmic metal layer;
etching the third area and the fourth area on the ohmic metal layer to obtain a source electrode, a grid electrode and a drain electrode;
wherein the third region is located within a region of the first intermediate layer; the first intermediate layer is an ohmic metal layer between the source electrode groove and the grid electrode groove; the fourth region is located within a region of the second intermediate layer; the second intermediate layer is an ohmic metal layer between the gate groove and the drain groove.
9. The method of claim 5, wherein the etching from the top surface of the dielectric layer down to the top surface of the P-GaN layer to obtain a first partial groove comprises:
and etching downwards on the top surface of the dielectric layer by using an ICP etching machine and extending to the top surface of the P-GaN layer, and annealing at a set temperature by using set gas to obtain a first part groove.
10. The method of claim 9, wherein the set gas is N 2 (ii) a The set temperature was 800 ℃.
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