CN114883387A - SM-JTE terminal structure of novel floating junction silicon carbide power device and preparation method thereof - Google Patents
SM-JTE terminal structure of novel floating junction silicon carbide power device and preparation method thereof Download PDFInfo
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- 229910010271 silicon carbide Inorganic materials 0.000 title claims abstract description 31
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 title claims abstract description 29
- 238000002360 preparation method Methods 0.000 title claims abstract description 8
- 239000000758 substrate Substances 0.000 claims abstract description 64
- 238000000034 method Methods 0.000 claims abstract description 30
- 238000004519 manufacturing process Methods 0.000 claims abstract description 25
- 238000005468 ion implantation Methods 0.000 claims abstract description 14
- 238000005229 chemical vapour deposition Methods 0.000 claims description 8
- 230000003247 decreasing effect Effects 0.000 claims 1
- 230000005684 electric field Effects 0.000 abstract description 10
- 238000010586 diagram Methods 0.000 description 6
- 230000007423 decrease Effects 0.000 description 4
- 238000009826 distribution Methods 0.000 description 4
- 230000035945 sensitivity Effects 0.000 description 3
- 238000000137 annealing Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 230000001419 dependent effect Effects 0.000 description 1
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- 239000004065 semiconductor Substances 0.000 description 1
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
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- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
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Abstract
The invention discloses an SM-JTE terminal structure of a novel floating junction silicon carbide power device and a preparation method thereof, wherein the method comprises the following steps: providing an N + substrate; manufacturing at least one layer of epitaxial structure on the surface of one side of the N + substrate; the epitaxial structure includes: the first N-epitaxial layer, and a floating junction p region and a JTE region which are formed after ion implantation is carried out on the surface of one side of the first N-epitaxial layer, which is far away from the N + substrate; growing a second N-epitaxial layer on the surface of one side of the at least one layer of epitaxial structure, which is far away from the N + substrate, and manufacturing a surface terminal; growing an oxide layer on the surface of one side of the second N-epitaxial layer far away from the substrate; and manufacturing a first electrode on the surface of one side of the second N-epitaxial layer far away from the substrate, and manufacturing a second electrode on the surface of one side of the N + substrate far away from the epitaxial structure, wherein the first electrode is contacted with the oxide layer. The invention divides the JTE area into a plurality of SMJTE structures, and can disperse the single-point electric field peak value of the JTE area to the SMJTE structures, thereby reducing the electric field peak value and simultaneously leading the power device to have stronger dose offset resistance.
Description
Technical Field
The invention belongs to the technical field of semiconductors, and particularly relates to an SM-JTE (Space Modulated Junction Termination Extension) terminal structure of a novel floating Junction silicon carbide power device and a preparation method thereof.
Background
In order to improve the performance of the 4H-SiC power device, a 'super junction' structure represented by a floating junction is applied to the relevant power device. The floating junction structure is formed by adding one or more discontinuous P + structures into an epitaxial layer of a traditional 4H-SiC power device, and is similar to a PN junction structure formed in the epitaxial layer. When the device works in a reverse state, the floating junction structure is added to change the originally triangular or trapezoidal electric field distribution in the epitaxial layer into an upper triangular distribution and a lower triangular distribution by taking the floating junction as a dividing line, so that the reverse breakdown voltage of the device is improved under the condition that the thickness and the concentration of the epitaxial layer are unchanged.
However, because the floating junction structure is added to the conventional device, the influence of various factors such as the epitaxial layer structure, the source region floating junction structure, the terminal region floating junction structure and the terminal structure on the device performance needs to be comprehensively considered when designing the device structure, and the design is complex. Therefore, it is necessary to perform design optimization research on the termination structure of the floating junction device in the related art to ensure the performance of the floating junction structure.
Disclosure of Invention
In order to solve the problems in the prior art, the invention provides a novel SM-JTE terminal structure of a floating junction silicon carbide power device and a preparation method thereof. The technical problem to be solved by the invention is realized by the following technical scheme:
in a first aspect, the present invention provides a method for preparing an SM-JTE terminal structure of a novel floating junction silicon carbide power device, comprising:
providing an N + substrate;
manufacturing at least one layer of epitaxial structure on one side surface of the N + substrate; the epitaxial structure includes: the first N-epitaxial layer, and a floating junction p region and a JTE region which are formed after ion implantation is carried out on the surface of one side, far away from the N + substrate, of the first N-epitaxial layer; the floating junction p region is positioned in an active region, the JTE region is positioned in a termination region, and the JTE region comprises a plurality of SMJTE structures which are arranged along a first direction; the first direction is a direction in which the active region points to the terminal region;
growing a second N-epitaxial layer on the surface of one side, far away from the N + substrate, of the at least one epitaxial structure, and manufacturing a surface terminal in the second N-epitaxial layer;
growing an oxide layer on the surface of one side, far away from the substrate, of the second N-epitaxial layer;
and manufacturing a first electrode on the surface of one side of the second N-epitaxial layer, which is far away from the substrate, and manufacturing a second electrode on the surface of one side of the N + substrate, which is far away from the epitaxial structure, wherein the first electrode is in contact with the oxide layer.
In one embodiment of the present invention, the epitaxial structure is prepared by the following steps:
growing a first N-epitaxial layer on the surface of one side of the N + substrate by utilizing a Chemical Vapor Deposition (CVD) process;
performing active region Al ion implantation on the surface of one side of the first N-epitaxial layer, which is far away from the N + substrate, to form a floating junction p region;
and carrying out Al ion implantation in a terminal region on the surface of one side of the first N-epitaxial layer, which is far away from the N + substrate, so as to form a JTE region.
In one embodiment of the invention, in the first direction, the widths of the plurality of SMJTE structures in the first direction gradually decrease, and the distances between two adjacent SMJTE structures gradually increase.
In one embodiment of the invention, in the first direction, the width of the SMJTE structure is 1 to 100 μm, and the distance between two adjacent SMJTE structures is 1 to 10 μm.
In one embodiment of the present invention, the doping concentration of the JTE region is 1 × 10 16 ～1×10 18 cm -3 。
In one embodiment of the invention, the thickness of the SMJTE structure is 0.5-2 μm in the direction perpendicular to the plane of the N + substrate.
In one embodiment of the invention, the doping concentration of the floating junction p region is 1 multiplied by 10 16 ～1×10 20 cm -3 。
In one embodiment of the present invention, the floating junction p-region includes a plurality of floating junctions arranged in a first direction;
in the first direction, the width of the floating knot is 1-5 mu m, and the distance between two adjacent floating knots is 1-5 mu m.
In one embodiment of the invention, the doping concentration of the N + substrate is 1 × 10 18 ～1×10 20 cm -3 And the thickness of the N + substrate is 50-400 mu m along the direction vertical to the plane of the N + substrate.
In a second aspect, the invention further provides an SM-JTE terminal structure of a novel floating junction silicon carbide power device, which is prepared by the method for preparing the SM-JTE terminal structure of the novel floating junction silicon carbide power device in the first aspect.
Compared with the prior art, the invention has the beneficial effects that:
the invention provides a novel SM-JTE terminal structure of a floating junction silicon carbide power device and a preparation method thereof, wherein a JTE region is formed in a terminal region of the power device and comprises a plurality of SMJTE structures arranged along a first direction, and the mode of dividing the JTE region into the plurality of SMJTE structures can disperse single-point electric field peak values of the JTE region to the SMJTE structures, so that the electric field peak values are reduced; furthermore, the sensitivity of SMJTE to the dose is reduced, and the dose window is enlarged, so that the power device has stronger dose offset resistance.
The present invention will be described in further detail with reference to the accompanying drawings and examples.
Drawings
Fig. 1 is a flowchart of a method for manufacturing an SM-JTE termination structure of a novel floating junction silicon carbide power device according to an embodiment of the present invention;
fig. 2 is a schematic diagram of a method for manufacturing an SM-JTE termination structure of a novel floating junction silicon carbide power device according to an embodiment of the present invention;
FIG. 3 is another schematic diagram of a method for fabricating an SM-JTE termination structure for a novel floating junction silicon carbide power device according to an embodiment of the present invention;
FIG. 4 is another schematic diagram of a method for fabricating an SM-JTE termination structure for a novel floating junction silicon carbide power device according to an embodiment of the present invention;
FIG. 5 is another schematic diagram of a method for fabricating an SM-JTE termination structure for a novel floating junction silicon carbide power device according to an embodiment of the present invention;
fig. 6 is another schematic diagram of a method for manufacturing an SM-JTE termination structure of a novel floating-junction silicon carbide power device according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to specific examples, but the embodiments of the present invention are not limited thereto.
Fig. 1 is a flowchart of a method for manufacturing an SM-JTE terminal structure of a novel floating-junction silicon carbide power device according to an embodiment of the present invention, and fig. 2 to 6 are schematic diagrams of a method for manufacturing an SM-JTE terminal structure of a novel floating-junction silicon carbide power device according to an embodiment of the present invention. Referring to fig. 1 to 6, an embodiment of the present invention provides a method for manufacturing an SM-JTE terminal structure of a novel floating junction silicon carbide power device, including:
s1, providing an N + substrate 1;
s2, manufacturing at least one epitaxial structure 2 on one side surface of the N + substrate 1; the epitaxial structure 2 includes: a first N-epitaxial layer 201, and a floating junction p region 202 and a JTE region 203 which are formed after ion implantation is carried out on the surface of one side of the first N-epitaxial layer 201 far away from the N + substrate 1; the floating junction p region 202 is located in an active region, the JTE region 203 is located in a termination region, and the JTE region 203 includes a plurality of SMJTE structures arranged along a first direction; the first direction is the direction in which the active region points to the termination region;
s3, growing a second N-epitaxial layer 3 on the surface of one side, far away from the N + substrate 1, of the at least one epitaxial structure 2, and manufacturing a surface terminal in the second N-epitaxial layer 3;
s4, growing an oxide layer on the surface of one side, far away from the substrate, of the second N-epitaxial layer 3;
s5, manufacturing a first electrode 5 on the surface of one side of the second N-epitaxial layer 3 far away from the substrate, and manufacturing a second electrode 6 on the surface of one side of the N + substrate 1 far away from the epitaxial structure 2, wherein the first electrode 5 is in contact with the oxide layer.
Specifically, in the method for preparing the SM-JTE termination structure of the floating junction silicon carbide power device according to the embodiment of the present invention, first, an N + substrate shown in fig. 2 is provided, and an epitaxial structure 2 is formed on a side surface of the N + substrate 1, referring to fig. 3, where the epitaxial structure 2 may include: a first N-epitaxial layer 201, a floating junction p region 202 and a JTE region 203; the floating junction p region 202 and the JTE region 203 are formed by performing ion implantation on a surface of a side of the first N-epitaxial layer 201 away from the N + substrate 1, the floating junction p region 202 is located in the active region, and the JTE region is located in the termination region, and the JTE region 203 includes a plurality of SMJTE structures arranged along a first direction, where the first direction is: the active region points in the direction of the termination region.
Alternatively, in step S2, the epitaxial structure 22 located above the N + substrate 11 may be a layer or multiple layers, which is not limited in this application.
Further, as shown in fig. 4-6, after the epitaxial structure 2 is manufactured, a second N-epitaxial layer 3 is grown on the surface of one side of at least one layer of the epitaxial structure 2 away from the N + substrate 1, a surface termination is manufactured in the second N-epitaxial layer 3, and then an oxide layer is grown on the surface of one side of the second N-epitaxial layer 3 away from the substrate by using a thermal oxidation process, wherein the oxidation temperature is 1100 ℃ to 1400 ℃. Finally, depositing metal layers on the surface of one side, away from the substrate, of the second N-epitaxial layer 3 and the surface of one side, away from the epitaxial structure 2, of the N + substrate 1, and respectively forming a first electrode 5 positioned on the upper surface of the second N-epitaxial layer 3 and a second electrode 6 positioned on the lower surface of the N + substrate 1 through an annealing process; illustratively, the metal deposited in step S5 may be Ti, Ni, etc., and the annealing temperature is 400-1000 ℃.
In this embodiment, the first electrode 5 may be an ohmic contact or a schottky contact, and the second electrode 6 may be an ohmic contact.
It should be understood that in the above termination structure provided by the present invention, the termination region of the power device forms the JTE region 203, and the JTE region 203 includes a plurality of SMJTE structures arranged along the first direction, such that the manner of dividing the JTE region 203 into a plurality of SMJTE structures can disperse the electric field peak of a single point of the JTE region 203 to the SMJTE structures, thereby reducing the electric field peak; furthermore, the sensitivity of SMJTE to the dose is reduced, and the dose window is enlarged, so that the power device has stronger dose offset resistance.
With continued reference to fig. 3, the epitaxial structure 2 is fabricated by the following steps:
growing a first N-epitaxial layer 201 on the surface of one side of the N + substrate 1 by using a Chemical Vapor Deposition (CVD) process;
performing active region Al ion implantation on the surface of one side of the first N-epitaxial layer 201, which is far away from the N + substrate 1, to form a floating junction p region 202;
and carrying out terminal region Al ion implantation on the surface of one side of the first N-epitaxial layer 201, which is far away from the N + substrate 1, so as to form a JTE region 203.
Specifically, in the process of manufacturing the epitaxial structure 2, firstly, a first N-epitaxial layer 201 is grown on one side surface of the N + substrate 1 by using a CVD (Chemical Vapor Deposition) process, wherein the growth temperature is 1600 ℃ to 1900 ℃; then, performing active region ion implantation on the surface of one side of the first N-epitaxial layer 201, which is far away from the N + substrate 1, wherein the implanted ions are Al and the implantation energy is 10 keV-800 keV, and forming a floating junction p region 202; furthermore, terminal region ion implantation is performed on the surface of one side of the first N-epitaxial layer 201 away from the N + substrate 1, the implanted ions are Al, the implantation energy is 10keV to 800keV, and after a plurality of SMJTE regions 203 are formed, a JTE region 203 is obtained.
Obviously, by repeating the above steps, an epitaxial structure 2 of an arbitrary layer can be formed on the upper surface of the N + substrate 1; in addition, the manufacturing process of the second N-epitaxial layer 3 on the surface of the side of the epitaxial structure 2 away from the N + substrate 1 is the same as that of the first N-epitaxial layer 201, and therefore, the details are not repeated here.
Optionally, in the first direction, the widths of the plurality of SMJTE structures in the first direction gradually decrease, and the spacing between two adjacent SMJTE structures gradually increases.
For the termination structure of a power device, the dose required at the outer side is usually smaller than that at the inner side, and the SMJTE structure is implemented by one ion implantation, so that the widths of a plurality of SMJTE structures are sequentially reduced along the direction from the active region to the termination region. Illustratively, the SMJTE structure has a width in the first direction of 1 to 100 μm.
It should be understood that, when the SMJTE structure is designed, the width of each SMJTE itself and the sum of the distances between the SMJTE itself and the adjacent SMJTEs need to be kept the same, and since the amount of charge required by the SMJTE structure decreases with increasing distance between the SMJTE structure and the main junction, the width of the SMJTE gradually decreases and the distance between the adjacent SMJTEs gradually increases in the direction from the active region to the termination region. Wherein, in the first direction, the distance between two adjacent SMJTE structures is 1-10 μm.
Optionally, the doping concentration of the JTE region 203 in this embodiment is 1 × 10 16 ～1×10 18 cm -3 ；
The thickness of the SMJTE structure is 0.5-2 μm along the direction perpendicular to the plane of the N + substrate 1.
Optionally, the floating junction p-region 202 has a doping concentration of 1 × 10 16 ～1×10 20 cm -3 。
In this embodiment, the floating junction p-region 202 includes a plurality of floating junctions arranged in a first direction; wherein, in the first direction, the width of the floating knot is 1-5 μm, and the distance between two adjacent floating knots is 1-5 μm.
Specifically, the floating junction p region 202 comprises a plurality of floating junctions arranged along a first direction, the distance between two adjacent floating junctions is 1-5 μm, the width of each floating junction in the first direction is 1-5 μm, and the thickness of each floating junction in the direction perpendicular to the plane of the N + substrate 1 is 0.5-2.0 μm. In the embodiment, the floating junction is introduced to enable the electric field distribution of the active region to be uniform, and further the breakdown voltage of the device is improved.
It should be noted that the shape of each floating junction in the floating junction p region may be a rectangle, a bar, or a polygon, which is not limited in this application.
Optionally, the doping concentration of the N + substrate 1 is 1 × 10 18 ～1×10 20 cm -3 And the thickness of the N + substrate 1 is 50-400 mu m along the direction vertical to the plane of the N + substrate 1.
As shown in fig. 6, an embodiment of the present invention further provides an SM-JTE terminal structure of a novel floating junction silicon carbide power device, which is manufactured by the above method for manufacturing an SM-JTE terminal structure of a novel floating junction silicon carbide power device.
The beneficial effects of the invention are that:
the invention provides a novel SM-JTE terminal structure of a floating junction silicon carbide power device and a preparation method thereof, wherein a JTE region is formed in a terminal region of the power device and comprises a plurality of SMJTE structures arranged along a first direction, and the mode of dividing the JTE region into the plurality of SMJTE structures can disperse single-point electric field peak values of the JTE region to the SMJTE structures, so that the electric field peak values are reduced; furthermore, the sensitivity of SMJTE to the dose is reduced, and the dose window is enlarged, so that the power device has stronger dose offset resistance.
In the description of the present invention, it is to be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", and the like, indicate orientations and positional relationships based on those shown in the drawings, and are used only for convenience of description and simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be considered as limiting the present invention.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise.
In the present invention, unless otherwise expressly stated or limited, "above" or "below" a first feature means that the first and second features are in direct contact, or that the first and second features are not in direct contact but are in contact with each other via another feature therebetween. Also, the first feature being "on," "above" and "over" the second feature includes the first feature being directly on and obliquely above the second feature, or merely indicating that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature includes the first feature being directly under and obliquely below the second feature, or simply meaning that the first feature is at a lesser elevation than the second feature.
In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples described in this specification can be combined and combined by those skilled in the art.
While the present application has been described in connection with various embodiments, other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed application, from a review of the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other elements or steps, and the word "a" or "an" does not exclude a plurality. A single processor or other unit may fulfill the functions of several items recited in the claims. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.
The foregoing is a more detailed description of the invention in connection with specific preferred embodiments and it is not intended that the invention be limited to these specific details. For those skilled in the art to which the invention pertains, several simple deductions or substitutions can be made without departing from the spirit of the invention, and all shall be considered as belonging to the protection scope of the invention.
Claims (10)
1. A method for preparing an SM-JTE terminal structure of a novel floating junction silicon carbide power device is characterized by comprising the following steps:
providing an N + substrate;
manufacturing at least one layer of epitaxial structure on one side surface of the N + substrate; the epitaxial structure includes: the first N-epitaxial layer, and a floating junction p region and a JTE region which are formed after ion implantation is carried out on the surface of one side, far away from the N + substrate, of the first N-epitaxial layer; the floating junction p region is positioned in an active region, the JTE region is positioned in a termination region, and the JTE region comprises a plurality of SMJTE structures which are arranged along a first direction; the first direction is a direction in which the active region points to the terminal region;
growing a second N-epitaxial layer on the surface of one side, far away from the N + substrate, of the at least one epitaxial structure, and manufacturing a surface terminal in the second N-epitaxial layer;
growing an oxide layer on the surface of one side, far away from the substrate, of the second N-epitaxial layer;
and manufacturing a first electrode on the surface of one side of the second N-epitaxial layer, which is far away from the substrate, and manufacturing a second electrode on the surface of one side of the N + substrate, which is far away from the epitaxial structure, wherein the first electrode is in contact with the oxide layer.
2. The method for preparing the SM-JTE terminal structure of the novel floating junction silicon carbide power device according to claim 1, wherein the epitaxial structure is prepared by the following steps:
growing a first N-epitaxial layer on the surface of one side of the N + substrate by utilizing a Chemical Vapor Deposition (CVD) process;
performing active region Al ion implantation on the surface of one side of the first N-epitaxial layer, which is far away from the N + substrate, to form a floating junction p region;
and carrying out Al ion implantation in a terminal region on the surface of one side of the first N-epitaxial layer, which is far away from the N + substrate, so as to form a JTE region.
3. The method of claim 1, wherein in the first direction, the widths of the SMJTE structures in the first direction are gradually decreased, and the distance between two adjacent SMJTE structures is gradually increased.
4. The method for preparing an SM-JTE terminal structure of a novel floating junction silicon carbide power device according to claim 3, wherein in the first direction, the width of the SMJTE structure is 1 to 100 μm, and the distance between two adjacent SMJTE structures is 1 to 10 μm.
5. The method for preparing SM-JTE termination structure of novel floating junction silicon carbide power device according to claim 4, wherein the doping concentration of the JTE region is 1 x 10 16 ～1×10 18 cm -3 。
6. The method for preparing an SM-JTE terminal structure of a novel floating junction silicon carbide power device according to claim 5, wherein the thickness of the SMJTE structure is 0.5 to 2 μm in a direction perpendicular to the plane of the N + substrate.
7. The method of claim 1, wherein the floating-junction p-region has a doping concentration of 1 x 10 16 ～1×10 20 cm -3 。
8. The method of claim 7, wherein the floating-junction p-region comprises a plurality of floating junctions arranged along a first direction;
in the first direction, the width of the floating junctions is 1-5 micrometers, and the distance between every two adjacent floating junctions is 1-5 micrometers.
9. The method of claim 1, wherein the N + substrate has a doping concentration of 1 x 10 18 ～1×10 20 cm -3 And the thickness of the N + substrate is 50-400 mu m along the direction vertical to the plane of the N + substrate.
10. A novel SM-JTE terminal structure of a floating junction silicon carbide power device, which is characterized by being prepared by the preparation method of the SM-JTE terminal structure of the novel floating junction silicon carbide power device disclosed by any one of claims 1 to 9.
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|---|---|---|---|---|
| CN117613105A (en) * | 2024-01-22 | 2024-02-27 | 西安电子科技大学 | Diode of silicon carbide floating junction for improving switching characteristics and preparation method thereof |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117613105A (en) * | 2024-01-22 | 2024-02-27 | 西安电子科技大学 | Diode of silicon carbide floating junction for improving switching characteristics and preparation method thereof |
| CN117613105B (en) * | 2024-01-22 | 2024-05-14 | 西安电子科技大学 | Diode of silicon carbide floating junction for improving switching characteristics and preparation method thereof |
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