CN114882849A

CN114882849A - GOA circuit and display panel

Info

Publication number: CN114882849A
Application number: CN202210521921.7A
Authority: CN
Inventors: 赖谷皇
Original assignee: Guangzhou China Star Optoelectronics Semiconductor Display Technology Co Ltd
Current assignee: Guangzhou China Star Optoelectronics Semiconductor Display Technology Co Ltd
Priority date: 2022-05-13
Filing date: 2022-05-13
Publication date: 2022-08-09
Anticipated expiration: 2042-05-13
Also published as: CN114882849B

Abstract

The application relates to a GOA circuit and a display panel, which comprise a plurality of cascaded GOA units, wherein if the nth GOA unit is the GOA unit in the previous two levels, an up-down pull control module is connected with a GSP signal, an m-2 level clock signal line and a first node, otherwise, the up-down pull control module is connected with a signal output end of the nth-2 level GOA unit, the m-2 level clock signal line and the first node; the upper pull-down module is connected with the mth level clock signal line, the first node and the second node; the capacitance module is connected with the first node and the second node; the pull-down maintaining module is connected with the mth level clock signal line, the first node, the second node and a third node connected with the first low level signal; the touch function adjusting module is connected with the Tp signal, the second node and the third node; and if the nth grade GOA unit is the GOA unit in the previous three grades, the first clearing module is connected with the VSS signal, the first node and the third node, otherwise, the first clearing module is connected with the GSP signal, the first node and the third node. The method and the device can effectively reduce the layout area of the panel and the loading of the touch module.

Description

GOA circuit and display panel

Technical Field

The application relates to the technical field of display, in particular to a GOA circuit and a display panel.

Background

With the continuous iterative development of display technologies, a Gate On Array (GOA) circuit is required in a panel driving architecture from a conventional liquid crystal display panel to a recently marketed self-luminous display panel to provide a gate driving signal required by the panel, so that the panel can work normally. Meanwhile, in recent years, manufacturers try to add originally external Touch modules to the panel, but after the panel is added to the Touch modules, the operation of the GOA circuit needs to be suspended when the sensors read sensing data. Therefore, if a Touch module is added to the GOA circuit during development, how to maintain the TFT charge leakage for a long time and ensure the normal of the dark panel wake-up function in the panel display are problems that need to be solved at present.

Disclosure of Invention

Therefore, it is necessary to provide a GOA circuit and a display panel for solving the technical problem in the prior art that how to ensure that TFT charges remain without leakage for a long time and the dark screen wake-up function of the display panel is normal after the GOA circuit is added with a Touch module.

In order to achieve the above object, in one aspect, the present application provides a GOA circuit, where the GOA circuit includes a plurality of cascaded GOA units, and each GOA unit includes an up-down pull control module, an up-down pull module, a down-pull maintenance module, a capacitance module, a first clearing module, and a touch function adjusting module;

if the nth-level GOA unit is a GOA unit in the previous two levels, the corresponding pull-up and pull-down control module is respectively connected with a GSP signal, an m-2-level clock signal line Ck (m-2) and a first node, if the nth-level GOA unit is a GOA unit behind the previous two levels, the corresponding pull-up and pull-down control module is respectively connected with a signal output end G (n-2) of the nth-2-level GOA unit, an m-2-level clock signal line Ck (m-2) and the first node, wherein n and m are positive integers;

the pull-up and pull-down module is respectively connected with an m-th level clock signal line Ckm, a first node and a second node;

the capacitance module is respectively connected with the first node and the second node;

the pull-down maintaining module is respectively connected with an m-th level clock signal line Ckm, a first node, a second node and a third node, wherein the third node is connected with a first low level signal;

the touch function adjusting module respectively contacts the control scanning signal Tp, the second node and the third node;

if the nth grade GOA unit is a GOA unit in the previous three grades, the first clearing module is respectively connected with the VSS signal, the first node and the third node, and if the nth grade GOA unit is a GOA unit behind the previous three grades, the first clearing module is respectively connected with the GSP signal, the first node and the third node.

Optionally, if the nth-stage GOA unit is a GOA unit in the previous two stages, the first end of the first sub-thin film transistor included in the corresponding up-down pull control module is connected to the GSP signal, and if the nth-stage GOA unit is a GOA unit after the previous two stages, the first end of the first sub-thin film transistor included in the corresponding up-down pull control module is connected to the signal output end G (n-2) of the nth-2-stage GOA unit;

the grid electrode of the first sub thin film transistor and the grid electrode of the second sub thin film transistor contained in the up-down pulling control module are both connected with the (m-2) th-level clock signal line Ck (m-2);

the second end of the first sub thin film transistor and the first end of the second sub thin film transistor are both connected with the sixth node;

the grid electrode of a fourth sub thin film transistor contained in the up-down pulling control module is connected with the first node, and the first end of the fourth sub thin film transistor is connected with the sixth node;

the grid electrode and the second end of the third sub-thin film transistor contained in the up-down pulling control module are both contacted with a control scanning signal Tp, and the first end of the third sub-thin film transistor is connected with the second end of the fourth sub-thin film transistor.

Optionally, a gate of a fiftieth thin film transistor included in the touch function adjusting module is connected to the touch scanning signal Tp, the first end of the fiftieth thin film transistor is connected to the second node, and the second end of the fiftieth thin film transistor is connected to the third node.

In order to achieve the above object, in another aspect, an embodiment of the present application further provides a GOA circuit, where the GOA circuit includes a plurality of cascaded GOA units, and each GOA unit includes an upper pull-down control module, an upper pull-down module, a pull-down maintaining module, a capacitance module, and a first clearing module;

if the nth-level GOA unit is a GOA unit in the previous three levels, the first clearing module is respectively connected with the VSS signal, the first node and the third node, and if the nth-level GOA unit is a GOA unit behind the previous three levels, the first clearing module is respectively connected with the GSP signal, the first node and the third node;

if the nth-level GOA unit is a GOA unit in the previous two levels, the first end of the first sub-thin film transistor included in the corresponding upper and lower pull control module is connected with a GSP signal, and if the nth-level GOA unit is a GOA unit after the previous two levels, the first end of the first sub-thin film transistor included in the corresponding upper and lower pull control module is connected with a signal output end G (n-2) of the nth-2-level GOA unit;

Optionally, a gate of a seventh thin film transistor included in the up-down pulling module is connected to the first node, a first end of the seventh thin film transistor is connected to the mth clock signal line Ckm, and a second end of the seventh thin film transistor is connected to the second node;

the first end of a first capacitor contained in the capacitor module is connected with the first node, and the second end of the first capacitor is connected with the second node;

if the nth-level GOA unit is a GOA unit in the previous three levels, the grid electrode of a sixth thin film transistor included in the first clearing module is connected with the VSS signal, and if the nth-level GOA unit is a GOA unit behind the previous three levels, the grid electrode of the sixth thin film transistor included in the first clearing module is connected with the GSP signal;

the first end of the sixth thin film transistor is connected with the first node, and the second end of the sixth thin film transistor is connected with the third node.

Optionally, gates of a third thin film transistor and a fifth thin film transistor included in the pull-down maintaining module are connected to the first node, a first end of the third thin film transistor is connected to the fourth node, a second end of the third thin film transistor is connected to the third node, a first end of the fifth thin film transistor is connected to the fifth node, and a second end of the fifth thin film transistor is connected to the third node;

a first end of a second capacitor contained in the pull-down maintaining module is connected with the mth level clock signal line Ckm, and a second end of the second capacitor is connected with a fourth node;

a grid electrode of a fourth thin film transistor contained in the pull-down maintaining module is connected with a fourth node, a first end of the fourth thin film transistor is connected with the mth level clock signal line Ckm, and a second end of the fourth thin film transistor is connected with a fifth node;

the gate of the eighth thin film transistor included in the pull-down maintaining module is connected to the fifth node, the first end is connected to the second node, and the second end is connected to the third node.

Optionally, each GOA unit further comprises at least one of a second purge module, a third purge module, and a fourth purge module;

the second clearing module is used for clearing the voltage of the first node under the control of the first clearing signal;

the third clearing module is used for clearing the voltage of the fifth node under the control of the second clearing signal;

the fourth clearing module is used for clearing the voltage of the second node under the control of the third clearing signal.

Optionally, the second clear module includes a ninth thin film transistor, a gate of the ninth thin film transistor is connected to the first clear signal line, a first end of the ninth thin film transistor is connected to the second node, and a second end of the ninth thin film transistor is connected to the second low-level signal;

and/or the presence of a gas in the gas,

the third clearing module comprises a tenth thin film transistor, the grid electrode of the tenth thin film transistor is connected with the second clearing signal line, the first end of the tenth thin film transistor is connected with the sixth node, and the second end of the tenth thin film transistor is connected with the third low-level signal;

and/or the presence of a gas in the gas,

the fourth clearing module comprises an eleventh thin film transistor, wherein the grid electrode of the eleventh thin film transistor is connected with the third clearing signal line, the first end of the eleventh thin film transistor is connected with the third node, and the second end of the eleventh thin film transistor is connected with the fourth low-level signal.

Optionally, the number of the clock signals included in one action period corresponds to the duty ratio of the clock signals, the clock signals included in one action period are sequentially effective in a time-sharing manner in the action period of the GOA circuit, and the pulse widths of the high-level signals in the same clock signal are all shorter than the pulse width of the low-level signal.

Optionally, if the number of the clock signals included in one action period is 6, the duty ratio of the clock signals is 50%;

if the number of clock signals included in one active period is 4, the duty ratio of the clock signal is 40% or 60%.

In order to achieve the foregoing object, in another aspect, an embodiment of the present application further provides a display panel, where the display panel includes a display module and a GOA circuit of any one of the foregoing modules; the GOA circuit is electrically connected with the display module and used for driving the display module to emit light.

One of the above technical solutions has the following advantages and beneficial effects:

according to the method and the device, the GSP signal during starting is utilized to effectively control the first clearing module to clear the voltage of the first node, so that the defects during initial driving of the GOA are reduced, and the risk of abnormal starting lighting pictures is reduced. The periodic clock signal and the output signal of the previous stage are used for controlling the pull-up and pull-down control module to charge the capacitor of the first node, the periodic clock signal and the voltage of the first node are used for controlling the pull-up and pull-down module to be turned on or turned off, and the output Gout of the GOA is synchronously made to be high potential when the periodic clock signal is changed into the high potential, so that the corresponding Pixel TFT is effectively turned on. The pull-down maintaining module is utilized to enable the output voltage Gout of the GOA to maintain the low level of Gout so that the corresponding Pixel TFT can be effectively turned off. The Touch function adjusting module is used for driving the panel to keep the same coupling between the output of the GOA unit and a Touch sensor (Touch sensor) in the Touch stage, and Touch sensor loading is reduced. According to the GOA circuit, the wiring quantity and the circuit layout area in the GOA circuit are effectively reduced by utilizing the collocation of the periodic clock signals and the TFTs. The GOA circuit is suitable for the panel requirement of the narrow frame. By utilizing the matching of the output signal waveform of the GOA unit and Touch, the Loading of a Touch module is effectively reduced, and the sensitivity of Touch and the function of maintaining dark screen awakening can be improved.

Drawings

Fig. 1 is a block diagram of a GOA unit according to an embodiment of the present disclosure.

Fig. 2 is a schematic diagram of a panel circuit in the prior art.

Fig. 3 is a circuit diagram of a pull-up/pull-down control module according to an embodiment of the present disclosure.

Fig. 4 is a circuit diagram of a pull-up/pull-down control module according to another embodiment of the present disclosure.

Fig. 5 is a circuit diagram of a GOA unit according to an embodiment of the present disclosure.

Fig. 6 is a circuit diagram of a GOA unit according to another embodiment of the present disclosure.

Fig. 7 is a circuit diagram of a GOA unit according to another embodiment of the present disclosure.

Fig. 8 is a circuit diagram of a GOA unit according to another embodiment of the present disclosure.

Fig. 9 is a schematic driving diagram of a panel according to an embodiment of the present application.

Fig. 10 is a waveform diagram of a multi-channel signal according to an embodiment of the present application.

Wherein the reference numerals are as follows:

the touch screen display device comprises an upper pull-down control module 100, an upper pull-down module 200, a pull-down maintaining module 300, a capacitance module 400, a first clearing module 500 and a touch function adjusting module 600.

Detailed Description

To facilitate an understanding of the present application, the present application will now be described more fully with reference to the accompanying drawings. Preferred embodiments of the present application are shown in the drawings. This application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

It will be understood that when an element is referred to as being "connected" to another element, it can be directly connected to the other element and be integral therewith, or intervening elements may also be present. The terms "mounted," "one end," "the other end," and the like are used herein for illustrative purposes only.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

Fig. 1 is a block diagram of a GOA unit according to an embodiment of the present disclosure, and referring to fig. 1, the GOA circuit includes a plurality of cascaded GOA units, each of which includes an upper pull-down control module 100, an upper pull-down module 200, a pull-down maintaining module 300, a capacitance module 400, a first clearing module 500, and a touch function adjusting module 600;

if the nth-level GOA unit is a GOA unit in the previous two levels, the corresponding pull-up and pull-down control module 100 is respectively connected to the GSP signal, the m-2-level clock signal line Ck (m-2) and the first node, if the nth-level GOA unit is a GOA unit after the previous two levels, the corresponding pull-up and pull-down control module 100 is respectively connected to the signal output terminal G (n-2) of the nth-2-level GOA unit, the m-2-level clock signal line Ck (m-2) and the first node, wherein n and m are positive integers;

the up-down pulling module 200 is respectively connected with the mth level clock signal line Ckm, the first node and the second node;

the capacitor module 400 is connected to the first node and the second node respectively;

the pull-down maintaining module 300 is respectively connected with an m-th level clock signal line Ckm, a first node, a second node and a third node, wherein the third node is connected with a first low level signal;

the touch function adjusting module 600 respectively contacts the control scan signal Tp, the second node, and the third node;

if the nth-level GOA unit is a GOA unit in the previous three levels, the first clearing module 500 is connected to the VSS signal, the first node, and the third node, respectively, and if the nth-level GOA unit is a GOA unit in the next three levels, the first clearing module 500 is connected to the GSP signal, the first node, and the third node, respectively.

Specifically, fig. 2 is a schematic diagram of a prior art panel circuit; referring to fig. 2, the panel circuit includes a GOA circuit and a Source IC and a Pixel TFT corresponding to each Pixel. The GOA circuit comprises a plurality of cascaded GOA units (G1, G2, G3 … Gn-1 and Gn). Each GOA cell is used to drive a row of Pixel TFTs. The Source IC includes a plurality of Source cells (S1, S2, S3 … Sn-1 and Sn). Each source cell is used to supply power to the Pixel TFTs of a column.

From the imaging principle of the liquid crystal panel, the operation of the liquid crystal panel is commonly controlled by the gate and source voltages. The grid voltage is responsible for turning on and turning off the TFT transistor below a specific pixel point, so that the on and off of the pixel point are influenced. And then, the source voltage charges a liquid crystal area where the pixel point is located, the rotation angle of liquid crystal molecules is influenced, and the gray level of the pixel point is further influenced.

The main functional module of the Gate On Array (GOA) is to design an S/R circuit by using the TFT process of the panel, so that the panel can provide the capability of scanning sequentially. The Pixel TFT uses the signal provided by GOA circuit and Source IC to make the corresponding Sub Pixel possess correct voltage, and then drives LC inversion to generate color picture acceptable to human eye.

Touch Technology (Touch Panel Technology) can be divided into three modes, namely Out-cell, On-cell and In-cell, according to the position of a Touch sensor (Touch sensor). The In-cell technology not only further reduces the thickness of the whole machine, but also can be manufactured together with the LCD, and the visibility of the LCD In a bright environment is not influenced. The GOA circuit can be widely applied to the In-cell technology integrating the touch panel function and the liquid crystal panel.

The pull-up and pull-down control module 100 is controlled by the m-2 level clock signal line Ck (m-2) to turn on or off, and the GSP signal or the output signal of the signal output terminal G (n-2) of the n-2 level GOA unit is used to control the capacitor module 400 at the first node to be charged and drive the pull-up and pull-down module 200 to be turned on. When the pull-up module 200 is turned on, if the clock signal output from the m-th level clock signal line Ckm changes from low level to high level, the output Gout of the n-th level GOA unit also changes to high level synchronously and is input to the panel AA area, and the corresponding Pixel TFT (thin film transistor corresponding to the Pixel) is driven to turn on, so that the Pixel charges the correct source voltage.

After the Pixel TFT in the AA area receives the source signal, the output Gout of the n-th-level GOA unit needs to be synchronously changed into low level, so that the Pixel TFT can be effectively closed, and the related source voltage can be effectively locked by driving. Therefore, the voltage at the first node keeps high, driving the pull-up/pull-down module 200 to pull down the output voltage of Gout.

After the nth GOA unit finishes operating, the pull-down maintaining module 300 in this embodiment is used to maintain the low voltage of Gout in order to continuously input the low voltage Gout to the Pixel TFT.

In addition, in order to reduce the driving defects during the startup, the present embodiment effectively drives the first clearing module 500 by using the GSP signal to clear the first node voltage, so as to reduce the risk of abnormal lighting pictures caused by the defects during the initial driving of the GOA.

In the Touch stage, the Touch function adjusting module 600 utilizes the Touch scan signal Tp to match the coupled first low level signal, so that Gout outputs an AC signal identical to that of a Touch Sensor module (Touch Sensor module, not shown in this application), thereby reducing loading of the Touch Sensor module, improving sensitivity of the Touch Sensor module, and maintaining a dark screen wake-up function.

The present embodiment utilizes the GSP signal during the startup to effectively control the first clearing module 500 to clear the voltage of the first node, so as to reduce the defects during the initial driving of the GOA and reduce the risk of abnormal startup lighting pictures. The upper and lower pull-up control module 100 is controlled by the periodic clock signal and the output signal of the previous stage to charge the capacitor module 400 of the first node, the upper and lower pull-up module 200 is controlled to be turned on or off by the periodic clock signal and the voltage of the first node, and the output Gout of the GOA is synchronously made to be a high potential when the periodic clock signal is changed to be the high potential, so that the corresponding Pixel TFT is effectively turned on. The pull-down maintaining module 300 is utilized to enable the output voltage Gout of the GOA to maintain the low level of Gout so that the corresponding Pixel TFT can be effectively turned off. According to the GOA circuit, the wiring quantity and the circuit layout area in the GOA circuit are effectively reduced by utilizing the collocation of the periodic clock signals and the TFTs. The GOA circuit is suitable for the panel requirement of the narrow frame. The touch function adjusting module 600 is further utilized to match the touch scanning signal Tp and the first low-level signal to reduce the loading of the touch sensor module, so that the sensitivity of the touch sensor module is improved, and the dark screen awakening function is maintained.

Fig. 3 is a circuit diagram of a pull-up and pull-down control module 100 according to an embodiment of the present application; referring to fig. 3, if the nth level GOA cell is the GOA cells in the previous two levels, the first end of the first sub-tft T1A included in the corresponding pull-up and pull-down control module 100 is connected to the GSP signal, and if the nth level GOA cell is the GOA cell after the previous two levels, the first end of the first sub-tft T1A included in the corresponding pull-up and pull-down control module 100 is connected to the signal output terminal G (n-2) of the nth-2 level GOA cell;

the gate of the first sub-thin film transistor T1A and the gate of the second sub-thin film transistor T1B included in the pull-up and pull-down control module 100 are both connected to the m-2 th-stage clock signal line Ck (m-2);

the second end of the first sub thin film transistor T1A and the first end of the second sub thin film transistor T1B are both connected to the sixth node;

the gate of the fourth sub-tft T2B included in the pull-up/down control module 100 is connected to the first node q (n), and the first node is connected to the sixth node;

the gate and the second terminal of the third sub-tft T2A included in the pull-up/down control module 100 both contact the control scan signal Tp and the second terminal of the first sub-tft T2B.

Specifically, the first sub thin film transistor T1A, the second sub thin film transistor T1B, the third sub thin film transistor T2A, and the fourth sub thin film transistor T2B are all thin film transistors TFT.

When the G (n-2) or GSP start signal and the clock signal provided by the m-2 th clock signal line Ck (m-2) both change from low level to high level, the first node is charged through the capacitor module 400, and Gout outputs the clock signal provided by the m-th clock signal line Ckm as low level.

The clock signal provided by the mth stage clock signal line Ckm changes from low level to high level, the first node stops charging through the capacitance block 400, and the Gout output changes from low level to high level to effectively turn on the corresponding Pixel TFT.

When the clock signal provided by the mth stage clock signal line Ckm changes from high level to low level, the first node still maintains high level, so the Gout output changes from high level to low level, and at this time, the Gout maintains low level due to the action of the pull-down maintaining module 300, so as to effectively turn off the corresponding Pixel TFT.

In this embodiment, in the pit stopping area at the Touch stage: when the first node q (n) of the nth level GOA unit is at a high voltage level, the touch scan signal Tp is transmitted to the Drain terminal of T1B through T12A and T12B, and both ends (source S and Drain D) of T1B are at a high voltage level, so Vgs is much smaller than Vth, and the risk of leakage of the first node q (n) can be reduced. Non-pit-stopping area: point q (n) is low, and T12B is off, so the touch scan signal Tp cannot be transmitted into T1B, and normal operation of the circuit is not affected; and recovering the conventional GOA circuit driving after the Touch stage is finished.

In the embodiment, the T1A, T1B, T12A, T12B and the Touch scan signal Tp in the pull-up and pull-down control module are used to drive Vgs < Vth of T1B, so that the risk of leakage of the first node q (n) of the GOA unit in the Touch phase can be reduced.

FIG. 4 is a circuit diagram of a pull-up/pull-down control module according to another embodiment of the present application; referring to fig. 4, if the nth level GOA cell is the GOA cells in the previous two levels, the first end of the first thin film transistor T1 included in the corresponding pull-up and pull-down control module 100 is connected to the GSP signal, and if the nth level GOA cell is the GOA cell following the previous two levels, the first end of the first thin film transistor T1 included in the corresponding pull-up and pull-down control module 100 is connected to the signal output terminal G (n-2) of the nth-2 level GOA cell;

the gate of the first thin film transistor T1 is connected to the m-2 th stage clock signal line Ck (m-2), and the second terminal is connected to the first node q (n).

Specifically, the first thin film transistor T1 is driven by the clock signal of the m-2 th stage clock signal line Ck (m-2), and when T1 is turned on, the first terminal of T1 charges the first node q (n) through T1, driving T7 to turn on.

In the case where T7 is turned on, if the voltage of the clock signal of the mth stage clock signal line Ckm changes from the low potential to the high potential, the second terminal of T7, i.e., the output terminal Gout, changes to the high potential in synchronization. Gout is input to the panel in AA area to drive the corresponding Pixel TFT to be opened, so that the Pixel is charged with the correct source voltage.

Since the first node q (n) is kept at the high voltage level by the first capacitor, the output of the second terminal Gout of T7 in the pull-up/down module 200 can be driven to the low voltage level, so as to effectively pull down the Gout voltage. Since Gout is connected to the first low level signal through the pull-down maintaining module 300, the pull-down maintaining module 300 can continuously pull down the potential of Gout at other time after the GOA unit finishes operating, so that Gout can effectively keep the low potential.

Fig. 5-8 are circuit diagrams of a GOA unit according to various embodiments of the present application, and referring to fig. 5-8, a gate of a fiftieth thin film transistor T50 included in the touch function adjusting module 600 is connected to a touch scan signal Tp, a first terminal is connected to a second node, and a second terminal is connected to a third node.

Specifically, when the Touch sensor of the panel is activated, the Touch control scanning signal Tp is changed from a low potential to a high potential, Gout is changed from a DC signal to an AC signal identical to Touch, and Gout outputs an AC signal identical to Touch in period. In the embodiment, the T50 and the TP signal are used in combination with the coupled first low level signal, so that the Gout outputs the AC signal which is the same as the Touch sensor, thereby reducing Touch sensor Loading and increasing Touch sensitivity.

The application also provides a GOA circuit, which comprises a plurality of cascaded GOA units, wherein each GOA unit comprises an upper pull-down control module 100, a lower pull-up module 200, a pull-down maintaining module 300, a capacitance module 400 and a first clearing module 500;

if the nth-level GOA unit is a GOA unit in the previous two levels, the corresponding up-down pull control module 100 is respectively connected to the GSP signal, the m-2-level clock signal line Ck (m-2) and the first node, and if the nth-level GOA unit is a GOA unit after the previous two levels, the corresponding up-down pull control module 100 is respectively connected to the signal output terminal G (n-2) of the nth-2-level GOA unit, the m-2-level clock signal line Ck (m-2) and the first node q (n), where n and m are positive integers;

the upper pull-down module 200 is respectively connected with the mth level clock signal line Ckm, a first node Q (n) and a second node;

the capacitor module 400 is respectively connected with a first node and a second node;

the pull-down maintaining module 300 is respectively connected with the mth level clock signal line Ckm, a first node q (n), a second node and a third node, wherein the third node is connected with a first low level signal;

if the nth grade of the GOA unit is a GOA unit in the previous three grades, the first clearing module 500 is respectively connected with the VSS signal, the first node q (n), and the third node, and if the nth grade of the GOA unit is a GOA unit in the previous three grades, the first clearing module 500 is respectively connected with the GSP signal, the first node q (n), and the third node;

if the nth-level GOA unit is a GOA unit in the previous two levels, the first end of the first sub-thin film transistor included in the corresponding pull-up and pull-down control module 100 is connected to the GSP signal, and if the nth-level GOA unit is a GOA unit after the previous two levels, the first end of the first sub-thin film transistor included in the corresponding pull-up and pull-down control module 100 is connected to the signal output end G (n-2) of the n-2 th-level GOA unit;

the grid electrode of the first sub thin film transistor and the grid electrode of the second sub thin film transistor contained in the pull-up and pull-down control module 100 are both connected with the m-2 level clock signal line Ck (m-2);

the gate of the fourth sub-tft included in the pull-up/down control module 100 is connected to the first node q (n), and the first node is connected to the sixth node;

the gate and the second terminal of the third sub-tft included in the pull-up/down control module 100 both contact the control scan signal Tp, and the first terminal is connected to the second terminal of the fourth sub-tft.

Specifically, the embodiment does not include the touch function adjusting module 600, and the pull-up and pull-down control module 100 is shown in fig. 3, which can reduce the risk of leakage of the first node.

Referring to fig. 5 to 8, the gate of the seventh thin film transistor T7 included in the pull-up/down module 200 is connected to the first node, the first terminal thereof is connected to the mth stage clock signal line Ckm, and the second terminal thereof is connected to the second node;

a first end of a first capacitor C1 included in the capacitor module 400 is connected to the first node q (n), and a second end is connected to the second node;

if the nth GOA cell is the GOA cell in the previous three levels, the gate of the sixth tft T6 included in the first erase module 500 is connected to the VSS signal, and if the nth GOA cell is the GOA cell in the next three levels, the gate of the sixth tft T6 included in the first erase module 500 is connected to the GSP signal;

the sixth thin film transistor T6 has a first terminal connected to the first node q (n) and a second terminal connected to the third node.

Specifically, the pull-up and pull-down module 200 includes a seventh thin film transistor T7, the first clear module 500 includes a sixth thin film transistor T6, and the capacitor module 400 includes a first capacitor C1.

The seventh thin Film transistor T7 and the sixth thin Film transistor T6 of the present embodiment are both thin Film transistors tft (thin Film transistor).

The first node q (n) is a common node of the pull-up and pull-down control module 100, the gate of the seventh tft T7, the first terminal of the sixth tft T6, and the first terminal of the first capacitor C1.

The second node is a common node of the second terminal of the first capacitor C1, the second terminal of the seventh tft T7, and the pull-down sustain module 300.

The third node is a common node of the second terminal of the sixth thin film transistor T6 and the pull-down sustain module 300.

T1A and T1B are driven by the clock signal of the (m-2) th stage clock signal line Ck (m-2), and when T1A and T1B are turned on, the first node Q (n) is charged by the first capacitor C1, driving to turn on T7.

Since the first node q (n) is kept at the high voltage level by the first capacitor C1, the output of the second terminal Gout of T7 in the pull-up/down module 200 can be driven to the low voltage level, so as to effectively pull down the Gout voltage level.

Since Gout is connected to the first low level signal through the pull-down maintaining module 300, the pull-down maintaining module 300 can continuously pull down Gout after the GOA unit is operated, so that Gout is effectively kept at a low level.

In one embodiment, the pull-down sustain module 300 includes a third thin film transistor and a fifth thin film transistor, wherein gates of the third thin film transistor and the fifth thin film transistor are connected to the first node, a first terminal of the third thin film transistor is connected to the fourth node, a second terminal of the third thin film transistor is connected to the third node, a first terminal of the fifth thin film transistor is connected to the fifth node, and a second terminal of the fifth thin film transistor is connected to the third node;

a first end of a second capacitor included in the pull-down maintaining module 300 is connected to the mth-stage clock signal line Ckm, and a second end is connected to the fourth node;

a gate of a fourth thin film transistor included in the pull-down maintaining module 300 is connected to the fourth node, a first end of the fourth thin film transistor is connected to the mth-stage clock signal line Ckm, and a second end of the fourth thin film transistor is connected to the fifth node;

the gate of the eighth tft included in the pull-down sustain module 300 is connected to the fifth node, the first end is connected to the second node, and the second end is connected to the third node.

Specifically, referring to fig. 5 to 8, the pull-down sustain module 300 includes a third thin film transistor T3, a fourth thin film transistor T4, a fifth thin film transistor T5, an eighth thin film transistor T8, and a second capacitor C2.

The third thin Film transistor T3, the fourth thin Film transistor T4, the fifth thin Film transistor T5, and the eighth thin Film transistor T8 are all thin Film transistors tft (thin Film transistor).

The fourth node is a common node of the second terminal of the second capacitor C2, the first terminal of the third thin film transistor T3, and the gate of the fourth thin film transistor T4.

The fifth node is a common node of the second terminal of the fourth thin film transistor T4, the first terminal of the fifth thin film transistor T5, and the gate of the eighth thin film transistor T8.

In the process of the clock signal from high level to low level to high level provided by the m-2 th level clock signal line Ck (m-2), the potential of the first node q (n) is in three stages of charge-sustain-discharge, and the discharge loop is that the first node q (n) pulls down the charge of the first node q (n) to low level through T1B, T1A and T8 of the previous level GOA unit.

After the GOA unit finishes working, the low potential must be continuously input to the Pixel TFT, so the circuit uses the pull-down maintaining module 300 to continuously maintain the low potential of Gout. At this time, the working principle mainly utilizes the periodic clock signal and the coupling capacitor to drive the fourth thin film transistor T4 to generate the switching signal, which can effectively transmit the clock signal of the mth clock signal line Ckm to the fifth node p (n), and at the same time, because the fifth node discharge path is only provided with the fifth thin film transistor T5, except that the first node is pulled to the low potential when the GOA unit normally works, the first node is pulled to the high potential, the high potential can be effectively maintained in the rest of the time, so the Gout potential can be continuously pulled down through the eighth thin film transistor T8, and at the same time, the first node can also be continuously maintained at the low potential through the T1A, the T1B and the eighth thin film transistor T8.

The number of GOA TFTs and the number of busline are reduced by the combination of the TFT functional modules, and the layout space of the GOA circuit is effectively reduced. The noise elimination circuit is designed by using the periodic clock signal CK and the capacitive coupling effect, so that the TFT Stress can be effectively reduced, and the reliability of the panel is improved.

The circuit diagram of the pull-up/down control module 100 shown in fig. 5 to 8 is specifically shown in fig. 3. The circuit diagram of the pull-up and pull-down control module 100 in fig. 5 to 8 is also replaced with the circuit diagram shown in fig. 4.

In one embodiment, each GOA unit further comprises at least one of a second purge module, a third purge module, and a fourth purge module;

In particular, the number and the type of the purge modules included in each GOA unit are not all the same, i.e. the number and the type of the purge modules included are not necessarily all the same. For example, some GOA units include one or two or three of the second purge module, the third purge module, and the fourth purge module. It is possible that some GOA units contain the same number and kind of flush modules. The number and the type of the cleaning modules contained in each GOA unit are not limited by the application.

In one embodiment, each GOA unit further comprises at least one of a second purging module, a fourth purging module;

In one embodiment, the second cleaning module includes a ninth thin film transistor;

the ninth thin film transistor is connected with the first clearing signal line at the grid electrode, the first end is connected with the first node, and the second end is connected with the second low-level signal.

Specifically, the ninth thin Film transistor T9 is a thin Film transistor tft (thin Film transistor) as shown in fig. 6 to 8.

In one embodiment, the third cleaning module includes a tenth thin film transistor;

the tenth thin film transistor has a gate connected to the second clear signal line, a first end connected to the fifth node, and a second end connected to the third low-level signal.

Specifically, the tenth thin Film transistor T10 is a thin Film transistor tft (thin Film transistor) as shown in fig. 7 to 8.

In one embodiment, the fourth cleaning module includes an eleventh thin film transistor;

the gate of the eleventh thin film transistor is connected to the third clear signal line, the first end of the eleventh thin film transistor is connected to the second node, and the second end of the eleventh thin film transistor is connected to the fourth low-level signal.

Specifically, the eleventh thin Film transistor T11 is a thin Film transistor tft (thin Film transistor) as shown in fig. 8.

In one embodiment, each GOA unit can further include a fifth clear module including a twelfth thin film transistor;

the grid electrode of the twelfth thin film transistor is connected with the fourth clearing signal line, the first end of the twelfth thin film transistor is connected with the fourth node, and the second end of the twelfth thin film transistor is connected with the fifth low-level signal.

Specifically, the twelfth thin Film transistor is a thin Film transistor tft (thin Film transistor).

In a specific embodiment, the first low level signal, the second low level signal, the third low level signal, the fourth low level signal and the fifth low level signal are all the same low level signal.

Of course, some of the first low-level signal, the second low-level signal, the third low-level signal, the fourth low-level signal, and the fifth low-level signal may be the same low-level signal, and some of the low-level signals may be another low-level signal, which is not limited in this application.

In one embodiment, the first clear signal corresponding to the first clear signal line, the second clear signal corresponding to the second clear signal line, the third clear signal corresponding to the third clear signal line, and the fourth clear signal corresponding to the fourth clear signal line are all the same clear signal. That is, the first clear signal line, the second clear signal line, the third clear signal line, and the fourth clear signal line are the same clear signal line.

Specifically, referring to fig. 5-8, it is shown in fig. 5 that the GOA unit only includes the first clear module 500, and the first low signal is VGL. In fig. 6, the GOA unit includes a first clear module and a second clear module, and the first low level signal and the second low level signal are the same low level signal VGL, and the first clear signal is CLR. Fig. 7 shows that the GOA unit includes a first clearing module, a second clearing module, and a third clearing module, and the first low level signal, the second low level signal, and the third low level signal are the same low level signal VGL, and the first clearing signal and the second clearing signal are the same clearing signal CLR. Fig. 8 shows that the GOA unit includes a first clearing module, a second clearing module, a third clearing module, and a fourth clearing module, and the first low level signal, the second low level signal, the third low level signal, and the fourth low level signal are all the same low level signal VGL, and the first clearing signal, the second clearing signal, and the third clearing signal are the same clearing signal CLR.

Through increasing the clear away circuit, can effectively reduce the effect of GOA residual charge to circuit functionality, effectively reduced the bad risk of GOA lighting a lamp.

The thin film transistor can be an N-type thin film transistor or a P-type thin film transistor. The first end of the same thin film transistor is a drain electrode, the second end is a source electrode, and the first end is a source electrode, and the second end is a drain electrode. The first terminal and the second terminal are determined as a drain or a source, depending on the type of the thin film transistor and the circuit connection condition.

In one embodiment, the number of the clock signals included in one active period corresponds to the duty ratio of the clock signals, and the clock signals included in one active period are sequentially effective in time division in the active period of the GOA circuit.

Specifically, the clock signal of the present application is a periodic clock signal. The clock signals are provided by corresponding clock signal lines. The clock signal included in one active period is sequentially time-shared and active in the active period. For example, if an active period contains 6 clock signals, then the 6 clock signals are active at different times during the active period. These 6 clock signals are still time-shared in the next active cycle.

The number of periodic clock signals is not constrained by the present application. No matter how many clock signals are set in one action period, the same function can be achieved as long as the corresponding duty ratio (duty ratio) is satisfied.

An m-2 th-level clock signal line Ck (m-2) and an m-level clock signal line Ckm are connected to the nth-level GOA unit, and thus, two clock signals are provided to the GOA unit, and the two clock signals are separated by 2 levels. The 2 clock signals may be clock signals of the same action period or clock signals of adjacent action periods.

For example, one duty cycle includes 6 clock signals, and if the clock signal supplied from the m-2 th stage clock signal line Ck (m-2) is the 6 th clock signal of a certain duty cycle, the clock signal supplied from the m-th stage clock signal line Ckm is the 2 nd clock signal of the next duty cycle.

In addition, one clock signal includes a high level signal and a low level signal. Different clock signals have different waveforms formed by high level signals and low level signals.

FIG. 9 is a schematic diagram illustrating driving of a panel according to an embodiment of the present application; referring to fig. 9, the left side is a waveform diagram of node voltages of the first node q (n) and Gout (i.e., Gn) during a Normal period (non-Touch period). The right side is a waveform diagram of node voltages of first nodes Q (n) and Gout (Gn) of the pit stop area before pit stop (non-pit stop area) and the pit stop area in the Touch stage.

FIG. 10 is a waveform diagram of a plurality of signals according to an embodiment of the present application; referring to fig. 10, the multiplex signals include a GSP signal, 6 clock signals Ck1-Ck6 included in one active period, a clear signal CLR, and a low level signal VGL. And all low level signals are the same low level signal VGL. And a first clear signal corresponding to the first clear signal line, a second clear signal corresponding to the second clear signal line, a third clear signal corresponding to the third clear signal line, and a fourth clear signal corresponding to the fourth clear signal line are all the same clear signal CLR.

The first-level clock signal line provides clock signals for GOA units which are 6 levels away, such as the 5 th-level GOA unit, the 11 th-level GOA unit, the 17 th-level GOA unit …, the 2159 th-level GOA unit and the like.

The second level clock signal line provides clock signals for GOA units 6 level apart, such as the GOA unit 6 level, the GOA unit 12 level, the GOA unit 18 level … level 2160 level.

The third-level clock signal line provides clock signals for the GOA units 6 levels away, such as the 1 st-level GOA unit, the 7 th-level GOA unit, the 13 th-level GOA unit, the 19 th-level GOA unit …, and the 2161 st-level GOA unit.

The fourth-level clock signal line supplies clock signals to the GOA units 6 levels away, such as the 2 nd, 8 th, 14 th, 20 th, and 2162 nd GOA units ….

The fifth level clock signal line provides clock signals for the GOA units 6 levels away, such as the 3 rd level GOA unit, the 9 th level GOA unit, the 15 th level GOA unit, the 21 st level GOA unit …, the 2163 rd level GOA unit, etc.

The sixth-level clock signal line supplies clock signals to GOA units 6 levels away, such as the 4 th-level GOA unit, the 10 th-level GOA unit, the 16 th-level GOA unit, and the 22 nd-level GOA unit …, the 2164 th-level GOA unit.

The working principle of the present application is illustrated by taking fig. 8 as an example:

in the non-Touch (Touch screen) phase:

the G (n-2) or GSP signal and the clock signal provided by the m-2 th clock signal line Ck (m-2) are simultaneously changed from low level to high level, at this time, the G (n-2) or GSP signal charges the first node q (n) through the first capacitor C1, at this time, T3 and T5 are also turned on, the fifth node p (n) is low level, and at this time, the touch scan signal Tp is a low level signal, so T12A and T50 are both in off state, T7 is turned on, and the output of Gout is the low level clock signal provided by the m-2 th clock signal line Ckm.

The first node q (n) stops charging, and when the clock signal supplied from the m-th stage clock signal line Ckm changes from low level to high level, the Gout output also changes from low level to high level.

When the clock signal provided by the mth stage clock signal line Ckm changes from high level to low level, the first node q (n) still maintains high level, so the Gout output changes from high level to low level, and the Gout pull-down (i.e. output low level) can be maintained by using the thin film transistors T3, T4, T5, T8 and the second capacitor C2 in the pull-down maintaining module and the clock signal provided by the mth stage clock signal line Ckm.

In the process of the clock signal provided by the m-2 stage clock signal line Ck (m-2) from the high level to the low level to the high level, the potential of the first node q (n) is in three stages of charging, maintaining and discharging. The discharging loop pulls the charge at the first node q (n) to a low level through T1B, T1A, and T8 of the previous GOA cell.

In the non-Touch stage, the Touch scan signal Tp is at a low level.

In Touch stage:

when the panel Touch sensor is started, the Touch scanning signal Tp changes from low level to high level, the thin film transistor T50 is turned on, the low level signal of Gout changes from DC signal to AC signal same as Touch, and Gout outputs AC signal with same period as Touch. By using the T50 and TP signal in combination with VGL coupling signal, the same AC signal as Touch sensor is outputted, so that Touch sensor Loading can be reduced and Touch sensitivity can be increased.

Stopping the pit area: the first node q (n) of the GOA is at a high voltage, the touch scan signal Tp is transmitted to the Drain terminal of T1B via T12A and T12B, and both ends (source and Drain) of T1B are at a high voltage, so Vgs is much smaller than Vth, thereby reducing the risk of leakage at the first node q (n).

Non-pit-stopping area: the first node q (n) is low, and T12B is turned off, so the touch scan signal Tp cannot be transmitted into T1B, and the normal operation of the circuit is not affected.

And recovering the conventional GOA circuit driving after the Touch stage is finished.

The special GOA circuit for the Incell utilizes T50 and a VGL coupling signal matched with a TP signal to drive a panel to keep the same coupling with a Touch Sensor in the Gout output of a Touch stage, and Touch Sensor Loading is reduced.

The pull-down control module is driven by a periodic clock signal to have the pull-down and pull-down maintaining functions of the first node q (n), and the pull-down and pull-down maintaining functions of the first node q (n) are compatible by the T8.

The GOA circuits designed by the prior art are all required by large-size panels, so that the GOA circuits have more TFTs, the common circuits have 18 to 20 TFTs, and the unipolar GOA circuits have more TFTs, so that the circuit design layout space is larger, and the requirements of small and medium-sized narrow frames cannot be met. The GOA circuit successfully and effectively reduces the number of Busline wires and the number of TFTs (thin film transistors) by utilizing the collocation of the periodic CLK clock signal and the TFT device required by the original design and reducing two DC signal lines (LC1 and LC2) and one VSS signal line, thereby successfully achieving the purpose of reducing the circuit layout area and being suitable for narrow-frame panels.

Driving Vgs < Vth with the pull-up and pull-down control modules T1A, T1B, T12A, T12B reduces the risk of leakage at the first node q (n) of the GOA cell in Touch phase.

The application also provides a display panel, which comprises a display module and the GOA circuit of any one of the display module and the GOA circuit; the GOA circuit is electrically connected with the display module and used for driving the display module to emit light.

The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.

The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the claims. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present patent shall be subject to the appended claims.

Claims

1. The GOA circuit is characterized by comprising a plurality of cascaded GOA units, wherein each GOA unit comprises an upper pull-down control module, a lower pull-up module, a pull-down maintaining module, a capacitance module, a first clearing module and a touch function adjusting module;

the up-down drawing module is respectively connected with an m-th level clock signal line Ckm, the first node and the second node;

the pull-down maintaining module is respectively connected with the mth level clock signal line Ckm, the first node, the second node and a third node, wherein the third node is connected with a first low level signal;

the touch function adjusting module is respectively contacted with a control scanning signal Tp, the second node and the third node;

if the nth-level GOA unit is a GOA unit in the previous three levels, the first clearing module is respectively connected with the VSS signal, the first node and the third node, and if the nth-level GOA unit is a GOA unit behind the previous three levels, the first clearing module is respectively connected with the GSP signal, the first node and the third node.

2. The GOA circuit of claim 1,

if the nth-level GOA unit is a GOA unit in the previous two levels, a first end of a first sub thin film transistor included in the corresponding upper and lower pull-down control module is connected with a GSP signal, and if the nth-level GOA unit is a GOA unit after the previous two levels, a first end of the first sub thin film transistor included in the corresponding upper and lower pull-down control module is connected with a signal output end G (n-2) of the nth-2-level GOA unit;

the grid electrode of the first sub thin film transistor and the grid electrode of the second sub thin film transistor contained in the up-down pulling control module are both connected with an m-2-th level clock signal line Ck (m-2);

the second end of the first sub thin film transistor and the first end of the second sub thin film transistor are both connected with a sixth node;

the grid electrode of a fourth sub-thin film transistor contained in the upper pull-down control module is connected with the first node, and the first end of the fourth sub-thin film transistor is connected with the sixth node;

and the grid and the second end of a third sub-thin film transistor contained in the upper and lower pull control module are both connected with the touch scanning signal Tp, and the first end is connected with the second end of the fourth sub-thin film transistor.

3. GOA circuit according to claim 1 or 2,

the gate of a fifty-th thin film transistor included in the touch function adjusting module is connected to the touch scanning signal Tp, the first end is connected to the second node, and the second end is connected to the third node.

4. A GOA circuit is characterized by comprising a plurality of cascaded GOA units, wherein each GOA unit comprises an upper pull-down control module, an upper pull-down module, a pull-down maintaining module, a capacitance module and a first clearing module;

if the nth-level GOA unit is a GOA unit in the previous three levels, the first clearing module is respectively connected with a VSS signal, the first node and a third node, and if the nth-level GOA unit is a GOA unit behind the previous three levels, the first clearing module is respectively connected with the GSP signal, the first node and the third node;

if the nth-level GOA unit is a GOA unit in the previous two levels, the first end of the first sub thin film transistor included in the corresponding upper and lower pull-down control module is connected with a GSP signal, and if the nth-level GOA unit is a GOA unit after the previous two levels, the first end of the first sub thin film transistor included in the corresponding upper and lower pull-down control module is connected with a signal output end G (n-2) of the (n-2) th-level GOA unit;

and the grid and the second end of a third sub thin film transistor contained in the up-down pulling control module are connected with the touch scanning signal Tp, and the first end of the third sub thin film transistor is connected with the second end of the fourth sub thin film transistor.

5. GOA circuit according to claim 1 or 4,

a grid electrode of a seventh thin film transistor contained in the upper pull-down module is connected with the first node, a first end of the seventh thin film transistor is connected with the mth level clock signal line Ckm, and a second end of the seventh thin film transistor is connected with the second node;

a first end of a first capacitor contained in the capacitor module is connected with the first node, and a second end of the first capacitor is connected with the second node;

if the nth-level GOA unit is a GOA unit in the previous three levels, the grid electrode of a sixth thin film transistor included in the first clearing module is connected with a VSS signal, and if the nth-level GOA unit is a GOA unit behind the previous three levels, the grid electrode of the sixth thin film transistor included in the first clearing module is connected with the GSP signal;

and the first end of the sixth thin film transistor is connected with the first node, and the second end of the sixth thin film transistor is connected with the third node.

6. The GOA circuit of claim 5,

the pull-down maintaining module comprises a first thin film transistor, a second thin film transistor, a third node, a fourth node, a third node, a fifth node, a first node, a second node, a third node, a fourth node, a fifth node, a fourth node, a fifth node, a fourth node, a third node, a fourth node, a third node, a fourth node, a fifth node, a fourth node, a third node, a fourth node, a third node, a fourth node, a;

a first end of a second capacitor contained in the pull-down maintaining module is connected with the m-th level clock signal line Ckm, and a second end of the second capacitor is connected with the fourth node;

a gate of a fourth thin film transistor included in the pull-down maintaining module is connected with the fourth node, a first end of the fourth thin film transistor is connected with the mth-level clock signal line Ckm, and a second end of the fourth thin film transistor is connected with the fifth node;

and the grid electrode of an eighth thin film transistor contained in the pull-down maintaining module is connected with the fifth node, the first end of the eighth thin film transistor is connected with the second node, and the second end of the eighth thin film transistor is connected with the third node.

7. The GOA circuit of claim 6, wherein each GOA unit further comprises at least one of a second purge module, a third purge module, and a fourth purge module;

the second clearing module is used for clearing the voltage of the first node under the control of a first clearing signal;

the third clearing module is used for clearing the voltage of the fifth node under the control of a second clearing signal;

the fourth clearing module is used for clearing the voltage of the second node under the control of a third clearing signal.

8. The GOA circuit of claim 7,

the second clearing module comprises a ninth thin film transistor, the grid electrode of the ninth thin film transistor is connected with the first clearing signal line, the first end of the ninth thin film transistor is connected with the second node, and the second end of the ninth thin film transistor is connected with the second low-level signal;

and/or the presence of a gas in the gas,

9. The GOA circuit according to claim 1 or 4, wherein the number of the clock signals included in one active period corresponds to a duty ratio of the clock signals, and the clock signals included in one active period are sequentially time-shared in the active period of the GOA circuit.

10. A display panel, comprising a display module and the GOA circuit of any one of claims 1 to 9;

the GOA circuit is electrically connected with the display module and used for driving the display module to emit light.