CN212061811U - Test circuit and display device thereof - Google Patents
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- CN212061811U CN212061811U CN202020910963.6U CN202020910963U CN212061811U CN 212061811 U CN212061811 U CN 212061811U CN 202020910963 U CN202020910963 U CN 202020910963U CN 212061811 U CN212061811 U CN 212061811U
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Abstract
The utility model discloses a test circuit for test display panel, test circuit includes a plurality of test element, and wherein, every test element includes: the first end is connected with the input end of the grid driving unit of the display panel to receive a test signal; the second end is connected with the output end of the grid driving unit so as to provide a test signal for the display panel; and the control end is connected with the reference signal end of the grid driving unit so as to receive a reference signal and control the test circuit to provide a test signal for the display panel according to the reference signal. The utility model discloses well test circuit is owing to used walking of partial GIA module line and signal, consequently not only saved complicated control signal, has simplified the test procedure, has reduced moreover and has walked the line, has reduced the test cost.
Description
Technical Field
The utility model relates to a show technical field, more specifically relates to a test circuit and display device thereof.
Background
Fig. 1 shows a schematic structure of a related art display device. As shown, the display device 1000 includes a display panel 1100, a gate driving circuit, and a source driving circuit (not shown). The gate driving circuit includes n stages of gate driving units 1200, n being a non-zero natural number. The display panel 1100 includes a plurality of pixel units 1110 arranged in an array, and n scan lines 1120 for transmitting gate driving signals, wherein each pixel unit 1110 includes a thin film transistor T and a liquid crystal capacitor CLCAnd a storage capacitor CST. In the display panel 1100, the gates of the thin film transistors T in the pixel units 1110 located in the same row are connected to the corresponding first-stage gate driving unit 1200 in the gate driving circuit through the same scanning line 1120, and the gate driving circuit gates each pixel unit 1110 in the display panel 1100 row by row through a plurality of scanning lines 1120; the source or drain of the tfts T in the pixel units 1110 in the same row are connected to a source driver circuit through the same data line, and the source driver circuit applies gray scale voltages to the pixel units 1110 through a plurality of data lines, so that the display panel displays images.
With the development of display devices, people have increasingly high demand for display devices with narrow borders. In order to realize a narrow frame of a display device, a Gate In Array (GIA) integration technology is generally adopted, i.e., a Gate driving circuit and a display panel are integrated on the same substrate, and this technology not only enables the display device to be more symmetrical and compact, but also reduces the cost and improves the resolution and the bending degree of the display panel. However, due to the complicated and complicated GIA lines, Pre Delivery Inspection (PDI) of the display device 1000 is difficult, and particularly, testing the wiring is difficult during the unit test stage or the mid-board test of the product signal.
In view of the foregoing, there is a need to provide a simple test circuit that can implement display panel inspection.
SUMMERY OF THE UTILITY MODEL
The utility model discloses the above-mentioned problem to existence among the prior art provides a test circuit, through increasing a test element in cascaded gate drive unit, tests display panel through test circuit, because test circuit has used gate drive unit's part to walk line and signal, consequently not only saved complicated control signal, simplified the test procedure, reduced moreover and walked the line, reduced the test cost.
According to the utility model discloses an aspect of the embodiment provides a test circuit for test display panel, test circuit includes a plurality of test element, and wherein, every test element includes: the first end is connected with the input end of the grid driving unit of the display panel to receive a test signal; the second end is connected with the output end of the grid driving unit so as to provide the test signal for the display panel; and the control end is connected with the reference signal end of the grid driving unit so as to receive a reference signal and control the test unit to provide the test signal for the display panel according to the reference signal.
Preferably, the input end of the gate driving unit is a start signal end or a clock signal end.
Preferably, a path between the first and second terminals of the test unit is connected when the reference signal is at a high level.
Preferably, a path between the first and second terminals of the test unit is opened when the reference signal is at a low level.
Preferably, the test unit comprises a thin film transistor, and a first end of the thin film transistor is connected with an input end of the gate driving unit; the second end of the grid driving unit is connected with the output end of the grid driving unit, and the control end of the grid driving unit is connected with the reference signal end of the grid driving unit.
Preferably, the first end of the thin film transistor is a source electrode or a drain electrode; and the second end of the thin film transistor is a drain electrode or a source electrode.
According to another aspect of the present invention, there is provided a display device, including: the test circuit comprises a plurality of test units, wherein the first end of each test unit is connected with the input end of the gate drive unit to receive a test signal, the second end of each test unit is connected with the output end of the gate drive unit to provide the test signal for the display panel, and the control end of each test unit is connected with the reference signal end of the gate drive unit to receive a reference signal and controls the test unit to provide the test signal for the display panel according to the reference signal.
Preferably, a path between the first and second terminals of the test unit is connected when the reference signal is at a high level.
Preferably, a path between the first and second terminals of the test unit is opened when the reference signal is at a low level.
Preferably, the test unit comprises a thin film transistor, and a first end of the thin film transistor is connected with an input end of the gate driving unit; the second end of the grid driving unit is connected with the output end of the grid driving unit, and the control end of the grid driving unit is connected with the reference signal end of the grid driving unit.
According to the utility model discloses test circuit and display device thereof, utilize existing gate drive unit to increase test circuit, the first end of each test unit in this test circuit is connected with one of the arbitrary input of gate drive unit, the second end is connected display panel's grid output line with gate drive unit, the control end is connected with gate drive unit's reference signal end, consequently, the part that has used gate drive unit is walked the line and is realized test signal to display panel, do not need to increase unnecessary test signal line and test pad, just can realize display panel's test, not only save complicated control signal, the testing process has been simplified, and it walks the line to have reduced the test, the testing cost is reduced.
According to the utility model discloses test circuit and display device thereof, the line of walking among the gate drive unit that test circuit used is the general line of walking of gate drive unit, for example for starting signal line, reference signal line and clock signal line etc. consequently test circuit in this application is suitable for the pixel array test of current all GIA products, does not receive the restriction that GIA circuit design changes.
According to the utility model discloses test Circuit and display device thereof, this test Circuit is connected with Gate Drive unit, is located the liquid crystal Cell (In Cell) In, consequently does not need GDC (Gate line Drive Circuit, selects the Drive Circuit of selecting the line) to light a lamp and can test to also can eliminate the TP horizontal line when testing, reinforcing detection effect.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings.
Fig. 1 shows a schematic structure of a related art display device.
Fig. 2 shows a schematic structural diagram of a display device according to a first embodiment of the present invention.
Fig. 3a shows a first circuit diagram of a gate driving unit for detection according to a first embodiment of the present invention.
Fig. 3b shows a circuit diagram of a gate driving unit for detection according to the first embodiment of the present invention.
Fig. 4 is a schematic structural diagram of a display device according to a second embodiment of the present invention.
Fig. 5a shows a first circuit diagram of a gate driving unit for detection according to a second embodiment of the present invention.
Fig. 5b shows a second circuit diagram of the gate driving unit for detection according to the second embodiment of the present invention.
Detailed Description
The invention will be described in more detail below with reference to the accompanying drawings. Like elements in the various figures are denoted by like reference numerals. For purposes of clarity, the various features in the drawings are not necessarily drawn to scale. Moreover, certain well-known elements may not be shown in the figures.
Numerous specific details of the invention, such as structure, materials, dimensions, processing techniques and techniques of components, are set forth in the following description in order to provide a more thorough understanding of the invention. However, as will be understood by those skilled in the art, the present invention may be practiced without these specific details.
Fig. 2 is a schematic structural diagram of a display device according to a first embodiment of the present application.
As shown in fig. 2, a display device 2000 according to an embodiment of the present invention includes a display panel 1100, a plurality of cascaded gate driving units 1200 and a testing circuit, where the testing circuit includes a plurality of testing units 2200, and the gate driving units 1200 and the display panel 1100 may be integrated on the same substrate to form an integrated gate driving structure.
The display panel 1100 includes pixel units 1110 arranged in an array and n scan lines 1120 transmitting gate driving signals, where n is a non-zero natural number. Each pixel unit 1110 comprises a first thin film transistor T and a liquid crystal capacitor CLCAnd a storage capacitor CSTWherein the gate electrode of the first thin film transistor T is connected to a scan line 1120. In the plurality of cascaded gate driving units 1200, one gate driving unit 1200 outputs one gate driving signal, each gate driving unit 1200 is connected to one scanning line 1120, and the gate driving signals are applied to the pixel units 1110 corresponding to the scanning lines 1120 in the display panel 1100 through the cascaded gate driving units 1200 and the scanning lines 1120, so that the pixel units 1110 in the corresponding row are turned on row by row.
The gate driving unit 1200 includes a plurality of signal terminals such as a pre-stage input terminal (e.g., G [ n-4], G [ n +4]), a clock terminal CLK, a low-level power supply terminal VGL, a high-level power supply terminal VGH, a start signal terminal STV, and a gate line output terminal G [ n ], where each signal terminal is connected to a signal input line or a signal output line, respectively, where the signal output line is a gate line and is connected to the display panel 1100; the plurality of signal line input lines are used to provide clock signals, enable signals, reference signals, and the like required by the gate driving unit 1200.
Each test unit 2200 includes a first terminal, a second terminal and a control terminal, wherein the first terminal is connected to the start signal terminal STV of the gate driving unit 1200 for receiving a test signal; the second terminal is connected to the gate line output terminal of the gate driving unit 1200, and is configured to provide a test signal to the display panel; the control terminal is connected to the reference signal terminal of the gate driving unit 1200 for receiving a reference signal, and in this embodiment, the low-level power supply terminal of the gate driving unit 1200 is, for example, the reference signal terminal. Each of the test units 2200 is turned on or off according to the reference signal, thereby controlling the test circuit to supply the test signal to the display panel.
In the first embodiment of fig. 2, only the low-level power supply terminal VGL, the start signal terminal STV and the gate line output terminal G [ n ] of the gate driving unit 1200 are shown, that is, the signal traces respectively connected to the reference signal terminal, the first terminal and the second terminal of the testing unit 2200 are shown. In this embodiment, the gate driving unit 1200 is connected to the display panel 1100, and supplies a driving signal to the display panel 1100 through the gate line output terminal G [ n ] and the gate line.
In this embodiment, the gate driving unit 1200 supplies a driving signal to the display panel 1100 through the gate line output terminal G [ n ] and the gate line. The testing unit 2200 is used for detecting the pixel unit 1110 in the display panel 1100, and specifically, the testing unit 2200 is a thin film transistor, such as an NMOS, denoted as TA. The control terminal of TA is connected to the reference signal terminal of the gate driving unit 1200, i.e. the low level signal terminal VGL, the first terminal is connected to the previous stage input terminal (e.g. the start signal terminal STV) of the gate driving unit 1200, and the second terminal is connected to the output terminal (e.g. the gate line output terminal G [ n ]) of the gate driving unit 1200, so as to be connected to the pixel array. The first terminal and the second terminal of the test unit 2200 are a source and a drain or a drain and a source of the thin film transistor TA, respectively, and the control terminal is a gate of the thin film transistor TA.
In this embodiment, when the pixel array of the display panel 1100 is detected, an ADD high voltage is input to the low-level signal terminal VGL of the gate driving unit 1200, and the reference signal received by the control terminal of each test unit 2200 is at a high level, because the test unit 2200 is an NMOS, a path between the first terminal and the second terminal of the test unit 2200 is turned on, and the test signal input through the start signal terminal STV of the gate driving unit 1200 reaches the pixel array through the test unit 2200 and the corresponding gate line, thereby detecting the pixel array. In the test stage, since the low level signal terminal VGL of the gate driving unit GIA is inputted with the ADD high voltage and the operation signal is not provided, the high voltage does not affect the GIA, and thus the gate driving unit 1200 does not operate.
In the normal display stage, the low level signal terminal VGL of the gate driving unit 1200 inputs a continuous dc low level signal, so the gate driving unit GIA works normally, and the testing unit 2200 does not turn on the NMOS because the reference signal received by the control terminal signal is low level, so the path between the first terminal and the second terminal of the testing unit 2200 is in a continuous off state, and the normal display of the display panel 1100 is not affected.
In the test circuit and the display device thereof according to the first embodiment of the present application, the test circuit includes the plurality of test units 2200, the thin film transistor TA through the test units 2200 detects the pixel array, and the first end, the second end and the control end of the thin film transistor TA are connected to the routing inherent in the gate driving unit 1200, so that the test circuit is simplified, and the test cost is saved.
Fig. 3a shows a first circuit schematic diagram of the gate driving unit for detection according to the first embodiment of the present invention, and fig. 3b shows a second circuit schematic diagram of the gate driving unit for detection according to the first embodiment of the present invention. Fig. 3a shows a circuit schematic diagram of the gate driving unit GIA being 8T1C GIA, and fig. 3b shows a circuit schematic diagram of the gate driving unit GIA being 16T1C GIA.
Referring to fig. 3a, which shows a circuit diagram of the gate driving unit and the test circuit of 8T1C, a control terminal of the thin film transistor TA of the test unit 2200 is connected to a reference signal terminal of the gate driving unit, such as a low level signal terminal VGL, a first terminal is connected to an input terminal of the gate driving unit, such as a start signal terminal STV, and a second terminal is connected to the pixel array through the gate line output terminal G [ n ]. In fig. 3a, the thin film transistor TA of the test unit 2200 is, for example, an NMOS, a Q point is located at a connection node of the first transistor and the third transistor, and a QB point is located at a connection node of the eighth transistor and the sixth transistor.
In the testing stage, a reference signal terminal of the gate driving unit is applied with a high voltage to ADD, a path between a first terminal and a second terminal of the thin film transistor TA of the testing unit 2200 is in an on state, a required testing signal is input to an input terminal of the gate driving unit, and since neither the clock signal terminal CLK nor the DC terminal is applied with a signal, a Q point and a QB point are in an off state, the high voltage does not affect the gate driving unit, but the testing signal enters the display panel through the testing unit 2200, and the pixel array is tested. In the normal display phase, since the reference signal terminal of the gate driving unit is at a low voltage level of the continuous dc, the path between the first terminal and the second terminal of the thin film transistor TA of the testing unit 2200 is in an off state, and the normal display of the display panel 1100 is not affected.
Referring to the schematic circuit diagram of the gate driving unit and the test circuit of 16T1C shown in fig. 3b, the control terminal of the thin film transistor TA of the test unit 2200 is connected to the reference signal terminal of the gate driving unit, such as the low level signal terminal VGL, the first terminal is connected to the input terminal of the gate driving unit, such as the start signal terminal STV, and the second terminal is connected to the pixel array through the gate line output terminal G [ n ].
In a test stage, a reference signal end of the gate driving unit is applied with high voltage to ADD, a path between a first end and a second end of a thin film transistor TA of the test circuit is in an open state, a required test signal is input to an input end of the gate driving unit, and since CLK and DC do not apply signals, a Q point and a QB point are in an off state, the high voltage does not affect the gate driving unit, but the test signal enters the display panel through the test circuit to test the pixel array. In the normal display phase, since the reference signal terminal of the gate driving unit is at a low voltage level of the continuous dc, the path between the first terminal and the second terminal of the thin film transistor TA of the test circuit is in an off state, and the normal display of the display panel 1100 is not affected.
Fig. 4 is a schematic structural diagram of a display device according to a second embodiment of the present invention. Fig. 5a shows a first circuit diagram of a gate driving unit and a testing circuit according to a second embodiment of the present invention. Fig. 5b shows a second circuit schematic diagram of the gate driving unit and the testing circuit according to the second embodiment of the present invention.
The second embodiment shown in fig. 4 is different from the first embodiment shown in fig. 2 in that the first terminal of the thin film transistor TA of the test unit is different from the gate driving unit connection input terminal. The same points as those in the first embodiment will not be described in detail, and only the differences will be described.
Referring to fig. 4, in the second embodiment, a control terminal of the thin film transistor TA, e.g., an NMOS, of the test unit 3200 is connected to a reference signal terminal, e.g., a low-level signal terminal VGL, of the gate driving unit 1200, a first terminal of the thin film transistor TA is connected to the clock signal terminal CLK of the gate driving unit, and a second terminal of the thin film transistor TA is connected to the pixel array through the gate line output terminal G [ n ].
In this embodiment, when the pixel array of the display panel 1100 is detected, an ADD high voltage is input to the reference signal terminal of the gate driving unit, the thin film transistor TA of the testing unit 3200 is turned on, for example, an NMOS, and the test signal input through the clock signal terminal CLK of the gate driving unit 1200 reaches the pixel array through the thin film transistor TA and the corresponding gate line, so that the pixel array is detected. In the test phase, the reference signal terminal of the gate driving unit inputs the ADD high voltage and no other working signal is provided, so the gate driving unit 1200 is not affected by the high voltage, and thus the gate driving unit 1200 does not work.
In the normal display stage, the reference signal terminal of the gate driving unit inputs a continuous dc low level signal, so that the gate driving unit 1200 normally operates, and the path between the first terminal and the second terminal of the thin film transistor TA of the testing unit 3200 is in a continuous off state, which does not affect the normal display of the display panel 1100.
Referring to fig. 5a and 5b, in the test phase, the low level signal terminal VGL is applied to ADD high voltage, the CLK signal line is applied with the required test signal, and since STV and DC are not applied, the Q point and QB point are in the off state, and the high voltage does not affect the gate driving unit. In the normal display phase, the low level signal terminal VGL of the gate driving unit is at a low level of a continuous direct current, so that the path between the first terminal and the second terminal of the thin film transistor TA is in an off state, and the normal display of the display panel is not affected.
According to the utility model discloses test circuit and display device thereof, utilize existing grid drive unit to increase a test circuit, the first end of each test unit is connected with one of the arbitrary input of grid drive unit in this test circuit, the second end is connected display panel's grid output line with grid drive unit, the control end is connected with grid drive unit's reference signal end, consequently, the part that has used grid drive unit is walked the line and is realized test signal to display panel, do not need to increase unnecessary test signal line and test pad, just can realize display panel's test, not only save complicated control signal, the testing process has been simplified, and reduced the test and walked the line, the testing cost is reduced.
According to the utility model discloses test circuit and display device thereof, the line of walking among the gate drive unit that test circuit used is the general line of walking of GIA product, therefore the test circuit of this application is suitable for the pixel array test of current all GIA products, does not receive the restriction that GIA circuit design changes.
According to the utility model discloses test Circuit and display device thereof, this test Circuit is In the LCD box (In Cell), consequently does not need GDC (Gate line Drive Circuit, selects the Drive Circuit of line) to light a lamp and can test to also can eliminate the TP horizontal line when testing, reinforcing detection effect.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed
Other elements may be identified as being inherent in such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
In accordance with the embodiments of the present invention as set forth above, these embodiments are not exhaustive and do not limit the invention to the precise embodiments described. The above description is only a preferred embodiment of the present invention, and should not be taken as limiting the invention, and any person skilled in the art can make various changes, modifications, etc. without departing from the scope of the present invention. The embodiments were chosen and described in order to best explain the principles of the invention and its practical application, to thereby enable others skilled in the art to best utilize the invention and its various embodiments with various modifications as are suited to the particular use contemplated.
Claims (10)
1. A test circuit for testing a display panel, the test circuit comprising a plurality of test cells, wherein each test cell comprises:
the first end is connected with the input end of the grid driving unit of the display panel to receive a test signal;
the second end is connected with the output end of the grid driving unit so as to provide the test signal for the display panel;
and the control end is connected with the reference signal end of the grid driving unit so as to receive a reference signal and control the test unit to provide the test signal for the display panel according to the reference signal.
2. The test circuit of claim 1, wherein the input terminal of the gate driving unit is an enable signal terminal or a clock signal terminal.
3. The test circuit of claim 1, wherein a path between the first and second terminals of the test cell is connected when the reference signal is high.
4. The test circuit of claim 1, wherein a path between the first and second terminals of the test cell is open when the reference signal is low.
5. The test circuit of claim 1, wherein the test unit comprises a thin film transistor, a first terminal of the thin film transistor being connected to the input terminal of the gate driving unit; the second end of the grid driving unit is connected with the output end of the grid driving unit, and the control end of the grid driving unit is connected with the reference signal end of the grid driving unit.
6. The test circuit of claim 5, wherein the first end of the thin film transistor is a source or a drain; and the second end of the thin film transistor is a drain electrode or a source electrode.
7. A display device, comprising: a display panel, a plurality of cascaded gate driving units and a test circuit,
wherein the plurality of cascaded gate driving units drive the display panel through gate lines;
the test circuit comprises a plurality of test units, wherein a first end of each test unit is connected with an input end of the gate driving unit to receive a test signal, a second end of each test unit is connected with an output end of the gate driving unit to provide the test signal for the display panel, and a control end of each test unit is connected with a reference signal end of the gate driving unit to receive a reference signal and control the test unit to provide the test signal for the display panel according to the reference signal.
8. The display device according to claim 7, wherein a path between the first terminal and the second terminal of the test unit is connected when the reference signal is at a high level.
9. The display device according to claim 7, wherein a path between the first terminal and the second terminal of the test unit is opened when the reference signal is low.
10. The display device according to claim 7, wherein the test unit comprises a thin film transistor, a first terminal of the thin film transistor being connected to an input terminal of the gate driving unit; the second end of the grid driving unit is connected with the output end of the grid driving unit, and the control end of the grid driving unit is connected with the reference signal end of the grid driving unit.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN112992024A (en) * | 2021-02-08 | 2021-06-18 | 昆山龙腾光电股份有限公司 | Display device and detection method thereof |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN112992024A (en) * | 2021-02-08 | 2021-06-18 | 昆山龙腾光电股份有限公司 | Display device and detection method thereof |
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