CN1148793C - Film carrier tape, tape carrier semiconductor device assembly, semiconductor device, its manufacturing method, package substrate, and electronic appliance - Google Patents
Film carrier tape, tape carrier semiconductor device assembly, semiconductor device, its manufacturing method, package substrate, and electronic appliance Download PDFInfo
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- CN1148793C CN1148793C CNB971914699A CN97191469A CN1148793C CN 1148793 C CN1148793 C CN 1148793C CN B971914699 A CNB971914699 A CN B971914699A CN 97191469 A CN97191469 A CN 97191469A CN 1148793 C CN1148793 C CN 1148793C
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/4985—Flexible insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/86—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using tape automated bonding [TAB]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12042—LASER
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Wire Bonding (AREA)
Abstract
A film carrier tape which makes it possible to reduce bending of leads in a manufacturing process, to produce a chip-size package with high reliability and to improve a production yield. The distal end portions of leads (54a, 54b) of a TAB are left as free ends from the pattern formation step without being connected to a frame (59) and are not at all processed till the final bonding step. On the other hand, a plurality of connecting portions (57a to 57j) are disposed in a packaging area of a semiconductor chip, and a large number of leads are connected at the inner side of the packaging surface of one IC chip and are electrically connected to the frame through the connecting portions.
Description
Technical field
The manufacture method, the band that the present invention relates to a kind of film carrier tape manufactured using carry the manufacture method of semiconductor device assembly, manufacture method, film carrier tape manufactured using, semiconductor device, base plate for packaging and the electronic equipment of semiconductor device, particularly, the manufacturing technology and the CSP encapsulation technology that relate to chip size/scale encapsulation (Chip Size/ScAle Package:CSP-chip-scale package).
Background technology
To the encapsulation of chip size/scale (Chip Size/ScAle Package: below, be referred to as CSP), though informal definition,, general package dimension is identical with chip size, or is interpreted as big slightly semiconductor packages (IC encapsulation).In order to advance high-density packages, so exploitation CSP technology is important.
As the existing embodiment that relates to the CSP technology, existing international open WO95/08856 communique.In this communique, go up the arrangement lead frame at lead frame supporting mass (particular manufacturing craft), lead-in wire cut-out (each bar) one by one, simultaneously the lead-in wire that has cut off is bent to downside with special utensil, adopted with the IC chip on pad be connected such mode.
In the method, need special mould and plant equipment, in addition, it is crooked that lead-in wire also takes place when the cut-out lead-in wire welds the IC chip easily.
Summary of the invention
The objective of the invention is to, utilize existing manufacturing process line as far as possible and both deposited technology, the limit alleviates the burden of equipment, the development effort of special technique etc., the limit reduces the lead-in wire bending of manufacturing process, and under high reliability, make the encapsulation of chip size, improve rate of finished products simultaneously.
The manufacture method of film carrier tape manufactured using of the present invention has: the operation that forms conductor foil on the insulating properties film;
Form the operation of conductor fig by above-mentioned conductor foil, this conductor fig has, and forms an end and has with a plurality of leads of the electrical connections of semiconductor chip, is located on the packaging area of above-mentioned semiconductor chip and coupling part that above-mentioned a plurality of leads is connected with each other, the framework that is electrically connected with all above-mentioned lead-in wire by above-mentioned coupling part as free end and at above-mentioned free end;
Above-mentioned conductor fig is implemented the operation of electroplating; And
Die-cut above-mentioned coupling part makes each bar of above-mentioned a plurality of leads become the electric operation that independent lead-in wire.
In the present invention, utilize the manufacturing process line of existing TAB (Tape Automated Bonding-belt is welded automatically) as far as possible and both deposited technology, and alleviate the development effort of facility load and special technique.
And most important guide-wire tip part (with the coupling part of semiconductor chip, so-called pointer) is free of attachment to framework, during from the formation figure, till cut-out (that is, disconnecting), welding sequence, does not add processing.In addition, in welding sequence,,, just do not cut off the worry that stress is added up so do not need to cut off because pointer disconnects yet.Just, after figure has formed,, thereby prevented the bending of lead-in wire because of not outer load is added on the lead-in wire.And, correctly go between and the pad of semiconductor chip between the position overlap.
But,, for example, implement in batch and electroplate, and must finally be electrically connected all lead-in wires with framework (framework) for to a plurality of leads on the insulating properties film that is formed at polyimides etc.
Thereby, in a first aspect of the present invention, a plurality of coupling parts of configuration are connected to inboard at a semiconductor die package face to a plurality of leads in the packaging area of semiconductor chip, and, constitute the structure that is connected with electric framework (framework) by this coupling part.Therefore, can give the framework making alive.For example, one pole (in general, being an electrode) is connected on the framework, electroplates in batch to containing leaded conductor fig.
And, with the common molding of insulating properties film and remove unwanted coupling part, each lead-in wire electricity is isolated.This molding can be carried out in batch, can not cause the complicated of operation.In addition, because " coupling part " is configured in the inboard of the encapsulating face of 1 IC chip, so leave the guide-wire tip part (pointer) that is positioned at Chip Packaging face border.Therefore, the cut-out of coupling part is to which guide-wire tip part (pointer) also not influence.
So, can prevent that lead-in wire is crooked, realize welding accurately, and don't make complex proceduresization.
In the operation that forms above-mentioned conductor fig, and then can between above-mentioned lead-in wire and above-mentioned coupling part, be formed for forming the pad portion of outside terminal for connecting.
And, before the operation that forms above-mentioned conductor foil, and then can have the die-cut operation that on the assigned position of above-mentioned insulating properties film, forms the hole.
Above-mentioned IC chip has the electrode of avoiding above-mentioned electrical connections position.
And then have, with above-mentioned lead-in wire in the end of an above-mentioned end for not existing together, at place, above-mentioned electrode place, form the operation of conductive bump.
For the base plate for packaging with printed circuit board etc. links up, will form conductive bump.
And then also can have, the zone beyond the above-mentioned electrical connections of removing above-mentioned conductor fig, and on the zone of the above-mentioned semiconductor chip of encapsulation, form protruding operation.
Also have, form in film carrier tape manufactured using one side under the situation of projection, also can when the manufacturing of CSP encapsulation, convex to form, rather than when the manufacturing of film carrier tape manufactured using, carry out the formation of its projection.
Also can form like this, before the operation that forms above-mentioned conductor fig, on above-mentioned insulating properties film, opening portion is set, above-mentioned free-ended end is positioned on the above-mentioned opening portion zone.
To weld accurately, opening portion is set exactly, make the top of lead-in wire become free end.
With the above-mentioned opening portion adjoining position of above-mentioned insulating properties film, on the free-ended extended line of above-mentioned lead-in wire, also can form above-mentioned lead-in wire curved detection mark.
Just in case, under the situation that lead-in wire bends, should detect its bending, and differentiation is substandard product.Thereby the crooked benchmark of differentiating of regulation lead-in wire has formed lead-in wire curved detection mark exactly.
As lead-in wire curved detection mark, can consider, for example, in " dummy leads " be located on the lead-in wire extended line, or the regulation place on the extended line of identical lead-in wire, adopt the way of on the insulating properties film, carrying out molding, make it to form " otch ".
Above-mentioned curved detection mark also can be used with above-mentioned conductor fig same processes to form in the formation operation of above-mentioned conductor fig.
Adopt the etched way of selection of conductor foil, also should form curved detection mark (dummy leads) with desirable conductor fig.If adopt this manufacture method, owing to do not need to be used to form the independent operation of curved detection with mark, thereby manufacturing process can be not complicated.
And then also can possess and have, by means of above-mentioned curved detection relatively, detect the operation of above-mentioned curved detection usefulness mark with the position between the above-mentioned end of the position of mark and above-mentioned lead terminal.
Therefore, can screen substandard product.
Also can be in the formation operation of above-mentioned conductor fig, form the part among the above-mentioned a plurality of leads, make it to possess from above-mentioned insulating properties film and to above-mentioned opening portion a pair of projection that protrudes and the coupling part that is connected above-mentioned a pair of projection.
Principle of the present invention is to be guide-wire tip (pointer) terminal, and makes it become free end.
Yet, should be corresponding with IC bonding pads position, for example, the top of a plurality of leads (pointer) must be positioned at the situation on the same line sometimes, under these circumstances, has to guide-wire tip (pointer) shape is made crooked shape.But if the top of a lead-in wire has become bending, then owing to gravity, the distortion of lead-in wire takes place in unwanted moment loading easily.Thereby, under these circumstances, also can use "
Font " lead-in wire of shape, with the tie point of two lead portion supports and IC chip.
Therefore, the moment of distortion is inoperative.Particularly, in order to make left and right sides balance good, wish to make symmetrical shape.
With above-mentioned projection and coupling part formation square is desirable.
Employing is done lead format to become, the figure that only is suitable for adopting rectangular coordinate system in TAB manufacturing process line (specifically, for example, remove outside radiation wire and the circular-arc figure, elevational plot) way of planform, so that differentiate lead-in wire bending etc. easily, also can discern automatically with transducer.
An above-mentioned side's projection and the opposing party's projection are provided with at interval, and other lead-in wire is mediate is advisable.
In the formation operation of above-mentioned conductor fig, also can implement processing at the thickness direction of lead-in wire, make that the electrical connections with the above-mentioned semiconductor chip of above-mentioned lead-in wire has become the shape of protruding.
In common TAB operation, with regard to being connected between the lead-in wire of TAB and the semiconductor chip, though form the bump electrode (projection) of metal on semiconductor chip, forming this bump electrode is quite to take a lot of trouble.Thereby, on semiconductor chip, do not form bump electrode, but form bump electrode (projection) in lead-in wire one side of TAB.For example, except that the top of lead-in wire, the regulation place is carried out half etch reduce thickness, and only make the guide-wire tip (pointer) of this part outstanding.Processing the technology of this guide-wire tip, is exactly the technology that real result is arranged that the applicant has developed, and utilizes existing this technology of TAB to realize.In addition, under these circumstances,, do not need the metal salient point electrode yet and simplified operation as long as aluminum pad is exposed in semiconductor chip one side.
Film carrier tape manufactured using of the present invention is with above-mentioned manufacture method manufacturing.
And obtain to be suitable for the film carrier tape manufactured using that CSP makes.
Film carrier tape manufactured using of the present invention has: formed fairlead insulating properties film;
On above-mentioned insulating properties film, an end extends setting and becomes free-ended lead-in wire in the zone of above-mentioned fairlead; And
The above-mentioned lead-in wire curved detection mark that on the above-mentioned insulating properties film that is positioned on the above-mentioned free-ended extended line, forms.
Also can be distolateral at another of above-mentioned lead-in wire, be formed for forming the pad portion of external connection terminals.
Film carrier tape manufactured using of the present invention has: formed fairlead insulating properties film;
On above-mentioned insulating properties film, form conductor fig, and the framework that conductor fig has a plurality of leads that is used for being connected with semiconductor chip, the coupling part that interconnects above-mentioned a plurality of leads is set in above-mentioned semiconductor die package zone and is electrically connected with all above-mentioned lead-in wire by above-mentioned coupling part; And
Above-mentioned coupling part at above-mentioned conductor fig can obtain shaped hole.
Film carrier tape manufactured using of the present invention has: the insulating properties film;
The a plurality of leads that forms in parallel on above-mentioned insulating properties film;
Be positioned at the close position of above-mentioned a plurality of leads, with predetermined distance at interval, interconnective pair of lead wires of while; And
Other lead-in wire that between above-mentioned pair of lead wires, forms.
Band of the present invention carries the manufacture method of semiconductor device assembly, be on an end of each above-mentioned terminal of the above-mentioned a plurality of leads of above-mentioned film carrier tape manufactured using, to connect the electrode of semiconductor chip, and make the method for band of a plurality of semiconductor-chip-mountings on above-mentioned insulating properties film having been carried the semiconductor device assembly.
Can effectively utilize the characteristics of TAB mode, be unit with the film carrier tape manufactured using, carries out continuous batch processing, makes the aggregate (assembly) of a plurality of semiconductor devices.Also just can dispatch from the factory to client with such assembly unit.
The present invention can also have encapsulating material is filled into operation between above-mentioned semiconductor chip and the above-mentioned insulating properties film.
Encapsulating material plays the coefficient of thermal expansion differences between protection semiconductor chip and absorption chip and the insulating properties film.As encapsulating material, can adopt materials such as epoxy resin, silicones, synthetic rubber.
The manufacture method of semiconductor device of the present invention, the band that adopts manufacture method that above-mentioned band carries the semiconductor device assembly to make carries the semiconductor device assembly and carries out final molding, makes semiconductor device thus.
Should finally carry out molding and be divided into singlely, obtain the semiconductor device (CSP encapsulation) of end article itself.In addition, also can in this stage, form conductive bump.
Semiconductor device of the present invention is made with the manufacture method of above-mentioned semiconductor device.
And the semiconductor device of acquisition high reliability.Owing to made packing forms, so processing such as also can wear out.
Base plate for packaging of the present invention is become on the conductor layer that is connected on the base plate for packaging by the described external connection terminals of above-mentioned semiconductor device.
It is a kind of semiconductor device that carries chip size packages (CSP), highdensity base plate for packaging.
For example, even under the situation of gassing, by means of the molding of " coupling part ", also work as the hole that gaseous emission is used in the hole that generates on the insulating properties film on the interface of encapsulating material and semiconductor chip, the gas of the steam that produces when for example, making the encapsulation heating etc. is outwards selected.Therefore, can not reduce the reliability of encapsulation.
Electronic equipment of the present invention constitutes by above-mentioned base plate for packaging has been installed.
Particularly, improved the predestined reliability of taking small-sized, the lightweight electronic equipment of mobile electronic apparatus and so on.
The manufacture method of semiconductor device of the present invention has: the operation that forms conductor foil on the insulating properties film;
Form the operation of conductor fig by above-mentioned conductor foil, and this conductor foil has, form an end as free end and above-mentioned free end be used for a plurality of leads that is connected of semiconductor chip, be arranged on above-mentioned semiconductor chip packaging area the interconnective coupling part of above-mentioned a plurality of leads, and the framework that is electrically connected with all above-mentioned lead-in wire by above-mentioned coupling part;
Above-mentioned conductor fig is implemented the operation of electroplating;
Die-cut above-mentioned coupling part makes each bar of above-mentioned a plurality of leads become the electric operation that independent lead-in wire;
The operation that the electrode of the part of above-mentioned lead-in wire and semiconductor chip is coupled together; With
Separate said frame and above-mentioned a plurality of leads at last, and form the operation of semiconductor device.
In the present invention, after the connection of semiconductor chip is finished, the lead-in wire of TAB and framework are cut, so do not worry the failure welding of the semiconductor chip that causes because of the bending that goes between.The requirement of package dimension is the method that is suitable for the situation of the mitigation of comparison.
Separate between the operation that forms semiconductor device with above-mentioned in the operation that is connected to above-mentioned electrode,
Can also have resin is filled into operation between above-mentioned semiconductor chip and the described insulating properties film.
Description of drawings
Fig. 1 is the profile of film carrier tape manufactured using of the 1st operation of expression manufacturing method for semiconductor device of the present invention, Fig. 2 is the profile of film carrier tape manufactured using of the 2nd operation of expression manufacturing method for semiconductor device of the present invention, Fig. 3 is the profile of film carrier tape manufactured using of the 3rd operation of expression manufacturing method for semiconductor device of the present invention, Fig. 4 is the profile of film carrier tape manufactured using of the 4th operation of expression manufacturing method for semiconductor device of the present invention, Fig. 5 is the profile of film carrier tape manufactured using of the 5th operation of expression manufacturing method for semiconductor device of the present invention, Fig. 6 is the profile of film carrier tape manufactured using of the 6th operation of expression manufacturing method for semiconductor device of the present invention, Fig. 7 is the profile of film carrier tape manufactured using of the 7th operation of expression manufacturing method for semiconductor device of the present invention, Fig. 8 is the profile of film carrier tape manufactured using of the 8th operation of expression manufacturing method for semiconductor device of the present invention, Fig. 9 is the profile of film carrier tape manufactured using of the 9th operation of expression manufacturing method for semiconductor device of the present invention, Figure 10 is the film carrier tape manufactured using of the 9th operation of expression manufacturing method for semiconductor device of the present invention and the profile of semiconductor chip, Figure 11 is the film carrier tape manufactured using of the 10th operation of expression manufacturing method for semiconductor device of the present invention and the profile of semiconductor chip, Figure 12 is the film carrier tape manufactured using of the 11st operation of expression manufacturing method for semiconductor device of the present invention and the profile of semiconductor chip, Figure 13 is the device profile map of the variation of expression semiconductor device of the present invention, Figure 14 is the plane graph of the film carrier tape manufactured using in the operation of Fig. 2, Figure 15 is the plane graph of the film carrier tape manufactured using in the operation of Fig. 6, Figure 16 is the plane graph of the film carrier tape manufactured using in the operation of Figure 10, Figure 17 is the plane graph of the film carrier tape manufactured using in Figure 11 operation, Figure 18 is the plane graph that has been separated into single semiconductor device of the present invention, Figure 19 is the characteristic pattern that is used to illustrate film carrier tape manufactured using manufacture method of the present invention (manufacture method of semiconductor device), Figure 20 is the another kind of characteristic pattern that is used to illustrate film carrier tape manufactured using manufacture method of the present invention (manufacture method of semiconductor device), Figure 21 A～21D is another characteristic pattern that is used to illustrate film carrier tape manufactured using manufacture method of the present invention (manufacture method of semiconductor device), Figure 22 is the figure of the variation of expression film carrier tape manufactured using manufacture method of the present invention (manufacture method of semiconductor device), Figure 23 is the profile of base plate for packaging of the present invention, and Figure 24 is the interior view of expression electronic equipment of the present invention.
Embodiment
The most preferred embodiment that is used to carry out an invention
Then, with reference to the description of drawings embodiments of the invention.
(1) the 1st embodiment
In the present embodiment, effectively utilize TAB (Tape Automated Bonding-belt is welded automatically) technology, and realized the manufacturing of the semiconductor device of chip size.If adopt the such method of present embodiment, then utilize manufacturing process line and the prior art of existing TAB as far as possible, alleviate the burden of equipment and the development effort of special technique, on the other hand, can under high reliability, make the encapsulation of chip size, simultaneously, improve its rate of finished products.
(principal character of present embodiment)
Before the explanation concrete example,, the principal character of present embodiment is described with Figure 19～Figure 21 D.
(a) as shown in figure 19, on the polyimide film 10 that is provided with regulation opening portion (fairlead 40a～40c, resin inject with hole 42 etc.), the conductor material that forms the paper tinsel shape with the conductor material of copper etc. is set, and this conductor material for example corroded etc., form conductor fig.This conductor fig also can be formed on the surface or the back side of polyimide film.And, can also on two faces, form.Under these circumstances,, also can on polyimide film, form through hole, utilize this through hole that the two sides is conducted though accompanying drawing does not draw.
This conductor fig possesses: framework (framework) 59a, 59b, 59c, lead-in wire (54a～54x, 54y etc.), whole form or split forms the pad 55 of conductive bump, a plurality of coupling parts (57a～57x, 57y etc.) that are used to interconnect each lead-in wire (with each pad), the suspension that is used to be electrically connected framework (framework) and the lead wire set (TR1～TR3) that goes between for example.
Also have, also can side be provided with projection assembling as required, and conductive bump needn't be arranged in pad portion, in addition, even for example be provided with under the situation of conductive bump in pad portion, also be not limited in pre-set when band forms or operation afterwards in, for example when encapsulation forms and be provided with later on.
The head portion of lead-in wire (54a～54x, 54y etc.) is the part that is connected with the IC chip, is referred to as pointer.(40a～40c) go up (that is, in the fairlead) is a terminal to each pointer, and makes it to become free end at fairlead.Just, the pointer that is positioned at fairlead one side has been predefined for terminal when figure forms, until all not standing what processing at last till connecting (welding) on the IC bonding pads.And, even when the IC bonding pads welded,, pointer do not need to cut off because becoming free end, therefore, also cause the pointer bending because of cutting off stress with regard to not taking place.Thereby, can go between and the IC chip between correct position involutory and the welding.
But in order to make a plurality of leads (54a etc.) of formation implement plating in batch on the insulating properties film to polyimides etc., all lead-in wires need to be electrically connected with framework (framework) 59a, 59b, 59c after all.Thereby, in the present embodiment, configuration a plurality of coupling parts (57a～57x, 57y etc.) in the packaging area of IC chip, and connect a plurality of leads in the inboard of the encapsulating face of 1 IC chip, and, by this coupling part (57a～57x, 57y etc.), become the formation that is connected with framework (framework) 59a, 59b, 59c, therefore, a utmost point of battery 800 is connected on framework (framework) 59a, 59b, the 59c, and the conductor fig of leaded to containing (54a etc.) is electroplated in batch.Also have, " packaging area of IC chip " and " encapsulating face of 1 IC chip " together, haply with wrap the CSP that represents with the chain-dotted line among Figure 19 and hold 700 consistent.
And unwanted coupling part (57a～57x, 57y etc.) carry out molding with the insulating properties film and remove, and make the electric independent of going up of each lead-in wire (54a～54x, 54y etc.).Such molding can be carried out in batches, can not cause the complicated of operation.In addition, though complicated as operation, the insulating properties film portion is not necessarily die-cut good, and die-cut lead portion makes electric the going up independently just that respectively go between at least.And,, leave the borderline guide-wire tip part (pointer) that is positioned at the Chip Packaging face with the encapsulating face inboard that coupling part (57a～57x, 57y etc.) are configured in 1 IC chip.Therefore cut off coupling part (57a～57x, 57y etc.), to the not influence of head portion (pointer) of any lead-in wire.
In the present embodiment, though be provided with a plurality of coupling part 57a ..., but reduce its number as far as possible, the molding operation is simplified.
Also have, adopt coupling part 57a ... the hole of carrying out the way of molding and forming also can be used as, and for example the hand-hole of epoxy resin (with reference to Figure 12) particularly, when the hole is positioned at central authorities, can carry out the injection of epoxy resin effectively in plan view.
And then if consider the intensity of polyimide film 10, the position that then disperses a plurality of coupling part 57a is desirable.Under these circumstances, coupling part 57a is carried out molding and formed the hole, the steam evacuation aperture of deaeration and completed semiconductor device in the time of can injecting as epoxy resin.
So, can prevent that lead-in wire is crooked, guarantee to realize welding, and do not make complex proceduresization.Can also electroplate in batch.
And though only show the part of circuitous pattern in Figure 19, in fact same circuitous pattern is formed on the film continuously.
(b) in the present embodiment, utilize existing TAB technology, effectively be utilized as target with existing manufacturing process line and existing technology.Just, as shown in figure 20, the insulating properties film 10 in the packaging area of an IC chip is supported by support bar 800a, 800b, 800c, 800d, and becomes an integral body with the other parts of insulating properties film.Therefore, can be the insulating properties film as handling unit, batch processing continuously.Also have, in Figure 20, be provided with 4 support bars, but 2 support bars are set at least.It is desirable to, with 2 support bars be arranged on relatively to the position, for example be arranged at parallel both sides.
But, under the situation of existing film carrier tape manufactured using, owing to do not have mark, so in the present embodiment, form the lead-in wire curved detection again with mark (as concrete example, dummy leads) with respect to the bending of head portion (pointer) of lead-in wire 54a.Just, dummy leads (52a etc.) is set, as the crooked benchmark of judging of pointer.
(52a etc.) are located on the extended line of pointer with dummy leads.Therefore, become and to have checked the pointer bending, become and to screen substandard product.Particularly, at the dummy leads shown in Figure 20 (52a etc.), the top is tapered, and the bending of the easier detection lead-in wire 54a that becomes, and can reduce the work man-hour that needs inspection.But,, also can be used for the inspection of pointer bending to dummy leads (52a etc.) even the top is attenuated.
When forming conductor fig, it is desirable forming dummy leads (52a etc.) simultaneously.But, be not limited thereto, for example, also can form dummy leads in addition with other material of anti-scolder agent etc.Also have, under these circumstances, dummy leads can form with well-known printing technology.
Also have, more than " dummy leads " said be the example of lead-in wire curved detection with mark, other mark also can use.For example, also can be that appropriate location at the insulating properties film carries out molding and forms otch, with this otch as the curved detection mark.
(c) guide-wire tip among the present invention (pointer) is a terminal, and to become free end be principle.
Yet, shown in Figure 21 A～Figure 21 D, sometimes must be on same line, dispose corresponding with IC bonding pads position, for example, the top of a plurality of leads (pointer).For example, shown in Figure 21 A, be on the same line with the pad 240c and the 240d of IC chip (CP).
Under this occasion, need be shown in Figure 21 B be made into lead-in wire 54 radial, or shown in Figure 21 C, make meander-like.
Yet radial lead-in wire and rectangular coordinate system are inconsistent, exist the problem that film carrier tape manufactured using is made, and, if the top complications of lead-in wire become free end,, be easy to generate reversing of lead-in wire because gravity causes unwanted moment to work.
Thereby, under these circumstances, make lead format such shown in Figure 21 D.Just, lead-in wire LR2 is set, makes it around lead-in wire LR1.Lead portion A, B, C that this lead-in wire LR2 is stretched out by the orientation that meets rectangular coordinate system constitute.That is, lead-in wire LR2 does not have free end, and become "
Font ".
The Y of lead-in wire LR1 partly is connected on the IC chip bonding pad 240d of Figure 21 A, and the X of lead-in wire LR2 partly is connected on the pad 240c.That is, make with 2 lead portion (A, C) and support tie point (X point) with the IC chip.Therefore, do not work the moment loading that reverses.In order to make left and right sides balance well, it is desirable that the shape of lead-in wire LR2 is made symmetrical shape.
(concrete example of manufacturing method for semiconductor device)
The concrete example of the manufacturing method for semiconductor device of present embodiment then, is described with Fig. 1～Figure 12 (profile) and Figure 14～Figure 18 (plane graph).Figure 14 is corresponding with Fig. 2, and Figure 15 is corresponding with Fig. 5, and Figure 16 is corresponding with Figure 10, and Figure 17 is corresponding with Figure 11.Particularly, till Fig. 1～Figure 10, be the operation that forms so-called flexible substrate, Figure 11 is a welding sequence, Figure 12 is the resin injection process.
Operation 1
As shown in Figure 1, have insulating properties film (specifically, polyimide film) 10, and at the back side of this polyimide film 10 application of adhesive 12.Also have,, except that the polyimides based material, can use various thin-film materials such as polyester system, BT resin system, glass epoxide system as the insulating properties film.In a word, the insulating properties film is to have flexual material.Also have, below the supposition example of polyimide film as the insulating properties film.
Operation 2
For example, adopt the desirable perforate ways such as die-cut, laser processing, chemical corrosion processing of punch press, as Fig. 2 and shown in Figure 14, optionally insulating properties film 10 is carried out opening, through hole 30 (30a～30x etc.), fairlead 40 (40a, 40b etc.), resin injection hole (42), resin stop aperture (44a, 44b) are set.Wherein, fairlead 40a, 40b as shown in figure 11, have formed the size that can insert soldering appliance 5000.
Also have, owing to all to form wiring on which face of insulating properties film, thereby determined the necessity that through hole 30 exists.And resin stop aperture (44a, 44b) is the key factor of adding, and also can not have this hole.Resin injects with hole (42), also can for example utilize fairlead 40 and saves it.But, if consider the injection rate of resin and the reliability of injecting, then actively to utilize resin to inject with hole (42) for well.
Operation 3
As shown in Figure 3, on the back side of polyimide film 10 (below among this figure), paste Copper Foil 50.Also have,, as operation 1 illustrates, also can no longer on predetermined polyimide film 10, establish adhesive 12 as being provided with adhesive in Copper Foil one side.
Operation 4
As shown in Figure 4, on two faces of substrate, form photoresist 60 and 62 on the Copper Foil 50 as being included in.In the figure, surface (among this figure a top) side is provided with photoresist all sidedly, and on the other hand, the back side one side is because of forming figure, and has the zone that photoresist is not set.
Operation 5
As shown in Figure 5, Copper Foil 50 is corroded, form the conductor fig of regulation, then, remove photoresist 62.The plane graph of this state is Figure 15.
As be shown in Figure 15, the conductor fig that is made of copper for example has framework 59a, 59b and 59c, lead-in wire (54a, 54b, LR1, LR2 etc.), the pad portion (55a～55x etc.) that is used to form conductive bump, coupling part (57a～57j) and dummy leads (52a, 52b etc.).In Figure 15,, add identical label with Figure 19, Figure 20 of before having illustrated, the part that Figure 21 D is identical.Among Figure 15, the Q that with dashed lines fences up partly is the part suitable with Figure 21 D.
Under such state, each member of formation except that dummy leads (52a, 52b etc.), that is, (57a～57j) has become electric conducting state framework 59a, 59b, 59c, lead-in wire (54a, 54b, LR1, LR2 etc.), the pad portion (55a～55x etc.) that is used to form conductive bump and coupling part.
Operation 6
(part that connects the IC chip: pointer) outstanding and form the bump electrode (Fig. 8) that connects usefulness, at first, as shown in Figure 6, conductor fig regulation is overleaf put formation photoresist 70,72,74 should to make the head portion of lead-in wire 54a etc.Also have, the length relation of lead-in wire 54a, 54b, LR1, LR2 is to the position of the AL electrode 240a～240d of IC chip 2000.And, as present embodiment, with IC chip 2000 in the polyimide film 10 relative to a side on, formed under the situation of lead-in wire 54a, 54b, LR1, LR2, these lead-in wires can not be welded on Al electrode 240a～240d agley.And, because these do not need to consider the shaping processing capacity, so just enough with shortest length.On the contrary, with IC chip 2000 in the polyimide film 10 relative to the opposite side of face on formed under the situation of lead-in wire 54a, 54b, LR1, LR2, owing to need make these lead-in wires crooked, be welded on Al electrode 240a～240d, consider amount of bow, and do these lead-in wires to such an extent that length is desirable a bit.
Operation 7
As shown in Figure 7, a side is partly corroded conductor fig at thickness direction overleaf.
As shown in Figure 8, remove photoresist 60,70,72 and 74.According to illustrated like that, in the head portion (part that is connected with the IC chip: pointer) formed protruding 56a of lead-in wire 54a etc.In welding sequence after this, this projection 56a is linked on the electrode of semiconductor chip Al.
Also have, at this moment, the part beyond pointer also is fit to form protruding 56b.For example, this projection 56b also can bring into play the gap effect that the resin that guarantees between conductor fig and the IC chip is filled usefulness.
Also have, in the TAB operation,, also on semiconductor chip, form the bump electrode (projection) of metal sometimes with regard to being connected between the lead-in wire of TAB and the semiconductor chip.At this moment, just on the electrode of semiconductor chip, form bump electrode.Material uses gold or scolding tin etc. usually.And, at this moment, on lead-in wire 54a one side, do not need projected electrode 56a.Therefore, under these circumstances, just do not need each operation of Fig. 6～Fig. 8 yet.
On the other hand, in the present embodiment, be to enumerate the example that forms bump electrode (projection) in lead-in wire one side of TAB, substitute and on semiconductor chip, form the example that bump electrode describes.The technology of processing this guide-wire tip is the technology of having developed that real result is arranged, and utilizes both to deposit TAB manufacturing process line and can realize.And, at this moment, as long as expose aluminum pad, and become and do not need the metal salient point electrode and simplify working process in semiconductor chip one side.
Operation 9
As shown in Figure 9, after having formed photoresist 80a, 80b on the surface of conductor fig, plating is implemented at the back side of conductor fig, and the coating that formation is made of Ni/Au (90a～90b).Nickel (Ni) plays the barrier metal effect.As what in Figure 19, also said, adopt to the alive way of framework 59a～59c and electroplate.For example, one pole (electrode in general) is connected on the framework and electroplates in batch.
Also have, be not limited to galvanoplastic.For example, also can apply plating to conductor fig with non-electrolytic plating method.The plating processing is removed photoresist 80a and 80b after finishing.
At first, as shown in figure 16, carry out the molding of coupling part 57a～57j.Consider operating efficiency, it is desirable carrying out molding in batches, but separately carries out good separately.Therefore, each 54a that goes between etc. becomes independence on electric.
Then, as shown in figure 10, in through hole 30, fill metal (nickel etc.) 98, then form outside terminal for connecting (solder ball) 100.Also have, though can in through hole, fill the different metal of scolder with aluminium etc. in order to reach high accuracy, but on minimizing manufacturing process this point, in through hole, fill scolder, shine the formation that original appearance realizes outside terminal for connecting, and (integral body) forms in batch.Therefore, finish the film carrier tape manufactured using (Figure 16) that CSP uses.
Also have, under the situation of electroless plating, also can not carry out molding.
In this stage, with being labeled as benchmark, pointer being checked, and carried out the sorting of substandard product and qualified products with the lead-in wire curved detection of dummy leads etc.
And in the present embodiment, though form the operation of this outside terminal for connecting at the in-process that forms flexible substrate, not limited.For example, also can form in any time after the welding of having carried out with semiconductor chip.And this moment, also only the inherent flexible substrate of through hole forms formation in advance in the operation, forms outside terminal for connecting (solder ball) 100 then in other operation.These can suitably be selected.Particularly, under the situation of scolding tin as outside terminal for connecting, the thermal impact that instrument produces in the time of considering to weld is so after welding, the method that forms outside terminal for connecting is desirable.
Operation 11
Then, as Figure 11, shown in Figure 17, the head portion of the Al electrode (pad) 204 (204a～204d etc.) of semiconductor chip 200 and each lead-in wire is coupled together (welding).With soldering set 5000, the protruding 56a limit heating on extruding top, limit, the way that produces the Au/Al alloy is carried out this connection.In Figure 17, be IC chip 200 with the part shown in the heavy line.Also have, the end of figure free end one side is positioned at the semiconductor chip zone.
Then, inject the resin (resin) of epoxy system etc.For example, as shown in figure 12, inject with hole (label 42 of Figure 17) from the resin injection.Also have, except that resin injects with the hole, fairlead 40 injects resin owing to for example also can utilize, and uses the hole so not necessarily need to be provided with the resin injection.But,, then obtain utilizing the good result of aspect if consider the reliability of injection rate and injection.
Cover the formed surface of Al electrode (active face) of whole semiconductor chip with resin.Particularly, the coupling part between IC chip 200 and the lead-in wire (54a etc.) has been capped fully.On the other hand, if resin stop aperture (44a, 44b) is set, then because it exists, metering is to the expansion of transverse direction.In Figure 12, label 300a, 300b and 300c represent the resin coating cap rock.Make the head portion of pointer be positioned at the result in the zone of semiconductor chip, the side of head portion is also sealed within the resin 300a.And, can in pointer, not establish yet potting resin of a projection side of 56 yet, whole pointer is imbedded in the resin.But at this moment, need be set at the position also lower to the extreme higher position of resin than the outer position of insulating properties film 10.If not like this, just become the connection that hinders outside terminal for connecting 100.
Then, make the resin thermmohardening of having injected.At this moment, in operation 10, when (57a～when 57j) carrying out molding, formed hole on insulating properties film 10 for example plays, and the gas leakage hole of the steam that produces during as the encapsulation heating etc. acts on, and useful to the reliability that improves encapsulation to the coupling part.And, in that (57a～when 57j) carrying out molding also can utilize certain several hole in the formed hole to carry out resin and inject to this coupling part.But utilizing all holes simultaneously but is worthless as the resin hand-hole.
Use above-mentioned operation, make the band that has connected a plurality of IC chips and carry the semiconductor device assembly.
Also have, in the above-described embodiments, as shown in figure 10, after having formed external connection terminals 100, made band through the operation of Figure 11, Figure 12 and carried the semiconductor device assembly, but be not limited thereto.
A part had been said, for example, also can form outside terminal for connecting 100 after the resin-sealed operation of Figure 12 in advance.At this moment, if cover the coupling part of IC chip 200 and lead-in wire 54 and IC chip 200 with resin after, external connection terminals is set again, when then externally splicing ear forms, just needn't worries to pollute chip area, thereby the advantage that improves reliability is arranged.
Operation 13
Continue to use the CSP end 700 shown in the chain-dotted line encirclement, insulating properties film 10 is carried out molding.Thereby, finish the semiconductor device (CSP) 1000 of this chip size as shown in figure 18.In Figure 18, the zone that adds oblique line is the zone that is covered with resin coating.
As illustrated, owing to only expose the section of suspension line TR1 and TR2, thereby moisture-proof is also fine.And, owing to take the mode that encapsulates, so the inspection that also can wear out etc.
Also have, in above embodiment,, be not limited thereto, also can be applied to form conductor fig on the surface of insulating properties film 10 though on the back side of insulating properties film 10, form conductor fig.
(2) the 2nd embodiment
As shown in figure 13, not only in the inboard of IC chip 2000, and also can form outside terminal for connecting (solder ball) 100b in the outside.
In the present embodiment, IC chip 200 is accommodated in the recess of the formed packaging container 300 of recess, and lead-in wire 50 is extended on this packaging container 300.And, in through hole, form metal electrode 98b, and solder ball is welded on this metal electrode 98b.
If the employing present embodiment then can freely increase the number of outside terminal for connecting (solder ball), and is not subjected to the restriction of IC chip 200 sizes.
(3) the 3rd embodiment
Under the more roomy situation of the requirement of package dimension, as shown in figure 22, IC chip 200 and lead-in wire between 54 be connected (welding) end after, carrying out molding (among Figure 22 with the outside of chip tie point, holding 900 places to carry out molding with the CSP shown in two dotted lines), also can adopt the manufacture method of cutting lead-in wire 54 from framework (framework) 59.
If adopt this manufacture method, because in the end will go between and framework apart in the operation, so do not worry owing to the crooked welding that causes of lead-in wire is defective.
(4) the 4th embodiment
Figure 23 is illustrated in and prints on the circuit board 2000, has assembled the state of the semiconductor device (CSP) 1000 of chip size of the present invention.
Outside terminal for connecting (solder ball) 100a, the 100b of the semiconductor device of chip size (CSP) 1000 is connected on the conductor fig 2100a and 2100b that prints circuit board (base plate for packaging) 2000.Because package dimension is exactly a chip size, so can make the encapsulation of very high-density.Also have, in Figure 23, label 202 is other IC that have been assembled on the printed circuit board 2000.
(5) the 5th embodiment
Figure 24 is the figure of gamma camera monolithic devices VTR inside of base plate for packaging of chip scale semiconductor device of the present invention (CSP) that represented assembled package.
In gamma camera monolithic devices VTR3000, packed into 2 base plate for packaging 2000a, 2000b have carried CSP1000 of the present invention and 1002 on each base plate for packaging.
In Figure 24, label 3100 expression resins, label 3200 expression resin unit, label 3300 expression battery cases, label 3310 expression batteries.
Like this, semiconductor device of the present invention (CSP) is owing to be chip size, so can be applied in the predestined portable machine that has small-sized, a light-weighted gamma camera monolithic devices VTR etc.And, semiconductor device of the present invention (CSP), together with moisture-proof and thermal endurance aspect, reliability is also all very high, its result, the reliability of raising e-machine.
Claims (27)
1, a kind of manufacture method of film carrier tape manufactured using is characterized in that comprising:
On the insulating properties film, form the operation of conductor foil;
Form the operation of conductor fig by above-mentioned conductor foil, this conductor fig has, and forms an end and has with a plurality of leads of the electrical connections of semiconductor chip, is located on the packaging area of above-mentioned semiconductor chip and coupling part that above-mentioned a plurality of leads is connected with each other, the framework that is electrically connected with all above-mentioned lead-in wire by above-mentioned coupling part as free end and at above-mentioned free end;
Above-mentioned conductor fig is implemented the operation of electroplating; And
Die-cut above-mentioned coupling part makes each bar of above-mentioned a plurality of leads become the electric operation that independent lead-in wire.
2, the manufacture method of film carrier tape manufactured using according to claim 1 is characterized in that, in the operation that forms described conductor fig, also is formed for forming the pad portion of outside terminal for connecting between described lead-in wire and described coupling part.
3, the manufacture method of film carrier tape manufactured using according to claim 1 is characterized in that, before the operation that forms above-mentioned conductor foil, also has the die-cut operation that is used for forming at the assigned position of above-mentioned insulating properties film the hole.
4, the manufacture method of film carrier tape manufactured using according to claim 1 is characterized in that, above-mentioned semiconductor chip has the electrode of avoiding above-mentioned electrical connections position,
Also have with above-mentioned lead-in wire in the different place, end of an above-mentioned end, in the residing local operation that forms conductive bump of above-mentioned electrode.
5, the manufacture method of film carrier tape manufactured using according to claim 1 is characterized in that, in the zone except that the above-mentioned electrical connections of above-mentioned conductor fig, and the assembling above-mentioned IC chip the zone form the projection operation.
6, the manufacture method of film carrier tape manufactured using according to claim 1, it is characterized in that, before the operation that forms above-mentioned conductor fig, make it to form, on above-mentioned insulating properties film, opening portion is set, and above-mentioned free-ended end is positioned on the above-mentioned opening portion zone.
7, the manufacture method of film carrier tape manufactured using according to claim 6 is characterized in that, with the above-mentioned opening portion position adjacent of above-mentioned insulating properties film, on the free-ended extended line of above-mentioned lead-in wire, form the curved detection mark of above-mentioned lead-in wire.
8, the manufacture method of film carrier tape manufactured using according to claim 7 is characterized in that, above-mentioned curved detection mark is in the formation operation of above-mentioned conductor fig, uses with above-mentioned conductor fig same processes to form.
9, the manufacture method of film carrier tape manufactured using according to claim 7 is characterized in that, also possesses according to the comparison with position between the above-mentioned end of the position of mark and above-mentioned lead terminal of above-mentioned curved detection, detects the operation of above-mentioned lead-in wire bending.
10, the manufacture method of film carrier tape manufactured using according to claim 6, it is characterized in that, in the formation operation of above-mentioned conductor fig, form the part among the above-mentioned a plurality of leads, it is possessed from the above-mentioned insulating properties film to above-mentioned opening portion outstanding a pair of projection and the coupling part that is connected above-mentioned pair of protruding portions.
11, the manufacture method of film carrier tape manufactured using according to claim 10 is characterized in that, above-mentioned projection and coupling part form the right angle.
12, the manufacture method of film carrier tape manufactured using according to claim 11 is characterized in that, an above-mentioned projection and another projection leave at interval and be provided with, and other goes between between the interval.
13, according to the manufacture method of each described film carrier tape manufactured using of claim 1～claim 12, it is characterized in that, in the formation operation of above-mentioned conductor fig, implement processing at the thickness direction of lead-in wire, make and the above-mentioned IC chip of above-mentioned lead-in wire between electrical connections become outstanding shape.
14, a kind of film carrier tape manufactured using is characterized in that comprising:
Formed the insulating properties film of fairlead;
On above-mentioned insulating properties film, extension is provided with an end and becomes free-ended lead-in wire in the zone of above-mentioned fairlead; And
The above-mentioned lead-in wire curved detection mark that on the above-mentioned insulating properties film that is positioned on the above-mentioned free-ended extended line, forms.
15, film carrier tape manufactured using according to claim 14 is characterized in that, is formed for the pad at another distolateral formation external connection terminals of above-mentioned lead-in wire.
16, a kind of film carrier tape manufactured using is characterized in that comprising:
Formed the insulating properties film of fairlead;
On above-mentioned insulating properties film, be provided with, be connected a plurality of leads of usefulness with semiconductor chip;
On above-mentioned insulating properties film, be located at the assembly area of above-mentioned semiconductor chip, the coupling part that above-mentioned a plurality of leads is connected with each other;
On above-mentioned insulating properties film, be provided with, be electrically connected to the framework of all above-mentioned lead-in wires by above-mentioned coupling part.
17, a kind of film carrier tape manufactured using is characterized in that comprising:
The insulating properties film;
The a plurality of leads that forms in parallel on above-mentioned insulating properties film;
Be positioned at the vicinity of above-mentioned a plurality of leads, by interval predetermined distance interconnective pair of lead wires of while; And
Be formed at another lead-in wire between the above-mentioned pair of lead wires.
18, a kind of band carries the manufacture method of semiconductor device assembly, it is characterized in that comprising
On the insulating properties film, form the operation of conductor foil;
Form the operation of conductor fig by above-mentioned conductor foil, this conductor fig has, the framework that forms coupling part that an end has a plurality of leads that is electrically connected with semiconductor chip with connecting portion as free end and at above-mentioned free end, the above-mentioned a plurality of leads on the packaging area of being located at above-mentioned semiconductor chip is connected with each other, is electrically connected with all above-mentioned lead-in wire by above-mentioned coupling part;
Above-mentioned conductor fig is implemented the operation of electroplating;
Die-cut above-mentioned coupling part makes each bar of above-mentioned a plurality of leads become the electric operation that independent lead-in wire; And
Connect the electrode of semiconductor chip, the operation that a plurality of semiconductor chips are installed at an end of the above-mentioned end separately of described a plurality of leads on above-mentioned insulating properties film.
19, the manufacture method of semiconductor device assembly according to claim 18 is characterized in that also comprising: the operation of packing matcrial between above-mentioned semiconductor chip and described insulating properties film.
20, a kind of manufacture method of semiconductor device is characterized in that comprising:
On the insulating properties film, form the operation of conductor foil;
Form the operation of conductor fig by above-mentioned conductor foil, this conductor fig has, the framework that forms coupling part that an end has a plurality of leads that is electrically connected with semiconductor chip with connecting portion as free end and at above-mentioned free end, the above-mentioned a plurality of leads on the packaging area of being located at above-mentioned semiconductor chip is connected with each other, is electrically connected with all above-mentioned lead-in wire by above-mentioned coupling part;
Above-mentioned conductor fig is implemented the operation of electroplating;
Die-cut above-mentioned coupling part makes each bar of above-mentioned a plurality of leads become the electric operation that independent lead-in wire; And
Connect the electrode of semiconductor chip, the operation that a plurality of semiconductor chips are installed at an end of the above-mentioned end separately of described a plurality of leads on above-mentioned insulating properties film; And
Carry out the operation of the last molding of above-mentioned insulating properties film.
21, a kind of semiconductor device is characterized in that comprising the described film carrier tape manufactured using of claim 14.
22, a kind of semiconductor device is characterized in that comprising the described film carrier tape manufactured using of claim 16, and forms porose on the above-mentioned coupling part.
23, a kind of semiconductor device is characterized in that comprising the described film carrier tape manufactured using of claim 17.
24, a kind of base plate for packaging is characterized in that: be connected on the conductor layer on the base plate for packaging by the external connection terminals of any described semiconductor device of claim 21 to 23 and constitute.
25, a kind of e-machine is characterized in that: be assembled with the described base plate for packaging of claim 24.
26, a kind of manufacture method of semiconductor device is characterized in that comprising:
On the insulating properties film, form the operation of conductor foil;
Form the operation of conductor fig by above-mentioned conductor foil, this conductor fig has, the framework that forms coupling part that an end has a plurality of leads that is connected usefulness with semiconductor chip as free end and at above-mentioned free end, the above-mentioned a plurality of leads on the packaging area of being located at above-mentioned semiconductor chip is connected with each other, is electrically connected with all above-mentioned lead-in wire by above-mentioned coupling part;
Above-mentioned conductor fig is implemented the operation of electroplating;
Die-cut above-mentioned coupling part makes each bar of above-mentioned a plurality of leads become the electric operation that independent lead-in wire;
The part of above-mentioned lead-in wire is connected to the operation on the electrode of semiconductor chip; And
Said frame is separated with above-mentioned a plurality of leads, form the operation of semiconductor device.
27, the manufacture method of semiconductor device according to claim 26, it is characterized in that, form between the operation of semiconductor device in the operation that connects above-mentioned electrode and above-mentioned separation, also have resin is filled into operation between above-mentioned semiconductor chip and the above-mentioned insulating properties film.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP298067/96 | 1996-10-22 | ||
| JP298067/1996 | 1996-10-22 | ||
| JP29806796 | 1996-10-22 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1206497A CN1206497A (en) | 1999-01-27 |
| CN1148793C true CN1148793C (en) | 2004-05-05 |
Family
ID=17854719
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB971914699A Expired - Fee Related CN1148793C (en) | 1996-10-22 | 1997-10-15 | Film carrier tape, tape carrier semiconductor device assembly, semiconductor device, its manufacturing method, package substrate, and electronic appliance |
Country Status (8)
| Country | Link |
|---|---|
| US (1) | US6130110A (en) |
| JP (1) | JP3584470B2 (en) |
| KR (1) | KR100455492B1 (en) |
| CN (1) | CN1148793C (en) |
| AU (1) | AU4571897A (en) |
| SG (1) | SG165145A1 (en) |
| TW (1) | TW358233B (en) |
| WO (1) | WO1998018163A1 (en) |
Families Citing this family (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007227979A (en) * | 1996-10-22 | 2007-09-06 | Seiko Epson Corp | Film carrier tape and semiconductor device |
| JP3536728B2 (en) * | 1998-07-31 | 2004-06-14 | セイコーエプソン株式会社 | Semiconductor device, tape carrier, manufacturing method thereof, circuit board, electronic device, and tape carrier manufacturing apparatus |
| JP3842548B2 (en) * | 2000-12-12 | 2006-11-08 | 富士通株式会社 | Semiconductor device manufacturing method and semiconductor device |
| JP2003110016A (en) * | 2001-09-28 | 2003-04-11 | Kobe Steel Ltd | Method of forming aerial metal wiring on semiconductor substrate |
| US7176055B2 (en) * | 2001-11-02 | 2007-02-13 | Matsushita Electric Industrial Co., Ltd. | Method and apparatus for manufacturing electronic component-mounted component, and electronic component-mounted component |
| JP2004165279A (en) * | 2002-11-11 | 2004-06-10 | Mitsui Mining & Smelting Co Ltd | Film carrier tape for mounting electronic component |
| US9318350B2 (en) * | 2003-04-15 | 2016-04-19 | General Dynamics Advanced Information Systems, Inc. | Method and apparatus for converting commerical off-the-shelf (COTS) thin small-outline package (TSOP) components into rugged off-the-shelf (ROTS) components |
| TWI231585B (en) * | 2004-03-02 | 2005-04-21 | Kingtron Electronics Co Ltd | Manufacturing method of film carrier |
| CN100342530C (en) * | 2004-07-30 | 2007-10-10 | 奇鋐科技股份有限公司 | Thermolysis modules possessing guidance air pipe and fan housing |
| JP4773864B2 (en) * | 2006-04-12 | 2011-09-14 | パナソニック株式会社 | Wiring board, semiconductor device using the same, and manufacturing method of wiring board |
| US7453148B2 (en) * | 2006-12-20 | 2008-11-18 | Advanced Chip Engineering Technology Inc. | Structure of dielectric layers in built-up layers of wafer level package |
| TWI365523B (en) * | 2008-01-08 | 2012-06-01 | Powertech Technology Inc | Wiring board ready to slot |
Family Cites Families (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5237770A (en) * | 1975-09-19 | 1977-03-23 | Seiko Instr & Electronics Ltd | Semiconductor device |
| JPS62150728A (en) * | 1985-12-25 | 1987-07-04 | Hitachi Ltd | Tape carrier and semiconductor device using the same |
| DE3634235C1 (en) * | 1986-10-08 | 1988-03-31 | Sueddeutsche Kuehler Behr | Matrix for a catalytic reactor for exhaust gas cleaning |
| JPS63141331A (en) * | 1986-12-03 | 1988-06-13 | Nec Corp | Lead frame for tape carrier semiconductor device |
| JPS6397235U (en) * | 1986-12-15 | 1988-06-23 | ||
| US4917286A (en) * | 1987-05-20 | 1990-04-17 | Hewlett-Packard Company | Bonding method for bumpless beam lead tape |
| KR970003915B1 (en) * | 1987-06-24 | 1997-03-22 | 미다 가쓰시게 | Semiconductor device and the use memory module |
| JPS6481330A (en) * | 1987-09-24 | 1989-03-27 | Nec Corp | Film carrier semiconductor device |
| JPH02210845A (en) * | 1989-02-10 | 1990-08-22 | Toshiba Corp | Film carrier tape |
| JPH063819B2 (en) * | 1989-04-17 | 1994-01-12 | セイコーエプソン株式会社 | Semiconductor device mounting structure and mounting method |
| JP3033227B2 (en) * | 1990-05-08 | 2000-04-17 | セイコーエプソン株式会社 | Semiconductor device |
| US5075252A (en) * | 1990-05-14 | 1991-12-24 | Richard Schendelman | Interdigitated trans-die lead method of construction for maximizing population density of chip-on-board construction |
| JPH0669276A (en) * | 1992-05-22 | 1994-03-11 | Nec Corp | Semiconductor device |
| US5477611A (en) * | 1993-09-20 | 1995-12-26 | Tessera, Inc. | Method of forming interface between die and chip carrier |
| JP2833996B2 (en) * | 1994-05-25 | 1998-12-09 | 日本電気株式会社 | Flexible film and semiconductor device having the same |
| CN1124644C (en) * | 1996-10-17 | 2003-10-15 | 精工爱普生株式会社 | Semiconductor device, method of its manufacture, circuit substrate, and film carrier tape |
-
1997
- 1997-10-15 SG SG200102991-7A patent/SG165145A1/en unknown
- 1997-10-15 WO PCT/JP1997/003707 patent/WO1998018163A1/en active IP Right Grant
- 1997-10-15 KR KR10-1998-0704773A patent/KR100455492B1/en not_active IP Right Cessation
- 1997-10-15 AU AU45718/97A patent/AU4571897A/en not_active Abandoned
- 1997-10-15 JP JP51920298A patent/JP3584470B2/en not_active Expired - Fee Related
- 1997-10-15 CN CNB971914699A patent/CN1148793C/en not_active Expired - Fee Related
- 1997-10-15 US US09/091,126 patent/US6130110A/en not_active Expired - Lifetime
- 1997-10-17 TW TW086115340A patent/TW358233B/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| US6130110A (en) | 2000-10-10 |
| JP3584470B2 (en) | 2004-11-04 |
| AU4571897A (en) | 1998-05-15 |
| SG165145A1 (en) | 2010-10-28 |
| WO1998018163A1 (en) | 1998-04-30 |
| CN1206497A (en) | 1999-01-27 |
| KR19990076662A (en) | 1999-10-15 |
| KR100455492B1 (en) | 2005-01-13 |
| TW358233B (en) | 1999-05-11 |
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