CN114866042B - Signal amplifying circuit - Google Patents
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- CN114866042B CN114866042B CN202210792019.9A CN202210792019A CN114866042B CN 114866042 B CN114866042 B CN 114866042B CN 202210792019 A CN202210792019 A CN 202210792019A CN 114866042 B CN114866042 B CN 114866042B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/30—Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters
- H03F1/306—Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters in junction-FET amplifiers
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/26—Modifications of amplifiers to reduce influence of noise generated by amplifying elements
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Abstract
The invention discloses a signal amplification circuit, comprising: the JFET current source unit is used for receiving an input signal, filtering noise signals in the input signal, amplifying useful signals and outputting gain useful signals; the input end of the first operational amplification unit is connected with the output end of the JFET current source unit, and the first operational amplification unit is used for amplifying and outputting the gain useful signal; a DC bias unit for generating a DC bias voltage; the first input end of the second operational amplification unit is connected with the output end of the direct current bias unit, the second input end of the second operational amplification unit is connected with the output end of the JFET current source unit, and the direct current working point of the JFET current source unit is set and stabilized according to the direct current bias voltage; and the gain setting unit is connected with the control end of the JFET current source unit, the output end of the first operational amplification unit and the output end of the second operational amplification unit, and adjusts the amplification factor of the JFET current source unit according to the output signal of the first operational amplification unit.
Description
Technical Field
The invention relates to the technical field of signal amplification, in particular to a signal amplification circuit.
Background
The weak signal detection technology is to detect useful weak signals from noise by using a series of signal processing methods. When a weak signal is detected in a low signal-to-noise ratio, the noise introduced by the device for acquiring the signal needs to be reduced as much as possible because the characteristic signal of the device is very weak. In the related art, a well-established integrated operational amplifier can achieve very low input voltage noise spectral density when a BJT (Bipolar Junction Transistor) is used as an input electrode. However, the input impedance of the BJT is not high, which cannot satisfy the high impedance input condition. However, in some applications, it is desirable to use a high impedance input. At present, no mature integrated operational amplifier on the market can reach very low input voltage noise spectrum density when a Junction Field-Effect Transistor (JFET) is input, and 1/f noise is also at a very low level.
Disclosure of Invention
The present invention is directed to solving, at least in part, one of the technical problems in the related art. Therefore, an object of the present invention is to provide a signal amplification circuit to achieve low noise at the premise of JFET input.
To achieve the above object, an embodiment of the present invention provides a signal amplifying circuit, including: the JFET current source unit is used for receiving an input signal, filtering a noise signal in the input signal, amplifying a useful signal in the input signal and outputting a gain useful signal; the input end of the first operational amplification unit is connected with the output end of the JFET current source unit, and the first operational amplification unit is used for amplifying and outputting the gain useful signal; a DC bias unit for generating a DC bias voltage; the first input end of the second operational amplification unit is connected with the output end of the direct current bias unit, the second input end of the second operational amplification unit is connected with the output end of the JFET current source unit, and the second operational amplification unit is used for setting and stabilizing a direct current working point of the JFET current source unit according to the direct current bias voltage; and the gain setting unit is respectively connected with the control end of the JFET current source unit, the output end of the first operational amplification unit and the output end of the second operational amplification unit, and the gain setting unit is used for adjusting the amplification factor of the JFET current source unit according to the output signal of the first operational amplification unit.
According to the signal amplification circuit provided by the embodiment of the invention, the JFET current source unit is used for receiving an input signal, filtering noise signals in the input signal, amplifying useful signals in the input signal to output gain useful signals, then the first operational amplification unit is used for amplifying the gain useful signals to obtain output signals, meanwhile, the second operational amplification unit is used for setting a direct current working point of the JFET current source unit by using direct current bias voltage generated by the direct current bias unit and stabilizing the direct current working point by using the gain useful signals, and the gain setting unit is used for adjusting the amplification factor of the JFET current source unit by using the output signals, so that low noise under the premise of JFET input can be realized.
Additional aspects and advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.
Drawings
Fig. 1 is a schematic structural diagram of a signal amplification circuit according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of a signal amplification circuit according to another embodiment of the present invention;
fig. 3 is a circuit diagram of a signal amplification circuit according to another embodiment of the present invention.
Detailed Description
A signal amplifying circuit according to an embodiment of the present invention is described below with reference to the drawings, in which the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described with reference to the drawings are illustrative and should not be construed as limiting the invention.
In order to realize low input voltage noise spectrum density on the premise of JFET input, a mode of constructing a preamplifier circuit by adopting a multi-path integrated operational amplifier parallel connection mode can be adopted. Although the scheme of parallel connection of multiple integrated operational amplifiers can also reduce the input voltage noise spectral density to a sufficiently low level, the scheme requires a large number of integrated operational amplifiers, which increases the cost on the one hand, and increases the area and design difficulty of the circuit board on the other hand, and is particularly difficult to apply to the circuit board with limited area.
Based on this, the invention provides a signal amplifying circuit.
Fig. 1 is a schematic structural diagram of a signal amplification circuit according to an embodiment of the present invention.
As shown in fig. 1, the signal amplification circuit 10 includes: a JFET current source unit 11, a first operational amplifier unit 12, a direct current offset unit 13, a second operational amplifier unit 14 and a gain setting unit 15.
Specifically, the JFET current source unit 11 is configured to receive an input signal, filter a noise signal in the input signal, amplify a useful signal in the input signal, and output a gain useful signal; the input end of the first operational amplification unit 12 is connected with the output end of the JFET current source unit 11, and the first operational amplification unit 12 is used for amplifying and outputting a gain useful signal; the dc bias unit 13 is configured to generate a dc bias voltage; a first input end of the second operational amplification unit 14 is connected with an output end of the direct current bias unit 13, a second input end of the second operational amplification unit 14 is connected with an output end of the JFET current source unit 11, and the second operational amplification unit 14 is used for setting and stabilizing a direct current working point of the JFET current source unit 11 according to the direct current bias voltage; the gain setting unit 15 is respectively connected to the control terminal of the JFET current source unit 11, the output terminal of the first operational amplification unit 12, and the output terminal of the second operational amplification unit 14, and the gain setting unit 15 is configured to adjust the amplification factor of the JFET current source unit 11 according to the output signal of the first operational amplification unit 12.
Referring to fig. 2, the first operational amplifier unit 12 includes a first operational amplifier therein, and the second operational amplifier unit 14 includes a second operational amplifier therein. The first operational amplifier is preferably a low input noise spectral density operational amplifier, and the second operational amplifier is preferably a low offset operational amplifier. The signal amplification circuit 10 further includes: one end of a sixth resistor R6, one end of a seventh resistor R7, one end of a sixth resistor R6 are connected with the first node, one end of a seventh resistor R7 is connected with the second node, the other end of the sixth resistor R6 and the other end of the seventh resistor R7 are connected with the second input end of the second operational amplification unit 14, so that a gain useful signal is acquired and input to the first input end of the second operational amplification unit 14.
Specifically, the JFET current source unit 11 receives an input signal, filters an unwanted noise signal therein, and amplifies a useful signal therein to obtain a gain useful signal, and inputs the gain useful signal to an input terminal of a first operational amplifier, the first operational amplifier amplifies the gain useful signal to obtain an output signal, the output signal is fed back to the gain setting unit 15, and the gain setting unit 15 adjusts the amplification capability of the JFET current source unit 11 on the useful signal using the feedback signal to adjust the gain of the entire circuit. The dc bias unit 13 generates a dc bias voltage, and transmits the dc bias voltage to the positive phase input terminal of the second operational amplifier, so that the negative phase input terminal of the second operational amplifier also obtains the dc bias voltage, and the dc bias voltage is transmitted to the JFET current source unit 11, so that the output voltage of the JFET current source unit 11 changes around the dc bias voltage, thereby realizing setting of a dc operating point of the JFET current source unit 11. Moreover, the output terminal of the second operational amplifier is also connected to the gain setting unit 15 to output an output signal to the gain setting unit 15 according to the dc bias voltage and the gain useful signal, so as to stabilize the dc operating point of the JFET current source.
Referring to fig. 3, the JFET current source unit 11 includes a first JFET transistor Q1, a second JFET transistor Q2, a third JFET transistor Q3, and a fourth JFET transistor Q4, and is constructed by discrete components of JFET transistors based on a CASCODE architecture, so as to reduce the influence of the miller effect. Further comprising: a positive power supply VA +, a first resistor R1, a second resistor R2, and a third resistor R3, wherein the positive power supply VA + is connected to one end of the first resistor R1, the other end of the first resistor R1 is connected to one end of the second resistor R2 and the third resistor R3, the other end of the second resistor R2 is connected to the drain of the first JFET Q1 and forms a first node, the other end of the third resistor R3 is connected to the drain of the second JFET Q2 and forms a second node, the source of the first JFET Q1 is connected to the drain of the third JFET Q3, the source of the second JFET Q2 is connected to the drain of the fourth JFET Q4, the positive and negative electrodes of the input terminal of the current source unit 11 are led out from the gate of the third JFET Q3 and the gate of the fourth JFET Q4, and the positive and negative electrodes of the output terminal of the current source unit 11 are led out from the first node and the second node. Further comprising: the first capacitor C1 and the fourth resistor R4 are connected in series, and one end of the series is connected to the first node, and the other end is connected to the second node, so as to reduce the noise of the output signal. Further comprising: and the gate bias power supply Vgg is connected with the gate of the first JFET tube Q1 and the gate of the second JFET tube Q2 and forms a third node to provide a gate bias voltage which is a direct current power supply. Further comprising: one end of the second capacitor C2, one end of the fifth resistor R5, one end of the fifth resistor R5 are connected to the gate bias power supply Vgg, the other end of the fifth resistor R5 and one end of the second capacitor C2 are connected to the third node, and the other end of the second capacitor C2 is grounded, so that ripples of the voltage provided by the gate bias power supply Vgg are reduced. The positive power supply VA + is connected with filter capacitors C6 and C11, wherein C11 is a ceramic capacitor, and C6 is an electrolytic capacitor or a tantalum capacitor.
The JFET current source cell 11 further includes: the input positive pole resistance R16, input negative pole resistance R17. R16 and R17 are used to configure the input impedance, which can be typically configured as a 50 ohm input or a high impedance input depending on user requirements.
The first operational amplification unit 12 includes: a first operational amplifier U1 and an output signal acquisition resistor R18.
A dc bias unit 13, comprising: the voltage regulator comprises a first voltage-regulator tube D1, an eighth resistor R8, a ninth resistor R9, a third capacitor C3 and a positive power supply VA +, wherein the positive power supply VA + is connected with the negative electrode of the first voltage-regulator tube D1, the positive electrode of the first voltage-regulator tube D1 is connected with one ends of the eighth resistor R8 and the ninth resistor R9, the other end of the eighth resistor R8 is grounded, the other end of the ninth resistor R9 is connected with one end of the third capacitor C3 to form a fourth node, the other end of the third capacitor C3 is grounded, and the output end of the direct current bias unit is led out of the fourth node. The dc bias unit 13 further includes filter capacitors C7 and C8, and the filter capacitors C7 and C8 are connected to the positive power supply VA +.
The second operational amplification unit 14 includes: a second operational amplifier U2, a fifteenth resistor R15, and a second operational amplifier unit capacitor C12.
The gain setting unit 15 includes: one end of a tenth resistor R10, one end of an eleventh resistor R11, one end of a twelfth resistor R12, one end of a thirteenth resistor R13 and one end of a fourteenth resistor R14, one end of a tenth resistor R10 is connected with the source of the third JFET transistor Q3 and one end of the twelfth resistor R12, the other end of the tenth resistor R10 is grounded, the other end of a twelfth resistor R12 is connected with one end of the fourteenth resistor R14, one end of an eleventh resistor R11 is connected with one end of the thirteenth resistor R13 and the source of the fourth JFET transistor Q4 to form a fifth node, the other end of the thirteenth resistor R13 is connected with one end of the fourteenth resistor R14, and the other end of the fourteenth resistor R14 is connected with a negative power supply VA-. Further comprising: and one end of a fourth capacitor C4, one end of a fourth capacitor C4 is connected with the fifth node, the other end of the fourth capacitor C4 is connected with the other end of the eleventh resistor R11 to form a sixth node, and the input end of the gain setting unit is led out from the sixth node.
The gain of the signal amplifying circuit 10 according to the embodiment of the present invention is determined by the tenth resistor R10, the eleventh resistor R11, the twelfth resistor R12 and the thirteenth resistor R13. In order to ensure the symmetry of the differential input link, the tenth resistor R10 and the eleventh resistor R11 have the same resistance, and the twelfth resistor R12 and the thirteenth resistor R13 have the same resistance. In order to ensure the stability of the whole loop, the output end of the first operational amplifier U1 is connected in parallel with the fourth capacitor C4, and the bandwidth of the loop is related to the capacitance value of the fourth capacitor C4. And a negative power supply VA-provides a negative power supply of the whole circuit and is connected with filter capacitors C9 and C10, wherein C10 is a ceramic capacitor, and C9 is an electrolytic capacitor or a tantalum capacitor.
Specifically, first, assuming that the voltage supplied from the positive power supply VA + is VA +, and assuming that the voltage stabilized by the first regulator diode D1 is Vt, the voltage output to the non-inverting input terminal of the second operational amplifier U2, that is, the voltage output to the inverting input terminal of the second operational amplifier U2 is Vt, and the voltages are transmitted to the positive and negative electrodes of the output terminal of the JFET current source cell 11, so that the current I flowing through the second resistor R2 flows D2 = (VA + -Vt)/(2 × R1+ R2), current I flowing through third resistor R3 D3 = (VA + — Vt)/(2 × R1+ R3), since the resistance of the second resistor R2 is the same as the resistance of the third resistor R3, i.e., I is as described above D2 Is equal to I D3 The currents flowing through the second resistor R2 and the third resistor R3 can be regarded as (VA + -Vt)/(2 × R1+ R2). By means of this current, the dc operating point of the JFET tube in the JFET current source cell 11 is set.
When the signal amplifying circuit 10 works, the anode of the input signal is connected with the grid electrode of the third JFET Q3, the cathode of the input signal is connected with the grid electrode of the fourth JFET Q4, noise in the input signal can be filtered, the useful signal can be amplified, and the gain useful signal can be obtained. The gain desired signal is input to an input terminal of a first operational amplifier U1, and the first operational amplifier U1 amplifies the gain desired signal to obtain an output signal. Further, an output signal collecting resistor R18 may be provided, and the output signal is obtained through the output signal collecting resistor R18.
Meanwhile, the sixth resistor R6 and the seventh resistor R7 can also collect the drain voltage V of the first JFET transistor Q1 OUT1 And the drain voltage V of the second JFET tube Q2 OUT2 And accordingly obtaining an output common mode level V CM =（V OUT1 +V OUT2 ) 2, and further outputs the output common mode level to the negative of the second operational amplifier U2The input terminals are connected so that the second operational amplifier U2 compares the error between the output common mode level and the dc bias voltage and feeds the error back to the gain setting unit 15 to change the current and thereby stabilize the dc operating point.
The output signal from the first operational amplifier U1 is fed back to the gain setting section 15, and the amplification capability of the JFET current source section 11 for a desired signal is adjusted based on the output signal, thereby stabilizing the circuit gain. Specifically, when the output signal increases, the fed-back signal increases, the current increases, and the drain voltage V of the second JFET transistor Q2 increases OUT2 Increasing, decreasing the gain useful signal, decreasing the output signal; when the output signal is smaller, the fed-back signal is smaller, the current is reduced, and the drain voltage V of the second JFET tube Q2 is reduced OUT2 The gain useful signal is decreased, the gain useful signal is increased, and the output signal is increased.
The JFET current source cell 11 may also adopt a single-ended input mode, that is, the positive electrode of the input signal is connected to the gate of the third JFET transistor Q3, and the negative electrode of the input signal is grounded.
To sum up, in the signal amplification circuit according to the embodiment of the present invention, the JFET current source unit receives the input signal, filters the noise signal in the input signal, amplifies the useful signal in the input signal to output the gain useful signal, the first operational amplification unit amplifies and outputs the gain useful signal to obtain the output signal, the second operational amplification unit sets the dc operating point of the JFET current source unit by using the dc bias voltage generated by the dc bias unit, and stabilizes the dc operating point by using the gain useful signal, and the gain setting unit adjusts the amplification factor of the JFET current source unit by using the output signal, thereby achieving low noise on the premise of JFET input.
It should be noted that the logic and/or steps represented in the flowcharts or otherwise described herein may be considered as a sequential list of executable instructions for implementing logical functions, and may be embodied in any computer-readable medium for use by or in connection with an instruction execution system, apparatus, or device, such as a computer-based system, processor-containing system, or other system that can fetch the instructions from the instruction execution system, apparatus, or device and execute the instructions. For the purposes of this description, a "computer-readable medium" can be any means that can contain, store, communicate, propagate, or transport the program for use by or in connection with the instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of the computer-readable medium would include the following: an electrical connection (electronic device) having one or more wires, a portable computer diskette (magnetic device), a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber device, and a portable compact disc read-only memory (CDROM). Additionally, the computer-readable medium could even be paper or another suitable medium upon which the program is printed, as the program can be electronically captured, via for instance optical scanning of the paper or other medium, then compiled, interpreted or otherwise processed in a suitable manner if necessary, and then stored in a computer memory.
It should be understood that portions of the present invention may be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments, the various steps or methods may be implemented in software or firmware stored in memory and executed by a suitable instruction execution system. If implemented in hardware, as in another embodiment, any one or combination of the following techniques, which are known in the art, may be used: a discrete logic circuit having a logic gate circuit for implementing a logic function on a data signal, an application specific integrated circuit having an appropriate combinational logic gate circuit, a Programmable Gate Array (PGA), a Field Programmable Gate Array (FPGA), or the like.
In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
In the description herein, the terms "central," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," "circumferential," and the like refer to orientations and positional relationships based on the orientation shown in the drawings, and do not indicate or imply that the referenced device or element must have a particular orientation, be constructed and operated in a particular orientation, and are not to be construed as limiting the present invention.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of the present invention, "a plurality" means at least two, e.g., two, three, etc., unless specifically limited otherwise.
In the description of the present specification, unless otherwise specified, the terms "mounted," "connected," "fixed," and the like are to be construed broadly, e.g., as meaning fixedly connected, detachably connected, or integrally formed; can be mechanically or electrically connected; they may be directly connected or indirectly connected through intervening media, or they may be connected internally or in any other suitable relationship, unless expressly stated otherwise. The specific meanings of the above terms in the present invention can be understood according to specific situations by those of ordinary skill in the art.
In the present invention, unless expressly stated or limited otherwise, the first feature "on" or "under" the second feature may be directly contacting the second feature or the first and second features may be indirectly contacting each other through intervening media. Also, a first feature "on," "over," and "above" a second feature may be directly or diagonally above the second feature, or may simply indicate that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature may be directly under or obliquely under the first feature, or may simply mean that the first feature is at a lesser elevation than the second feature.
Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention, and that variations, modifications, substitutions and alterations can be made to the above embodiments by those of ordinary skill in the art within the scope of the present invention.
Claims (7)
1. A signal amplification circuit, comprising:
the JFET current source unit is used for receiving an input signal, filtering noise signals in the input signal, amplifying useful signals in the input signal and outputting gain useful signals;
the input end of the first operational amplification unit is connected with the output end of the JFET current source unit, and the first operational amplification unit is used for amplifying and outputting the gain useful signal;
a DC bias unit for generating a DC bias voltage;
a first input end of the second operational amplification unit is connected with an output end of the direct current bias unit, a second input end of the second operational amplification unit is connected with an output end of the JFET current source unit, and the second operational amplification unit is used for setting and stabilizing a direct current working point of the JFET current source unit according to the direct current bias voltage;
the gain setting unit is respectively connected with the control end of the JFET current source unit, the output end of the first operational amplification unit and the output end of the second operational amplification unit, and the gain setting unit is used for adjusting the amplification factor of the JFET current source unit according to the output signal of the first operational amplification unit;
the JFET current source unit is built by discrete component JFET tubes based on a CASCODE framework;
the JFET current source unit comprises:
a first JFET tube, a second JFET tube, a third JFET tube, a fourth JFET tube, a positive power supply, a first resistor, a second resistor and a third resistor, wherein the positive power supply is connected with one end of the first resistor, the other end of the first resistor is connected with one ends of the second resistor and the third resistor, the other end of the second resistor is connected with the drain electrode of the first JFET tube, and forms a first node, the other end of the third resistor is connected with the drain electrode of the second JFET tube, and forming a second node, the source of the first JFET tube being connected to the drain of the third JFET tube, the source electrode of the second JFET tube is connected with the drain electrode of the fourth JFET tube, the positive electrode and the negative electrode of the input end of the JFET current source unit are led out from the grid electrode of the third JFET tube and the grid electrode of the fourth JFET tube, the positive electrode and the negative electrode of the output end of the JFET current source unit are led out from the first node and the second node;
the source electrode of the third JFET tube and the source electrode of the fourth JFET tube are both connected with the gain setting unit;
the JFET current source unit further comprises:
and the grid bias power supply is connected with the grid electrode of the first JFET tube and the grid electrode of the second JFET tube and forms a third node so as to provide grid bias voltage.
2. The signal amplification circuit of claim 1, wherein the JFET current source cell further comprises:
and one end of the first capacitor and the fourth resistor which are connected in series is connected to the first node, and the other end of the first capacitor and the fourth resistor are connected to the second node, so that the noise of the output signal is reduced.
3. The signal amplification circuit of claim 1, wherein the JFET current source cell further comprises:
the grid bias power supply is connected with the grid, one end of the fifth resistor is connected with the grid bias power supply, the other end of the fifth resistor is connected with one end of the second capacitor at the third node, and the other end of the second capacitor is grounded so as to reduce ripples of voltage provided by the grid bias power supply.
4. The signal amplification circuit of claim 1, further comprising:
one end of the sixth resistor is connected with the first node, one end of the seventh resistor is connected with the second node, and the other end of the sixth resistor and the other end of the seventh resistor are connected with the second input end of the second operational amplification unit so as to collect the gain useful signal and input the gain useful signal to the first input end of the second operational amplification unit.
5. The signal amplification circuit of claim 1, wherein the dc bias unit comprises:
the direct current bias unit comprises a first voltage-regulator tube, an eighth resistor, a ninth resistor, a third capacitor and the positive power supply, wherein the positive power supply is connected with the negative electrode of the first voltage-regulator tube, the positive electrode of the first voltage-regulator tube is connected with one ends of the eighth resistor and the ninth resistor, the other end of the eighth resistor is grounded, the other end of the ninth resistor is connected with one end of the third capacitor to form a fourth node, the other end of the third capacitor is grounded, and the output end of the direct current bias unit is led out from the fourth node.
6. The signal amplification circuit according to claim 1, wherein the gain setting unit includes:
the transistor comprises a tenth resistor, an eleventh resistor, a twelfth resistor, a thirteenth resistor and a fourteenth resistor, wherein one end of the tenth resistor is connected with the source electrode of the third JFET tube and one end of the twelfth resistor, the other end of the tenth resistor is grounded, the other end of the twelfth resistor is connected with one end of the fourteenth resistor, one end of the eleventh resistor is connected with one end of the thirteenth resistor and the source electrode of the fourth JFET tube to form a fifth node, the other end of the thirteenth resistor is connected with one end of the fourteenth resistor, and the other end of the fourteenth resistor is connected with a negative power supply.
7. The signal amplification circuit according to claim 6, wherein the gain setting unit further comprises:
one end of the fourth capacitor is connected with the fifth node, the other end of the fourth capacitor is connected with the other end of the eleventh resistor to form a sixth node, and the input end of the gain setting unit is led out from the sixth node.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0322519A3 (en) * | 1987-12-31 | 1990-02-14 | Motorola, Inc. | Operational amplifier utilizing trimmable current sources |
| JPH10256844A (en) * | 1997-03-14 | 1998-09-25 | Toshiba Corp | Output stage circuit for operational amplifier |
| US7253680B2 (en) * | 2003-05-21 | 2007-08-07 | World Energy Labs (2), Inc. | Amplifier system with current-mode servo feedback |
| JP4434759B2 (en) * | 2004-01-23 | 2010-03-17 | Ｎｅｃエレクトロニクス株式会社 | Operational amplifier circuit |
| US7327189B2 (en) * | 2004-08-17 | 2008-02-05 | National Instruments Corporation | Differential structure programmable gain instrumentation amplifier |
| JP5272948B2 (en) * | 2009-07-28 | 2013-08-28 | ソニー株式会社 | Amplifier circuit, semiconductor integrated circuit, wireless transmission system, communication device |
| WO2016185426A1 (en) * | 2015-05-20 | 2016-11-24 | Wizedsp Ltd. | An ultra-low-power and low-noise amplifier |
| CN112436811B (en) * | 2020-10-13 | 2021-06-08 | 华南理工大学 | Operational amplifier, chip and method based on metal oxide TFT |
| CN114710123A (en) * | 2022-04-19 | 2022-07-05 | 国仪量子(合肥)技术有限公司 | Amplifying circuit and signal detector |
-
2022
- 2022-07-07 CN CN202210792019.9A patent/CN114866042B/en active Active
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| Publication number | Publication date |
|---|---|
| CN114866042A (en) | 2022-08-05 |
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Address after: 230088 floor 1-4, zone a, building E2, phase II, innovation industrial park, No. 2800, innovation Avenue, high tech Zone, Hefei, Anhui Province Patentee after: Guoyi Quantum Technology (Hefei) Co.,Ltd. Address before: 230088 floor 1-4, zone a, building E2, phase II, innovation industrial park, No. 2800, innovation Avenue, high tech Zone, Hefei, Anhui Province Patentee before: Guoyi Quantum (Hefei) Technology Co.,Ltd. |