CN114864735B - Phototransistor preparation method and transistor array based on femtosecond laser - Google Patents

Abstract

The invention discloses a femtosecond laser-based photoelectric transistor preparation method and a transistor array. It includes steps: S10, providing a silicon base layer with a silicon dioxide layer on the top surface; S20, forming a three-layer thin film structure on the upper surface of the silicon dioxide layer; S30, based on the femtosecond laser processing technology and preset pattern information, vertically An etching process is performed from above the three-layer thin film structure in the surface direction of the three-layer thin film structure to form a transistor array composed of multiple stacked junctionless phototransistors. Adjacent stacked junctionless phototransistors are separated by trenches. The femtosecond laser-based phototransistor preparation method of the present invention omits the photolithography step in the traditional patterning process by using femtosecond laser micro-nano processing technology, thereby reducing the preparation process cost of the transistor device, composite photosensitive materials and semiconductors Materials that use photogenerated carriers to inject into semiconductors to improve the mobility of electrons and holes in the device and obtain higher photocurrent response.

Description

Phototransistor preparation method and transistor array based on femtosecond laser

1Technical field

The present invention relates to the field of semiconductor technology, and in particular, to a femtosecond laser-based phototransistor preparation method and array.

2 Background technology

The pattern transfer process of traditional micromachining technology requires the use of photolithography technology, which usually requires the use of a physical mask. The pattern on the mask is copied to the substrate through ultraviolet light, and then developed to form the required pattern. Traditional micromachining process steps are cumbersome. Due to factors such as instability of process equipment or incomplete hygiene and cleaning steps, various defects are easily introduced during the process, and the stability and low cost of transistor devices cannot be guaranteed.

In order to improve the problems in the transistor manufacturing process and device performance, it is necessary to propose a phototransistor manufacturing method based on femtosecond laser to solve or at least alleviate the above defects.

3 Contents of the invention

The photoelectric transistor preparation method based on femtosecond laser provided by the present invention solves the technical problem that the stability of the transistor device cannot be ensured in the existing transistor device produced by photolithography technology using a physical mask.

In order to achieve the above objects, the technical solutions adopted by the present invention are as follows:

A method for preparing a phototransistor based on femtosecond laser, including the following steps: S10, providing a silicon base layer with a silicon dioxide layer on the top surface; S20, forming a three-layer thin film structure on the upper surface of the silicon dioxide layer, so The three-layer film structure includes a photosensitive material layer in the middle layer and transparent semiconductor film layers located on the upper and lower sides of the photosensitive material layer respectively; S30, based on the femtosecond laser processing technology and preset pattern information, along the vertical direction of the The surface direction of the three-layer thin film structure is etched from above the three-layer thin film structure to form a transistor array composed of a plurality of stacked junctionless phototransistors, and two adjacent stacked junctionless phototransistors pass through the fly The three-layer film structure is separated by trenches formed by second laser etching.

Further, the step S10 specifically includes: ultrasonically cleaning the silicon wafer substrate with acetone, alcohol and deionized water in sequence, and then drying the silicon wafer substrate to obtain the silicon base layer.

Further, the step S20 specifically includes: S21, depositing a heavily doped semiconductor material by sputtering on the upper surface of the silicon dioxide layer to form the lower part of the transparent semiconductor film layer with a thickness of 5-20 nm. Transparent semiconductor thin film layer; S22, spin-coat a photosensitive material on the upper surface of the transparent semiconductor thin film layer to form the photosensitive material layer with a thickness of 5-10 nanometers; S23, sputter on the upper surface of the photosensitive material layer A heavily doped semiconductor is deposited to form the transparent semiconductor thin film layer with a thickness of 5-20 nanometers on top of the transparent semiconductor thin film layer.

Further, the transparent semiconductor film layer includes at least one of a tin-indium oxide conductive semiconductor film layer, an indium-zinc oxide conductive semiconductor film, and an aluminum-zinc oxide conductive semiconductor film.

Further, the photosensitive material uses photosensitive quantum dots or nanometal particles.

Further, a plurality of the stacked junctionless phototransistors are arranged in an array, at least two of the stacked junctionless phototransistors arranged in the transverse direction form a transistor row, and at least two of the stacked junctionless phototransistors arranged in the longitudinal direction form a transistor row. The junctionless phototransistor forms a transistor column, further including step S40 of arranging a first solid gate dielectric layer on the surface of the transistor row, wherein the first solid gate dielectric layer covers the top surface of the three-layer film structure and A source electrode and a drain electrode are formed on the top surface of each stacked junctionless phototransistor on the groove side wall surface and the groove bottom surface, and the source electrode and the drain electrode are located opposite to each other. A second solid gate dielectric layer is provided on both sides of the first solid gate dielectric layer and/or on the surface of the transistor column, wherein the second solid gate dielectric layer covers the top surface of the three-layer thin film structure and A source electrode and a drain electrode are formed on the top surface of each stacked junctionless phototransistor on the groove side wall surface and the groove bottom surface, and the source electrode and the drain electrode are located opposite to each other. both sides of the second solid gate dielectric layer.

Further, step S40 specifically includes: injecting ionic liquid on the surface of the three-layer film structure and the trench, the ionic liquid being used to form the first solid-state gate dielectric layer and/or the second solid-state gate dielectric layer. gate dielectric layer.

The present invention also provides a transistor array, prepared by the above-mentioned femtosecond laser-based photoelectric transistor preparation method, including at least one transistor row, each of the transistor rows including at least two laminated junctionless photovoltaic transistors arranged at intervals along the lateral direction. Transistors, two adjacent stacked junctionless phototransistors are separated by trenches formed by femtosecond laser etching, each of the stacked junctionless phototransistors includes a gate layer with a gate dielectric layer on top , a three-layer thin film structure is provided on the upper surface of the gate dielectric layer.

The present invention also provides a transistor array, prepared by the above-mentioned femtosecond laser-based phototransistor preparation method, including at least one transistor row, each of the transistor rows including a plurality of stacked junctionless phototransistors arranged at intervals along the lateral direction. , two adjacent stacked junctionless phototransistors are separated by trenches formed by femtosecond laser etching, each of the stacked junctionless phototransistors includes a silicon base layer with a silicon dioxide layer on the top surface , a three-layer film structure is provided on the upper surface of the silicon base layer, a solid gate dielectric layer is provided on the top surface of the three-layer film structure, the solid gate dielectric layer is provided in the trench, and the two adjacent ones are The stacked junctionless phototransistors are connected through the solid gate dielectric layer.

The invention has the following beneficial effects:

The femtosecond laser-based phototransistor preparation method of the present invention is based on the solution that the source and drain electrodes and channel layers are made of the same semiconductor thin film material. By using femtosecond laser micro-nano processing technology, the light in the traditional patterning process is omitted. engraving step, thereby reducing the cost of the preparation process of the transistor device, and at the same time reducing the uncertain factors in the patterning process. It is easy to integrate to form a transistor array, improves the uniformity and stability of the transistor device, and is conducive to ensuring the stability of the transistor device. and low cost; by arranging a three-layer thin film structure on the upper surface of the silicon dioxide layer (gate dielectric layer), based on femtosecond laser processing technology, a trench with a top opening and penetrating the three-layer thin film structure is processed on the silicon base layer. Adjacent laminated junctionless phototransistors are separated by trenches. By designing the channel layer of the laminated junctionless phototransistor into three layers, a photosensitive material layer is placed between the two transparent semiconductor film layers. The composite photosensitive material and Semiconductor materials use photogenerated carriers to inject into semiconductors to increase the mobility of device electrons and holes and obtain higher photocurrent response.

In addition to the objects, features and advantages described above, the present invention has other objects, features and advantages. The present invention will be described in further detail below with reference to the drawings.

4 Description of the drawings

The drawings forming a part of this application are used to provide a further understanding of the present invention. The illustrative embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the attached picture:

Figure 1 is a schematic flow diagram in a preferred embodiment of the present invention;

Figure 2 is a schematic flow diagram of another preferred embodiment of the present invention;

Figure 3 is a schematic structural diagram of the first state in the preferred embodiment of the present invention;

Figure 4 is a schematic structural diagram of the second state in the preferred embodiment of the present invention;

Figure 5 is a schematic structural diagram of the third state in the preferred embodiment of the present invention;

Figure 6 is a schematic structural diagram of the fourth state in the preferred embodiment of the present invention.

5 specific implementation modes

It should be understood that the specific embodiments described here are only used to explain the present invention and are not intended to limit the present invention.

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without making creative efforts fall within the scope of protection of the present invention.

It should be noted that all directional indications (such as up, down, left, right, front, back...) in the embodiment of the present invention are only used to explain the relationship between components in a specific posture (as shown in the drawings). Relative positional relationship, movement conditions, etc., if the specific posture changes, the directional indication will also change accordingly.

In addition, descriptions involving "first", "second", etc. in the present invention are for descriptive purposes only and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of indicated technical features. Therefore, features defined as "first" and "second" may explicitly or implicitly include at least one of these features. In addition, the technical solutions in various embodiments can be combined with each other, but it must be based on the realization by those of ordinary skill in the art. When the combination of technical solutions is contradictory or cannot be realized, it should be considered that such a combination of technical solutions does not exist. , nor within the protection scope required by the present invention.

Please refer to Figures 1, 3, 4 and 5. A method for manufacturing a phototransistor based on femtosecond laser in a preferred embodiment provided by the present invention includes the steps:

S10, providing a silicon base layer with a silicon dioxide layer on the top surface;

S20, form a three-layer film structure on the upper surface of the silicon dioxide layer. The three-layer film structure includes a photosensitive material layer in the middle layer and transparent semiconductor film layers (transparent conductive semiconductor oxide film) respectively located on the upper and lower sides of the photosensitive material layer. layer);

S30, based on the femtosecond laser processing technology and preset pattern information, etches from the top of the three-layer thin film structure along the surface direction perpendicular to the three-layer thin film structure to form a transistor array composed of multiple stacked junctionless phototransistors. Two adjacent stacked junctionless phototransistors are separated by trenches formed by femtosecond laser etching that penetrate the three-layer film structure.

Specifically, S30, based on the femtosecond laser processing technology and preset pattern information, etches from the top of the three-layer thin film structure along the surface direction perpendicular to the three-layer thin film structure to form a plurality of stacked junctionless phototransistors. Transistor array; wherein each stacked junctionless phototransistor in the transistor row in the transistor array is separated by trenches formed by femtosecond laser etching that penetrate the three-layer film structure and part of the gate dielectric layer, and the transistor array Each stacked junctionless phototransistor in the transistor column is separated by trenches formed by femtosecond laser etching that penetrate the three-layer film structure and part of the gate dielectric layer.

Optionally, in step S30, based on the femtosecond laser processing technology, based on preset pattern information, (wherein, the preset pattern information may be information such as the preset pattern is a cylinder shape, a quadrilateral shape, or other polygonal shapes, and two adjacent The stacked junctionless phototransistors are separated by trenches formed by femtosecond laser etching that penetrate the three-layer thin film structure and part of the gate dielectric layer), and are separated from the three-layer thin film structure in the direction perpendicular to the surface of the three-layer thin film structure. Etching is performed on the top until a trench with an open top and running through the three-layer film structure is processed on the silicon base layer, so that adjacent stacked junctionless phototransistors in the transistor row are separated by the trench with an open top. The transistor array includes transistor rows and transistor columns separated by trenches. The stacked junctionless phototransistors in the transistor rows and transistor columns are separated by trenches that penetrate the three-layer film structure and part of the gate dielectric layer formed by femtosecond laser etching. Come on.

It can be understood that in this embodiment, a heavily doped silicon wafer substrate with thermally produced silicon dioxide on the top is selected as the silicon base layer.

The phototransistor preparation method based on femtosecond laser in this embodiment uses femtosecond laser micro-nano processing technology to omit the photolithography step in the traditional patterning process, thereby reducing the preparation process cost of the transistor device and reducing the number of patterns. Uncertain factors in the process of transistorization are easily integrated to form a transistor array, which improves the uniformity and stability of transistor devices and is conducive to ensuring the stability and low cost of transistor devices; by forming a silicon dioxide layer (gate dielectric layer) on the A three-layer thin film structure is provided on the surface. Based on femtosecond laser processing technology, a trench with a top opening and running through the three-layer thin film structure is processed on the silicon base layer. Adjacent stacked junctionless phototransistors are separated by the trench. The channel layer of the laminated junctionless phototransistor is designed into three layers. A photosensitive material layer is set between the two transparent semiconductor film layers. The photosensitive material and the semiconductor material are combined. Photogenerated carriers are injected into the semiconductor to increase the electrons and holes of the device. mobility and obtain higher photocurrent response.

It can be understood that the transistor array formed by the above method is processed by femtosecond laser to form trenches at the corresponding positions to obtain a preset pattern. At this time, the top transparent semiconductor film layer is used as the junctionless source and drain electrode to line the transistor array. The silicon at the bottom (silicon base layer) regulates the bottom gate (gate layer).

Please refer to Figures 2, 3, 4, 5 and 6. Another preferred embodiment of the present invention provides a femtosecond laser-based phototransistor preparation method, which includes the steps:

S10, providing a silicon base layer with a silicon dioxide layer on the top surface;

S20, form a three-layer thin film structure on the upper surface of the silicon dioxide layer. The three-layer thin film structure includes a photosensitive material layer in the middle layer and transparent semiconductor thin film layers respectively on the upper and lower sides of the photosensitive material layer;

S30, based on the femtosecond laser processing technology and preset pattern information, etches from the top of the three-layer thin film structure along the surface direction perpendicular to the three-layer thin film structure to form a transistor array composed of multiple stacked junctionless phototransistors. Two adjacent stacked junction-less phototransistors are separated by trenches formed by femtosecond laser etching that penetrate the three-layer film structure;

Wherein, a plurality of stacked junctionless phototransistors are arranged in an array, at least two stacked junctionless phototransistors arranged in the transverse direction form a transistor row, and at least two stacked junctionless phototransistors arranged in the longitudinal direction form a transistor column. ;

It also includes step S40 of arranging a first solid gate dielectric layer on the surface of the transistor row, wherein the first solid gate dielectric layer covers the top surface of the three-layer thin film structure and the groove side wall surface and groove bottom surface of the trench, so that in each A source and a drain are formed on the top surface of a stacked junctionless phototransistor. The source and drain are oppositely located on both sides of the first solid gate dielectric layer, and/or a second solid gate dielectric is provided on the surface of the transistor column. layer, wherein the second solid-state gate dielectric layer covers the top surface of the three-layer thin film structure and the trench sidewalls and trench bottom surfaces of the trenches to form source and drain electrodes on the top surface of each stacked junctionless phototransistor. The source electrode and the drain electrode are oppositely located on both sides of the second solid gate dielectric layer.

Optionally, in this embodiment, a solid gate dielectric layer is provided on the surface of the transistor array. The solid gate dielectric layer includes a first solid gate dielectric layer and/or a second solid gate dielectric layer, wherein the first solid gate dielectric layer is formed along the The transistor rows are arranged in the length direction, and the first solid gate dielectric layer is located in the middle of the transistor row. The first solid gate dielectric layer is arranged to form the source and drain electrodes on the surface of the stacked junctionless phototransistor. The phototransistor unit is opposite to the first The middle section of the solid gate dielectric layer is symmetrically arranged; wherein, the second solid gate dielectric layer is arranged along the length direction of the transistor column, and the second solid gate dielectric layer is located in the middle of the transistor column. A source and a drain are formed on the surface of the junctionless phototransistor, and the phototransistor units are arranged symmetrically with respect to the middle section of the second solid gate dielectric layer.

It can be understood that in this embodiment, a heavily doped silicon wafer substrate with thermally produced silicon dioxide on the top is selected as the silicon base layer.

The phototransistor preparation method based on femtosecond laser in this embodiment uses femtosecond laser micro-nano processing technology to omit the photolithography step in the traditional patterning process, thereby reducing the preparation process cost of the transistor device and reducing the number of patterns. Uncertain factors in the process of transistorization are easily integrated to form a transistor array, which improves the uniformity and stability of transistor devices and helps ensure the stability and low cost of transistor devices; by setting a three-layer thin film structure on the upper surface of the gate dielectric layer , based on femtosecond laser processing technology, a trench that penetrates the three-layer thin film structure is processed on the silicon base layer. Adjacent stacked junctionless phototransistors are separated by the trench, and a solid gate dielectric layer is set on the surface of the transistor array. , any independent transistor unit can be connected to other adjacent transistor units through the solid gate dielectric layer, that is, the transistor can be controlled by other connected transistors through the solid gate dielectric layer; by stacking the junctionless phototransistor The channel layer is designed as three layers. A photosensitive material layer is set between the two transparent semiconductor film layers. The photosensitive material and the semiconductor material are combined. Photogenerated carriers are injected into the semiconductor to improve the mobility of electrons and holes in the device and obtain higher photocurrent response.

It can be understood that in the transistor array processed by the above method, the transistor units in the transistor array can be controlled by bottom gate, or can be controlled by multi-side gate through the top solid gate dielectric layer. Specifically, materials such as ionic liquid are dropped in to form a solid gate dielectric layer of solid electrolyte type, and the top transparent semiconductor film layer of other phototransistor units is used as a side gate to regulate the current.

Based on the above two embodiments, further explanation is as follows.

Research has found that light, as a common and easily regulated form of stimulation, has been introduced into synaptic transistor devices, which has become a hot research direction in recent years. Introducing light into neural synaptic devices is the basic idea of phototransistors. Current research mainly focuses on light as an input signal to regulate device performance. Therefore, synaptic devices with good current response to light stimulation are the key to realizing low-energy artificial vision systems and neuromorphic computing. However, traditional field effect transistors have many process steps and are complex; the optical response of single-channel layer thin film transistors is relatively poor, and phototransistors with single channel layers alone cannot achieve excellent photosensitive characteristics at the same time; at the same time, with the development of single synaptic transistor devices Research is becoming more and more mature. Like other electronic components, optoelectronic synapse transistor devices will gradually move towards integration and arraying. Three-terminal devices can introduce multi-gate control to achieve more complex functions, but the device density is relatively small and the space utilization rate is low. Low, integration is difficult, the stability and uniformity of each device in the array is an important performance indicator, which puts forward higher-level requirements for material performance and processing technology.

In the present invention, the transistor manufacturing process and device performance are improved. By using femtosecond laser micro-nano processing technology, the photolithography step in the traditional patterning process is omitted, thereby reducing the cost of the manufacturing process and reducing the uncertainty in the manufacturing process. factors; in addition, based on the original dual-channel layer structure with stable switching characteristics, high mobility and appropriate turn-on voltage, photosensitive materials such as quantum dots or metal nanoparticles are spin-coated into the middle of the channel layer to utilize photogenerated carriers Semiconductors are injected to improve the mobility of electrons and holes in the device and obtain a higher photocurrent response. The phototransistor array formed by this is more conducive to research on artificial vision and neuromorphic computing.

Further, the step S10 specifically includes: ultrasonically cleaning the silicon wafer substrate with acetone, alcohol and deionized water in sequence, and then drying the silicon wafer substrate to obtain the silicon base layer. In order to ensure the various properties of the transistor device, during the specific operation, the heavily doped silicon wafer substrate with 250-300 nm thermally grown silicon dioxide is ultrasonically cleaned with acetone, alcohol and deionized water, and the silicon wafer is obtained after drying. For the base layer, the cleaned silicon wafer substrate is dried through a nitrogen gun.

Further, step S20 specifically includes: S21, depositing a heavily doped semiconductor material on the upper surface of the silicon dioxide layer by sputtering to form a transparent semiconductor film layer with a thickness of 5-20 nanometers and located under the transparent semiconductor film layer; S22, The upper surface of the transparent semiconductor film layer is spin-coated with a photosensitive material to form a photosensitive material layer with a thickness of 5-10 nanometers; S23, a heavily doped semiconductor is deposited on the upper surface of the photosensitive material layer by sputtering to form a photosensitive material layer with a thickness of 5-20 nanometers. a transparent semiconductor thin film layer on top of the transparent semiconductor thin film layer. Optionally, step S20 specifically includes: depositing a heavily doped semiconductor on the upper surface of the silicon base layer through a sputtering process to provide a transparent semiconductor film layer on top of the silicon base layer; A photosensitive material is spin-coated on the layer to form a photosensitive material layer; a heavily doped semiconductor is deposited on the upper surface of the photosensitive material layer through a sputtering process to form a transparent semiconductor thin film layer on the upper surface of the photosensitive material layer.

Further, the transparent semiconductor film layer includes at least one of a tin-indium oxide conductive semiconductor film layer, an indium-zinc oxide conductive semiconductor film, and an aluminum-zinc oxide conductive semiconductor film. Optionally, the transparent semiconductor film layer includes at least one of a tin-doped indium oxide (ITO) conductive semiconductor film layer, an indium-doped zinc oxide (IZO) conductive semiconductor film, and an aluminum-doped zinc oxide (AZO) conductive semiconductor film. .

In the present invention, in order to ensure various performances of the transistor device, during specific operations, a tin-indium oxide conductive semiconductor film layer with a film thickness of 20 nanometers is provided as a transparent semiconductor film layer.

Further, the photosensitive material uses photosensitive quantum dots or nanometal particles.

In the present invention, in order to ensure various performances of the transistor device, during specific operations, a photosensitive quantum dot layer with a film thickness of 10 nanometers is provided as the photosensitive material layer.

Further, step S40 specifically includes: injecting ionic liquid along the length direction of the transistor row into the surface of the three-layer film structure and the trench between the two adjacent stacked junctionless phototransistors, with the ionic liquid located in the middle of the transistor row. area, in which the ionic liquid is used to form a solid gate dielectric layer; the ionic liquid is injected along the length direction of the transistor column into the surface of the three-layer film structure and the trench between the two adjacent stacked junctionless phototransistors, and the ions The liquid is in the middle region of the transistor column, where the ionic liquid is used to form the solid gate dielectric layer.

The present invention provides a specific implementation as follows:

Select heavily doped P-type silicon with 300nm thermally grown silicon dioxide (gate dielectric) as the substrate, select the indium tin oxide (ITO) film layer as the transparent semiconductor film (heavily doped semiconductor layer) layer, and select photosensitive material as the photosensitive material. Quantum dots, solid ionic electrolytes, selective ionic liquids.

The femtosecond laser-based phototransistor preparation method includes the following steps:

Step 1: Use acetone, alcohol and deionized water to ultrasonically clean the heavily doped silicon wafer substrate with 300nm thermally grown silica and dry it;

Step 2: Put the silicon wafer substrate (silicon base layer) into the radio frequency magnetron sputtering vacuum chamber, and deposit a transparent ITO film on the substrate as a heavily doped semiconductor layer through the sputtering process, with a film thickness of 20nm. ;

Step 3: Spin-coat a layer of photosensitive quantum dots or nanometal particles with a thickness of 5-10nm on the deposited ITO film;

Step 4: After leaving the photosensitive quantum dots for a certain period of time to dry, put the silicon wafer into the radio frequency magnetron sputtering vacuum chamber again, and magnetron sputter to deposit a 20nm thick ITO film on the photosensitive quantum dots as a heavy doping layer. Hybrid semiconductor layer;

As shown in Figure 1, at this time, a three-layer film structure (ITO film-photosensitive quantum dot-ITO film) is obtained on a heavily doped silicon wafer substrate with 300nm thermally grown silicon dioxide;

Step 5: As shown in Figure 2, focus the femtosecond laser on the sample placed on the workbench, and then the laser will etch according to the set pattern running route to form corresponding grooves, thus obtaining the sample as shown in Figure 2 The stacked junctionless transistor array shown has multiple independent phototransistor units. Each independent stacked junctionless transistor uses the top ITO film as the source, channel and drain, and the heavily doped P-type silicon substrate as the bottom gate; gate

Step 6: Inject the ionic liquid into the trench formed by the femtosecond laser and the top ITO film (the ionic liquid does not completely cover the ITO film, leaving space as the source and drain) to form a solid gate dielectric. At this time, the source and drain electrodes are drawn out from the surface of one top ITO film area, and the gate electrode is drawn out from the surface of the other top ITO film area, and side gate control is performed to obtain an independent thin film transistor.

The beneficial effects are as follows:

The use of femtosecond laser micro-nano processing reduces uncertainties in the patterning process, is easy to integrate to form a transistor array, and improves the uniformity and stability of the device; compared with field effect transistors with a single channel layer structure, dual The layer channel structure field effect transistor can increase the mobility while obtaining a moderate threshold voltage. At the same time, the use of photosensitive materials in the middle of the heavily doped semiconductor film can achieve wide spectrum detection and improve the device's highly sensitive response to light; this stack has no Junction phototransistor arrays can be controlled using either a bottom gate or multiple side gates via a top solid electrolyte. In summary, the manufacturing method of the phototransistor array provided by the present invention avoids the cumbersome steps of traditional photolithography, reduces the introduction of uncertain factors, ensures the stability of the device, and greatly reduces the process cost; at the same time, the three-channel The sandwich structure improves the mobility of electrons and holes in the device and can achieve higher photocurrent response. It has very broad application prospects in the research of artificial vision and neuromorphic computing.

The present invention also provides a transistor array, prepared by the above-mentioned femtosecond laser-based phototransistor preparation method, including at least one transistor row, each transistor row including at least two laminated junctionless phototransistors arranged at intervals along the lateral direction, Two adjacent stacked junction-free phototransistors are separated by trenches formed by femtosecond laser etching. Each stacked junction-free phototransistor includes a gate layer with a gate dielectric layer on top. The surface is provided with a three-layer film structure. Optionally, multiple transistor rows are arranged at intervals through trenches to form a transistor array.

The present invention also provides a transistor array, prepared by the above-mentioned femtosecond laser-based phototransistor preparation method, including at least one transistor row, each transistor row including a plurality of laminated junctionless phototransistors arranged at intervals along the lateral direction. Two adjacent stacked junction-free phototransistors are separated by trenches formed by femtosecond laser etching. Each stacked junction-free phototransistor includes a silicon base layer with a silicon dioxide layer on the top surface, and the upper surface of the silicon base layer A three-layer thin film structure is provided. The top surface of the three-layer thin film structure is provided with a solid gate dielectric layer. The solid gate dielectric layer is provided in the trench. Two adjacent stacked junctionless phototransistors are connected through the solid gate dielectric layer. Optionally, multiple transistor rows are arranged at intervals through trenches to form a transistor array.

The above are only preferred embodiments of the present invention and are not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and changes. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention shall be included in the protection scope of the present invention.

Claims (8)

1. A method for preparing a phototransistor based on femtosecond laser is characterized by comprising the following steps:

s10, providing a silicon-based layer with a silicon dioxide layer on the top surface;

s20, forming a three-layer film structure on the upper surface of the silicon dioxide layer, wherein the three-layer film structure comprises a photosensitive material layer in the middle layer and transparent semiconductor film layers respectively on the upper side and the lower side of the photosensitive material layer; a photosensitive material layer is arranged between the two transparent semiconductor film layers, the photosensitive material and the semiconductor material are compounded, and photon-generated carriers are injected into the semiconductor to improve the mobility of electrons and holes of the device, so that higher photocurrent response is obtained;

the step S20 specifically includes: s21, forming the transparent semiconductor film layer with the thickness of 5-20 nanometers at the lower part of the transparent semiconductor film layer on the upper surface of the silicon dioxide layer by sputtering deposition of a heavily doped semiconductor material; s22, forming a photosensitive material layer with the thickness of 5-10 nanometers on the upper surface of the transparent semiconductor film layer by spin coating the photosensitive material; s23, forming a transparent semiconductor film layer with the thickness of 5-20 nanometers on the upper part of the transparent semiconductor film layer on the upper surface of the photosensitive material layer through sputtering deposition of a heavily doped semiconductor;

and S30, carrying out etching processing from the upper part of the three-layer film structure along the direction vertical to the surface of the three-layer film structure based on the femtosecond laser processing technology according to preset pattern information to form a transistor array composed of a plurality of laminated knotless phototransistors, wherein two adjacent laminated knotless phototransistors are separated by a groove formed by femtosecond laser etching and penetrating through the three-layer film structure.

2. The method for manufacturing a laminated knotless phototransistor based on the femtosecond laser technology as recited in claim 1, wherein,

the step S10 specifically includes: and sequentially ultrasonically cleaning the silicon wafer substrate by adopting acetone, alcohol and deionized water, and drying to obtain the silicon substrate.

3. The method for manufacturing a phototransistor based on femtosecond laser as recited in claim 1, wherein,

the transparent semiconductor film layer comprises at least one of a tin indium oxide conductive semiconductor film layer, an indium zinc oxide conductive semiconductor film and an aluminum zinc oxide conductive semiconductor film.

4. The method for manufacturing a phototransistor based on femtosecond laser as recited in claim 1, wherein,

the photosensitive material adopts photosensitive quantum dots or nano metal particles.

5. A method for producing a phototransistor based on a femtosecond laser as recited in any one of claims 1 to 4,

the plurality of laminated knotless phototransistors are arranged in an array, at least two laminated knotless phototransistors arranged in a transverse direction form a transistor row, at least two laminated knotless phototransistors arranged in a longitudinal direction form a transistor column,

the method further comprises a step S40 of disposing a first solid gate dielectric layer on the surface of the transistor row, wherein the first solid gate dielectric layer covers the top surface of the three-layer thin film structure and the side wall surface and bottom surface of the trench to form a source electrode and a drain electrode on the top surface of each of the stacked bingeless phototransistors, the source electrode and the drain electrode being oppositely disposed on two sides of the first solid gate dielectric layer, and/or

And a second solid gate dielectric layer is arranged on the surface of the transistor column, wherein the second solid gate dielectric layer covers the top surface of the three-layer film structure, the side wall surface of the groove and the bottom surface of the groove, so that a source electrode and a drain electrode are formed on the top surface of each laminated knotless phototransistor, and the source electrode and the drain electrode are oppositely arranged on two sides of the second solid gate dielectric layer.

6. The method for manufacturing a laminated knotless phototransistor based on the femtosecond laser technology as recited in claim 5, wherein,

the step S40 specifically includes:

and implanting ion liquid into the surface of the three-layer film structure and the groove, wherein the ion liquid is used for forming the first solid gate dielectric layer and/or the second solid gate dielectric layer.

7. A transistor array, characterized in that it is prepared by the method for preparing a phototransistor based on femtosecond laser as set forth in any one of claims 1 to 4,

comprises at least one transistor row, each transistor row comprises at least two laminated knotless phototransistors which are arranged at intervals along the transverse direction, two adjacent laminated knotless phototransistors are separated by a groove formed by femtosecond laser etching,

each laminated bingeless phototransistor comprises a gate layer with a gate dielectric layer on the top, and a three-layer thin film structure is arranged on the upper surface of the gate dielectric layer.

8. A transistor array, characterized in that it is prepared by the method for preparing a phototransistor based on femtosecond laser as set forth in any one of claims 5 to 6,

comprises at least one transistor row, each transistor row comprises a plurality of laminated knotless phototransistors which are arranged at intervals along the transverse direction, two adjacent laminated knotless phototransistors are separated by a groove formed by femtosecond laser etching,

each laminated bingeless phototransistor comprises a silicon substrate with a silicon dioxide layer on the top surface, a three-layer thin film structure is arranged on the upper surface of the silicon substrate, a solid gate dielectric layer is arranged on the top surface of the three-layer thin film structure, the solid gate dielectric layer is arranged in the groove, and two adjacent laminated bingeless phototransistors are connected through the solid gate dielectric layer.