CN114864735B - Photo transistor preparation method based on femtosecond laser and transistor array - Google Patents
Photo transistor preparation method based on femtosecond laser and transistor array Download PDFInfo
- Publication number
- CN114864735B CN114864735B CN202210513849.3A CN202210513849A CN114864735B CN 114864735 B CN114864735 B CN 114864735B CN 202210513849 A CN202210513849 A CN 202210513849A CN 114864735 B CN114864735 B CN 114864735B
- Authority
- CN
- China
- Prior art keywords
- layer
- transistor
- femtosecond laser
- laminated
- knotless
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000002360 preparation method Methods 0.000 title abstract description 13
- 239000004065 semiconductor Substances 0.000 claims abstract description 74
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 48
- 239000000463 material Substances 0.000 claims abstract description 48
- 238000000034 method Methods 0.000 claims abstract description 43
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 41
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 41
- 239000010703 silicon Substances 0.000 claims abstract description 41
- 235000012239 silicon dioxide Nutrition 0.000 claims abstract description 24
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 24
- 238000012545 processing Methods 0.000 claims abstract description 20
- 238000005516 engineering process Methods 0.000 claims abstract description 19
- 230000004044 response Effects 0.000 claims abstract description 9
- 238000005530 etching Methods 0.000 claims abstract description 8
- 239000000969 carrier Substances 0.000 claims abstract description 6
- 239000010408 film Substances 0.000 claims description 79
- 239000007787 solid Substances 0.000 claims description 49
- 239000010409 thin film Substances 0.000 claims description 42
- 239000000758 substrate Substances 0.000 claims description 27
- 150000002500 ions Chemical class 0.000 claims description 14
- 238000010329 laser etching Methods 0.000 claims description 14
- 239000007788 liquid Substances 0.000 claims description 13
- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 claims description 10
- 238000004519 manufacturing process Methods 0.000 claims description 10
- 230000000149 penetrating effect Effects 0.000 claims description 10
- 238000000151 deposition Methods 0.000 claims description 9
- 239000002096 quantum dot Substances 0.000 claims description 9
- 238000004544 sputter deposition Methods 0.000 claims description 9
- 230000008021 deposition Effects 0.000 claims description 6
- 238000001035 drying Methods 0.000 claims description 6
- LFQSCWFLJHTTHZ-UHFFFAOYSA-N Ethanol Chemical compound CCO LFQSCWFLJHTTHZ-UHFFFAOYSA-N 0.000 claims description 5
- 238000004140 cleaning Methods 0.000 claims description 5
- 239000008367 deionised water Substances 0.000 claims description 5
- 229910021641 deionized water Inorganic materials 0.000 claims description 5
- 238000004528 spin coating Methods 0.000 claims description 5
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 5
- MRNHPUHPBOKKQT-UHFFFAOYSA-N indium;tin;hydrate Chemical compound O.[In].[Sn] MRNHPUHPBOKKQT-UHFFFAOYSA-N 0.000 claims description 4
- 239000002923 metal particle Substances 0.000 claims description 4
- JAONJTDQXUSBGG-UHFFFAOYSA-N dialuminum;dizinc;oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Al+3].[Al+3].[Zn+2].[Zn+2] JAONJTDQXUSBGG-UHFFFAOYSA-N 0.000 claims description 3
- YVTHLONGBIQYBO-UHFFFAOYSA-N zinc indium(3+) oxygen(2-) Chemical compound [O--].[Zn++].[In+3] YVTHLONGBIQYBO-UHFFFAOYSA-N 0.000 claims description 3
- 230000008569 process Effects 0.000 abstract description 20
- 238000000059 patterning Methods 0.000 abstract description 9
- 238000001259 photo etching Methods 0.000 abstract description 7
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 230000000946 synaptic effect Effects 0.000 description 4
- 230000005669 field effect Effects 0.000 description 3
- 238000001755 magnetron sputter deposition Methods 0.000 description 3
- 238000011160 research Methods 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 238000004364 calculation method Methods 0.000 description 2
- 238000005459 micromachining Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 210000005036 nerve Anatomy 0.000 description 2
- 239000007784 solid electrolyte Substances 0.000 description 2
- 238000011282 treatment Methods 0.000 description 2
- 239000011787 zinc oxide Substances 0.000 description 2
- 238000010276 construction Methods 0.000 description 1
- 230000008094 contradictory effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 239000003792 electrolyte Substances 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 229910003437 indium oxide Inorganic materials 0.000 description 1
- PJXISJQVUVHSOJ-UHFFFAOYSA-N indium(iii) oxide Chemical compound [O-2].[O-2].[O-2].[In+3].[In+3] PJXISJQVUVHSOJ-UHFFFAOYSA-N 0.000 description 1
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000002608 ionic liquid Substances 0.000 description 1
- 238000013532 laser treatment Methods 0.000 description 1
- 239000002082 metal nanoparticle Substances 0.000 description 1
- 230000001537 neural effect Effects 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000025474 response to light stimulus Effects 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
- 238000001228 spectrum Methods 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/08—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors
- H01L31/10—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors characterised by potential barriers, e.g. phototransistors
- H01L31/101—Devices sensitive to infrared, visible or ultraviolet radiation
- H01L31/112—Devices sensitive to infrared, visible or ultraviolet radiation characterised by field-effect operation, e.g. junction field-effect phototransistor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic Table
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Electromagnetism (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
- Light Receiving Elements (AREA)
Abstract
The invention discloses a photo-transistor preparation method based on femtosecond laser and a transistor array. The method comprises the following steps: s10, providing a silicon-based layer with a silicon dioxide layer on the top surface; s20, forming a three-layer film structure on the upper surface of the silicon dioxide layer; s30, etching from the upper side of the three-layer film structure along the direction perpendicular to the surface of the three-layer film structure based on the femtosecond laser processing technology according to preset pattern information to form a transistor array composed of a plurality of laminated knotless phototransistors, wherein adjacent laminated knotless phototransistors are separated by grooves. According to the preparation method of the photoelectric transistor based on the femtosecond laser, disclosed by the invention, the photoetching step in the traditional patterning process is omitted by using the femtosecond laser micro-nano processing technology, so that the preparation process cost of the transistor device is reduced, the photosensitive material and the semiconductor material are compounded, the mobility of electrons and holes of the device is improved by injecting photon-generated carriers into the semiconductor, and higher photocurrent response is obtained.
Description
1 technical field
The invention relates to the technical field of semiconductors, in particular to a method and an array for preparing a photoelectric transistor based on femtosecond laser.
2 background art
The pattern transfer process of conventional micromachining processes requires the use of photolithographic techniques, typically requiring the use of physical reticles, which are then developed to form the desired pattern by ultraviolet light to replicate the pattern on the reticle onto a substrate. The traditional micromachining process has complicated steps, various defects are easily introduced in the process due to the factors of unstable process equipment or incomplete sanitation and cleaning steps, and the stability and low cost of the transistor device cannot be ensured.
In order to improve the transistor fabrication process and device performance, it is necessary to propose a method for fabricating a phototransistor based on a femtosecond laser to solve or at least alleviate the above-mentioned drawbacks.
3 summary of the invention
The preparation method of the photoelectric transistor based on the femtosecond laser solves the technical problem that the stability of the transistor device cannot be ensured in the existing transistor device manufactured by adopting the photoetching technology of a physical mask.
In order to achieve the above purpose, the technical scheme adopted by the invention is as follows:
a method for preparing a phototransistor based on femtosecond laser comprises the following steps: s10, providing a silicon-based layer with a silicon dioxide layer on the top surface; s20, forming a three-layer film structure on the upper surface of the silicon dioxide layer, wherein the three-layer film structure comprises a photosensitive material layer in the middle layer and transparent semiconductor film layers respectively on the upper side and the lower side of the photosensitive material layer; and S30, carrying out etching processing from the upper part of the three-layer film structure along the direction vertical to the surface of the three-layer film structure based on the femtosecond laser processing technology according to preset pattern information to form a transistor array composed of a plurality of laminated knotless phototransistors, wherein two adjacent laminated knotless phototransistors are separated by a groove formed by femtosecond laser etching and penetrating through the three-layer film structure.
Further, the step S10 specifically includes: and sequentially ultrasonically cleaning the silicon wafer substrate by adopting acetone, alcohol and deionized water, and drying to obtain the silicon substrate.
Further, the step S20 specifically includes: s21, forming the transparent semiconductor film layer with the thickness of 5-20 nanometers at the lower part of the transparent semiconductor film layer on the upper surface of the silicon dioxide layer by sputtering deposition of a heavily doped semiconductor material; s22, forming a photosensitive material layer with the thickness of 5-10 nanometers on the upper surface of the transparent semiconductor film layer by spin coating the photosensitive material; s23, forming the transparent semiconductor film layer with the thickness of 5-20 nanometers on the upper part of the transparent semiconductor film layer on the upper surface of the photosensitive material layer through sputtering deposition of a heavily doped semiconductor.
Further, the transparent semiconductor thin film layer includes at least one of a tin indium oxide conductive semiconductor thin film layer, an indium zinc oxide conductive semiconductor thin film, and an aluminum zinc oxide conductive semiconductor thin film.
Further, the photosensitive material adopts photosensitive quantum dots or nano metal particles.
Further, the plurality of stacked bingeless phototransistors are arranged in an array, at least two stacked bingeless phototransistors arranged in a lateral direction form a transistor row, at least two stacked bingeless phototransistors arranged in a longitudinal direction form a transistor column, and further comprising a step S40 of providing a first solid gate dielectric layer on a surface of the transistor row, wherein the first solid gate dielectric layer covers a top surface of the three-layer thin film structure and a groove side wall surface and a groove bottom surface of the groove, so that a source electrode and a drain electrode are formed on the top surface of each stacked bingeless phototransistor, the source electrode and the drain electrode are located on two opposite sides of the first solid gate dielectric layer, and/or providing a second solid gate dielectric layer on a surface of the transistor column, wherein the second solid gate dielectric layer covers a top surface of the three-layer thin film structure and a groove side wall surface and a groove bottom surface of the groove, so that a source electrode and a drain electrode are formed on the top surface of each stacked bingeless phototransistor, and the source electrode and the drain electrode are located on two opposite sides of the second solid gate dielectric layer.
Further, the step S40 specifically includes: and implanting ion liquid into the surface of the three-layer film structure and the groove, wherein the ion liquid is used for forming the first solid gate dielectric layer and/or the second solid gate dielectric layer.
The invention also provides a transistor array, which is prepared by the method for preparing the photoelectric transistor based on the femtosecond laser, and comprises at least one transistor row, wherein each transistor row comprises at least two laminated knotless photoelectric transistors which are arranged at intervals along the transverse direction, two adjacent laminated knotless photoelectric transistors are separated by a groove formed by the femtosecond laser etching, each laminated knotless photoelectric transistor comprises a grid electrode layer with a grid dielectric layer at the top, and the upper surface of the grid dielectric layer is provided with a three-layer film structure.
The invention also provides a transistor array, which is prepared by the method for preparing the photoelectric transistor based on the femtosecond laser, and comprises at least one transistor row, wherein each transistor row comprises a plurality of laminated knotless photoelectric transistors which are arranged at intervals along the transverse direction, two adjacent laminated knotless photoelectric transistors are separated by a groove formed by the femtosecond laser etching, each laminated knotless photoelectric transistor comprises a silicon substrate with a silicon dioxide layer on the top surface, the upper surface of the silicon substrate is provided with a three-layer film structure, the top surface of the three-layer film structure is provided with a solid gate dielectric layer, the inside of the groove is provided with the solid gate dielectric layer, and the two adjacent laminated knotless photoelectric transistors are connected by the solid gate dielectric layer.
The invention has the following beneficial effects:
according to the preparation method of the photoelectric transistor based on the femtosecond laser, provided by the invention, the photoetching step in the traditional patterning process is omitted by using the femtosecond laser micro-nano processing technology based on the scheme that the source electrode, the drain electrode and the channel layer are made of the same semiconductor film material, so that the preparation process cost of the transistor device is reduced, meanwhile, uncertain factors in the patterning process are reduced, the transistor array is easy to integrate, the uniformity and the stability of the transistor device are improved, and the stability and the low cost of the transistor device are guaranteed; the upper surface of the silicon dioxide layer (gate dielectric layer) is provided with a three-layer film structure, a groove with an opening at the top and penetrating through the three-layer film structure is processed on the silicon substrate based on a femtosecond laser processing technology, adjacent laminated knotless phototransistors are separated by the groove, a channel layer of the laminated knotless phototransistor is designed into three layers, a photosensitive material layer is arranged between two transparent semiconductor film layers, the photosensitive material and the semiconductor material are compounded, the mobility of electrons and holes of the device is improved by injecting photon-generated carriers into the semiconductor, and higher photocurrent response is obtained.
In addition to the objects, features and advantages described above, the present invention has other objects, features and advantages. The present invention will be described in further detail with reference to the drawings.
Description of the drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the invention. In the drawings:
FIG. 1 is a schematic flow diagram in a preferred embodiment of the present invention;
FIG. 2 is a schematic flow diagram in another preferred embodiment of the present invention;
FIG. 3 is a schematic view of a first state structure in a preferred embodiment of the present invention;
FIG. 4 is a schematic diagram of a second state structure in a preferred embodiment of the present invention;
FIG. 5 is a third state diagram of the preferred embodiment of the present invention;
fig. 6 is a schematic view of a fourth state structure in a preferred embodiment of the present invention.
5 detailed description of the preferred embodiments
It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.
The following description of the embodiments of the present invention will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
It should be noted that all directional indicators (such as up, down, left, right, front, and rear … …) in the embodiments of the present invention are merely used to explain the relative positional relationship, movement, etc. between the components in a particular posture (as shown in the drawings), and if the particular posture is changed, the directional indicator is changed accordingly.
Furthermore, the description of "first," "second," etc. in this disclosure is for descriptive purposes only and is not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In addition, the technical solutions of the embodiments may be combined with each other, but it is necessary to base that the technical solutions can be realized by those skilled in the art, and when the technical solutions are contradictory or cannot be realized, the combination of the technical solutions should be considered to be absent and not within the scope of protection claimed in the present invention.
Referring to fig. 1, 3, 4 and 5, a method for preparing a phototransistor based on a femtosecond laser according to a preferred embodiment of the present invention includes the steps of:
s10, providing a silicon-based layer with a silicon dioxide layer on the top surface;
s20, forming a three-layer thin film structure on the upper surface of the silicon dioxide layer, wherein the three-layer thin film structure comprises a photosensitive material layer in the middle layer and transparent semiconductor thin film layers (transparent conductive semiconductor oxide thin film layers) respectively arranged on the upper side and the lower side of the photosensitive material layer;
s30, etching from the upper side of the three-layer film structure along the direction perpendicular to the surface of the three-layer film structure based on the femtosecond laser processing technology according to preset pattern information to form a transistor array composed of a plurality of laminated knotless phototransistors, wherein two adjacent laminated knotless phototransistors are separated by a groove formed by femtosecond laser etching and penetrating through the three-layer film structure.
Specifically, S30, performing etching processing from above the three-layer thin film structure along a direction perpendicular to the surface of the three-layer thin film structure based on the preset pattern information by using the femtosecond laser processing technology to form a transistor array composed of a plurality of stacked knotless phototransistors; each laminated non-junction phototransistor in the transistor row in the transistor array is separated by a groove formed by femto-second laser etching and penetrating through the three-layer thin film structure and part of the gate dielectric layer, and each laminated non-junction phototransistor in the transistor column in the transistor array is separated by a groove formed by femto-second laser etching and penetrating through the three-layer thin film structure and part of the gate dielectric layer.
Optionally, in step S30, based on the preset pattern information according to the femtosecond laser processing technology (wherein the preset pattern information may be information of a preset pattern such as a cylinder, a quadrangle or other polygon, and the adjacent two stacked knotless phototransistors are separated by a trench formed by femtosecond laser etching and penetrating through the three-layer thin film structure and a part of the gate dielectric layer), etching is performed from above the three-layer thin film structure along a direction perpendicular to the surface of the three-layer thin film structure until a trench with a top opening and penetrating through the three-layer thin film structure is processed on the silicon substrate, so that the adjacent stacked knotless phototransistors in the transistor row are separated by the trench with the top opening. The transistor array comprises transistor rows and transistor columns separated by trenches, and the stacked junction-free phototransistors in the transistor rows and transistor columns are separated by trenches formed through the three-layer thin film structure and a portion of the gate dielectric layer by femtosecond laser etching.
It will be appreciated that in this embodiment, the heavily doped silicon wafer substrate with thermally produced silicon dioxide on top is chosen as the silicon base layer.
According to the photo-transistor preparation method based on the femtosecond laser, a photoetching step in a traditional patterning process is omitted by using a femtosecond laser micro-nano processing technology, so that the preparation process cost of a transistor device is reduced, meanwhile, uncertain factors in the patterning process are reduced, a transistor array is easy to integrate and form, the uniformity and the stability of the transistor device are improved, and the stability and the low cost of the transistor device are guaranteed; the upper surface of the silicon dioxide layer (gate dielectric layer) is provided with a three-layer film structure, a groove with an opening at the top and penetrating through the three-layer film structure is processed on the silicon substrate based on a femtosecond laser processing technology, adjacent laminated knotless phototransistors are separated by the groove, a channel layer of the laminated knotless phototransistor is designed into three layers, a photosensitive material layer is arranged between two transparent semiconductor film layers, the photosensitive material and the semiconductor material are compounded, the mobility of electrons and holes of the device is improved by injecting photon-generated carriers into the semiconductor, and higher photocurrent response is obtained.
It can be understood that the transistor array formed by the above method is processed by femtosecond laser treatment, and then the grooves are formed at the corresponding positions to obtain preset patterns, at this time, the top transparent semiconductor film layer is used as a non-junction source drain electrode, and the silicon (silicon-based layer) at the substrate is used as a bottom gate (gate layer) for regulation and control.
Referring to fig. 2, 3, 4, 5 and 6, another preferred embodiment of a method for preparing a phototransistor based on a femtosecond laser according to the present invention includes the steps of:
s10, providing a silicon-based layer with a silicon dioxide layer on the top surface;
s20, forming a three-layer thin film structure on the upper surface of the silicon dioxide layer, wherein the three-layer thin film structure comprises a photosensitive material layer positioned in the middle layer and transparent semiconductor thin film layers respectively positioned on the upper side and the lower side of the photosensitive material layer;
s30, etching from the upper part of the three-layer film structure along the direction perpendicular to the surface of the three-layer film structure based on the femtosecond laser processing technology according to preset pattern information to form a transistor array composed of a plurality of laminated knotless phototransistors, wherein two adjacent laminated knotless phototransistors are separated by a groove which penetrates through the three-layer film structure and is formed by femtosecond laser etching;
the plurality of laminated knotless phototransistors are arranged in an array, at least two laminated knotless phototransistors which are arranged along the transverse direction form a transistor row, and at least two laminated knotless phototransistors which are arranged along the longitudinal direction form a transistor column;
the method further comprises step S40, wherein a first solid gate dielectric layer is arranged on the surface of the transistor row, the first solid gate dielectric layer covers the top surface of the three-layer film structure and the groove side wall surface and the groove bottom surface of the groove, so that a source electrode and a drain electrode are formed on the top surface of each laminated knotless photo transistor, the source electrode and the drain electrode are oppositely arranged on two sides of the first solid gate dielectric layer, and/or a second solid gate dielectric layer is arranged on the surface of the transistor column, wherein the second solid gate dielectric layer covers the top surface of the three-layer film structure and the groove side wall surface and the groove bottom surface of the groove, so that a source electrode and a drain electrode are formed on the top surface of each laminated knotless photo transistor, and the source electrode and the drain electrode are oppositely arranged on two sides of the second solid gate dielectric layer.
Optionally, in this embodiment, a solid gate dielectric layer is disposed on a surface of the transistor array, where the solid gate dielectric layer includes a first solid gate dielectric layer and/or a second solid gate dielectric layer, the first solid gate dielectric layer is disposed along a length direction of the transistor row, the first solid gate dielectric layer is located in a middle of the transistor row, and by disposing the first solid gate dielectric layer to form a source electrode and a drain electrode on a surface of the stacked knotless phototransistor, and the phototransistor unit is symmetrically disposed with respect to a middle section of the first solid gate dielectric layer; the second solid gate dielectric layer is arranged along the length direction of the transistor column, the second solid gate dielectric layer is positioned in the middle of the transistor column, and a source electrode and a drain electrode are formed on the surface of the laminated knotless photoelectric transistor by arranging the second solid gate dielectric layer, and the photoelectric transistor units are symmetrically arranged relative to the middle section of the second solid gate dielectric layer.
It will be appreciated that in this embodiment, the heavily doped silicon wafer substrate with thermally produced silicon dioxide on top is chosen as the silicon base layer.
According to the photo-transistor preparation method based on the femtosecond laser, a photoetching step in a traditional patterning process is omitted by using a femtosecond laser micro-nano processing technology, so that the preparation process cost of a transistor device is reduced, meanwhile, uncertain factors in the patterning process are reduced, a transistor array is easy to integrate and form, the uniformity and the stability of the transistor device are improved, and the stability and the low cost of the transistor device are guaranteed; the upper surface of the grid dielectric layer is provided with a three-layer film structure, a groove penetrating through the three-layer film structure is processed on the silicon substrate based on the femtosecond laser processing technology, adjacent laminated knotless photoelectric transistors are separated by the groove, the surface of the transistor array is provided with a solid-state grid dielectric layer, any independent transistor unit can be communicated with adjacent other transistor units through the solid-state grid dielectric layer, namely, the communicated other transistors can regulate and control the transistor through the solid-state grid dielectric layer; the channel layer of the laminated junction-free photoelectric transistor is designed into three layers, a photosensitive material layer is arranged between two transparent semiconductor film layers, the photosensitive material and the semiconductor material are compounded, and photon-generated carriers are injected into the semiconductor to improve the mobility of electrons and holes of the device, so that higher photocurrent response is obtained.
It can be appreciated that the transistor array formed by the above method can be used for bottom gate modulation of transistor units in the transistor array, and can also be used for multi-side gate modulation through a top solid gate dielectric layer. Specifically, materials such as ionic liquid are dripped into the semiconductor thin film to form a solid gate dielectric layer of a solid electrolyte type, and the top transparent semiconductor thin film layer of other photoelectric transistor units is used as a side gate to regulate and control current.
Based on the two embodiments described above, further explanation is made as follows.
It has been found that light is introduced into a neural synaptic transistor device as a common, readily controllable stimulus, and has become a hot spot in recent years. The introduction of light into the construction of a neurosynaptic device is the basic idea of a phototransistor. Current research is focused mainly on light as an input signal to regulate device performance, so a synaptic device with good current response to light stimulus is a key to realizing low-energy artificial vision system and nerve morphology calculation. The traditional field effect transistor has more process steps and complex process; the optical response of the single-channel layer thin film transistor is poor, and the photo-sensitive characteristic with excellent performance cannot be realized at the same time only by the single-channel layer phototransistor; meanwhile, as the research of single synaptic transistor devices is more mature, the photoelectric synaptic transistor devices are gradually integrated and arrayed as the rest electronic elements, three-terminal devices can be used for introducing multi-gate regulation and control to realize more complex functions, but the device density is relatively smaller, the space utilization rate is low, the integration is difficult, and the stability and uniformity of each device in the array are important performance indexes, so that the requirements of higher layers on the material performance and the processing technology are provided.
According to the invention, the transistor manufacturing process and the device performance are improved, and the femto-second laser micro-nano processing technology is used, so that the photoetching step in the traditional patterning process is omitted, thereby reducing the manufacturing process cost and reducing the uncertain factors in the manufacturing process; in addition, on the basis of the original double-channel layer structure with stable switching characteristics, high mobility and proper starting voltage, photosensitive materials such as quantum dots or metal nano particles are coated in a spin mode in the middle of the channel layer, the mobility of electrons and holes of the device is improved by injecting photo-generated carriers into the semiconductor, and higher photocurrent response is obtained.
Further, the step S10 specifically includes: and sequentially ultrasonically cleaning the silicon wafer substrate by adopting acetone, alcohol and deionized water, and drying to obtain the silicon substrate. In order to ensure various performances of transistor devices, during specific operation, acetone, alcohol and deionized water are sequentially adopted to ultrasonically clean a heavily doped silicon wafer substrate with 250-300 nm thermal growth silicon dioxide, a silicon base layer is obtained after drying treatment, and the cleaned silicon wafer substrate is subjected to drying treatment through a nitrogen gun.
Further, step S20 specifically includes: s21, forming a transparent semiconductor film layer with the thickness of 5-20 nanometers at the lower part of the transparent semiconductor film layer on the upper surface of the silicon dioxide layer by sputtering deposition of a heavily doped semiconductor material; s22, forming a photosensitive material layer with the thickness of 5-10 nanometers on the upper surface of the transparent semiconductor film layer by spin coating the photosensitive material; s23, forming a transparent semiconductor film layer with the thickness of 5-20 nanometers on the upper part of the transparent semiconductor film layer on the upper surface of the photosensitive material layer through sputtering deposition of a heavily doped semiconductor. Optionally, step S20 specifically includes: depositing a heavily doped semiconductor on the upper surface of the silicon base layer through a sputtering process to form a transparent semiconductor film layer positioned on the top of the silicon base layer; spin-coating a photosensitive material on a transparent semiconductor film layer on top of a silicon base layer to form a photosensitive material layer; and depositing a heavily doped semiconductor on the upper surface of the photosensitive material layer through a sputtering process to form a transparent semiconductor film layer on the upper surface of the photosensitive material layer.
Further, the transparent semiconductor thin film layer includes at least one of a tin indium oxide conductive semiconductor thin film layer, an indium zinc oxide conductive semiconductor thin film, and an aluminum zinc oxide conductive semiconductor thin film. Optionally, the transparent semiconductor thin film layer includes at least one of a tin-doped indium oxide (ITO) conductive semiconductor thin film layer, an indium-doped zinc oxide (IZO) conductive semiconductor thin film, and an aluminum-doped zinc oxide (AZO) conductive semiconductor thin film.
In the invention, in order to ensure various performances of a transistor device, a tin indium oxide conductive semiconductor thin film layer with a film thickness of 20 nanometers is provided as a transparent semiconductor thin film layer in specific operation.
Further, the photosensitive material adopts photosensitive quantum dots or nano metal particles.
In the invention, in order to ensure various performances of a transistor device, a photosensitive quantum dot layer with a film thickness of 10 nanometers is provided as a photosensitive material layer in specific operation.
Further, the step S40 specifically includes: implanting ion liquid into the surface of the three-layer film structure and the grooves between two adjacent laminated knotless phototransistors along the length direction of the transistor row, wherein the ion liquid is positioned in the middle area of the transistor row, and the ion liquid is used for forming a solid gate dielectric layer; and implanting ion liquid into the surface of the three-layer film structure and the grooves between two adjacent laminated junction-free phototransistors along the length direction of the transistor array, wherein the ion liquid is positioned in the middle area of the transistor array, and the ion liquid is used for forming a solid gate dielectric layer.
The invention provides a specific embodiment as follows:
the heavily doped P-type silicon with 300nm thermally grown silicon dioxide (gate dielectric) on the silicon is selected as a substrate, the transparent semiconductor film (heavily doped semiconductor layer) layer is selected as an Indium Tin Oxide (ITO) film layer, the photosensitive material is selected as photosensitive quantum dots, and the solid ion electrolyte is selected as ion liquid.
The preparation method of the phototransistor based on the femtosecond laser comprises the following steps:
step 1: sequentially ultrasonically cleaning a heavily doped silicon wafer substrate with 300nm thermally grown silicon dioxide by adopting acetone, alcohol and deionized water, and drying;
step 2: placing the silicon wafer substrate (silicon substrate) into a radio frequency magnetron sputtering vacuum cavity, and depositing a layer of transparent ITO film on the substrate through a sputtering process to serve as a heavily doped semiconductor layer, wherein the film thickness is 20nm;
step 3; spin-coating a layer of photosensitive quantum dots or nano metal particles with the thickness of 5-10nm on the deposited ITO film;
step 4: placing for a certain time, after the photosensitive quantum dots are dried, placing the silicon wafer into a radio frequency magnetron sputtering vacuum cavity again, and performing magnetron sputtering to deposit a layer of ITO film with the thickness of 20nm on the photosensitive quantum dots to serve as a heavily doped semiconductor layer;
as shown in fig. 1, a three-layer thin film structure (ITO thin film-photosensitive quantum dot-ITO thin film) was obtained on a heavily doped silicon wafer substrate with 300nm thermally grown silicon dioxide at this time;
step 5: focusing femtosecond laser on a sample placed on a workbench, and etching the sample according to a set pattern running route to form corresponding grooves, thereby obtaining a laminated non-junction transistor array with a plurality of independent phototransistor units as shown in fig. 2, wherein each independent laminated non-junction transistor takes a top ITO film as a source electrode, a channel and a drain electrode and a heavily doped P-type silicon substrate as a bottom gate;
step 6: and (3) injecting the ion liquid into the groove formed by the femtosecond laser and forming a solid gate medium by the top ITO film (the ion liquid does not fully cover the ITO film and leaves the position as a source electrode and a drain electrode). At this time, the source electrode and the drain electrode are led out from the surface of one top ITO film area, and the grid electrode is led out from the surface of the other top ITO film area, so that the side grid regulation and control are carried out, and the independent thin film transistor is obtained.
The beneficial effects are as follows:
the femtosecond laser micro-nano processing is used, so that uncertain factors in the patterning process are reduced, a transistor array is easy to integrate and form, and the uniformity and stability of the device are improved; compared with a field effect transistor with a single channel layer structure, the field effect transistor with the double-layer channel structure can improve mobility and obtain moderate threshold voltage, and meanwhile, the photosensitive material is used in the middle of the heavily doped semiconductor film, so that wide spectrum detection can be realized, and the high sensitivity response of the device to light can be improved; the stacked junction-free phototransistor array can be controlled by using a bottom gate or a multi-side gate through a top solid electrolyte. In conclusion, the manufacturing method of the phototransistor array avoids the complicated steps of the traditional photoetching, reduces the introduction of uncertain factors, ensures the stability of devices and greatly reduces the process cost; meanwhile, the three-channel sandwich structure improves the mobility of electrons and holes of the device, can obtain higher photocurrent response, and has very wide application prospect in the research of artificial vision and nerve morphology calculation.
The invention also provides a transistor array, which is prepared by the method for preparing the photoelectric transistor based on the femtosecond laser, and comprises at least one transistor row, wherein each transistor row comprises at least two laminated knotless photoelectric transistors which are arranged at intervals along the transverse direction, the two adjacent laminated knotless photoelectric transistors are separated by a groove formed by the femtosecond laser etching, each laminated knotless photoelectric transistor comprises a grid electrode layer with a grid dielectric layer at the top, and the upper surface of the grid dielectric layer is provided with a three-layer film structure. Optionally, a plurality of transistor rows are arranged at intervals by trenches to form a transistor array.
The invention also provides a transistor array, which is prepared by the method for preparing the photoelectric transistor based on the femtosecond laser, and comprises at least one transistor row, wherein each transistor row comprises a plurality of laminated knotless photoelectric transistors which are arranged at intervals along the transverse direction, two adjacent laminated knotless photoelectric transistors are separated by a groove formed by the femtosecond laser etching, each laminated knotless photoelectric transistor comprises a silicon base layer with a silicon dioxide layer on the top surface, the upper surface of the silicon base layer is provided with a three-layer film structure, the top surface of the three-layer film structure is provided with a solid gate dielectric layer, the inside of the groove is provided with the solid gate dielectric layer, and the two adjacent laminated knotless photoelectric transistors are connected by the solid gate dielectric layer. Optionally, a plurality of transistor rows are arranged at intervals by trenches to form a transistor array.
The above is only a preferred embodiment of the present invention, and is not intended to limit the present invention, but various modifications and variations can be made to the present invention by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (8)
1. A method for preparing a phototransistor based on femtosecond laser is characterized by comprising the following steps:
s10, providing a silicon-based layer with a silicon dioxide layer on the top surface;
s20, forming a three-layer film structure on the upper surface of the silicon dioxide layer, wherein the three-layer film structure comprises a photosensitive material layer in the middle layer and transparent semiconductor film layers respectively on the upper side and the lower side of the photosensitive material layer; a photosensitive material layer is arranged between the two transparent semiconductor film layers, the photosensitive material and the semiconductor material are compounded, and photon-generated carriers are injected into the semiconductor to improve the mobility of electrons and holes of the device, so that higher photocurrent response is obtained;
the step S20 specifically includes: s21, forming the transparent semiconductor film layer with the thickness of 5-20 nanometers at the lower part of the transparent semiconductor film layer on the upper surface of the silicon dioxide layer by sputtering deposition of a heavily doped semiconductor material; s22, forming a photosensitive material layer with the thickness of 5-10 nanometers on the upper surface of the transparent semiconductor film layer by spin coating the photosensitive material; s23, forming a transparent semiconductor film layer with the thickness of 5-20 nanometers on the upper part of the transparent semiconductor film layer on the upper surface of the photosensitive material layer through sputtering deposition of a heavily doped semiconductor;
and S30, carrying out etching processing from the upper part of the three-layer film structure along the direction vertical to the surface of the three-layer film structure based on the femtosecond laser processing technology according to preset pattern information to form a transistor array composed of a plurality of laminated knotless phototransistors, wherein two adjacent laminated knotless phototransistors are separated by a groove formed by femtosecond laser etching and penetrating through the three-layer film structure.
2. The method for manufacturing a laminated knotless phototransistor based on the femtosecond laser technology as recited in claim 1, wherein,
the step S10 specifically includes: and sequentially ultrasonically cleaning the silicon wafer substrate by adopting acetone, alcohol and deionized water, and drying to obtain the silicon substrate.
3. The method for manufacturing a phototransistor based on femtosecond laser as recited in claim 1, wherein,
the transparent semiconductor film layer comprises at least one of a tin indium oxide conductive semiconductor film layer, an indium zinc oxide conductive semiconductor film and an aluminum zinc oxide conductive semiconductor film.
4. The method for manufacturing a phototransistor based on femtosecond laser as recited in claim 1, wherein,
the photosensitive material adopts photosensitive quantum dots or nano metal particles.
5. A method for producing a phototransistor based on a femtosecond laser as recited in any one of claims 1 to 4,
the plurality of laminated knotless phototransistors are arranged in an array, at least two laminated knotless phototransistors arranged in a transverse direction form a transistor row, at least two laminated knotless phototransistors arranged in a longitudinal direction form a transistor column,
the method further comprises a step S40 of disposing a first solid gate dielectric layer on the surface of the transistor row, wherein the first solid gate dielectric layer covers the top surface of the three-layer thin film structure and the side wall surface and bottom surface of the trench to form a source electrode and a drain electrode on the top surface of each of the stacked bingeless phototransistors, the source electrode and the drain electrode being oppositely disposed on two sides of the first solid gate dielectric layer, and/or
And a second solid gate dielectric layer is arranged on the surface of the transistor column, wherein the second solid gate dielectric layer covers the top surface of the three-layer film structure, the side wall surface of the groove and the bottom surface of the groove, so that a source electrode and a drain electrode are formed on the top surface of each laminated knotless phototransistor, and the source electrode and the drain electrode are oppositely arranged on two sides of the second solid gate dielectric layer.
6. The method for manufacturing a laminated knotless phototransistor based on the femtosecond laser technology as recited in claim 5, wherein,
the step S40 specifically includes:
and implanting ion liquid into the surface of the three-layer film structure and the groove, wherein the ion liquid is used for forming the first solid gate dielectric layer and/or the second solid gate dielectric layer.
7. A transistor array, characterized in that it is prepared by the method for preparing a phototransistor based on femtosecond laser as set forth in any one of claims 1 to 4,
comprises at least one transistor row, each transistor row comprises at least two laminated knotless phototransistors which are arranged at intervals along the transverse direction, two adjacent laminated knotless phototransistors are separated by a groove formed by femtosecond laser etching,
each laminated bingeless phototransistor comprises a gate layer with a gate dielectric layer on the top, and a three-layer thin film structure is arranged on the upper surface of the gate dielectric layer.
8. A transistor array, characterized in that it is prepared by the method for preparing a phototransistor based on femtosecond laser as set forth in any one of claims 5 to 6,
comprises at least one transistor row, each transistor row comprises a plurality of laminated knotless phototransistors which are arranged at intervals along the transverse direction, two adjacent laminated knotless phototransistors are separated by a groove formed by femtosecond laser etching,
each laminated bingeless phototransistor comprises a silicon substrate with a silicon dioxide layer on the top surface, a three-layer thin film structure is arranged on the upper surface of the silicon substrate, a solid gate dielectric layer is arranged on the top surface of the three-layer thin film structure, the solid gate dielectric layer is arranged in the groove, and two adjacent laminated bingeless phototransistors are connected through the solid gate dielectric layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210513849.3A CN114864735B (en) | 2022-05-11 | 2022-05-11 | Photo transistor preparation method based on femtosecond laser and transistor array |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210513849.3A CN114864735B (en) | 2022-05-11 | 2022-05-11 | Photo transistor preparation method based on femtosecond laser and transistor array |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN114864735A CN114864735A (en) | 2022-08-05 |
| CN114864735B true CN114864735B (en) | 2024-03-15 |
Family
ID=82636578
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210513849.3A Active CN114864735B (en) | 2022-05-11 | 2022-05-11 | Photo transistor preparation method based on femtosecond laser and transistor array |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN114864735B (en) |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20080020161A (en) * | 2006-08-31 | 2008-03-05 | 삼성전자주식회사 | Method for manufacturing polysilicon layer and method for manufacturing thin film transistor using the same |
| CN101325181A (en) * | 2008-08-05 | 2008-12-17 | 友达光电股份有限公司 | Thin-film transistor array substrate and preparation method thereof |
| CN101540342A (en) * | 2008-03-18 | 2009-09-23 | 株式会社半导体能源研究所 | Thin film transistor and display device |
| CN102623398A (en) * | 2012-03-21 | 2012-08-01 | 中国科学院宁波材料技术与工程研究所 | Method for manufacturing junction-free thin film transistor |
| KR20210009147A (en) * | 2019-07-16 | 2021-01-26 | 현대자동차주식회사 | A method of manufacturing optical sensor using quantum dot and the optical sensor |
| CN113471359A (en) * | 2021-05-21 | 2021-10-01 | 北京大学深圳研究生院 | Neurosynaptic-like device and method of manufacturing the same |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7470943B2 (en) * | 2005-08-22 | 2008-12-30 | International Business Machines Corporation | High performance MOSFET comprising a stressed gate metal silicide layer and method of fabricating the same |
| JP4963120B2 (en) * | 2006-02-14 | 2012-06-27 | 独立行政法人産業技術総合研究所 | Optical field effect transistor and integrated photo detector using the same |
| AU2013255707A1 (en) * | 2012-05-03 | 2014-11-13 | Nexcis | Laser etching a stack of thin layers for a connection of a photovoltaic cell |
| WO2019081492A1 (en) * | 2017-10-26 | 2019-05-02 | Emberion Oy | Photosensitive field-effect transistor |
-
2022
- 2022-05-11 CN CN202210513849.3A patent/CN114864735B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20080020161A (en) * | 2006-08-31 | 2008-03-05 | 삼성전자주식회사 | Method for manufacturing polysilicon layer and method for manufacturing thin film transistor using the same |
| CN101540342A (en) * | 2008-03-18 | 2009-09-23 | 株式会社半导体能源研究所 | Thin film transistor and display device |
| CN101325181A (en) * | 2008-08-05 | 2008-12-17 | 友达光电股份有限公司 | Thin-film transistor array substrate and preparation method thereof |
| CN102623398A (en) * | 2012-03-21 | 2012-08-01 | 中国科学院宁波材料技术与工程研究所 | Method for manufacturing junction-free thin film transistor |
| KR20210009147A (en) * | 2019-07-16 | 2021-01-26 | 현대자동차주식회사 | A method of manufacturing optical sensor using quantum dot and the optical sensor |
| CN113471359A (en) * | 2021-05-21 | 2021-10-01 | 北京大学深圳研究生院 | Neurosynaptic-like device and method of manufacturing the same |
Non-Patent Citations (7)
| Title |
|---|
| A gate-tunable symmetric bipolar junction transistor fabricated via femtosecond laser processing;Su, BW, et al;《Nanoscale Advances》;第2卷(第4期);全文 * |
| Emerging photoelectric devices for neuromorphic vision applications: principles, developments, and outlooks;Zhang Yi, et al;《Science and Technology of Advanced Materials》;第24卷(第1期);全文 * |
| Wonbong Choi 等.《石墨烯的合成与应用》.哈尔滨工业大学出版社,2021,(第1版),第138页. * |
| 溶液法制备金属氧化物薄膜晶体管的研究进展;吴宝仔;廖荣;刘玉荣;;半导体技术;20180503(05);全文 * |
| 雷仕湛等.《激光智能制造技术》.复旦大学出版社,2018,(第1版),第280页. * |
| 飞秒激光实现微机电系统加工短流程工艺;王建中;史铁林;熊良才;;激光技术(01);全文 * |
| 飞秒激光诱导金属表面微纳米结构的基础研究;黄永光;《中国博士学位论文全文数据库 工程科技I辑》(第09期);全文 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN114864735A (en) | 2022-08-05 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR101280827B1 (en) | Array substrate and method of fabricating the same | |
| US20180212062A1 (en) | Coplanar double gate electrode oxide thin film transistor and manufacture method thereof | |
| KR20110084178A (en) | Method for making side growth semiconductor nanowires and transistors obtained by said method | |
| WO2013118706A1 (en) | Thin-film transistor having three-dimensional structure, and method for manufacturing same | |
| KR20190129223A (en) | Oxide semiconductor thin film photo transistor and method of manufacturing the same | |
| CN105866984A (en) | Graphene electro-optical modulator and preparation method thereof | |
| US20230352496A1 (en) | Array substrate and display panel | |
| JP2014516421A (en) | Pixel capacitor | |
| KR101427776B1 (en) | Quasi-surface emission vertical-type organic light-emitting transistors and method for manufacturing the same | |
| CN107579128B (en) | A kind of focal plane imaging device and preparation method thereof based on graphene | |
| US10483405B2 (en) | Metal oxide thin-film transistor and manufacturing method for the same | |
| CN114864735B (en) | Photo transistor preparation method based on femtosecond laser and transistor array | |
| WO2024139360A1 (en) | Single-crystal perovskite cell preparation method and single-crystal perovskite cell prepared using same | |
| CN108075017B (en) | Manufacturing method of IBC battery | |
| CN111969037A (en) | Air-gap graphene field effect tube structure and preparation method | |
| CN104347639A (en) | Thin film transistor substrate and manufacturing method thereof | |
| WO2023082652A1 (en) | Thin film transistor memory and preparation method therefor | |
| KR101476125B1 (en) | Thin film type Solar Cell and Method for manufacturing the same | |
| CN115020590A (en) | Perovskite photoelectric detector, perovskite photoelectric detector array and preparation method thereof | |
| CN113805364A (en) | Photonic crystal microcavity-graphene electro-optic modulator | |
| CN111584675A (en) | Photoelectric detection device and preparation method thereof | |
| CN114050167B (en) | Medical field-oriented semiconductor silicon-based hybrid imaging chip and preparation method thereof | |
| US6147901A (en) | Semiconductor memory operating electrically and optically, retaining information without power supply | |
| KR101309487B1 (en) | Solar cell with light-scattering lens and manufacturing method for the same | |
| CN115377178B (en) | Multi-grid surrounding transistor and preparation method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |