CN111477628B - A kind of semi-floating gate TFT memory and preparation method thereof - Google Patents

Abstract

The invention belongs to the technical field of integrated circuit memories, and particularly relates to a semi-floating gate TFT memory and a preparation method thereof. The semi-floating gate TFT memory of the invention comprises: an L-shaped back gate; the top of the L-shaped blocking layer on the bottom of the back gate is flush with the top of the back gate; the top of the L-shaped floating gate is flush with the top of the barrier layer; the upper surface of the tunneling layer at the bottom of the floating gate is kept flat with the top of the floating gate; a channel on the upper surfaces of the tunneling layer and the floating gate; a source and a drain on the channel; the floating gate and the channel are made of semiconductor materials and have opposite conduction types, and the floating gate, the channel, the barrier layer and the back gate form a grid control diode. The data writing and erasing of the semi-floating gate TFT memory are realized by the gate control diode, so that the data erasing speed can be accelerated.

Description

A kind of semi-floating gate TFT memory and preparation method thereof

technical field

The invention belongs to the technical field of integrated circuit memory, and in particular relates to a semi-floating gate TFT memory and a preparation method thereof.

Background technique

Non-volatile memory is an indispensable component in modern electronic devices. At present, non-volatile memory on the market is still dominated by silicon-based devices. However, the traditional floating gate structure non-volatile memory based on single crystal silicon substrate usually involves a high temperature process due to the complex fabrication process, so it is difficult to fabricate an embedded non-volatile memory on a glass substrate, which leads to the integration of the non-volatile memory. Restricted when going to the display panel.

At present, a non-volatile memory based on thin film transistor (TFT) structure has attracted widespread attention. This memory can not only be fabricated on glass or flexible substrates, but also has a process technology that can be well matched with the traditional TFT process technology. It is compatible and has great application prospects in the field of advanced system panels or system packaging (SOP) in the future. However, for the existing TFT memory structure, the charge movement between the channel and the trapping layer is still achieved through the tunnel layer, resulting in a relatively slow write operation, which greatly limits its application in the cache field.

SUMMARY OF THE INVENTION

The purpose of the present invention is to provide a semi-floating gate TFT memory with fast data erasing and writing speed and a preparation method thereof.

The semi-floating gate TFT memory provided by the present invention includes:

Back grid, L-shaped;

a blocking layer, formed on the bottom of the back gate and in an L shape, the top of which is flush with the top of the back gate;

a floating gate, which is formed on the bottom of the blocking layer and is L-shaped, the top of which is flush with the top of the blocking layer;

a tunneling layer, formed at the bottom of the floating gate, the upper surface of which is flush with the top of the floating gate;

a channel, formed on the upper surface of the tunnel layer and the floating gate;

a source electrode and a drain electrode formed on the channel;

The floating gate and the channel are both semiconductor materials and have opposite conductivity types, and the floating gate, the channel, the blocking layer and the back gate constitute a gated diode.

In the semi-floating gate TFT memory of the present invention, preferably, the floating gate is NiO, Cu ₂ O, SnO or low temperature polysilicon.

In the semi-floating gate TFT memory of the present invention, preferably, the tunneling layer is selected from Al ₂ O ₃ , SiO ₂ , HfO ₂ , ZrO 2 , Ta ₂ O ₅ , TiO ₂ , La ₂ O ₃ , HfZrO ₄ , or A laminate consisting of the aforementioned materials.

In the semi-floating gate TFT memory of the present invention, preferably, the channel is IGZO, ZnO, In ₂ O ₃ or n-type low temperature polysilicon.

In the semi-floating gate TFT memory of the present invention, preferably, the source electrode and the drain electrode are Au/Ti, Au/Cr or TiAlNiAu.

The preparation method of the semi-floating gate TFT memory provided by the present invention comprises the following steps:

(1) Provide a substrate to form an L-shaped back gate;

(2) forming a barrier layer on the bottom of the back gate, so that the barrier layer is L-shaped, and the top is level with the top of the back gate;

(3) forming a floating gate on the bottom of the blocking layer, so that the floating gate is L-shaped, and the top is level with the top of the blocking layer;

(4) forming a tunneling layer on the bottom of the floating gate, the upper surface of which is flush with the top of the floating gate;

(5) forming a channel on the upper surface of the tunneling layer and the floating gate;

(6) A source electrode and a drain electrode are formed on the channel.

Wherein, the floating gate and the channel are both semiconductor materials and have opposite conductivity types, and the floating gate, the channel, the blocking layer and the back gate constitute a gated diode.

In the preparation method of the semi-floating gate TFT memory of the present invention, preferably, the floating gate is NiO, Cu ₂ O, SnO or low temperature polysilicon.

In the preparation method of the semi-floating gate TFT memory of the present invention, preferably, the tunneling layer is selected from Al ₂ O ₃ , SiO ₂ , HfO ₂ , ZrO 2 , Ta ₂ O ₅ , TiO ₂ , La ₂ O ₃ , HfZrO ₄ , or a stack of the aforementioned materials.

In the preparation method of the semi-floating gate TFT memory of the present invention, preferably, the channel is IGZO, ZnO, In ₂ O ₃ or n-type low temperature polysilicon.

In the preparation method of the semi-floating gate TFT memory of the present invention, preferably, the source electrode and the drain electrode are Au/Ti, Au/Cr or TiAlNiAu.

The data writing and erasing of the semi-floating gate TFT memory of the present invention are all realized by gated diodes, which can speed up the data erasing and writing speed.

Description of drawings

FIG. 1 is a flow chart of a method for fabricating a semi-floating gate TFT memory.

FIG. 2 is a schematic structural diagram of an L-shaped back gate.

FIG. 3 is a schematic diagram of the device structure after depositing an insulating medium.

FIG. 4 is a schematic diagram of the device structure after forming the L-type barrier layer.

FIG. 5 is a schematic diagram of the device structure after forming and depositing the P-type semiconductor material.

FIG. 6 is a schematic diagram of the structure of the device after the L-shaped floating gate is formed.

FIG. 7 is a schematic diagram of the device structure after forming the tunneling layer.

FIG. 8 is a schematic diagram of the device structure after depositing the n-type semiconductor material.

FIG. 9 is a schematic diagram of the device structure after the channel is formed.

FIG. 10 is a schematic diagram of the device structure of the semi-floating gate TFT memory.

Detailed ways

The present invention will be further introduced below in conjunction with the embodiments and the accompanying drawings. It should be understood that the embodiments are only used to explain the present invention, and are not intended to limit the present invention. All other embodiments obtained by persons of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

In the description of the present invention, it should be noted that the orientation or positional relationship indicated by the terms "upper", "lower", "vertical", "horizontal", etc. is based on the orientation or positional relationship shown in the accompanying drawings, and is only for convenience The invention is described and simplified without indicating or implying that the device or element referred to must have a particular orientation, be constructed and operate in a particular orientation, and therefore should not be construed as limiting the invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed to indicate or imply relative importance.

Furthermore, numerous specific details of the present invention are described below, such as device structures, materials, dimensions, processing techniques and techniques, in order to provide a clearer understanding of the present invention. However, as can be understood by one skilled in the art, the present invention may be practiced without these specific details. Unless specifically indicated below, various parts of the device may be constructed of materials known to those skilled in the art, or materials developed in the future with similar functions may be employed.

FIG. 1 is a flowchart of a method for fabricating a semi-floating gate TFT memory, and FIGS. 2 to 10 are schematic structural diagrams of each step of the method for fabricating a semi-floating gate TFT memory. As shown in Figure 2, the specific preparation steps are:

In step S1, a substrate is provided as the back gate 200 of the semi-floating gate TFT memory. The substrate can be a low-resistance silicon substrate, an ITO substrate, and a flexible substrate covered with a conductive film on the surface. A low-resistance silicon substrate is used in this embodiment mode. Then the photoresist is spin-coated, and a pattern for defining the shape is formed by a photolithographic process including exposure and development; finally, the photoresist is used as a mask, and dry etching is performed, such as ion milling etching, plasma etching, reactive ion etching, etc. Etching, laser ablation, inductively coupled plasma etching, or wet etching using an etchant solution to form a back gate with an L-shaped appearance, the resulting structure is shown in Figure 2.

In step S2 , an insulating medium is deposited on the surface of the back gate 200 as a blocking layer 201 , and the obtained structure is shown in FIG. 3 . In this embodiment, Al ₂ O ₃ is formed as the barrier layer by atomic layer deposition, but the present invention is not limited to this, and the barrier layer can also be made of other suitable materials, such as SiO ₂ , HfO ₂ , ZrO ₂ , Ta ₂ O ₅ , TiO ₂ , La ₂ O ₃ , HfZrO ₄ or a stack composed of the aforementioned materials, etc., can also be formed by chemical vapor deposition, physical vapor deposition, pulsed laser deposition, electron beam evaporation, and the like. Then, a photoresist is applied, and a pattern for defining a shape is formed by a photolithography process including exposure and development; finally, using the photoresist as a mask, dry etching, such as ion milling etching, plasma etching, reaction Ion etching, laser ablation, inductively coupled plasma etching, or wet etching using an etchant solution forms a barrier layer structure having an L-shaped appearance, the resulting structure is shown in FIG. 4 .

In step S3, a layer of p-type semiconductor is deposited as a floating gate material, and the obtained structure is shown in FIG. 5 . In this embodiment, NiO is formed by atomic layer deposition as the floating gate material, but the invention is not limited to this, and the floating gate material can also be other suitable materials, such as Cu ₂ O, SnO, p-type low temperature polysilicon, etc. , the formation method can also be chemical vapor deposition, physical vapor deposition, pulsed laser deposition, electron beam evaporation and the like. Then, a photoresist is applied, and a pattern for defining a shape is formed by a photolithographic process including exposure and development. Finally, using the photoresist as a mask, the appearance is formed by dry etching, such as ion milling etching, plasma etching, reactive ion etching, laser ablation, inductively coupled plasma etching, or by wet etching using an etchant solution. The L-shaped floating gate 202 has a structure as shown in FIG. 6 .

Step S4, depositing a layer of insulating medium as a tunneling layer, then applying photoresist, and forming a pattern for defining a shape through a photolithography process including exposure and development; finally, using the photoresist as a mask, through a dry method Etching, such as ion milling etching, plasma etching, reactive ion etching, laser ablation, inductively coupled plasma etching, or by wet etching using an etchant solution to form the tunneling layer 203 flush with the top of the floating gate, the resulting structure is as shown in Figure 7. In this embodiment, Al ₂ O ₃ is formed as the tunneling layer by the method of atomic layer deposition, but the invention is not limited to this, and the tunneling layer can also be other suitable materials, such as SiO ₂ , HfO ₂ , ZrO ₂ , Ta ₂ O ₅ , TiO ₂ , La ₂ O ₃ , HfZrO ₄ or a stack composed of the aforementioned materials, etc., the formation method can also be chemical vapor deposition, physical vapor deposition, pulsed laser deposition, electron beam evaporation, etc.

In step S5, a layer of n-type semiconductor is deposited as a channel material, and the obtained structure is shown in FIG. 8 . In this embodiment, indium gallium zinc oxide (IGZO) is formed as the channel material by physical vapor deposition, but the invention is not limited to this, and the channel material can also be other suitable materials, such as ZnO, In ₂ O ₃ or n-type low temperature polysilicon can also be formed by chemical vapor deposition, atomic layer deposition, pulsed laser deposition, electron beam evaporation, and the like. Then photoresist is applied, and a pattern for defining the shape is formed by a photolithography process including exposure and development; finally, the photoresist is used as a mask, and dry etching is performed, such as ion milling etching, plasma etching, reactive ion etching, etc. , laser ablation, inductively coupled plasma etching, or wet etching using an etchant solution to form a channel layer 204 covering only the tunneling layer and the floating gate, the resulting structure is shown in FIG. 9 .

In step S6, the Au/Ti stack is grown by the method of physical vapor deposition, and the source electrode 205 and the drain electrode 206 are formed by photolithography and etching, and the obtained structure is shown in FIG. 10 . However, the present invention is not limited to this, and the source and drain materials may also be Au/Cr or TiAlNiAu.

As shown in FIG. 10, the semi-floating gate TFT memory includes: a back gate 200, which is L-shaped; a blocking layer 201, which is formed on the bottom of the back gate 200 and is L-shaped, the top of which is flush with the top of the back gate 200; The floating gate 202 is formed on the bottom of the blocking layer 201 and is L-shaped, the top of which is flush with the top of the blocking layer 201 ; The tops are flat; the channel 204 is formed on the upper surface of the tunneling layer 203 and the floating gate 202; the source electrode 205 and the drain electrode 206 are formed on the channel 204; the floating gate 202 and the channel 204 are both semiconductor materials, and Having opposite conductivity types, the floating gate 202, the channel 204, the barrier layer 201, and the back gate 200 constitute a gated diode.

The floating gate material is NiO, Cu ₂ O, SnO or low temperature polysilicon. The tunneling layer material is preferably Al ₂ O ₃ , SiO ₂ , HfO ₂ , ZrO 2 , Ta ₂ O ₅ , TiO ₂ , La ₂ O ₃ , HfZrO ₄ or a stack composed of the aforementioned materials. The channel material is preferably IGZO, ZnO, In ₂ O ₃ or n-type low temperature polysilicon. The source and drain materials are preferably Au/Ti, Au/Cr or TiAlNiAu.

In the semi-floating gate TFT memory of the present invention, the floating gate 202 and the channel 204 form a diode. Meanwhile, the floating gate 202, the channel 204, the blocking layer 201 and the back gate 200 constitute a gated diode. When a positive voltage is applied to the back gate 200, the diode is forward biased and turned on, and electrons flow from the channel material 204 into the floating gate material 202, resulting in a change in the threshold voltage of the TFT memory; when a negative voltage is applied to the back gate 200, the diode is reverse biased, However, since the energy band of the floating gate material 202 is regulated by the back gate 200 through the blocking layer 201 in the vertical direction, the valence band of the p-type floating gate material 202 will rise above the conduction band of the n-type channel material 204 , which is located at the floating gate at this time. Electrons in the valence band of material 202 can tunnel to the conduction band of channel material 204, thereby restoring the TFT memory to its original state. Two states of charge writing and erasing are realized by the inflow and outflow of electrons in the floating gate material. The data writing and erasing of the semi-floating gate TFT memory of the present invention are all realized by gate-controlled diodes, which can speed up the data erasing and writing speed. Moreover, the process process can be fully compatible with the traditional TFT process.

The above are only specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art who is familiar with the technical scope disclosed by the present invention can easily think of changes or substitutions. All should be included within the protection scope of the present invention.

Claims (10)

1. a semi-floating gate TFT memory, is characterized in that, comprises: Back grid (200), L-shaped; a blocking layer (201), formed on the bottom of the back gate (200), and in an L-shape, the top of which is flush with the top of the back gate (200); a floating gate (202), formed on the bottom of the blocking layer (201), in an L-shape, the top of which is flush with the top of the blocking layer (201); a tunneling layer (203), formed at the bottom of the floating gate (202), the upper surface of which is flush with the top of the floating gate (202); a channel (204), formed on the upper surface of the tunneling layer (203) and the floating gate (202); a source (205) and a drain (206) formed on the channel (204); The floating gate (202) and the channel (204) are both semiconductor materials and have opposite conductivity types, the floating gate (202), the channel (204), the barrier layer (201) and all The back gate (200) constitutes a gated diode. 2. The semi-floating gate TFT memory according to claim 1, wherein the floating gate (202) is NiO, Cu2O, _SnO or low temperature polysilicon. 3. The semi-floating gate TFT memory according to claim 1, wherein the tunneling layer (203) is selected from Al ₂ O ₃ , SiO ₂ , HfO ₂ , ZrO 2 , Ta ₂ O ₅ , TiO ₂ , La ₂ O ₃ , HfZrO ₄ , or a stack of the aforementioned materials. 4. The semi-floating gate TFT memory according to claim 1, wherein the channel (204) is IGZO, ZnO, In ₂ O ₃ or n-type low temperature polysilicon. 5. The semi-floating gate TFT memory according to claim 1, wherein the source electrode (205) and the drain electrode (206) are Au/Ti, Au/Cr or TiAlNiAu. 6. A method for preparing a semi-floating gate TFT memory, wherein the specific steps are: providing a substrate to form an L-shaped back gate (200); A barrier layer (201) is formed on the bottom of the back gate (200), so that the barrier layer (201) is L-shaped, and the top of the barrier layer (201) is flush with the top of the back gate (200). A floating gate (202) is formed on the bottom of the blocking layer (201), so that the floating gate (202) is L-shaped, and the top is level with the top of the blocking layer (201); forming a tunneling layer (203) on the bottom of the floating gate (202), the upper surface of which is flush with the top of the floating gate (202); forming a channel (204) on the upper surface of the tunneling layer (203) and the floating gate (202); forming a source (205) and a drain (206) on the channel (204), Wherein, the floating gate (202) and the channel (204) are both semiconductor materials and have opposite conductivity types, the floating gate (202), the channel (204), and the barrier layer (201) And the back gate (200) constitutes a gated diode. 7 . The method for manufacturing a semi-floating gate TFT memory according to claim 6 , wherein the floating gate ( 202 ) is NiO, Cu ₂ O, SnO or low temperature polysilicon. 8 . 8 . The method for preparing a semi-floating gate TFT memory according to claim 6 , wherein the tunneling layer ( 203 ) is selected from Al ₂ O ₃ , SiO ₂ , HfO ₂ , ZrO 2 , Ta ₂ O ₅ , TiO ₂ , La ₂ O ₃ , HfZrO ₄ , or a laminate consisting of the foregoing materials. 9 . The method for manufacturing a semi-floating gate TFT memory according to claim 6 , wherein the channel ( 204 ) is IGZO, ZnO, In ₂ O ₃ or n-type low temperature polysilicon. 10 . 10. The method for fabricating a semi-floating gate TFT memory according to claim 6, wherein the source electrode (205) and the drain electrode (206) are Au/Ti, Au/Cr or TiAlNiAu.

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