CN114864678A - 半导体元件结构 - Google Patents

半导体元件结构 Download PDF

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Publication number
CN114864678A
CN114864678A CN202210207987.9A CN202210207987A CN114864678A CN 114864678 A CN114864678 A CN 114864678A CN 202210207987 A CN202210207987 A CN 202210207987A CN 114864678 A CN114864678 A CN 114864678A
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layer
semiconductor
bipolar
silicon
dielectric
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Inventor
徐崇威
江国诚
黄懋霖
朱龙琨
余佳霓
程冠伦
王志豪
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本公开提供一种半导体元件结构。半导体元件结构包括一或多个第一半导体层以及双极层，围绕第一半导体层的每一个，其中双极层包括锗。半导体元件结构也包括盖层，围绕并接触双极层，其中盖层包括硅以及一或多个第二半导体层，设置邻近第一半导体层。半导体元件结构还包括栅极电极层，围绕第一半导体层的每一个和第二半导体层的每一个。

Description

半导体元件结构
技术领域
本发明实施例涉及半导体元件结构及其形成方法，尤其涉及纳米片晶体管及其形成方法。
背景技术
半导体集成电路(integrated circuit,IC)业界历经了快速地成长。在集成电路材料和设计中的技术演进产生各种世代的集成电路，其中每个世代具有比前一个世代更小且更复杂的电路。在集成电路演进的过程中，功能密度(例如每个芯片面积中互连元件的数量)大致增加，而几何尺寸(例如可使用工艺创建出的最小的组件(或走线))缩小。这样的缩小尺寸工艺总体而言通过增加生产效率和降低相关成本以提供利益。这样的尺寸缩小也增加了新的挑战。
在追求较高的元件密度、较高性能以及较低的成本的过程中，来自制造和设计两者问题的挑战导致发展出立体设计，如多重栅极场效晶体管(field effect transistor,FET)，包括纳米片场效晶体管。在纳米片场效晶体管中，通道的每一侧的表面皆被栅极电极围绕，允许在通道中更完整的空乏，且得到较少的短通道效应(short-channel effect)和较佳的栅极控制。随着晶体管尺寸持续地微缩，纳米片场效晶体管需要进一步的改善。
发明内容
一种半导体元件结构，包括：一或多个第一半导体层；双极层(dipole layer)，围绕第一半导体层的每一个，其中双极层包括锗；盖层(capping layer)，围绕并接触双极层，其中盖层包括硅；一或多个第二半导体层，设置邻近第一半导体层；以及栅极电极层，围绕第一半导体层的每一个和第二半导体层的每一个。
一种半导体元件结构，包括：介电部件；一或多个第一半导体层，设置邻近介电部件的第一侧；第一双极层，围绕第一半导体层的每一个，其中第一双极层包括锗；第一界面层，围绕第一双极层，其中第一界面层包括含氧材料，而第一界面层具有第一厚度；一或多个第二半导体层，设置邻近介电部件的第二侧；第二界面层，围绕第二半导体层的每一个，其中第二界面层包括含氧材料，而第二界面层具有第二厚度，第二厚度大于第一厚度；以及第一栅极电极层，围绕第一半导体层的每一个和第二半导体层的每一个。
一种半导体元件结构的形成方法，包括：形成第一鳍片结构和第二鳍片结构，第一鳍片结构和第二鳍片结构的每一个包括多个第一半导体层和多个第二半导体层交错堆叠；形成牺牲栅极结构于第一鳍片结构和第二鳍片结构上；形成源极/漏极部件于牺牲栅极结构的两侧上，源极/漏极部件接触第一鳍片结构和第二鳍片结构的第一半导体层；移除第二半导体层的部分以露出第一鳍片结构和第二鳍片结构的每个第一半导体层的部分；形成双极层以围绕第一鳍片结构的每个第一半导体层的露出部分，其中双极层包括锗；形成盖层以围绕并接触双极层；形成第一界面层以围绕盖层；形成第二界面层以围绕第二鳍片结构的每个第一半导体层的露出部分；以及形成栅极电极层以围绕第一鳍片结构和第二鳍片结构的每个第一半导体层。
附图说明
以下将配合所附附图详述本发明实施例。应强调的是，依据在业界的标准做法，各种特征并未按照比例绘制。事实上，可任意地放大或缩小各种部件的尺寸，以清楚地表现出本公开实施例的特征。
图1～图8是根据一些实施例，制造半导体元件结构的各种阶段的透视图。
图9A、图10A、图11A、图12A、图13A、图14A、和图15A是根据一些实施例，制造半导体元件结构的各种阶段的其中一个沿着图8的剖面A-A的剖面示意图。
图9B、图10B、图11B、图12B、图13B、图14B、和图15B是根据一些实施例，半导体元件结构沿着图8的剖面B-B的剖面示意图。
图9C、图10C、图11C、图12C、图13C、图14C、和图15C是根据一些实施例，制造半导体元件结构的各种阶段的其中一个沿着图8的剖面C-C的剖面示意图。
图16、图16a、图17、图17a、图17b、图18～图24、图24a、图24b、和图25是根据一些实施例，示出制造半导体元件结构的各种阶段于图15B的区域的放大示意图。
图26A、图26B、图26C、和图26D和图27A、图27B、图27C、和图27D是根据一些实施例，制造半导体元件结构的各种阶段的其中一个分别沿着图8的剖面A-A、B-B、C-C以及D-D的剖面示意图。
附图标记如下：
100:半导体元件结构
101:基底
104:半导体层堆叠
106:第一半导体层
108:第二半导体层
110:掩模结构
110a:垫层
110b:硬掩模
112:鳍片结构
114:沟槽
116:井部
117:包覆层
118:绝缘材料
119:衬层
120:隔离区
121:介电材料
123:沟槽
125:介电材料
127:介电部件
129:互混层
130:牺牲栅极结构
132:牺牲栅极介电层
134:牺牲栅极电极层
136:掩模层
138:栅极间隔物
144:介电间隔物
146:外延源极/漏极部件
147:区域
150:双极层
151:开口
152:硬掩模
153:区域
154:掩模层
155:区域
156:界面层
157:盖层
157’:盖层
159:外部
160:高介电常数介电层
161:盖层
162:接触蚀刻停止层
163:界面层
164:层间介电层
165:正极性双极层
166:沟槽
167:负极性双极层
172:栅极电极层
173:自对准接触层
174:N型栅极电极层
176:源极/漏极接触件
178:硅化物层
179:第二栅极电极层
A:部分
A-A:剖面
B:部分
B-B:剖面
C:部分
C-C:剖面
D:部分
D-D:剖面
E:部分
T1:厚度
T2:厚度
T3:厚度
T4:厚度
W1:宽度
具体实施方式
以下公开提供了许多的实施例或范例，用于实施本公开的不同部件。组件和配置的具体范例描述如下，以简化本公开实施例。当然，这些仅仅是范例，并非用以限定本公开实施例。举例来说，叙述中提及第一部件形成于第二部件之上，可包括形成第一和第二部件直接接触的实施例，也可包括额外的部件形成于第一和第二部件之间，使得第一和第二部件不直接接触的实施例。另外，本公开可在各种范例中重复元件符号及/或字母。这样重复是为了简化和清楚的目的，其本身并非主导所讨论各种实施例及/或配置之间的关系。
再者，此处可使用空间上相关的用语，如“在…之下”、“下方的”、“低于”、“在…上方”、“上方的”、“顶部的”、“上部的”和类似用语可用于此，以便描述如图所示一元件或部件和其他元件或部件之间的关系。这些空间用语企图包括使用或操作中的元件的不同方位，以及附图所述的方位。当元件被转至其他方位(旋转90°或其他方位)，则在此所使用的空间相对描述可同样依旋转后的方位来解读。
尽管本公开的实施例是关于纳米片通道场效晶体管的讨论，本公开的一些面向的实施可用于其他工艺中及/或其他元件中，如平面式场效晶体管、鳍式场效晶体管(finfield effect transistor,finFET)、水平全绕式栅极(horizontal gate all around,HGAA)场效晶体管、垂立全绕式栅极(vertical gate all around,VGAA)场效晶体管以及其他合适的元件。所属技术领域中技术人员将轻易地理解在本公开的范围内所思及而制作出的其他修改。在适用全绕式栅极晶体管结构的情况下，可通过任何合适方法图案化全绕式栅极晶体管结构。举例来说，可使用一或多个光刻工艺(包括双重图案化或多重图案化工艺)来图案化结构。一般来说，双重图案化或多重图案化工艺结合了光刻工艺与自对准工艺，以创建出例如，比使用单一、直接光刻工艺所得的节距更小的图案。举例来说，在一实施例中，在基底上方形成牺牲层，并使用光刻工艺对其进行图案化。使用自对准工艺在图案化的牺牲层旁边形成间隔物。之后移除牺牲层，然后可以使用剩余的间隔物作为掩模以图案化全绕式栅极结构。
图1～图8、图9A～图9C、图10A～图10C、图11A～图11C、图12A～图12C、图13A～图13C、图14A～图14C、图15A～图15C、图16～图25、图26A～图26D、和图27A～图27D图是根据本公开的实施例，示出用来制造半导体元件结构100的示例工艺。应理解的是，可在图1～图8、图9A～图9C、图10A～图10C、图11A～图11C、图12A～图12C、图13A～图13C、图14A～图14C、图15A～图15C、图16～图25、图26A～图26D、和图27A～图27D所示的工艺之前、之中以及之后提供额外步骤，且可针对工艺的额外实施例取代或消除下述的一些步骤。步骤/工艺的顺序并非用以限定，而可以互换。
图1～图8是根据一些实施例，制造半导体元件结构100的各种阶段的透视图。如图1所示，半导体元件结构100包括形成于基底101上的半导体层堆叠104。基底101可为半导体基底。基底101可包括单晶半导体材料，如硅(silicon,Si)、锗(germanium,Ge)、硅锗(silicon germanium,SiGe)、砷化镓(gallium arsenide,GaAs)、锑化铟(indiumantimonide,InSb)、磷化镓(gallium phosphide,GaP)、锑化镓(gallium antimonide,GaSb)、砷化铟铝(indium aluminum arsenide,InAlAs)、砷化铟镓(indium galliumarsenide,InGaAs)、磷化镓锑(gallium antimony phosphide,GaSbP)、砷化镓锑(galliumantimony arsenide,GaSbAs)、或磷化铟(indium phosphide,InP)。在一实施例中，基底101以硅形成。在一些实施例中，基底101为绝缘层上硅(silicon-on-insulator,SOI)基底，具有设置于两个硅层之间的绝缘层(未示出)，作为增强的目的。在一面向，绝缘层为含氧层。
基底101可包括被杂质(例如具有P型导电类型或N型导电类型的掺质)掺杂的各种区域。取决于电路的设计，掺质可为例如针对N型场效晶体管的硼和针对P型场效晶体管的磷。
半导体层堆叠104包括以不同材料形成的半导体层，以加速在多重栅极元件中形成纳米片通道，如纳米片通道场效晶体管。在一些实施例中，半导体层堆叠104包括第一半导体层106和第二半导体层108。在一些实施例中，半导体层堆叠104包括交错铺设第一半导体层106和第二半导体层108。第一半导体层106和第二半导体层108以具有不同蚀刻选择比及/或氧化率的半导体材料所形成。举例来说，第一半导体层106可以硅形成，而第二半导体层108可以硅锗形成。在一些范例中，第一半导体层106可以硅锗形成，而第二半导体层108可以硅形成。替代地，在一些实施例中，第一半导体层106和第二半导体层108任一个可为或包括其他材料，如锗、碳化硅(silicon carbide,SiC)、砷化锗(germanium arsenide,GeAs)、磷化镓、磷化铟、砷化铟(indium arsenide,InAs)、锑化铟、砷磷化镓(galliumarsenic phosphide,GaAsP)、砷化铝铟、砷化铝镓(aluminum gallium arsenide,AlGaAs)、砷化铟镓、磷化镓铟(gallium indium phosphide,GaInP)、砷磷化镓铟(gallium indiumarsenic phosphide,GaInAsP)、或其组合。
第一半导体层106和第二半导体层108的厚度可能不同，取决于应用及/或元件性能考虑。在一些实施例中，每个第一半导体层106和第二半导体层108具有介于约5nm和30nm之间范围的厚度。在其他实施例中，每个第一半导体层106和第二半导体层108具有介于约10nm和20nm之间范围的厚度。在一些实施例中，每个第一半导体层106和第二半导体层108具有介于约6nm和12nm之间范围的厚度。每个第二半导体层108的厚度可等于、小于、或大于第一半导体层106的厚度。最终可移除第二半导体层108，并用来定义半导体元件结构100的相邻通道之间的垂直间距。
第一半导体层106或其部分可在之后的制造阶段中形成半导体元件结构100的纳米片通道。此处的所使用的“纳米片”用语是用来表示具有纳米等级(或甚至微米等级)尺寸的任何材料部分，且具有拉长的形状，无论此部分的剖面形状。因此，此用语代指表圆形以及实质上为圆形的剖面细长材料部分，以及具有例如圆柱形或实质上矩形剖面的柱状(beam-shaped)或条状(bar-shaped)材料部分。半导体元件结构100的纳米片通道可被栅极电极围绕。半导体元件结构100可包括纳米片晶体管。纳米片晶体管可被称为纳米线晶体管、全绕式栅极晶体管、多重桥接通道(multi-bridge channel,MBC)晶体管、或任何具有栅极电极围绕通道的晶体管。使用第一半导体层106来定义半导体元件结构100的一或多个通道将进一步于下论述。
通过任何合适的沉积工艺(如外延)形成第一半导体层106和第二半导体层108。举例来说，可通过分子束外延(molecular beam epitaxy,MBE)工艺、金属有机化学气相沉积(metal organic chemical vapor deposition,MOCVD)工艺及/或其他合适的外延成长工艺进行半导体层堆叠104膜层的外延成长。尽管三个第一半导体层106和三个第二半导体层108交错排列(如图1所示)，应理解的是，可在半导体层堆叠104中形成任何数量的第一半导体层106和第二半导体层108，取决于半导体元件结构100的每个场效晶体管所预定需要的纳米片通道数量。举例来说，第一半导体层106的数量(其为通道的数量)可介于2和8之间。
在图2中，由半导体层堆叠104形成鳍片结构112。每个鳍片结构112具有包括第一半导体层106和第二半导体层108的上部、由基底101形成的井部116以及掩模结构110的部分。在形成鳍片结构112之前，在半导体层堆叠104上形成掩模结构110。掩模结构110可包括垫层110a和硬掩模110b。垫层110a可为含氧层(如二氧化硅层)或含氮层(如氮化硅(Si3N4))。可通过任何合适的沉积工艺(如化学气相沉积(chemical vapor deposition,CVD)工艺)形成掩模结构110。
可使用合适的工艺(包括光刻和蚀刻工艺)制造鳍片结构112。在一些实施例中，光刻工艺可包括在掩模结构110上形成光刻胶层(未示出)、曝光光刻胶成图案、进行曝光后烘烤工艺以及显影光刻胶以形成图案化光刻胶。然后，可使用图案化光刻胶来保护基底101的区域，以及形成于其上的膜层，而蚀刻工艺在未被保护的区域形成沟槽114穿过掩模结构110、半导体层堆叠104、并进入基底101，从而得到延伸的鳍片结构112。鳍片结构112沿着Y方向的宽度W1是在约3nm和44nm之间的范围。在一些实施例中，鳍片结构112沿着Y方向的宽度W1是在约20nm和30nm之间的范围。可使用干蚀刻(例如反应式离子蚀刻(reactive ionetch,RIE))、湿蚀刻及/或其组合蚀刻沟槽114。尽管示出两个鳍片结构112，鳍片结构的数量并非限制为两个。
在图3中，在形成鳍片结构112之后，在鳍片结构112之间的沟槽114中形成绝缘材料118。绝缘材料118填入在相邻鳍片结构112之间的沟槽114直到鳍片结构112被埋入于绝缘材料118中。然后，进行平坦化操作(如化学机械研磨(chemical mechanical polishing,CMP)方法及/或回蚀方法)以露出鳍片结构112的顶部。可以氧化硅(silicon oxide,SiO)、氮化硅(silicon nitride,SiN)、氧氮化硅(silicon oxynitride,SiON)、氧碳氮化硅(silicon oxycarbonitride,SiOCN)、碳氮化硅(silicon carbonitride,SiCN)、氟掺杂硅酸玻璃(fluorine-doped silicate glass,FSG)、低介电常数(low-k)介电材料、或任何合适的介电材料形成绝缘材料118。可通过任何合适的方法形成绝缘材料118，如低压化学气相沉积(low-pressure chemical vapor deposition,LPCVD)、等离子体辅助化学气相沉积(plasma-enhanced chemical vapor deposition,PECVD)、或流动性化学气相沉积(flowable chemical vapor deposition,FCVD)。
接着，凹蚀绝缘材料118以形成隔离区120。绝缘材料118的凹蚀露出部分的鳍片结构112。可使用合适的工艺(如干蚀刻工艺、湿蚀刻工艺、或其组合)形成隔离区120。绝缘材料118的顶面可齐平或低于接触井部116的第二半导体层108的表面。
在图4中，通过外延工艺在鳍片结构112的露出部分上形成包覆层(claddinglayer)117。在一些实施例中，首先可在鳍片结构112上形成半导体衬层(未示出)，之后在半导体衬层上形成包覆层117。在形成包覆层117期间，半导体衬层可扩散进入包覆层117中。在任一情况下，包覆层117接触半导体层堆叠104。在一些实施例中，包覆层117和第二半导体层108包括具有相同蚀刻选择比的相同材料。举例来说，包覆层117和第二半导体层108可为或包括硅锗。后续可移除包覆层117和第二半导体层108以创造出用来形成栅极电极层的空间。
在图5中，在包覆层117上和绝缘材料118的顶面上形成衬层119。衬层119可包括低介电常数介电材料(例如具有K值低于7的材料)，如二氧化硅(silicon dioxide,SiO2)、氮化硅、碳氮化硅、氧碳化硅(silicon oxycarbide,SiOC)、或氧碳氮化硅。可通过顺应性工艺(如原子层沉积(atomic layer deposition,ALD)工艺)形成衬层119。然后，在沟槽114中(图4)和在衬层119上形成介电材料121。介电材料121可为含氧材料，如通过流动性化学气相沉积形成的氧化物。含氧材料可据由小于约7的K值，例如小于约3。可进行平坦化工艺(如化学机械研磨工艺)以移除衬层119和介电材料121形成于鳍片结构112上方的部分。在平坦化工艺之后，包覆层117设置于硬掩模110b上的部分露出。
接着，使用任合适的工艺凹蚀衬层119和介电材料121至最顶端的第一半导体层106的水平面。举例来说，在一些实施例中，在凹蚀工艺之后，衬层119和介电材料121的顶面可被凹蚀成与最顶端的第一半导体层106的顶面齐平。蚀刻工艺可为选择性蚀刻工艺，其不会移除包覆层117的半导体材料。凹蚀工艺的结果是，在鳍片结构112之间形成沟槽123。
在图6中，在沟槽123中(图5)和在介电材料121和衬层119上形成介电材料125。介电材料125可包括氧化硅、氮化硅、碳化硅、碳氮化硅、氧氮化硅、氧碳氮化硅、氧化铝(aluminum oxide,AlO)、氮化铝(aluminum nitride,AlN)、氧氮化铝(aluminumoxynitride,AlON)、氧化锆(zirconium oxide,ZrO)、氮化锆(zirconium nitride,ZrN)、氧化锆铝(zirconium aluminum oxide,ZrAlO)、氧化铪(hafnium oxide,HfO)、或其他合适的介电材料。在一些实施例中，介电材料125包括高介电常数(high-k)介电材料(例如具有K值大于7的材料)。可通过任何合适的工艺(如化学气相沉积、等离子体辅助化学气相沉积、流动性化学气相沉积、或原子层沉积工艺)形成介电材料125。进行平坦化工艺(如化学机械研磨工艺)直到露出掩模结构110的硬掩模110b。平坦化工艺移除介电材料125和包覆层117设置在掩模结构110上的部分。衬层119、介电材料121以及介电材料125可一起被称为介电部件127或混合鳍片(hybrid fin)。介电部件127可作为将后续形成的源极/漏极(source/drain,S/D)外延部件和相邻的栅极电极层分隔开的介电鳍片。
在图7中，凹蚀包覆层117，并移除掩模结构110。可通过任何合适的工艺(如干蚀刻、湿蚀刻、或其组合)进行包覆层117的凹蚀。可控制凹蚀工艺使得剩余的包覆层117实质上与半导体层堆叠104中最顶端的第一半导体层106的顶面在相同水平面。凹蚀工艺可为选择性蚀刻工艺，其不会移除介电材料125。可通过任何合适的工艺(如干蚀刻、湿蚀刻、或其组合)进行掩模结构110的移除。
在图8中，在半导体元件结构100上形成一或多个牺牲栅极结构130(谨示出一个)。在鳍片结构112的一部分上形成牺牲栅极结构130。每个牺牲栅极结构130可包括牺牲栅极介电层132、牺牲栅极电极层134以及掩模层136。可通过依序地沉积牺牲栅极介电层132、牺牲栅极电极层134以及掩模层136的毯覆式膜层，接着进行图案化和蚀刻工艺来形成牺牲栅极介电层132、牺牲栅极电极层134以及掩模层136。举例来说，图案化工艺包括光刻工艺(例如光刻或电子束(electron beam,e-beam)光刻)，其可进一步包括光刻胶涂布(例如旋转涂布(spin-on coating))、软烤(soft bake)、掩模对准(mask aligning)、曝光(exposure)、曝光后烘烤、光刻胶显影(developing)、清洗、烘干(例如旋干及/或硬烤(hard baking))、其他合适的光刻技术及/或其组合。在一些实施例中，蚀刻工艺可包括干蚀刻(例如反应式离子蚀刻(reactive ion etch,RIE))、湿蚀刻、其他蚀刻方法及/或其组合。
通过图案化牺牲栅极结构130，鳍片结构112的半导体层堆叠104在牺牲栅极结构130的两侧上部分露出。鳍片结构112被牺牲栅极结构130的牺牲栅极电极层134覆盖的部分可作为半导体元件结构100的通道区。在牺牲栅极结构130的两侧上部分露出的鳍片结构112定义半导体元件结构100的源极/漏极区。在一些实施例中，尽管示出一个牺牲栅极结构130，可沿着X方向排列两个或更多个牺牲栅极结构130。
接着，在牺牲栅极结构130的侧壁上形成栅极间隔物138。首先，栅极间隔物138的形成可首先通过沉积顺应性膜层，其后续会被回蚀来形成侧壁栅极间隔物138。举例来说，可在半导体元件结构100的露出表面上顺应性地设置间隔物材料层。可通过原子层沉积工艺形成顺应性间隔物材料层。在后续，使用例如反应式离子蚀刻对间隔物材料层进行异向性(anisotropic)蚀刻。在异向性蚀刻工艺期间，由水平表面(如鳍片结构112、包覆层117、介电材料125的顶部)移除大部分的间隔物材料层，留下在垂立表面上(如牺牲栅极结构130的侧壁)的栅极间隔物138。栅极间隔物138可以介电材料形成，如氧化硅、氮化硅、碳化硅、氧氮化硅、碳氮化硅、氧碳化硅、氧碳氮化硅及/或其组合。
图9A、图10A、图11A、图12A、图13A、图14A、和图15A是根据一些实施例，制造半导体元件结构100的各种阶段的其中一个沿着图8的剖面A-A的剖面示意图。图9B、图10B、图11B、图12B、图13B、图14B、和图15B是根据一些实施例，半导体元件结构100沿着图8的剖面B-B的剖面示意图。图9C、图10C、图11C、图12C、图13C、图14C、和图15C是根据一些实施例，制造半导体元件结构100的各种阶段的其中一个沿着图8的剖面C-C的剖面示意图。剖面A-A在鳍片结构112中沿着X方向的平面。剖面B-B在牺牲栅极结构130中且与剖面A-A垂直的平面。剖面C-C在外延源极/漏极部件146中(图11C)沿着Y方向且与剖面A-A垂直的平面。
在图9A～图9C中，使用一或多个合适的蚀刻工艺(如干蚀刻、湿蚀刻、或其组合)选择性地凹蚀鳍片结构112、包覆层117以及介电材料125未被牺牲栅极结构130和栅极间隔物138覆盖的露出部分。在一些实施例中，移除鳍片结构112的半导体层堆叠104的露出部分，而露出部分井部116。如图9A所示，凹蚀鳍片结构112的露出部分至与接触基底101的井部116的第二半导体层108的底面齐平或稍微较低的水平面。凹蚀工艺可包括凹蚀鳍片结构112的露出部分和包覆层117的露出部分的蚀刻工艺。
在图10A～图10C中，沿着X方向水平地移除半导体层堆叠104的每个第二半导体层108的边缘部分。移除第二半导体层108的边缘部分形成凹口(cavity)。在一些实施例中，通过选择性湿蚀刻工艺移除部分第二半导体层108。在以硅锗形成第二半导体层108和以硅形成第一半导体层106的情况下，可使用湿蚀刻剂选择性地蚀刻第二半导体层108，湿蚀刻剂如氢氧化铵(ammonium hydroxide,NH4OH)、四甲基氢氧化铵(tetramethylammoniumhydroxide,TMAH)、乙二胺邻苯二酚(ethylenediamine pyrocatechol,EDP)、或氢氧化钾(potassium hydroxide,KOH)的溶液，但不以此为限。
在移除每个第二半导体层108的边缘部分之后，在凹口中沉积介电层以形成介电间隔物144。介电间隔物144可以由低介电常数介电材料形成，如氧氮化硅、碳氮化硅、氧碳化硅、氧碳氮化硅、或氮化硅。介电间隔物144的形成可首先通过使用顺应性沉积工艺(如原子层沉积)形成顺应性介电层，然后进行异向性蚀刻以移除顺应性介电层除了介电间隔物144以外的部分。在异向性蚀刻工艺期间，介电间隔物144被第一半导体层106保护。剩余的第二半导体层108沿X方向被覆盖在介电间隔物144之间。
在图11A～图11C中，在鳍片结构112的井部116上形成外延源极/漏极部件146。外延源极/漏极部件146可包括用于N型场效晶体管的硅、磷化硅(silicon phosphide,SiP)、碳化硅、或碳磷化硅(silicon phosphocarbide,SiCP)的一或多个膜层，或用于P型场效晶体管的硅、硅锗、或锗的一或多个膜层。外延源极/漏极部件146可垂直地和水平地成长以形成刻面(facet)，其可对应于用于基底101的材料的结晶面。通过使用化学气相沉积、原子层沉积、或分子束外延的外延成长方法形成外延源极/漏极部件146。外延源极/漏极部件146与第一半导体层106和介电间隔物144接触。外延源极/漏极部件146可为源极/漏极区。举例来说，一对外延源极/漏极部件146位于牺牲栅极结构130的一侧上的其中一个可为源极区，而该对外延源极/漏极部件146位于牺牲栅极结构130的另一侧上的另外一个可为漏极区。一对外延源极/漏极部件146包括通过通道(例如第一半导体层106)连接的源极外延部件146和漏极外延部件146。在本公开中，源极和漏极可互换使用，且其结构大抵相同。
在图12A～图12C中，在形成外延源极/漏极部件146之后，在半导体元件结构100的露出表面上顺应性地形成接触蚀刻停止层(contact etch stop layer,CESL)162。接触蚀刻停止层162覆盖外延源极/漏极部件146、栅极间隔物138、介电材料125以及半导体层堆叠104的露出表面。接触蚀刻停止层162可包括含氧材料或含氮材料，例如氮化硅、碳氮化硅、氧氮化硅、氮化碳(carbon nitride,CN)、氧化硅、碳氧化硅(silicon carbon oxide,SiCO)、其他类似材料、或其组合，且可通过化学气相沉积、等离子体辅助化学气相沉积、原子层沉积、或任何合适的沉积技术形成。接着，在半导体元件结构100的接触蚀刻停止层162上形成层间介电(interlayer dielectric,ILD)层164。层间介电层164的材料可包括四乙氧基硅烷(tetraethylorthosilicate,TEOS)氧化物、未掺杂硅酸玻璃、或掺杂氧化硅(如硼掺杂磷硅酸玻璃(boron-doped phospho-silicate glass,BPSG)、氟掺杂硅酸玻璃(fluorine-doped silicate glass,FSG)、磷硅酸玻璃(phospho-silicate glass,PSG)、硼硅酸玻璃(boro-silicate glass,BSG)及/或包括硅、氧、碳及/或氢的其他合适的介电材料)。可通过等离子体辅助化学气相沉积工艺或其他合适的沉积技术沉积层间介电层164。在一些实施例中，在形成层间介电层164之后，可对半导体元件结构100进行热工艺以退火层间介电层164。
在图13A～图13C中，在形成层间介电层164之后，在半导体元件结构100上进行平坦化操作(如化学机械研磨)以移除部分层间介电层164、部分接触蚀刻停止层162以及掩模层136直到露出牺牲栅极电极层134。
在图14A～图14C中，移除牺牲栅极结构130。牺牲栅极结构130的移除形成沟槽166于牺牲栅极电极层134和牺牲栅极介电层132被移除的区域中。沟槽166露出包覆层117和第一半导体层106的顶部的部分。在移除牺牲栅极结构130的期间，层间介电层164保护外延源极/漏极部件146。可使用等离子体干蚀刻及/或湿蚀刻移除牺牲栅极结构130。可首先通过任何合适的工艺(如干蚀刻、湿蚀刻、或其组合)移除牺牲栅极电极层134，接着也可通过任何合适的工艺(如干蚀刻、湿蚀刻、或其组合)进行牺牲栅极介电层132的移除。在一些实施例中，可以使用如四甲基氢氧化铵溶液的湿蚀刻剂来选择性地移除牺牲栅极电极层134，但不移除栅极间隔物138、介电材料125以及接触蚀刻停止层162。在一些实施例中，可通过用于移除牺牲栅极电极层134及/或牺牲栅极介电层132的蚀刻剂凹蚀栅极间隔物138。
在图15A～图15C中，移除包覆层117和第二半导体层108。包覆层117和第二半导体层108的移除露出介电间隔物144和第一半导体层106。移除工艺可为任何合适的蚀刻工艺(如干蚀刻、湿蚀刻、或其组合)。蚀刻工艺可为选择性蚀刻工艺，其移除包覆层117(图14B)和第二半导体层108，但不移除栅极间隔物138、接触蚀刻停止层162、介电材料125以及第一半导体层106。结果是，在第一半导体层106周围形成开口151，且第一半导体层106未被介电间隔物144覆盖的部分露出于开口151。
图16、图16a、图17、图17a、图17b、图18～图24、图24a、图24b、和图25是根据一些实施例，示出制造半导体元件结构100的各种阶段于图15B的区域147的放大示意图。在图16中，形成双极层150围绕第一半导体层106的露出表面并于基底101的井部116上。取决于纳米片晶体管的导电类型，双极层150可被配置为包括正极性或负极性。在介电部件127的一侧上的区域153的纳米片晶体管可被指定为P型场效晶体管或N型场效晶体管，而在介电部件127的另一侧上的区域155的纳米片晶体管可被指定为N型场效晶体管或P型场效晶体管。替代地，区域153和155皆可被指定为P型场效晶体管或N型场效晶体管。在任何情况下，双极层150可作为增强或调整纳米片晶体管的临界电压(threshold voltage)。在图16所示的实施例中，在区域153的纳米片晶体管被指定为N型场效晶体管，而在区域155的纳米片晶体管被指定为P型场效晶体管。在这样的情况下，双极层150可为由本质包括正极性的材料所形成的正极性双极(positive polarity dipole,p-dipole)层。举例来说，双极层150可为含锗材料、含铝材料、含钛材料、或其他类似材料。在一实施例中，双极层150为含锗材料，如纯锗。此处所使用的用语“纯锗”是指具有至少99.9％比重的锗元素的材料。在双极层150由锗形成的情况下，第一半导体层106和井部116的半导体表面促进双极层150于其上的选择性成长，而在绝缘材料118、衬层119以及介电材料125的介电表面上成长很少的或没有双极层150。在一些实施例中，双极层150可以进一步包含氧。
可通过原子层沉积、原子层外延(atomic layer epitaxy,ALE)、化学气相沉积、或任何合适的顺应性沉积技术形成双极层150，以确保双极层150的均匀厚度。合适的源气体可包括含锗气体，其可为锗烷(germane,GeH4)或更高阶的锗烷，如具有实验式(empiricalformula)为GexH(2x+2)的化合物(例如二锗烷(digermane,Ge2H6)、三锗烷(trigermane,Ge3H8)、四锗烷(tetragermane,Ge4H10)、或其他类似材料)。也可使用氯化锗的衍生物(derivative)，如二氯化锗(germanium dichloride,GeCl2)、四氯化锗(germaniumtetrachloride,GeCl4)、或二氯锗烷(dichlorogermane,GeCl2H2)。
双极层150在第一半导体层106的露出表面上和在基底101的井部116上具有均匀的厚度。基于纳米片晶体管所需的临界电压及/或元件性能的考虑来选择双极层150的厚度。在一些实施例中，双极层150具有约
Figure BDA0003531943870000161
至
Figure BDA0003531943870000162
的厚度。若双极层150的厚度小于约
Figure BDA0003531943870000163
双极层150可能无法如预期针对P型及/或N型场效晶体管有效地调节的临界电压。另一方面，若双极层150的厚度大于
Figure BDA0003531943870000164
纳米片通道(例如第一半导体层106)之间所创造的空间可能不够容纳后续膜层(例如，盖层157、高介电常数电介层160、栅极电极层172、或其他类似部件)
在一些实施例中，可选地对半导体元件结构100进行热处理。热处理的结果是，双极层150中的锗扩散进入第一半导体层106和井部116并与其中的硅混合以形成互混层(intermixed layer)129。互混层129可被视为修改后的第一半导体层106/井部116。本公开所使用的用语“混合层”表示第一半导体层106/井部116与双极层150的反应产物，其可为化合物、组合物、或混合物，取决于所使用的热处理。在一些实施例中，互混层129可为掺杂来自双极层150的材料的第一半导体层106。图16a为半导体元件结构100的部分A的放大示意图，示出在第一半导体层106和双极层150之间形成的互混层129。互混层129具有沿着其厚度逐渐地并连续地变化的硅锗浓度轮廓。在一实施例中，互混层129在与双极层150的界面具有第一浓度的硅锗，而在与第一半导体层106的界面的部分具有第二浓度的硅锗，第二浓度的硅锗低于第一浓度的硅锗。
可原位(in-situ)或非原位(ex-situ)进行热处理，且可为任何类型的退火，如快速热退火(rapid thermal anneal,RTA)、尖波退火(spike anneal)、浸入式退火(soakanneal)、激光退火(laser anneal)、炉退火(furnace anneal)、或其他类似方法。可在约450℃至1200℃范围的温度下进行热处理约0.05秒至60分钟，例如约10秒至30秒。可在气体的环境中(如含氧气体、含氢气体、含氩气体、含氦气体、或其组合)进行热处理。示例性气体可包括于氮气(nitrogen,N2)、氨气(ammonia,NH3)、氧气(oxygen,O2)、一氧化二氮(dinitrogen monoxide,N2O)、氩气(argon,Ar)、氦气(helium,He)、氢气(hydrogen,H)、或其他类似气体，但不以此为限。
在图17中，在半导体元件结构100的露出表面上形成盖层157。在双极层150上形成盖层157以围绕第一半导体层106的表面并于基底101的井部116上。盖层157也形成在衬层119和介电材料125的露出表面上。在一些实施例中，也可在绝缘材料118的一部分上形成盖层157。盖层157避免在后续工艺期间(如前清洁工艺)，下方的双极层150中的锗穿透。盖层157可减少正极性双极层的锗流失至少80％，允许正极性双极层在约-20mV到-650mV的范围中提供更大的临界电压调整能力。由于减少了正极性双极层的锗流失，可改善每小时晶片数量(wafer per hour,WPH)的产能需求。
盖层157可具有不同于双极层150的成分(包括所含的元素和其元素的百分比)。在一些实施例中，盖层157可包括含氧材料或含硅材料(如氧化物、氧化硅、氧氮化硅、氧氮化物、或其他类似材料)，或由上述材料形成，且可通过任何合适的技术形成，如原子层沉积(热原子层沉积或等离子体辅助原子层沉积(plasma-enhanced atomic layerdeposition,PEALD))、化学气相沉积、臭氧氧化(ozone oxidation)、或任何合适的顺应性沉积工艺。在一实施例中，盖层157是氧化物。可选地，对盖层157进行前清洁工艺以由盖层157的露出表面移除残留物。前清洁工艺可为任何合适的湿清洁工艺，如氨-双氧水混合物(ammonium hydroxide–hydrogen peroxide mixture,APM)工艺(其至少包括水(water,H2O)、氨水(ammonium hydroxide,NH4OH)以及双氧水(hydrogen peroxide,H2O2))、盐酸-双氧水混合物(hydrochloric acid–hydrogen peroxide mixture,HPM)工艺(其至少包括水、双氧水以及盐酸(hydrochloric acid,HCl))、硫酸-双氧水混合物(sulfuric acid–hydrogen peroxide mixture,SPM)工艺(也被称为食人鱼清洁(piranha clean))(其至少包括双氧水和硫酸(sulfuric acid,H2SO4))、或其组合。在完成前清洁工艺时，可进一步氧化部分盖层157以形成用于N型和P型场效晶体管的界面层(interfacial layer,IL)。图17a为半导体元件结构100的部分B的放大示意图，示出盖层157的外部159被氧化以形成界面层。也就是说，外部159为界面层或界面层的一部分。在一些实施例中，外部159具有约
Figure BDA0003531943870000171
至
Figure BDA0003531943870000172
的厚度T1。
在一些实施例中，盖层为通过氧化双极层150的外部所形成的氧化物。图17b示出通过氧化双极层150的外部所形成盖层157’的实施例，同时，图17b为半导体元件结构100的部分C的放大示意图。因此，在完成氧化时，外部围绕并与核心的双极层150接触。在以锗形成双极层150的情况下，双极层150具有包含氧化锗的外部(例如盖层157’)和包含锗的内部(例如核心的双极层150)。在一些实施例中，在氧化锗中的锗浓度为约1原子百分比至60原子百分比。在一些实施例中，在氧化锗中的锗浓度为约10原子百分比或更高，例如约20原子百分比至50原子百分比。由于盖层157’施加于下方的纳米片通道的压缩应力(compressivestress)，在纳米片通道(例如在区域155的第一半导体层106)上形成具有约10原子百分比或更高的锗浓度的盖层可改善P型场效晶体管的载子(例如空穴)迁移率。当使用(100)平面作为纳米片通道沿着Y方向的顶面时，这样的压缩应力增加(100)方向平面上的硅空穴迁移率。
可使用氧化工艺(如热氧化工艺(thermal oxidation process)、快速热氧化(rapid thermal oxidation,RTO)工艺、临场蒸气产生(in-situ steam generation,ISSG)工艺、或增强型临场蒸气产生(enhanced in-situ steam generation,EISSG)工艺)形成盖层157’。在一范例中，通过在含氧环境中对双极层150进行快速热退火来形成盖层157’。可在约600℃至1100℃的温度下进行热氧化约10秒至约30秒的时间。氧化的温度和时间可影响盖层157’的厚度。举例来说，更高的温度和更长的氧化时间可能导致更厚的盖层157’。盖层157’可具有约
Figure BDA0003531943870000181
至
Figure BDA0003531943870000182
的厚度T2，其取决于双极层150的厚度和氧化而有所变化。
在一些实施例中，其可与本公开的任何一个或更多个实施例结合，盖层157可具有与第一半导体层106相同的成分。图18示出以与第一半导体层106相同的材料形成盖层161的实施例。在一实施例中，盖层161为硅，例如纯硅。此处所使用的用语“纯硅”是指具有至少99.9％比重的硅元素的材料。在另一实施例中，盖层161实质上为纯硅，并具有在盖层161中例如小于2％或1％的锗。可使用任何合适的沉积工艺原位(例如在双极层150所形成的相同的工艺腔体中)或非原位形成盖层161。在一实施例中，盖层161为通过外延工艺所形成的硅层。外延工艺可使用含硅前驱物(precursor)(如硅烷(silane)、卤化硅烷、有机硅烷、或其衍生物)和载子气体(如氢气、氮气、氩气、氦气、或其组合)。盖层161可具有约
Figure BDA0003531943870000191
至
Figure BDA0003531943870000192
的厚度。在形成盖层161之后，进行前清洁工艺以由盖层161的露出表面移除残留物。前清洁工艺可为任何合适的湿清洁工艺，如上述的氨-双氧水混合物工艺、盐酸-双氧水混合物工艺、硫酸-双氧水混合物工艺、或其组合。在一些实施例中，在完成前清洁工艺时，部分盖层161被氧化以形成用于N型和P型场效晶体管的界面层。图19示出盖层161的表面部分被氧化以形成包绕第一半导体层106的界面层163(例如氧化硅)的实施例，其导致盖层161(例如硅)设置于界面层163和双极层150之间。界面层163可具有约
Figure BDA0003531943870000193
至
Figure BDA0003531943870000194
的厚度T3，其取决于盖层161的厚度和氧化而有所变化。
在图20中，在半导体元件结构100的露出表面上形成硬掩模152。在盖层157上(或在一些替代实施例中的盖层157’或界面层163上)形成硬掩模152以围绕第一半导体层106的表面并于基底101的井部116上。也在衬层119和介电材料125上的盖层157上形成硬掩模152。硬掩模152可为用来保护未被处理的区域的介电层。在一些实施例中，可以氧化铝、氮化铝、硅、氧化硅、氮化硅、其他类似材料、或其组合形成硬掩模152，且可通过任何合适的沉积技术形成(如原子层沉积、化学气相沉积、物理气相沉积(physical vapor deposition,PVD)、或其他类似方法)。硬掩模152可具有约1nm至5nm的厚度。
在图21中，形成掩模层154以覆盖至少在区域155的纳米片晶体管，其在一些实施例中被指定为P型场效晶体管。掩模层154首先填入开口151(图20)至一水平，使得在区域153和155的纳米片晶体管和介电部件127浸没于掩模层154中。在区域153的盖层157上设置的硬掩模152的一部分的后续蚀刻工艺期间，掩模层154保护在区域155的盖层157上设置的硬掩模152的一部分。掩模层154可为任何合适的掩模材料，如光刻胶层、底部抗反射涂(bottom anti-reflective coating,BARC)层、旋覆式玻璃(spin-on glass,SOG)层、或旋覆式碳(spin-on carbon,SOC)层，且可通过旋转涂布或任何合适的沉积技术沉积。接着，图案化和蚀刻掩模层154以露出在区域153的纳米片晶体管，其在一些实施例中被指定为N型场效晶体管。使用灰化工艺及/或一或多道蚀刻工艺(如干蚀刻、湿蚀刻、或其组合)移除在区域153未被掩模层154覆盖的硬掩模152、盖层157以及双极层150。蚀刻工艺露出在区域153的第一半导体层106和井部116的表面。蚀刻工艺也露出部分衬层119和部分介电材料125，如图21所示。
取决于应用，可通过例如形成和变化一或多个双极层和功函数金属的厚度或其他方式来调整特定区域的N型及/或P型场效晶体管的临界电压。在一些实施例中，在图案化和蚀刻掩模层154以露出在区域153的纳米片晶体管的通道之后，移除工艺仅可移除硬掩模152和盖层157，而不移除在区域153的双极层150。通过在不同区域保留及/或移除双极层，半导体元件结构的不同区域中的纳米片场效晶体管可在不同的临界电压下操作。
在图22中，形成界面层156以围绕在区域153的第一半导体层106的露出表面。在一些实施例中，界面层156也可形成于基底101的井部116上。界面层156可包括含氧材料或含硅材料(如氧化硅、氧氮化硅、氧氮化物、铪硅酸盐(hafnium silicate,HfSiO)、或其他类似材料，或以上述材料形成。在一实施例中，界面层156为氧化硅。在一些实施例中，以与界面层163或盖层157的外部159不同的材料形成界面层156。可通过化学气相沉积、原子层沉积、或任何合适的顺应性沉积技术形成界面层156。在一实施例中，使用原子层沉积形成界面层156。基于元件性能的考虑选择界面层156的厚度。在一些实施例中，在区域153的界面层156具有大于在区域155的厚度T1(图17a)、厚度T2(图17b)、或厚度T3(图19)的厚度T4。在一实施例中，界面层156具有约
Figure BDA0003531943870000201
至
Figure BDA0003531943870000202
范围的厚度T4。
在图23中，移除掩模层154和硬掩模152。可使用灰化工艺及/或一或多道蚀刻工艺(如干蚀刻、湿蚀刻、或其组合)移除掩模层154和硬掩模152。选择材料的蚀刻选择比，使得移除工艺选择性地移除掩模层154和硬掩模152，但不移除盖层157和界面层156。在移除掩模层154和硬掩模152时，区域155上的开口151露出，而露出在区域155围绕第一半导体层106的盖层157(或在一些替代实施例中的盖层157’或界面层163)。在一些实施例中，进一步对盖层157和界面层156的露出表面进行湿清洁工艺，如上述的氨-双氧水混合物工艺、盐酸-双氧水混合物工艺、硫酸-双氧水混合物工艺、或其组合。
在图24中，在半导体元件结构100的露出表面上形成高介电常数(high-k,HK)介电层160。在一些实施例中，形成高介电常数介电层160以包绕并接触在区域153和155两者的第一半导体层106上的盖层157(或在一些替代实施例中的盖层157’或界面层163)。高介电常数介电层160也形成于并接触未被盖层157覆盖的衬层119和介电材料125上。高介电常数介电层160可包括氧化铪(hafnium oxide,HfO2)、铪硅酸盐、硅氧氮化铪(hafnium siliconoxynitride,HfSiON)、氧化铪铝(hafnium aluminum oxide,HfAlO)、氧化铪镧(hafniumlanthanum oxide,HfLaO)、氧化铪锆(hafnium zirconium oxide,HfZrO)、氧化铪钽(hafnium tantalum oxide,HfTaO)、氧化铪钛(hafnium titanium oxide,HfTiO)、氧化镧(lanthanum oxide,LaO)、氧化铝、硅氧化铝(aluminum silicon oxide,AlSiO)、氧化锆、氧化钛(titanium oxide,TiO)、氧化钽(tantalum oxide,Ta2O5)、氧化钇(yttrium oxide,Y2O3)、氧氮化硅、或其他合适的高介电常数材料。高介电常数介电层160可为通过顺应性工艺(如原子层沉积工艺或化学气相沉积工艺)所形成的顺应性膜层。高介电常数介电层160可具有约
Figure BDA0003531943870000211
至
Figure BDA0003531943870000212
范围的厚度。
接着，在高介电常数介电层160上形成栅极电极层172。栅极电极层172填入开口151(图23)并围绕在区域153和155的每个第一半导体层106的部分。栅极电极层172包括一或多层的导电材料，如多晶硅(polysilicon)、铝(aluminum,Al)、铜(copper,Cu)、钛(titanium,Ti)、钽(tantalum,Ta)、钨(tungsten,W)、钴(cobalt,Co)、钼(molybdenum,Mo)、氮化钽(tantalum nitride,TaN)、硅化镍(nickel silicide,NiSi)、硅化钴(cobaltsilicide,CoSi)、氮化钛(titanium nitride,TiN)、氮化钨(tungsten nitride,WN)、碳氮化钨(tungsten carbonitride,WCN)、钛铝(titanium aluminum,TiAl)、氮化钛钽(titanium tantalum nitride,TiTaN)、氮化钛铝(titanium aluminum nitride,TiAlN)、碳氮化钽(tantalum carbonitride,TaCN)、碳化钽(tantalumcarbide,TaC)、硅氮化钽(tantalum silicon nitride,TaSiN)、金属合金、其他合适的材料及/或其组合。可通过物理气相沉积、化学气相沉积、原子层沉积、电镀(electro-plating)、或其他合适的方法形成栅极电极层172。在一些实施例中，栅极电极层172包括P型栅极电极层，如氮化钛、氮化钽、氮化钛钽、氮化钛铝、碳氮化钨、钨、镍、钴、或其他合适的材料。
在一些实施例中，其可与本公开的任何一个或更多个实施例结合，可在高介电常数介电层160和栅极电极层172之间形成可选的双极层。取决于在区域153和155的纳米片晶体管的导电类型，可配置可选的双极层以包括正极性或负极性。可选的双极层作为增强或修改在区域153和155的纳米片晶体管的临界电压。在区域155的纳米片晶体管为P型场效晶体管的情况下，可选的双极层可为使用原子层沉积、化学气相沉积、或任何合适的顺应性沉积技术所形成正极性双极层。图24a示出在区域155的纳米片晶体管的高介电常数介电层160和栅极电极层172之间形成正极性双极层165的部分D的一个实施例。用于正极性双极层165的合适材料可以包括氧化铝(aluminum oxide,Al2O3)、二氧化钛(titanium oxide,TiO2)、氧化锗(germanium oxide,GeO2)、氧化锌(zinc oxide,ZnO)、氧化镓(galliumoxide,GaO)、其他类似材料、或其组合，但不以此为限。在一些实施例中，可以与双极层150相同的材料形成正极性双极层165。图24b示出在区域153的纳米片晶体管的高介电常数介电层160和栅极电极层172之间形成负极性双极层167的部分E的另一个实施例。用于负极性双极层167的合适材料可以包括氧化镧(lanthanum oxide,La2O3)、氧化镁(magnesiumoxide,MgO)、氧化钇、氧化钆(gadolinium oxide,Gd2O3)、其他类似材料，或其组合，但不以此为限。正极性双极层165或负极性双极层167的厚度可在约
Figure BDA0003531943870000221
至
Figure BDA0003531943870000222
的范围中变化。
在一些实施例中，其可与本公开的任何一个或更多个实施例结合，可在区域153的纳米片晶体管的高介电常数介电层160和栅极电极层172之间形成可选的栅极电极层。可选的栅极电极层也可形成于衬层119、介电材料125以及基底101的井部116上的高介电常数电介质层160上。可选的栅极电极层可为N型栅极电极层或P型栅极电极层，取决于应用。可选的栅极电极层可包括一或多层的导电材料，例如多晶硅、铝、铜、钛、钽、钨、钴、钼、氮化钽、硅化镍、硅化钴、氮化钛、氮化钨、碳氮化钨、钛铝、氮化钛钽、氮化钛铝、氮化钽、碳氮化钽、碳化钽、硅氮化钽、金属合金、其他合适的材料及/或其组合。图25示出在区域153的纳米片晶体管的高介电常数介电层160和栅极电极层172之间形成N型栅极电极层174的实施例。在一些实施例中，N型栅极电极层174包括碳化钛铝(titanium aluminum carbide,TiAlC)、碳化钽铝(tantalum aluminum carbide,TaAlC)、硅碳化钛铝(titanium silicon aluminumcarbide,TiSiAlC)、碳化钛(titanium carbide,TiC)、硅碳化钽铝(tantalum siliconaluminum carbide,TaSiAlC)、或其他合适的材料。
图26A、图26B、图26C、和图26D和图27A、图27B、图27C、和图27D是根据一些实施例，制造半导体元件结构100的各种阶段的其中一个分别沿着图8的剖面A-A、B-B、C-C以及D-D的剖面示意图。剖面D-D在鳍片结构112中(图8)沿着X方向且与剖面A-A平行的平面。特别来说，图26A～图26D示出在形成栅极电极层172以包绕在区域153和155的第一半导体层106的一部分之后的阶段。
在图27A～图27D中，在区域153和155的N型和P型场效晶体管上进行一或多道金属栅极回蚀(metal gate etching back,MGEB)工艺。进行金属栅极回蚀工艺，使得栅极电极层172、高介电常数介电层160、界面层156(图27D)以及盖层157(图27A)被凹蚀至低于栅极间隔物138的顶面的水平。在一些实施例中，栅极间隔物138也被凹蚀至低于接触蚀刻停止层162的顶面的水平，如图27A所示。在栅极电极层172、高介电常数介电层160、界面层156、盖层157上以及栅极间隔物138之间形成自对准(self-aligned)接触层173。自对准接触层173可为具有与栅极间隔物138相关的蚀刻选择比的介电材料。在一些实施例中，自对准接触层173包括氮化硅。可使用自对准接触层173以定义半导体元件结构100的自对准接触区。
在形成自对准接触层173之后，形成接触开口穿过层间介电层164和接触蚀刻停止层162(图26A和图26D)以露出外延源极/漏极部件146。然后，在外延源极/漏极部件146上形成硅化物层178以将外延源极/漏极部件146导电耦合至后续形成的源极/漏极接触件176。可通过在外延源极/漏极部件146上沉积金属源层并进行快速热退火工艺来形成硅化物层178。金属源层包括选自钨、钴、镍、钛、钼以及钽的金属层，或选自氮化钨、氮化钴(cobaltnitride,CoN)、氮化镍(nickel nitride,NiN)、氮化钛、氮化钼(molybdenum nitride,MoN)以及氮化钽的金属氮化物层。在快速热退火工艺期间，在外延源极/漏极部件146上的部分金属源层与在外延源极/漏极部件146中的硅反应以形成硅化物层178。然后，移除金属源层未反应的部分。
在形成硅化物层178之后，在接触开口中形成导电材料并形成源极/漏极接触件176。可以包括钌(ruthenium,Ru)、钼、钴、镍、钨、钛、钽、铜、铝、氮化钛以及氮化钽的一或多种材料形成导电材料。尽管未示出，在形成源极/漏极接触件176之前，可在接触开口的侧壁上形成阻挡层(例如化钛、氮化钽、或其他类似材料)。然后，进行平坦化工艺(如化学机械研磨)以移除接触材料的多余沉积物并露出自对准接触层173的顶面。
应理解的是，半导体元件结构100可进一步进行互补式金属氧化物半导体(complementary metal oxide semiconductor,CMOS)及/或后段工艺(back-end of line,BEOL)工艺以形成各种部件(如晶体管、接触件/导孔、互连金属层、介电层、钝化层、或其他类似部件)。半导体元件结构100也可包括在基底101的背侧上(backside)的背侧接触件(未示出)，通过翻转半导体元件结构100、移除基底101以及通过背侧接触件选择性地连接外延源极/漏极部件146的源极或漏极部件/端点至背侧电力轨(例如，正电压电源端(VDD)或负电压地端(VSS))。取决于应用，可连接外延源极/漏极部件146的源极或漏极部件/端点和栅极电极层172至前侧(frontside)电源。
此处所描述的各种实施例或范例提供比现有技术较佳的多个优势。根据本公开的实施例，由纯锗形成的正极性双极层设置在P型纳米片场效晶体管的纳米片通道和界面层(或高介电常数介电层)之间。以氧化物盖层覆盖正极性双极层，以避免在后续工艺中(例如前清洁工艺)，下方的双极层中的锗穿透。盖层减少正极性双极层的锗流失至少80％，允许正极性双极层在约-20mV到-650mV的范围中提供更大的临界电压调整能力。由于减少了正极性双极层的锗流失，可改善每小时晶片数量的产能需求。在一些实施例中，盖层为具有锗浓度约10原子百分比或更高的氧化锗，由于盖层施加于下方的纳米片通道的压缩应力，可改善P型纳米片场效晶体管的载子迁移率。
一实施例为一种半导体元件结构。结构包括一或多个第一半导体层；双极层，围绕第一半导体层的每一个，其中双极层包括锗。结构也包括盖层，围绕并接触双极层，其中盖层包括硅；一或多个第二半导体层，设置邻近一或多个第一半导体层。结构还包括栅极电极层，围绕第一半导体层的每一个和第二半导体层的每一个。
在一些实施例中，双极层具有外部，围绕内部，其中外部包括氧化锗，而内部包括锗。在一些实施例中，在外部中的锗浓度为约10原子百分比或更高。在一些实施例中，半导体元件结构还包括互混层，形成于每个第一半导体层和双极层之间。在一些实施例中，互混层具有沿着其厚度逐渐地和连续地改变的硅锗浓度。在一些实施例中，半导体元件结构还包括第一界面层，围绕并接触第二半导体层每一个。在一些实施例中，半导体元件结构还包括第二界面层，围绕第一半导体层的每一个，其中盖层设置于第二界面层和双极层之间。在一些实施例中，第一界面层和第二界面层以相同材料形成。在一些实施例中，第一界面层和第二界面层以不同材料形成。在一些实施例中，半导体元件结构还包括高介电常数介电层，围绕盖层和第二半导体层的每一个。
另一实施例为一种半导体元件结构。结构包括介电部件；一或多个第一半导体层，设置邻近介电部件的第一侧；第一双极层，围绕第一半导体层的每一个，其中第一双极层包括锗。结构也包括第一界面层，围绕第一双极层，其中第一界面层包括含氧材料，而第一界面层具有第一厚度。结构也包括一或多个第二半导体层，设置邻近介电部件的第二侧；第二界面层，围绕第二半导体层的每一个，其中第二界面层包括含氧材料，而第二界面层具有第二厚度，第二厚度大于第一厚度。结构还包括第一栅极电极层，围绕第一半导体层的每一个和第二半导体层的每一个。
在一些实施例中，第一双极层具有外部，围绕内部，其中外部包括氧化锗，而内部包括锗。在一些实施例中，在外部中的锗浓度为约10原子百分比或更高。在一些实施例中，半导体元件结构还包括互混层，形成于每个第一半导体层和第一双极层之间。在一些实施例中，互混层具有第一硅锗浓度于互混层和第一双极层的界面，而互混层于互混层和每个第一半导体层的界面的部分具有第二硅锗浓度，第二硅锗浓度低于第一硅锗浓度。在一些实施例中，半导体元件结构还包括高介电常数介电层，设置于介电部件的表面上，而高介电常数介电层围绕第一界面层和第二界面层。
进一步实施例为一种半导体元件结构的形成方法。方法包括形成第一鳍片结构和第二鳍片结构，第一鳍片结构和第二鳍片结构的每一个包括多个第一半导体层和多个第二半导体层交错堆叠；形成牺牲栅极结构于第一鳍片结构和第二鳍片结构上；形成源极/漏极部件于牺牲栅极结构的两侧上，源极/漏极部件接触第一鳍片结构和第二鳍片结构的第一半导体层；移除第二半导体层的部分以露出第一鳍片结构和第二鳍片结构的每个第一半导体层的部分；形成双极层以围绕第一鳍片结构的每个第一半导体层的露出部分，其中双极层包括锗。方法也包括形成盖层以围绕并接触双极层；形成第一界面层以围绕盖层；形成第二界面层以围绕第二鳍片结构的每个第一半导体层的露出部分；以及形成栅极电极层以围绕第一鳍片结构和第二鳍片结构的每个第一半导体层。
在一些实施例中，半导体元件结构的形成方法还包括对双极层进行热处理，使得在双极层中的锗部分扩散进入并与第一鳍片结构的每个第一半导体层混合。在一些实施例中，形成盖层还包括氧化双极层的外部，而外部包括氧化锗。在一些实施例中，形成盖层还包括形成硅层于双极层上；以及对硅层进行湿清洁工艺以氧化硅层的表面部分。
以上概述数个实施例的特征，以使所属技术领域中技术人员可以更加理解本公开实施例的观点。所属技术领域中技术人员应理解，可轻易地以本公开实施例为基础，设计或修改其他工艺和结构，以达到与在此介绍的实施例相同的目的及/或优势。所属技术领域中技术人员也应理解，此类等效的结构并无悖离本公开的精神与范围，且可在不违背本公开的精神和范围下，做各式各样的改变、取代和替换。

Claims (1)

1.一种半导体元件结构，包括：
一或多个第一半导体层；
一双极层，围绕多个所述第一半导体层的每一个，其中该双极层包括锗；
一盖层，围绕并接触该双极层，其中该盖层包括硅；
一或多个第二半导体层，设置邻近多个所述第一半导体层；以及
一栅极电极层，围绕多个所述第一半导体层的每一个和多个所述第二半导体层的每一个。
CN202210207987.9A 2021-03-30 2022-03-04 半导体元件结构 Pending CN114864678A (zh)

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